CY39165Z676-125NC [CYPRESS]
CPLDs at FPGA Densities; CPLD器件的FPGA密度型号: | CY39165Z676-125NC |
厂家: | CYPRESS |
描述: | CPLDs at FPGA Densities |
文件: | 总86页 (文件大小:1209K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Delta39K™ ISR™
CPLD Family
CPLDs at FPGA Densities™
• Carry-chain logic for fast and efficient arithmetic opera-
tions
Features
• High density
• Multiple I/O standards supported
— 30K to 200K usable gates
— 512 to 3072 macrocells
— 136 to 428 maximum I/O pins
—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs
• Programmable slew rate control on each I/O pin
• User-programmableBusHoldcapabilityoneachI/O pin
• Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec,
rev. 2.2)
— Twelve dedicated inputs including four clock pins,
four global I/O control signal pins and four JTAG
interface pins for boundary scan and reconfig-
urability
• CompactPCI hot swap ready
• Embedded memory
• Multiple package/pinout offering across all densities
—208 to 676 pins in PQFP, BGA, and FBGA packages
—Simplifies design migration across density
—Self-Boot™ solution in BGA and FBGA packages
• In-System Reprogrammable™ (ISR™)
— 80K to 480K bits embedded SRAM
• 16K to 96K bits of (dual-port) channel memory
• High speed – 233-MHz in-system operation
• AnyVolt™ interface
— 3.3V, 2.5V,1.8V, and 1.5V I/O capability
• Low-power operation
—JTAG-compliant on-board programming
— 0.18-mm six-layer metal SRAM-based logic process
—Design changes do not cause pinout changes
• IEEE1149.1 JTAG boundary scan
— Full-CMOS implementation of product term array
— Standby current as low as 5mA
• Simple timing model
Development Software
— No penalty for using full 16 product terms/macrocell
— No delay for single product term steering or sharing
• Flexible clocking
— Spread Aware™ PLL drives all four clock networks
• Allows 0.6% spread spectrum input clocks
• Several multiply, divide and phase shift options
— Four synchronous clock networks per device
— Locally generated product term clock
— Clock polarity control at each register
• Warp®
—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
—Active-HDL SIM post-synthesis timing simulator
—Architecture Explorer for detailed design analysis
—Static Timing Analyzer for critical path analysis
—Available on Windows 95/98/2000/XP™ and
Windows NT™ for $99
—Supports all Cypress programmable logic products
Delta39K™ ISR CPLD Family Members
[2]
Standby ICC
Cluster Channel
Speed-tPD
TA = 25°C
3.3/2.5V
5 mA
Typical
Gates[1]
memory memory Maximum fMAX2 Pin-to-Pin
Device
39K30
Macrocells
512
(Kbits)
64
(Kbits)
16
I/O Pins
174
(MHz)
233
(ns)
7.2
7.2
7.5
8.5
8.5
16K – 48K
23K – 72K
46K – 144K
77K – 241K
92K – 288K
39K50
768
96
24
218
233
5 mA
39K100
39K165
39K200
1536
192
320
384
48
302
222
10 mA
20 mA
20 mA
2560
80
386
181
3072
96
428
181
Notes:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby ICC values are with PLL not utilized, no output load and stable inputs.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03039 Rev. *H
Revised August 1, 2003
Delta39K™ ISR™
CPLD Family
Delta39K Speed Bins[3]
Device
39K30
VCC
233
X
200
181
125
X
83
X
3.3/2.5V
3.3/2.5V
3.3/2.5V
3.3/2.5V
3.3/2.5V
39K50
X
X
X
39K100
39K165
39K200
X
X
X
X
X
X
X
X
X
Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs
Self-Boot Solution[4]
208 EQFP
256 FBGA
484-FBGA
256-FBGA
388-BGA
484-FBGA
676-FBGA
28 × 28 mm
17 × 17 mm
23 × 23 mm
17 × 17 mm
35 × 35 mm
23 × 23 mm
27 × 27 mm
Device 0.5-mm pitch 1.0-mm pitch 1.0-mm pitch 1.0-mm pitch 1.27-mm pitch 1.0-mm pitch 1.0-mm pitch
39K30
39K50
136
136
136
136
136
174
180
180
174
218
294
294
294
218
39K100
39K165
39K200
302
356
368
302
386
428
Notes:
3. Speed bins shown here are for commercial operating range. Please refer to Delta39K ordering information on industrial-range speed bins on page 38.
4. Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000
programming/erase cycles and can retain data for at least 100 years.
Document #: 38-03039 Rev. *H
Page 2 of 86
Delta39K™ ISR™
CPLD Family
PLL and Clock MUX
GCLK[3:0]
GCTL[3:0]
4
4
I/O Bank 7
I/O Bank 6
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 7
LB 6
LB 5
LB 4
LB 0
LB 7
LB 6
LB 6
LB 5
LB 4
LB 1
LB 2
LB 3
LB 1
LB 2
LB 3
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 5
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 5
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 5
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
I/O Bank 2
I/O Bank 3
Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
The architecture is based on Logic Block Clusters (LBC) that
General Description
are connected by Horizontal and Vertical (H and V) routing
channels. Each LBC features eight individual Logic Blocks
(LB) and two cluster memory blocks. Adjacent to each LBC is
a channel memory block, which can be accessed directly from
the I/O pins. Both types of memory blocks are highly config-
urable and can be cascaded in width and depth. See Figure 1
for a block diagram of the Delta39K architecture.
The Delta39K family, based on a 0.18-mm, six-layer metal
CMOS logic process, offers a wide range of high-density
solutions at unparalleled system performance. The Delta39K
family is designed to combine the high speed, predictable
timing, and ease of use of CPLDs with the high densities and
low power of FPGAs. With devices ranging from 30,000 to
200,000 usable gates, the family features devices ten times
the size of previously available CPLDs. Even at these large
densities, the Delta39K family is fast enough to implement a
fully synthesizable 64-bit, 66-MHz PCI core.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
Document #: 38-03039 Rev. *H
Page 3 of 86
Delta39K™ ISR™
CPLD Family
figure the devices without having design changes cause
pinout or timing changes in most cases. The Cypress ISR
function is implemented through a JTAG-compliant serial
interface. Data is shifted in and out through the TDI and TDO
pins respectively. Superior routability, simple timing, and the
ISR allows users to change existing logic designs while simul-
taneously fixing pinout assignments and maintaining system
performance.
Global Routing Description
The routing architecture of the Delta39K is made up of
horizontal and vertical (H and V) routing channels. These
routing channels allow signals from each of the Delta39K
architectural components to communicate with one another. In
addition to the horizontal and vertical routing channels that
interconnect the I/O banks, channel memory blocks, and logic
block clusters, each LBC contains a Programmable Inter-
connect Matrix (PIM™), which is used to route signals
among the logic blocks and the cluster memory blocks.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification,
meeting the electrical and timing requirements. The Delta39K
family also features user programmable bus-hold and slew
rate control capabilities on each I/O pin.
Figure 2 is a block diagram of the routing channels that
interface within the Delta39K architecture. The LBC is exactly
the same for every member of the Delta39K CPLD family.
AnyVolt Interface
Logic Block Cluster (LBC)
All Delta39KV devices feature an on-chip regulator, which
accepts 3.3V or 2.5V on the VCC supply pins and steps it down
to 1.8V internally, the voltage level at which the core operates.
The Delta39K architecture consists of several logic block
clusters, each of which have eight Logic Blocks (LB) and two
cluster memory blocks connected via a Programmable Inter-
connect Matrix (PIM) as shown in Figure 3. Each cluster
memory block consists of 8-Kbit single-port RAM, which is
configurable as synchronous or asynchronous. The cluster
memory blocks can be cascaded with other cluster memory
blocks within the same LBC as well as other LBCs to
implement larger memory functions. If a cluster memory block
is not specifically utilized by the designer, Cypress’s Warp
software can automatically use it to implement large blocks of
logic.
With Delta39K’s AnyVolt technology, the I/O pins can be
connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devices
are 3.3V-tolerant regardless of VCCIO or VCC settings.
Table 1.
Device
VCC
VCCIO
39KV
3.3V or 2.5V
3.3V or 2.5V or 1.8V or 1.5V[5]
All LBCs interface with each other via horizontal and vertical
routing channels.
I/O Block
LB
LB
LB
LB
LB
LB
LB
LB
72
64
Cluster
PIM
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
Channel
Memory
Block
Cluster
Memory
Block
Cluster
Memory
Block
72
64
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
Figure 2. Delta39K Routing Interface
Note:
5. For HSTL only.
Document #: 38-03039 Rev. *H
Page 4 of 86
Delta39K™ ISR™
CPLD Family
Clock Inputs
GCLK[3:0]
4
Logic
Block
0
Logic
Block
7
36
16
36
16
Logic
Block
1
Logic
Block
6
36
16
36
16
Logic
Block
2
Logic
Block
5
36
16
36
16
PIM
Logic
Block
3
Logic
Block
4
36
16
36
16
Cluster
Memory
0
Cluster
Memory
1
25
8
25
8
CC = Carry Chain
64 Inputs From
Vertical Routing
Channel
64 Inputs From
Horizontal Routing
Channel
144 Outputs to
Horizontal and Vertical
cluster-to-channel PIMs
Figure 3. Delta39K Logic Block Cluster Diagram
Logic Block
provides two important capabilities without affecting perfor-
mance: product term steering and product term sharing.
The LB is the basic building block of the Delta39K architecture.
It consists of a product term array, an intelligent product-term
allocator, and 16 macrocells.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Delta39K devices,
product terms are steered on an individual basis. Any number
between 1 and 16 product terms can be steered to any
macrocell.
Product Term Array
Each logic block features a 72 x 83 programmable product
term array. This array accepts 36 inputs from the PIM. These
inputs originate from device pins and macrocell feedbacks as
well as cluster memory and channel memory feedbacks.
Active LOW and active HIGH versions of each of these inputs
are generated to create the full 72-input field. The 83 product
terms in the array can be created from any of the 72 inputs.
Product Term Sharing
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Two of the remaining three
product terms in the logic block are used as asynchronous set
and asynchronous reset product terms. The final product term
is the Product Term clock (PTCLK) and is shared by all 16
macrocells within a logic block.
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
programmed once. The Delta39K product term allocator
allows sharing across groups of four macrocells in a variable
fashion. The software automatically takes advantage of this
capability so that the user does not have to intervene.
Product Term Allocator
Through the product term allocator, Warp software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the logic block. The product term allocator
Note that neither product term sharing nor product term
steering have any effect on the speed of the product. All
steering and sharing configurations have been incorporated in
the timing specifications for the Delta39K devices.
.
Document #: 38-03039 Rev. *H
Page 5 of 86
Delta39K™ ISR™
CPLD Family
Macrocell
tions are implemented through the use of carry-in arithmetic,
which drives through the circuit quickly. Figure 4 shows that
the carry chain logic within the macrocell consists of two
product terms (CPT0 and CPT1) from the PTA and an input
carry-in for carry logic. The inputs to the carry chain mux are
connected directly to the product terms in the PTA. The output
of the carry chain mux generates the carry-out for the next
macrocell in the logic block as well as the local carry input that
is connected to an input of the XOR input mux. Carry-in and a
configuration bit are inputs to an AND gate. This AND gate
provides a method of segmenting the carry chain in any
macrocell in the logic block.
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode. Figure 4
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the
macrocell level with the separate preset and reset product
terms. Each of these product terms features programmable
polarity. This allows the registers to be preset or reset based
on an AND expression or an OR expression.
An XOR gate in the Delta39K macrocell allows for many
different types of equations to be realized. It can be used as a
polarity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows
additional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to
implement adders, subtractors, magnitude comparators,
parity tree, or even generic XOR logic. The output of the
macrocell is either registered or combinatorial.
Macrocell Clocks
Clocking of the register is highly flexible. Four global
synchronous clocks (GCLK[3:0]) and a PTCLK are available
at each macrocell register. Furthermore, a clock polarity mux
within each macrocell allows the register to be clocked on the
rising or the falling edge (see macrocell diagram in Figure 4).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and
reset using the PRESET and RESET mux. Both signals are
active high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in Figure 4) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
Carry Chain Logic
The Delta39K macrocell features carry chain logic which is
used for fast and efficient implementation of arithmetic opera-
tions. The carry logic connects macrocells in up to four logic
blocks for a total of 64 macrocells. Effective data path opera-
Carry In
(from macrocell n-1)
PRESET
Mux
0
1
C
XOR Input
Mux
3
Carry Chain
Mux
C
Output
Mux
CPT0
CPT1
C
2
To PIM
C
DPSET
C
Q
FROM PTM
Up To 16 PTs
Clock
Clock Mux
Polarity
RESQ
Mux
GCLK[3:0]
PTCLK
3
C
C
0
1
Carry Out
(to macrocell n+1)
3
C
RESET
Mux
Figure 4. Delta39K Macrocell
Document #: 38-03039 Rev. *H
Page 6 of 86
Delta39K™ ISR™
CPLD Family
Embedded Memory
Cluster Memory Initialization
Each member of the Delta39K family contains two types of
embedded memory blocks. The channel memory block is
placed at the intersection of horizontal and vertical routing
channels. Each channel memory block is 4096 bits in size and
can be configured as asynchronous or synchronous Dual-Port
RAM, Single-Port RAM, Read-Only memory (ROM), or
synchronous FIFO memory. The memory organization is
configurable as 4K × 1, 2K × 2, 1K × 4 and 512K × 8. The
second type of memory block is located within each LBC and
is referred to as a cluster memory block. Each LBC contains
two cluster memory blocks that are 8192 bits in size. Similar
to the channel memory blocks, the cluster memory blocks can
be configured as 8K × 1, 4K × 2, 2K × 4 and 1K × 8
asynchronous or synchronous Single-Port RAM or ROM.
The cluster memory powers up in an undefined state, but is set
to a user-defined known state during configuration. To facilitate
the use of look-up-table (LUT) logic and ROM applications, the
cluster memory blocks can be initialized with a given set of
data when the device is configured at power up. For LUT and
ROM applications, the user cannot write to memory blocks.
Channel Memory
The Delta39K architecture includes an embedded memory
block at each crossing point of horizontal and vertical routing
channels. The channel memory is a 4096-bit embedded
memory block that can be configured as asynchronous or
synchronous single-port RAM, dual-port RAM, ROM, or
synchronous FIFO memory.
Data, address, and control inputs to the channel memory are
driven from horizontal and vertical routing channels. All data
and FIFO logic outputs drive dedicated tracks in the horizontal
and vertical routing channels. The clocks for the channel
memory block are selected from four global clocks and pin
inputs from the horizontal and vertical channels. The clock
muxes also include a polarity mux for each clock so that the
user can choose an inverted clock.
Cluster Memory
Each logic block cluster of the Delta39K contains two 8192-bit
cluster memory blocks. Figure 5 is a block diagram of the
cluster memory block and the interface of the cluster memory
block to the cluster PIM.
The output of the cluster memory block can be optionally regis-
tered to perform synchronous pipelining or to register
asynchronous Read and Write operations. The output
registers contain an asynchronous RESET which can be used
in any type of sequential logic circuits (e.g., state machines).
Dual-Port (Channel Memory) Configuration
Each port has distinct address inputs, as well as separate data
and control inputs that can be accessed simultaneously. The
inputs to the Dual-Port memory are driven from the horizontal
and vertical routing channels. The data outputs drive
dedicated tracks in the routing channels. The interface to the
routing is such that Port A of the Dual-Port interfaces primarily
with the horizontal routing channel and Port B interfaces
primarily with the vertical routing channel.
There are four global clocks (GCLK[3:0]) and one local clock
available for the input and the output registers. The local clock
for the input registers is independent of the one used for the
output registers. The local clock is generated in the user
design in a macrocell or comes from an I/O pin.
Write
Control
Logic
DIN[7:0]
3
D Q
C
C
2
8
C
ADDR[12:0]
D Q
WE
D Q
1024x8
Asynchronous
SRAM
10
C
Cluster PIM
GCLK[3:0]
5:1
Local CLK
DOUT[7:0]
RESET
3
3
8
C
C
Read
Control
Logic
Q D
R
C
2
C
GCLK[3:0]
Local CLK
5:1
3
C
C
Figure 5. Block Diagram of Cluster Memory Block
Document #: 38-03039 Rev. *H
Page 7 of 86
Delta39K™ ISR™
CPLD Family
The clocks for each port of the Dual-Port configuration are
selected from four global clocks and two local clocks. One
local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs of the dual-
port memory can also be registered. Clocks for the output
registers are also selected from four global clocks and two
local clocks. One clock polarity mux per port allows the use of
true or complement polarity for input and output clocking
purposes.
The FIFO block contains all of the necessary FIFO flag logic,
including the Read and Write address pointers. The FIFO flags
include an empty/full flag (EF), half-full flag (HF), and program-
mable almost-empty/full (PAEF) flag output. The FIFO config-
uration has the ability to perform simultaneous Read and Write
operations using two separate clocks. These clocks may be
tied together for a single operation or may run independently
for asynchronous Read/Write (with regard to each other) appli-
cations. The data and control inputs to the FIFO block are
driven from the horizontal or vertical routing channels. The
data and flag outputs are driven onto dedicated routing tracks
in both the horizontal and vertical routing channels. This allows
the FIFO blocks to be expanded by using multiple FIFO blocks
on the same horizontal or vertical routing channel without any
speed penalty.
Arbitration
The Dual-Port configuration of the Channel Memory Block
provides arbitration when both ports access the same address
at the same time. Depending on the memory operation being
attempted, one port always gets priority. See Table 2 for
details on which port gets priority for Read and Write opera-
tions. An active-LOW “Address Match” signal is generated
when an address collision occurs.
In FIFO mode, the Write and Read ports are controlled by
separate clock and enable signals. The clocks for each port
are selected from four global clocks and two local clocks.
One local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs from the
Read port of the FIFO can also be registered. One clock
polarity mux per port allows using true or complement polarity
for Read and Write operations. The Write operation is
controlled by the clock and the Write enable pin. The Read
operation is controlled by the clock and the Read enable pin.
The enable pins can be sourced from horizontal or vertical
channels.
Table 2. Arbitration Result: Address Match Signal
Becomes Active
Result of
Port A Port B Arbitration
Comment
Read
Read No arbitration Both ports read at the
required
same time
Write
Read Port A gets
priority
If Port B requestsfirst then
it will read the current
data. The output will then
change to the newly
Channel Memory Initialization
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To facil-
itate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a
given set of data when the device is configured at power up.
For LUT and ROM applications, the user cannot write to
memory blocks.
written data by Port A
Read
Write
Write Port B gets
priority
If Port A requestsfirst then
it will read the current
data. The output will then
change to the newly
written data by Port B
Write Port A gets
priority
Port B is blocked until Port
A is finished writing
Channel Memory Routing Interface
Similar to LBC outputs, the channel memory blocks feature
dedicated tracks in the horizontal and vertical routing channels
for the data outputs and the flag outputs, as shown in
Figure 6. This allows the channel memory blocks to be
expanded easily. These dedicated lines can be routed to I/O
pins as chip outputs or to other logic block clusters to be used
in logic equations.
FIFO (Channel Memory) Configuration
The channel memory blocks are also configurable as
synchronous FIFO RAM. In the FIFO mode of operation, the
channel memory block supports all normal FIFO operations
without the use of any general-purpose logic resources in the
device.
Document #: 38-03039 Rev. *H
Page 8 of 86
Delta39K™ ISR™
CPLD Family
inputs are driven from
the routing channels
4096-bit Dual-Port
Array
Global Clock
Signals
Configurable as
Async/Sync Dual-Port
or Sync FIFO
GCLK[3:0]
Configurable as
4K x 1, 2K x 2, 1K x 4,
and 512 x 8 block sizes
All channel memory outputs
drive dedicated tracks in the
routing channels
Horizontal Channel
Figure 6. Block Diagram of Channel Memory Block
I/O Cell
I/O Banks
The Delta39K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are eight I/O
banks per device as shown in Figure 7, and all I/Os from an
I/O bank are located in the same section of a package for PCB
layout convenience.
Figure 8 is a block diagram of the Delta39K I/O cell. The I/O
cell contains a three-state input buffer, an output buffer, and a
register that can be configured as an input or output register.
The output buffer has a slew rate control option that can be
used to configure the output for a slower slew rate. The input
of the device and the pin output can each be configured as
registered or combinatorial; however, only one path can be
configured as registered in a given design.
Delta39K devices support True Vertical Migration™ (i.e., for
each package type, Delta39K devices of different densities
keep given pins in the same I/O banks). This allows for easy
and simple implementation of multiple I/O standards during the
design and prototyping phase, before a final density has been
determined. Please refer to the application note titled “Family,
Package and Density Migration in Delta 39K and Quantum38K
CPLDs.”
The output enable in an I/O cell can be selected from one of
the four global control signals or from one of two Output
Control Channel (OCC) signals. The output enable can be
configured as always enabled or always disabled or it can be
controlled by one of the remaining inputs to the mux. The
selection is done via a mux that includes VCC and GND as
inputs.
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
bank 7
bank 6
Each I/O bank can use any supported I/O standard by
supplying appropriate VREF and VCCIO voltages and config-
uring the I/O through the Warp software. All the VREF and
VCCIO pins in an I/O bank must be connected to the same VREF
and VCCIO voltage respectively. This requirement restricts the
number of I/O standards supported by an I/O bank at any given
time.
Delta39K
The number of I/Os which can be used in each I/O bank
depend on the type of I/O standards and the number of VCCIO
and GND pins being used. This restriction is derived from the
electromigration limit of the VCCIO and GND bussing on the
chip. Please refer to the note on page 17 and the application
note titled “Delta39K Family Device I/O Standards and Config-
urations” for details.
bank 2
bank 3
Figure 7. Delta39K I/O Bank Block Diagram
Document #: 38-03039 Rev. *H
Page 9 of 86
Delta39K™ ISR™
CPLD Family
Registered OE
Mux
OE Mux
D
Q
From
C
Output PIM
3
C
Input
Mux
RES
To Routing
Channel
Register Input
Mux
C
C
Output Mux
Bus
Hold
I/O
Register Enable
Mux
D
E
Q
Clock
C
C
Polarity
Mux
Slew
Rate
RES
3
C
C
Control
Clock Mux
C
C
2
3
Register Reset
Mux
C
Figure 8. Block Diagram of I/O Cell
Table 3.
I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. These global control signals, driven from four
dedicated pins, can only be used as active-high signals and
are available only to the I/O cells thereby implementing fast
resets, register and output enables.
I/O Standards
I/O
Termination
Standard
V
REF (V)
Max.
VCCIO
Voltage (VTT)
Min.
LVTTL
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
N/A
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.5
In addition, there are six OCC signals available to each I/O
cell. These control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8. Unlike global control signals, these OCC signal can
be driven from internal logic or and I/O pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock
0.9
1.3
1.1
1.7
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
1.5
1.3
1.7
1.5
1.15
1.15
0.68
0.68
0.68
0.68
1.35
1.35
0.9
1.25
1.25
0.75
0.75
1.5
Slew Rate Control
The output buffer has a slew rate control option. This allows
the output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
HSTL II
0.9
HSTL III
HSTL IV
0.9
0.9
1.5
Document #: 38-03039 Rev. *H
Page 10 of 86
Delta39K™ ISR™
CPLD Family
Programmable Bus Hold
For example, a system that operates on a 32-bit data path that
runs at 40 MHz can be implemented with 16-bit circuitry that
runs internally at 80 MHz. PLLs can also be used to take
advantage of the positioning of the internally generated clock
edges to shift performance towards improved setup, hold or
clock-to-out times.
On each I/O pin, user-programmable-bus-hold is included.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-
interface applications. Bus-hold additionally allows unused
device pins to remain unconnected on the board, which is
particularly useful during prototyping as designers can route
new signals to the device without cutting trace connections to
VCC or GND. For more information, see the application note
titled “Understanding Bus-Hold–A Feature of Cypress
CPLDs.”
There are several frequency multiply (X1, X2, X3, X4, X5, X6,
X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options
available to create a wide range of clock frequencies from a
single clock input (GCLK[0]). For increased flexibility, there are
seven phase shifting options which allow clock skew/deskew
by 45°, 90°, 135°, 180°, 225°, 270°, or 315°.
The Spread Aware feature refers to the ability of the PLL to
track a spread-spectrum input clock such that its spread is
seen on the output clock with the PLL staying locked. The total
amount of spread on the input clock should be limited to 0.6%
of the fundamental frequency. Spread Aware feature is
supported only with X1, X2, and X4 multiply options.
Clocks
Delta39K has four dedicated clock input pins (GCLK[3:0]) to
accept system clocks. One of these clocks (GCLK[0]) may be
selected to drive an on-chip phase-locked loop (PLL) for
frequency modulation (see Figure 9 for details).
The Voltage Controlled Oscillator (VCO), the core of the
Delta39K PLL is designed to operate within the frequency
range of 100 MHz to 266 MHz. Hence, the multiply option
combined with input (GCLK[0]) frequency should be selected
such that this VCO operating frequency requirement is met.
This is demonstrated in Table 4 (columns 1, 2, and 3).
The global clock tree for a Delta39K device can be driven by
a combination of the dedicated clock pins and/or the PLL-
derived clocks. The global clock tree consists of four global
clocks that go to every macrocell, memory block, and I/O cell.
Clock Tree Distribution
Another feature of this PLL is the ability to drive the output
clock (INTCLK) off the Delta39K chip to clock other devices on
the board, as shown in Figure 9 above. This off-chip clock is
half the frequency of the output clock as it has to go through a
register (I/O register or a macrocell register).
The global clock tree performs two primary functions. First, the
clock tree generates the four global clocks by multiplexing four
dedicated clocks from the package pins and four PLL driven
clocks. Second, the clock tree distributes the four global clocks
to every cluster, channel memory, and I/O block on the die.
The global clock tree is designed such that the clock skew is
minimized while maintaining an acceptable clock delay.
This PLL can also be used for board de-skewing purpose by
driving a PLL output clock off-chip, routing it to the other
devices on the board and feeding it back to the PLL’s external
feedback input (GCLK[1]). When this feature is used, only
limited multiply, divide and phase shift options can be used.
Table 4 describes the valid multiply and divide options that can
be used without external feedback. Table 5 describes the valid
multiply and divide options that can be used with an external
feedback.
Spread Aware PLL
Each device in the Delta39K family features an on-chip PLL
designed using Spread Aware technology for low EMI applica-
tions. In general, PLLs are used to implement time-division-
multiplex circuits to achieve higher performance with fewer
device resources.
off-chip signal (external feedback)
INTCLK0, INTCLK1, INTCLK2, INTCLK3
Any Register (TFF)
Send a global clock off
chip
GCLK1
Normal I/O signal path
Lock Detect/IO pin
C
Clock Tree
Delay
Phase selection
Divide
¸1-6,8,16
2
C
INTCLK0
GCLK0
fb
fb
Lock
2
Phase selection
C
Divide
¸ 1-6,8,16
Clk
00
0
Clk 45
INTCLK1
GCLK1
Clk
0
2
Phase selection
GCLK0
90
Clk 135
Source
Clock
C
0
Divide
¸1-6,8,16
0
Clk 180
Clk
INTCLK2
0
225
Clk
GCLK2
0
270
Clk
2
PLL
X1, X2, X3, X4, 5X,
0
315
C
Phase selection
X6, X8, X16
Divide
¸1-6,8,16
INTCLK3
GCLK3
2
C
Figure 9. Block Diagram of Spread Aware PLL
Document #: 38-03039 Rev. *H
Page 11 of 86
Delta39K™ ISR™
CPLD Family
Table 6 describes the valid phase shift options that can be
For more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree”.
used with or without an external feedback.
Table 7 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
Table 4. Valid PLL Multiply and Divide Options—without External Feedback
Valid Multiply Options
Input Frequency
Valid Divide Options
Output Frequency (INTCLK[3:0]) Off-chip Clock
(GCLK[0])
fPLLI (MHz)
VCO Output
Value Frequency (MHz)
Value
fPLLO (MHz)
DC–12.5
6.25–133
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
Frequency
DC–12.5
N/A
1
N/A
N/A
DC–6.25
100–133
50–133
100–133
100–266
100–266
100–266
100–266
100–266
100–266
200–266
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
3.125–66
3.125–133
3.1–266
2
33.3–88.7
25–66
3
4
3.125–133
3.1–133
20–53.2
16.6–44.3
12.5–33
12.5–16.625
5
6
3.1–133
8
3.125–133
3.125–133
16
Table 5. Valid PLL Multiply and Divide Options—With External Feedback
Valid Multiply Options
Valid Divide Options
Input (GCLK) Frequency
fPLLI (MHz)
VCO Output
Frequency (MHz)
Output (INTCLK) Frequency
fPLLO (MHz)
Off-chip Clock
Frequency
Value
Value
50–133
1
1
1
1
1
1
1
100–266
100–266
100–266
100–266
125–266
150–266
200–266
1
2
3
4
5
6
8
100–266
50–133
25–66.5
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
33.33–88.66
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
25–53.2
25–44.34
25–33.25
Table 6. Recommended PLL Phase Shift Options
Without External Feedback
With External Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
0°
Table 7. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Divide
Factor
Period
(ns)
0°
(ns)
45°
(ns)
90°
(ns)
135°
(ns)
180°
(ns)
225°
(ns)
270°
(ns)
315°
(ns)
Duty Cycle%
1
2
4
40–60
50
0
0
0
0
0
0
0
0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
8
3
12
16
20
24
32
64
33–67
50
4
5
40–60
50
6
8
50
16
50
Document #: 38-03039 Rev. *H
Page 12 of 86
Delta39K™ ISR™
CPLD Family
CompactPCI Hot Swap
output (from corner to corner on the device), incurs a worst-
case delay in the 39K100 regardless of the amount of logic or
which horizontal and vertical channels are used. This is the tPD
shown in Figure 10. For synchronous systems, the input set-
up time to the output macrocell register and the clock to output
time are shown as the parameters tMCS and tMCCO shown in
the Figure 10. These measurements are for any output and
synchronous clock, regardless of the logic placement.
The CompactPCI Hot Swap specification allows the removal
and insertion of cards into CompactPCI sockets without
switching-off the bus. Delta39K CPLDs can be used as a
CompactPCI host or target on these cards.
This feature is useful in telecommunication and networking
applications as it allows implementation of high availability
systems, where repairs and upgrades can be done without
downtime.
The Delta39K features:
• no dedicated vs. I/O pin delays
• no penalty for using 0 – 16 product terms
• no added delay for steering product terms
• no added delay for sharing product terms
• no output bypass delays.
Delta39K CPLDs are CompactPCI Hot Swap Ready per
CompactPCI Hot Swap specification R2.0, with the following
exception:
• The I/O cells do not provide bias voltage support. External
resistors can be used to achieve this, per section 3.1.3.1 of
the CompactPCI Hot Swap specification R2.0. A simple
board level solution is provided in the application note titled
“Hot-Swapping Delta39K and Quantum38K CPLDs.”
The simple timing model of the Delta39K family eliminates
unexpected performance penalties.
Family, Package, and Density Migration in Delta39K
CPLDs
Timing Model
One important feature of the Delta39K family is the simplicity
of its timing. All combinatorial and registered/synchronous
delays are worst case and system performance is static (as
shown in the AC specs section) as long as data is routed
through the same horizontal and vertical channels. Figure 10
illustrates the true timing model for the 200-MHz devices. For
synchronous clocking of macrocells, a delay is incurred from
macrocell clock to macrocell clock of separate Logic Blocks
within the same cluster, as well as separate Logic Blocks
within different clusters. This is respectively shown as tSCS and
tSCS2 in Figure 10. For combinatorial paths, any input to any
The Delta39K CPLDs combine dense logic, embedded mem-
ory and configurable I/O standards. Further design flexibility is
added by the easy migration options available between differ-
ent packages and densities of Delta39K CPLD offerings.
This migration flexibility makes changes or additions to
designs simple even after PCB layout. It also provides the
ability for experimental designs to be used on production
PCBs. Please refer to the application note titled “Family,
Package, and Density Migration in Delta39K CPLDs.”
Document #: 38-03039 Rev. *H
Page 13 of 86
Delta39K™ ISR™
CPLD Family
tSCS
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PM
PIM
LB 2
LB 3
LB 2
LB 3
tMCS
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
8 Kb
SRAM
8 Kb
SRAM
GCLK[3:0]
4
4
4
4
tSCS2
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 2
LB 3
tPD
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 2
LB 5
LB 4
LB 5
LB 5
LB 4
LB 4
LB 3
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
tMCCO
Figure 10. Timing Model for 39K100 Device
IEEE 1149.1-compliant JTAG Operation
The Delta39K family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
The Delta39K family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
Configuration
Each device of the Delta39K family is available in a volatile and
a Self-Boot package. Cypress’s CPLD boot EEPROM is used
to store configuration data for the volatile solution and an
embedded on-chip FLASH memory device is used for the Self-
Boot solution.
Boundary Scan
The Delta39K family supports Bypass, Sample/Preload,
Extest, Intest, Idcode and Usercode boundary scan instruc-
tions. The JTAG interface is shown in Figure 11.
For volatile Delta39K packages, programming is defined as
the loading of a user’s design into the external CPLD boot
EEPROM. For Self-Boot Delta39K packages, programming is
defined as the loading of a user’s design into the on-chip
FLASH internal to the Delta39K package. Configuration is
defined as the loading of a user’s design into the Delta39K die.
In-System Reprogramming (ISR)
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
Document #: 38-03039 Rev. *H
Page 14 of 86
Delta39K™ ISR™
CPLD Family
Delta39K devices to complete the desired reconfiguration or
diagnostic operations. Contact your local sales office for infor-
mation on the availability of this option.
Instruction Register
TDI
TDO
Programming
The on-chip FLASH device of the Delta39K Self-Boot package
is programmed by issuing the appropriate IEEE STD 1149.1
JTAG instruction to the internal FLASH memory via the JTAG
interface. This can be done automatically using ISR/STAPL
software. The configuration bits are sent from a PC through
the JTAG port into the Delta39K via the C3ISR programming
cable. The data is then internally passed from Delta39K to the
on-chip FLASH. For more information on how to program the
Delta39K through ISR/STAPL, please refer to the ISR/STAPL
User Guide.
Bypass Reg.
Boundary Scan
idcode
JTAG
TAP
CONTROLLER
TMS
TCLK
Usercode
ISR Prog.
The external CPLD boot EEPROM used to store configuration
data for the Delta39K volatile package is programmed through
Cypress’s CYDH2200E CPLD Boot PROM Programming Kit
via a two-wire interface. For more information on how to
program the CPLD boot EEPROM, please refer to the data
sheet titled “CYDH2200E CPLD Boot PROM Programming
Kit.” For more information on the architecture and timing speci-
fication of the boot EEPROM, refer to the data sheet titled
“512K/1Mb CPLD Boot EEPROM” or “2-Mbit CPLD Boot
EEPROM.”
Data Registers
Figure 11. JTAG Interface
Configuration can begin in two ways. It can be initiated by
toggling the Reconfig pin from LOW to HIGH, or by issuing the
appropriate IEEE STD 1149.1 JTAG instruction to the
Delta39K device via the JTAG interface. There are two IEEE
STD 1149.1 JTAG instructions that initiate configuration of the
Delta39K. The Self Config instruction causes the Delta39K to
(re)configure with data stored in the serial boot PROM or the
embedded FLASH memory. The Load Config instruction
causes the Delta39K to (re)configure according to data
provided by other sources such as a PC, automatic test
equipment (ATE), or an embedded micro-controller/processor
via the JTAG interface. For more information on configuring
Delta39K devices, refer to the application note titled “Config-
uring Delta39K/Quantum38K” at http://www.cypress.com.
Third-Party Programmers
Cypress support is available on a wide variety of third-party
programmers. All major programmers (including BP Micro,
System General, Hi-Lo) support the Delta39K family.
Development Software Support
Warp
Warp is a state-of-the-art design environment for designing
with Cypress programmable logic. Warp utilizes a subset of
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware
Description Language (HDL) for design entry. Warp accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Delta39K device. For simulation, Warp provides a graphical
waveform simulator as well as VHDL and Verilog Timing
Models.
There are two configuration options available for issuing the
IEEE STD 1149.1 JTAG instructions to the Delta39K. The first
method is to use a PC with the C3ISR programming cable and
software. With this method, the ISR pins of the Delta39K
devices in the system are routed to a connector at the edge of
the printed circuit board. The C3ISR programming cable is
then connected between the PC and this connector. A simple
configuration file instructs the ISR software of the
programming operations to be performed on the Delta39K
devices in the system. The ISR software then automatically
completes all of the necessary data manipulations required to
accomplish configuration, reading, verifying, and other ISR
functions. For more information on the Cypress ISR interface,
see the ISR Programming Kit data sheet (CY3900i).
VHDL and Verilog are open, powerful, non-proprietary
Hardware Description Languages (HDLs) that are standards
for behavioral design entry and simulation. HDL allows
designers to learn a single language that is useful for all facets
of the design process.
The second configuration option for the Delta39K is to utilize
the embedded controller or processor that already exists in the
system. The Delta39K ISR software assists in this method by
converting the device HEX file into the ISR serial stream that
contains the ISR instruction information and the addresses
and data of locations to be configured. The embedded
controller then simply directs this ISR stream to the chain of
Third-Party Software
Cypress products are supported in a number of third-party
design entry and simulation tools. Refer to the third-party
software data sheet or contact your local sales office for a list
of currently supported third party vendors.
Document #: 38-03039 Rev. *H
Page 15 of 86
Delta39K™ ISR™
CPLD Family
Junction Temperature...................................................135°C
Maximum Ratings
V
V
CC to Ground Potential...................................–0.5V to 4.6V
CCIO to Ground Potential................................–0.5V to 4.6V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
(39K200, 208 EQFP) .................................–45°C to +125°C
Storage Temperature
(all other densities and packages) ..............–65°C to +150°C
Soldering Temperature................................................. 220°C
Ambient Temperature with
Power Applied...............................................–40°C to +85°C
DC Voltage Applied to Outputs
in High-Z state..................................................–0.5V to 4.5V
DC Input voltage...............................................–0.5V to 4.5V
DC Current into Outputs........................................ ± 20 mA[6]
Static Discharge Voltage
(per JEDEC EIA./JESD22–A114A)............................ >2001V
Latch-up Current ..................................................... >200 mA
Operating Range
Ambient
Temperature
Junction
Temperature
Output
Condition
VCCJTAG
/
Range
VCCIO
VCC
VCCCNFG VCCPLL VCCPRG
Commercial
0°C to +70°C
0°C to +85°C
3.3V
2.5V
1.8V
1.5V
3.3V
2.5V
1.8V
1.5V
3.3V ± 0.3V 3.3V±0.3Vor Same as Sameas 3.3V ±
2.5V ± 0.2V
(39KV)
VCCIO
VCC
0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V[5]
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V[5]
Industrial
–40°C to +85°C –40°C to +100°C
DC Characteristics
VCCIO = 3.3V VCCIO = 2.5V
VCCIO = 1.8V
Test
Conditions
Parameter
Description
Min. Max. Min. Max. Min.
Max.
Unit
VDRINT
Data Retention VCC Voltage
(config data may be lost below this)
1.5
1.5
1.5
V
VDRIO
Data Retention VCCIO Voltage
(config data may be lost below this)
1.2
1.2
1.2
V
[7]
IIX
Input Leakage Current
Output Leakage Current
GND ≤ VI ≤ 3.6V
–10
–10
10
10
–10
–10
10
10
–10
–10
10
10
µA
µA
IOZ
GND ≤ VO ≤
VCCIO
[8]
IOS
Output Short Circuit Current
VCCIO = Max.
VOUT = 0.5V
–160
–160
–160
µA
µA
µA
IBHL
IBHH
Input Bus Hold LOW Sustaining Current VCC = Min.
VPIN = VIL
+40
–40
+30
–30
+25
–25
Input Bus Hold HIGH Sustaining Current VCC = Min.
VPIN = VIH
IBHLO
IBHHO
ICC0
Input Bus Hold LOW Overdrive Current VCC = Max.
Input Bus Hold HIGH Overdrive Current VCC = Max.
+250
–250
All bins
20
20
30
60
60
+200
–200
All bins
20
20
30
60
60
+150
µA
µA
µA
–150
–125 bin –83 bin
Standby Current
39K30
3
3
5
12
12
20
40
40
39K50
39K100
39K165
39K200
10
10
Note:
6. DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and VTT = 1.5).
7. Input Leakage current is ±10µA for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec
for these pins in ±200µA
Delta39K100
Package
388-BGA
484-FBGA
676-FBGA
Pins
B4, C2
B8, G9
F11, J11
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03039 Rev. *H
Page 16 of 86
Delta39K™ ISR™
CPLD Family
Capacitance
Parameter
Description
Test Conditions
Vin = VCCIO @ f = 1 MHz 25°C
Vin = VCCIO @ f = 1 MHz 25°C
Vin = VCCIO @ f = 1 MHz 25°C
Min.
Max.
10
Unit
pF
CI/O
Input/Output Capacitance
Clock Signal Capacitance
PCI-compliant[9] Capacitance
CCLK
CPCI
5
12
pF
8
pF
DC Characteristics (I/O)[10]
VOH (V)
VOH (min.)
VOL (V)
VOL
VIH (V)
VIL (V)
VREF VCCIO
I/O Standards (V)
LVTTL –2 mA N/A
LVTTL –4 mA
LVTTL –6 mA
LVTTL –8 mA
LVTTL –12 mA
LVTTL –16 mA
LVTTL –24 mA
LVCMOS
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.0
2.5
@ IOH
=
@ IOL
2 mA
4 mA
6 mA
8 mA
=
(max.)
Min.
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
1.7V
Max.
Min.
Max.
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.7V
–2 mA
–4 mA
2.4
2.4
2.4
2.4
2.4
2.4
2.4
0.4
VCCIO + 0.3 –0.3V
CCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
CCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
CCIO + 0.3 –0.3V
0.4
V
–6 mA
0.4
–8 mA
0.4
V
–12 mA
–16 mA
–24 mA
–0.1 mA
12 mA
16 mA
24 mA
0.4
0.4
V
0.4
VCCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
VCCIO + 0.3 –0.3V
V
CCIO – 0.2V 0.1 mA
0.2
LVCMOS3
–0.1 mA VCCIO – 0.2V 0.1 mA
0.2
–0.1 mA
–1.0 mA
–2.0 mA
2.1
2.0
1.7
0.1 mA
1.0 mA
2.0 mA
0.2
VCCIO + 0.3 –0.3V
LVCMOS2
0.4
0.7
LVCMOS18
3.3V PCI
1.8
–2 mA VCCIO – 0.45V 2.0 mA
0.45
0.65VCCIO VCCIO + 0.3 –0.3V 0.35VCCIO
3.3
[11]
–0.5 mA
0.9VCCIO
1.5 mA 0.1VCCIO 0.5VCCIO VCCIO + 0.5 –0.5V 0.3VCCIO
36 mA[12]
GTL+
1.0
1.5
0.6
0.7
VREF + 0.2
VREF – 0.2
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
3.3
3.3
2.5
–8 mA
V
CCIO – 1.1V
8 mA
VREF + 0.2 VCCIO + 0.3 –0.3V VREF – 0.2
VREF + 0.2 VCCIO + 0.3 –0.3V VREF – 0.2
VREF + 0.18 VCCIO + 0.3 –0.3V VREF – 0.18
VREF + 0.18 VCCIO + 0.3 –0.3V VREF – 0.18
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
VREF + 0.1 VCCIO + 0.3 –0.3V VREF – 0.1
1.5
–16 mA VCCIO – 0.9V 16 mA
–7.6 mA CCIO – 0.62V 7.6 mA
0.5
1.25
1.25
0.75
0.75
0.9
V
0.54
0.35
0.4
2.5 –15.2 mA VCCIO – 0.43V 15.2 mA
1.5
1.5
1.5
1.5
–8 mA
VCCIO – 0.4V
8 mA
HSTL II
HSTL III
HSTL IV
–16 mA VCCIO – 0.4V 16 mA
0.4
–8 mA
–8 mA
V
CCIO – 0.4V 24 mA
0.4
0.9
VCCIO – 0.4V 48 mA
0.4
Configuration Parameters
Parameter
tRECONFIG
Description
Min.
Unit
Reconfig pin LOW time before it goes HIGH
200
ns
• VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG
• All VCCIOs on a bank should be tied to the same potential
and powered up together.
• All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
• Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
Power-up Sequence Requirements
• Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
• The part will not start configuration until VCC, VCCIO
VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached
nominal voltage.
.
,
Notes:
9. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer
to the application note titled “Delta39K and Quantum38K I/O Standards and Configurations” for details.
•
•
The source current limit per I/O bank per Vccio pin is 165 mA.
The sink current limit per I/O bank per GND pin is 230 mA.
11. See “Power-up Sequence Requirements” below for VCCIO requirement.
12. 25W resistor terminated to termination voltage of 1.5V.
Document #: 38-03039 Rev. *H
Page 17 of 86
Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Descriptions Over the Operating Range[13]
Parameter
Description
Combinatorial Mode Parameters
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the
horizontal or vertical channel associated with that cluster
tPD
tEA
tER
Global control to output enable
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel
associated with the cluster the macrocell is in
tPRR
tPRO
tPRW
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated
with the cluster that the macrocell is in to any pin output on those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest
cluster on the horizontal or vertical channel the pin is associated with
Synchronous Clocking Parameters
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
tMCS
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a
global clock
tMCH
tMCCO
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the
cluster that macrocell is in
tIOS
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Clock to output of an I/O cell register to the output pin associated with that register
tIOH
tIOCO
tSCS
tSCS2
tICS
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the
macrocell is in
tOCS
tCHZ
tCLZ
fMAX
Clock to output disable (high-impedance)
Clock to output enable (low-impedance)
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal or vertical
channel
fMAX2
Product Term Clock
tMCSPT
tMCHPT
tMCCOPT
tSCS2PT
Set-up time for macrocell used as input register, from input to product term clock
Hold time of macrocell used as an input register
Product term clock to output delay from input pin
Register to register delay through array logic in different clusters on the same channel using a product term clock
Channel Interconnect Parameters
tCHSW Adder for a signal to switch from a horizontal to vertical channel and vice-versa
tCL2CL Cluster-to-cluster delay adder (through channels and channel PIM)
Miscellaneous Delays
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter
can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array required by a given
signal path
tCPLD
tMCCD
tIOD
Adder for carry chain logic per macrocell
Delay from the input of the output buffer to the I/O pin
Delay from the I/O pin to the input of the channel buffer
tIOIN
Note:
13. Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa.
Document #: 38-03039 Rev. *H
Page 18 of 86
Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Descriptions Over the Operating Range[13] (continued)
Parameter
Description
Delay from the clock pin to the input of the clock driver
tCKIN
tIOREGPIN Delay from the I/O pin to the input of the I/O register
PLL Parameters
tMCCJ
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
tDWSA
tDWOSA
tLOCK
tINDUTY
fPLLI
Input duty cycle
Input frequency of the PLL
fPLLO
Output frequency of the PLL
fPLLVCO
PSAPLLI
fMPLLI
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the fPLLI sweeps between fPLLI
(1–PSAPLLI/100) and fPLLI* (1+ PSAPLLI/100)
*
JTAG Parameters
tJCKH
tJCKL
tJCP
tJSU
tJH
TCLK HIGH time
TCLK LOW time
TCLK clock period
JTAG port set-up time (TDI/TMS inputs)
JTAG port hold time (TDI/TMS inputs)
JTAG port clock to output time (TDO)
JTAG port valid output to high impedance (TDO)
JTAG port high impedance to valid output (TDO)
tJCO
tJXZ
tJZX
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
tCLMPWE
tCLMSA
tCLMHA
tCLMSD
tCLMHD
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Synchronous Mode Parameters
tCLMCYC1
ClockcycletimeforflowthroughReadandWriteoperations (frommacrocellregister throughclustermemory
back to a macrocell register in the same cluster)
tCLMCYC2
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
tCLMH
tCLMDV1
tCLMDV2
tCLMMACS1
tCLMMACS2
tMACCLMS1
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
Document #: 38-03039 Rev. *H
Page 19 of 86
Delta39K™ ISR™
CPLD Family
Cluster Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
tMACCLMS2
Internal Parameters
tCLMCLAA Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Description
Macrocell clock to cluster memory output clock in the same cluster
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
tCHMAA
tCHMPWE
tCHMSA
tCHMHA
tCHMSD
tCHMHD
tCHMBA
Channel memory access time. Delay from address change to Read data out
Write enable pulse width
Address set-up to the beginning of Write enable with both signals from the same I/O block
Address hold after the end of Write enable with both signals from the same I/O block
Data set-up to the end of Write enable
Data hold after the end of Write enable
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
Clock cycle time for flow through Read and Write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
tCHMCYC1
tCHMCYC2
Clock cycle time for pipelined Read and Write operations (from channel memory input register through the
memory to channel memory output register)
tCHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
tCHMH
tCHMDV1
tCHMDV2
tCHMBDV
tCHMMACS1
tCHMMACS2
tMACCHMS1
tMACCHMS2
Global clock to data valid on output pins for pipelined data.
Channel memory synchronous dual-port address match (busy, clock to data valid)
Channel memory input clock to macrocell clock in the same cluster
Channel memory output clock to macrocell clock in the same cluster
Macrocell clock to channel memory input clock in the same cluster
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
tCHMCLK Read and Write minimum clock cycle time
tCHMFS
Data, Read enable, and Write enable set-up time relative to pin inputs
Data, Read enable, and Write enable hold time relative to pin inputs
Data access time to output pins from rising edge of Read clock (Read clock to data valid)
Channel memory FIFO Read clock to macrocell clock for Read data
Macrocell clock to channel memory FIFO Write clock for Write data
tCHMFH
tCHMFRDV
tCHMMACS
tMACCHMS
Synchronous FIFO Flag Parameters
tCHMFO
Read or Write clock to respective flag output at output pins
tCHMMACF
tCHMFRS
Read or Write clock to macrocell clock with FIFO flag
Master Reset Pulse Width
tCHMFRSR
tCHMFRSF
tCHMSKEW1
tCHMSKEW2
tCHMSKEW3
Master Reset Recovery Time
Master Reset to Flag and Data Output Time
Read/Write Clock Skew Time for Full Flag
Read/Write Clock Skew Time for Empty Flag
Read/Write Clock Skew Time for Boundary Flags
Document #: 38-03039 Rev. *H
Page 20 of 86
Delta39K™ ISR™
CPLD Family
Channel Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
Description
Internal Parameters
tCHMCHAA
Asynchronous channel memory access time from input of channel memory to output of channel memory
Switching Characteristics — Parameter Values Over the Operating Range
125
83
233
200
181
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Combinatorial Mode Parameters
tPD
7.2
4.5
4.5
7.5
5.0
5.0
8.5
5.6
5.3
10
9.0
9.0
15
10
10
ns
ns
ns
ns
ns
ns
tEA
tER
tPRR
tPRO
tPRW
6.0
9.5
3.3
6.0
10
6.0
10.5
4.0
8.0
13
10
15
3.6
6.0
7.0
Synchronous Clocking Parameters
tMCS
tMCH
tMCCO
tIOS
2.7
0
3.0
0
3.5
0
5.0
0
6.7
0
ns
ns
5.8
3.8
6.0
4.0
7.0
4.5
10
12
ns
1.0
0.9
1.0
1.0
1.2
1.2
2.0
2.0
2.5
2.5
ns
tIOH
ns
tIOCO
tSCS
tSCS2
tICS
7.0
8.0
ns
3.4
4.3
4.5
4.5
3.5
4.5
5.0
5.0
3.6
5.5
5.5
5.5
6.4
8.0
8.0
8.0
9.6
12
12
12
ns
ns
ns
tOCS
tCHZ
tCLZ
ns
3.5
3.5
3.8
6.0
7.0
ns
1.5
1.5
1.5
1.5
1.5
ns
fMAX
fMAX2
294
233
286
222
278
181
156
125
104
83
MHz
MHz
Product Term Clocking Parameters
tMCSPT
tMCHPT
tMCCOPT
tSCS2PT
2.7
0.9
3.0
1.0
3.3
1.4
5.0
2.0
6.0
2.5
ns
ns
ns
ns
7.5
8.0
8.8
11.0
15.0
6.0
6.5
7.2
10.0
15.0
Channel Interconnect Parameters
tCHSW
0.9
1.8
1.0
2.0
1.2
2.3
1.7
2.8
2.0
3.0
ns
ns
tCL2CL
Miscellaneous Parameters
tCPLD
2.8
3.0
3.3
4.0
5.0
ns
ns
tMCCD
0.22
0.25
0.28
0.35
0.38
PLL Parameters
tMCCJ
tDWSA
tDWOSA
tLOCK
–150
–1.35
–150
150
–0.85
150
–150
–1.35
–150
150
–150
–1.35
–150
150
–180
–2.0
–180
180
–1.5
180
250
–200
–2.9
–200
200
–2.4
200
250
ps
ns
ps
–0.85
150
–0.85
150
250
250
250
ms
Document #: 38-03039 Rev. *H
Page 21 of 86
Delta39K™ ISR™
CPLD Family
Switching Characteristics — Parameter Values Over the Operating Range (continued)
125
83
233
200
181
Parameter
tINDUTY
Min.
40
Max.
60
Min.
40
Max.
60
Min.
40
Max.
60
Min.
40
Max.
60
Min.
40
Max.
60
Unit
%
[14]
fPLLO
6.2
266
133
266
+0.3
50
6.2
266
133
266
+0.3
50
6.2
266
133
266
+0.3
50
6.2
200
100
266
+0.3
50
6.2
200
100
266
+0.3
50
MHz
MHz
MHz
%
[14]
fPLLI
12.5
100
–0.3
12.5
100
–0.3
12.5
100
–0.3
12.5
100
–0.3
12.5
100
–0.3
fPLLVCO
PSAPLLI
fMPLLI
KHz
JTAG Parameters
tJCKH
tJCKL
tJCP
tJSU
tJH
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
ns
ns
ns
ns
ns
ns
ns
ns
tJCO
tJXZ
tJZX
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).[15] Apply following adjustments if the inputs and outputs
are configured to operate at other standards.
Output Delay Adjustments
Slow Slew Rate
Fast Slew Rate
(additional delay to fast slew rate)
tIODSLOW tEASLOW tERSLOW tIOIN
2.6
Input Delay Adjustments
tCKIN tIOREGPIN
0
I/O Standard
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
LVCMOS
tIOD
2.75
tEA tER
0
0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0
0
0
0
1.8
1.8
0
0
0
2.5
0
0
2.5
0
0
0
1.2
0
0
2.4
0
0
0
0.6
0
0
2.3
0
0
0
0.16
0
0
0
2.0
0
0
0
0
0
0
1.6
0
0
0
0
0
2.0
0
0
0
LVCMOS3
0.14
0.41
1.6
0.05
0.1
0.7
0
0
2.0
0.1
0.2
0.5
0
0.1
0.2
0.4
0
0.2
0.4
0.3
0
LVCMOS2
0
2.0
LVCMOS18
3.3V PCI
0.1
2.1
–0.14
0
2.0
GTL+
0.02[16] 0.6[16]
0.9[16]
0.1
0
2.0
0.5
0.5
0.5
0.4
0.3
0.3
0.2
0.3
0.3
SSTL3 I
–0.15
–0.4
0.3
0.2
2.0
SSTL3 II
2.0
Notes:
14. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
Document #: 38-03039 Rev. *H
Page 22 of 86
Delta39K™ ISR™
CPLD Family
Output Delay Adjustments
Slow Slew Rate
Fast Slew Rate
tEA tER
0.4
(additional delay to fast slew rate)
tIODSLOW
2.0
Input Delay Adjustments
I/O Standard
SSTL2 I
SSTL2 II
HSTL I
tIOD
tEASLOW tERSLOW tIOIN
tCKIN
0.5
0.5
0.5
0.5
0.5
0.5
tIOREGPIN
0.6
–0.02
–0.22
0.94
0.79
0.77
0.44
0
0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
0.9
0.9
0.5
0.5
0.5
0.5
0.2
0.9
0.8
0.5
0.6
2.0
0.6
0.5
0.5
0.1
0
2.0
0.3
HSTL II
2.0
0.3
HSTL III
HSTL IV
2.0
0.3
2.0
0.3
Cluster Memory Timing Parameter Values Over the Operating Range
233 200 181
Max.
Asynchronous Mode Parameters
83
125
Parameter
Min.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tCLMAA
tCLMPWE
tCLMSA
tCLMHA
tCLMSD
tCLMHD
10.2
11
12
17
20
ns
ns
ns
ns
ns
ns
5.5
1.8
0.9
5.5
0.4
6
6.5
2.2
1.1
6.5
0.6
10
3.2
1.8
10
12
4.0
2.0
12
2.0
1.0
6.0
0.5
0.9
1.0
Synchronous Mode Parameters
tCLMCYC1
tCLMCYC2
tCLMS
9.5
5.0
2.8
0
10
5.0
3.0
0
10.5
5.5
3.8
0
15
8.0
4.0
0
20
10.0
5.0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLMH
tCLMDV1
10
11
12
17
10
20
15
tCLMDV2
7.0
7.5
8.0
tCLMMACS1
tCLMMACS2
tMACCLMS1
tMACCLMS2
7.7
4.5
3.6
6.0
8.0
5.0
4.0
6.5
8.5
5.5
4.4
7.0
12
8.0
6.6
10
15
10
8.0
12
Internal Parameters
tCLMCLAA
6
6
6.5
10
12
ns
Channel Memory Timing Parameter Values Over the Operating Range
233 200 181
83
125
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Dual-Port Asynchronous Mode Parameters
tCHMAA
tCHMPWE
tCHMSA
tCHMHA
tCHMSD
tCHMHD
tCHMBA
10
11
12
17
20
ns
ns
ns
ns
ns
ns
ns
5.5
1.8
0.9
5.5
0.4
6.0
2.0
1.0
6.0
0.5
6.5
2.2
1.1
6.5
0.6
10
3.2
1.8
10
12
4.0
2.0
12
0.9
1.0
8.5
9.0
10.0
14.0
16.0
Document #: 38-03039 Rev. *H
Page 23 of 86
Delta39K™ ISR™
CPLD Family
Channel Memory Timing Parameter Values Over the Operating Range (continued)
Dual-Port Synchronous Mode Parameters
tCHMCYC1
tCHMCYC2
tCHMS
9.5
5.0
3.0
0
10
5.3
3.3
0
10
5.4
3.9
0
15
7.4
5.0
0
20
10.6
6.0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCHMH
tCHMDV1
10
7.0
8.5
11
7.5
9.0
12
8.0
17
10
20
15
tCHMDV2
tCHMBDV
tCHMMACS1
tCHMMACS2
tMACCHMS1
tMACCHMS2
10.0
14.0
16.0
8.5
4.8
4.6
7.3
9.0
5.0
5.0
7.3
10.0
5.5
5.4
7.7
14.0
8.0
16.0
10
7.6
9.0
10.0
13.0
Synchronous FIFO Data Parameters
tCHMCLK
tCHMFS
4.8
3.7
0
5.0
4.0
0
5.4
4.3
0
7.4
6.0
0
10.6
7.0
0
ns
ns
ns
tCHMFH
tCHMFRDV
tCHMMACS
tMACCHMS
6.5
7.0
11
7.5
10.0
15
13.0
20
4.6
4.7
5.0
5.0
5.4
5.4
7.4
7.4
10.6
10.6
ns
ns
Synchronous FIFO Flag Parameters
tCHMFO
10.5
11.5
ns
ns
ns
ns
ns
ns
ns
ns
tCHMMACF
8.5
4.5
9
9.5
5.5
13
17
10
tCHMFRS
5.0
8.0
tCHMFRSR
3.6
9.5
1.8
1.8
4.6
4.0
10.0
2.0
4.4
11.0
2.2
6.6
15.0
3.2
8.0
18.0
4.0
tCHMFRSF
tCHMSKEW1
tCHMSKEW2
tCHMSKEW3
Internal Parameters
tCHMCHAA
2.0
2.2
3.2
4.0
5.0
5.4
7.4
10.6
6.5
7.0
7.5
10.0
13.0
ns
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Document #: 38-03039 Rev. *H
Page 24 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Registered Output with Synchronous Clocking (Macrocell)
INPUT
tMCS
tMCH
SYNCHRONOUS
CLOCK
REGISTERED
OUTPUT
tMCCO
Registered Input in I/O Cell
DATA
INPUT
tIOH
tIOS
INPUT REGISTER
CLOCK
tIOCO
REGISTERED
OUTPUT
Clock to Clock
INPUT REGISTER
CLOCK
tICS
tSCS
MACROCELL
REGISTER CLOCK
PT Clock to PT Clock
DATA
INPUT
tMCSPT
tSCS2PT
PT CLOCK
Document #: 38-03039 Rev. *H
Page 25 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Asynchronous Reset/Preset
tPRW
RESET/PRESET
INPUT
tPRO
REGISTERED
OUTPUT
tPRR
CLOCK
Output Enable/Disable
GLOBAL CONTROL
INPUT
tER
tEA
OUTPUTS
Document #: 38-03039 Rev. *H
Page 26 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Cluster Memory Asynchronous Timing
WRITE
READ
READ
ADDRESS (AT
THE CLUSTER
INPUT)
WRITE ENABLE
tCLMPWE
INPUT
tCLMCLAA
tCLMCLAA
OUTPUT
Cluster Memory Asynchronous Timing 2
WRITE
READ
READ
ADDRESS (AT THE
I/O PIN)
tCLMHA
tCLMSA
WRITE ENABLE
tCLMPWE
INPUT
tCLMHD
tCLMSD
tCLMAA
tCLMAA
OUTPUT
Document #: 38-03039 Rev. *H
Page 27 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Cluster Memory Synchronous Flow-Through Timing
READ
WRITE
READ
GLOBAL
CLOCK
tCLMCYC1
tCLMS
tCLMH
ADDRESS
tCLMS
tCLMH
tCLMS
tCLMH
WRITE
ENABLE
REGISTERED
INPUT
tCLMDV1
tCLMDV1
tCLMDV1
REGISTERED
OUTPUT
Cluster Memory Internal Clocking
MACROCELL
INPUT CLOCK
tMACCLMS1
tCLMMACS1
CLUSTER MEMORY
INPUT CLOCK
tCLMMACS2
tMACCLMS2
CLUSTER MEMORY
OUTPUT CLOCK
Document #: 38-03039 Rev. *H
Page 28 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Cluster Memory Output Register Timing (Asynchronous Inputs)
ADDRESS
WRITE
ENABLE
INPUT
tCLMCYC2
GLOBAL CLOCK
(OUTPUT REGISTER)
tCLMDV2
REGISTERED
OUTPUT
Cluster Memory Output Register Timing (Synchronous Inputs)
ADDRESS
WRITE
ENABLE
INPUT
tCLMCYC2
GLOBAL CLOCK
(INPUT REGISTER)
tCLMS
tCLMH
GLOBAL CLOCK
(OUTPUT REGISTER)
tCLMDV2
REGISTERED
OUTPUT
Document #: 38-03039 Rev. *H
Page 29 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory DP Asynchronous Timing
An+1
An+2
ADDRESS
An-1
An
tCHMHA
tCHMSA
tCHMPWE
WRITE
ENABLE
tCHMSD
tCHMHD
DATA
INPUT
Dn
tCHMAA
tCHMAA
Dn–1
OUTPUT
Dn+1
Dn
Channel Memory Internal Clocking
MACROCELL INPUT
CLOCK
tMACCHMS1
tCHMMACS1
CHANNEL MEMORY
INPUT CLOCK
tCHMMACS2
tMACCHMS2
CHANNEL MEMORY
OUTPUT CLOCK
Document #: 38-03039 Rev. *H
Page 30 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Internal Clocking 2
MACROCELL INPUT
CLOCK
tCHMMACS
FIFO READ
CLOCK
tMACCHMS
FIFO WRITE
CLOCK
tCHMMACF
FIFO READ OR
WRITE CLOCK
Channel Memory DP SRAM Flow-Through R/W Timing
CLOCK
tCHMCYC1
tCHMS
tCHMH
An+3
An+2
An–1
An
An+1
ADDRESS
WRITE
ENABLE
tCHMS
tCHMH
DATA
INPUT
Dn–1
Dn+1
Dn+3
tCHMDV1
tCHMDV1
tCHMDV1
tCHMDV1
Dn+1
Dn–1
Dn
Dn+2
Dn+3
OUTPUT
Document #: 38-03039 Rev. *H
Page 31 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory DP SRAM Pipeline R/W Timing
CLOCK
tCHMCYC2
tCHMS
tCHMH
An–1
An
An+2
An+1
An+3
ADDRESS
tCHMH
tCHMS
WRITE
ENABLE
tCHMH
tCHMS
DATA
INPUT
Dn+3
Dn–1
Dn+1
tCHMDV2
tCHMDV2
tCHMDV2
Dn–1
Dn
Dn+1
OUTPUT
Dn+2
Dual-Port Asynchronous Address Match Busy Signal
Bn
An
ADDRESS A
An–1
An
An+1
ADDRESS B
tCHMBA
tCHMBA
ADDRESS
MATCH
Document #: 38-03039 Rev. *H
Page 32 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Dual-Port Synchronous Address Match Busy Signal
CLOCK
An–1
An
ADDRESS A
ADDRESS B
An
Bn–1
Bn+1
tCHMS
tCHMS
ADDRESS
MATCH
tCHMBDV
tCHMBDV
Document #: 38-03039 Rev. *H
Page 33 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Empty/Write Timing
PORT B CLOCK
tCHMCLK
tCHMFS
tCHMFH
WRITE ENABLE
REGISTERED
INPUT
Dn+1
EMPTY FLAG
(Active LOW)
tCHMSKEW2
tCHMFO
tCHMFO
PORT A CLOCK
READ ENABLE
RE
tCHMFRDV
REGISTERED
OUTPUT
Document #: 38-03039 Rev. *H
Page 34 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Full/Read Timing
PORT A CLOCK
tCHMCLK
tCHMFS
tCHMFH
READ ENABLE
tCHMFRDV
REGISTERED
OUTPUT
FULL FLAG
(Active LOW)
tCHMFO
tCHMSKEW1 tCHMFO
PORT B CLOCK
WRITE ENABLE
tCHMS
tCHMH
REGISTERED
INPUT
Document #: 38-03039 Rev. *H
Page 35 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT B CLOCK
tCHMCLK
tCHMFH
tCHMFS
WRITE ENABLE
PROGRAMMABLE
ALMOST EMPTY FLAG
(active LOW)
tCHMSKEW3
tCHMFO
tCHMFO
PORT A CLOCK
READ ENABLE
tCHMFH
tCHMFS
PORT B CLOCK
tCHMCLK
WRITE ENABLE
tCHMFO
tCHMFO
PROGRAMMABLE
ALMOST FULL FLAG
(Active LOW)
tCHMSKEW3
PORT A CLOCK
READ ENABLE
Document #: 38-03039 Rev. *H
Page 36 of 86
Delta39K™ ISR™
CPLD Family
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Master Reset Timing
tCHMFRS
MASTER
RESET INPUT
tCHMFRSR
READ ENABLE /
WRITE ENABLE
tCHMFRSF
EMPTY/FULL
PROGRAMMABLE
ALMOST EMPTY
FLAGS
tCHMFRSF
HALF-FULL/
PROGRAMMABLE
ALMOST FULL
FLAGS
tCHMFRSF
REGISTERED
OUTPUT
C Y 3 9 1 0 0 V 6 7 6 - 2 0 0 M B C
Cypress Semiconductor ID
Family Type
39 = Delta39K Family
Operating Conditions
Commercial
Industrial
0°C to +70°C
--40°C to +85°C
Gate Density
30=30k Usable Gates
50=50k Usable Gates
100=100k Usable Gates
165 = 165k Usable Gates
200 = 200k Usable Gates
Package Type
N
= Plastic Quad Flat Pack (PQFP)
NT = Thermally Enhanced Quad Flat Pack (EQFP)
BG = Ball Grid Array (BGA)
BB = Fine-pitch Ball Grid Array (FBGA)
1.0-mm Lead Pitch
MG = Self-Boot Solution -- Ball Grid Array
MB = Self-Boot Solution -- Fine Pitch Ball Grid Array
1.0-mm Lead Pitch
Operating Reference Voltage
V = 3.3V or 2.5V Supply Voltage
Z = 1.8V
Supply Voltage
Pin Count
208 = 208 Leads
256 = 256 Balls
388 = 388 Balls
484 = 484 Balls
676 = 676 Balls
Speed
233 = 233 MHz
200 = 200 MHz
181 = 181 MHz
125 = 125 MHz
83 = 83 MHz
Document #: 38-03039 Rev. *H
Page 37 of 86
Delta39K™ ISR™
CPLD Family
Delta39K Part Numbers (Ordering Information)
Speed
(MHz)
Package
Name
Self-Boot Operating
Device
Ordering Code
CY39030V208-233NTC
CY39030V256-233BBC
CY39030V256-233MBC
CY39030V208-125NTC
CY39030V256-125BBC
CY39030V256-125MBC
CY39030V208-125NTI
CY39030V256-125BBI
CY39030V208-83NTC
CY39030V256-83BBC
CY39030V256-83MBC
CY39030V208-83NTI
CY39030V256-83BBI
CY39050V208-233NTC
CY39050V256-233BBC
CY39050V388-233MGC
CY39050V484-233MBC
CY39050V208-125NTC
CY39050V256-125BBC
CY39050V388-125MGC
CY39050V484-125MBC
CY39050V208-125NTI
CY39050V256-125BBI
CY39050V208-83NTC
CY39050V256-83BBC
CY39050V388-83MGC
CY39050V484-83MBC
CY39050V208-83NTI
CY39050V256-83BBI
CY39100V208B-200NTC
CY39100V256B-200BBC
CY39100V484B-200BBC
CY39100V388B-200MGC
CY39100V676B-200MBC
Package Type
Solution
Range
39K30
233
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Plastic Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Commercial
÷
÷
125
Industrial
83
Commercial
÷
Industrial
39K50
39K50
39K100
233
125
Commercial
÷
÷
MB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
÷
÷
125
83
Industrial
Commercial
÷
÷
MB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Plastic Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Industrial
200
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
Document #: 38-03039 Rev. *H
Page 38 of 86
Delta39K™ ISR™
CPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Speed
(MHz)
Package
Name
Self-Boot Operating
Device
Ordering Code
Package Type
Solution
Range
39K100
125
CY39100V208B-125NTC
CY39100V256B-125BBC
CY39100V484B-125BBC
CY39100V388B-125MGC
CY39100V676B-125MBC
CY39100V208B-125NTI
CY39100V256B-125BBI
CY39100V484B-125BBI
CY39100V208B-83NTC
CY39100V256B-83BBC
CY39100V484B-83BBC
CY39100V388B-83MGC
CY39100V676B-83MBC
CY39100V208B-83NTI
CY39100V256B-83BBI
CY39100V484B-83BBI
CY39165V208-181NTC
CY39165V484-181BBC
CY39165V388-181MGC
CY39165V676-181MBC
CY39165V208-125NTC
CY39165V484-125BBC
CY39165V388-125MGC
CY39165V676-125MBC
CY39165V208-125NTI
CY39165V484-125BBI
CY39165V208-83NTC
CY39165V484-83BBC
CY39165V388-83MGC
CY39165V676-83MBC
CY39165V208-83NTI
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
BB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Industrial
83
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB256 256-Lead Fine Pitch Ball Grid Array
BB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Industrial
39K165
181
125
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Industrial
83
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
Industrial
CY39165V484-83BBI
Document #: 38-03039 Rev. *H
Page 39 of 86
Delta39K™ ISR™
CPLD Family
Delta39K Part Numbers (Ordering Information) (continued)
Speed
(MHz)
Package
Name
Self-Boot Operating
Device
Ordering Code
CY39200V208-181NTC
CY39200V484-181BBC
CY39200V388-181MGC
CY39200V676-181MBC
CY39200V208-125NTC
CY39200V484-125BBC
CY39200V388-125MGC
CY39200V676-125MBC
CY39200V208-125NTI
CY39200V484-125BBI
CY39200V208-83NTC
CY39200V484-83BBC
CY39200V388-83MGC
CY39200V676-83MBC
CY39200V208-83NTI
CY39200V484-83BBI
Package Type
Solution
Range
39K200
181
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
125
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
Industrial
83
Commercial
÷
÷
MB676 676-Lead Fine Pitch Ball Grid Array
NT208 208-Lead Enhanced Quad Flat Pack
BB484 484-Lead Fine Pitch Ball Grid Array
Industrial
CPLD Boot EEPROM[17] Part Numbers (Ordering Information)
Speed
(MHz)
Package
Name
Operating
Range
Device
Ordering Code
AT17LV002-10JC
AT17LV002-10JC
AT17LV010-10JC
AT17LV010-10JI
AT17LV512-10JC
AT17LV512-10JI
Package Type
2 Mbit
15
10
15
10
15
10
20J
20J
20J
20J
20J
20J
20-Lead Plastic Leaded Chip Carrier Commercial
20-Lead Plastic Leaded Chip Carrier Industrial
20-Lead Plastic Leaded Chip Carrier Commercial
20-Lead Plastic Leaded Chip Carrier Industrial
20-Lead Plastic Leaded Chip Carrier Commercial
1 Mbit
512 Kbit
20-Lead Plastic Leaded Chip Carrier
Industrial
Recommended ATMEL CPLD Boot EEPROM for corresponding Delta39K CPLDs
CPLD Device
39K30
Recommended boot EEPROM
AT17LV512
39K50
AT17LV512
39K100
39K165
39K200
AT17LV010
AT17LV002
AT17LV002
Note:
17. Refer to the data sheets at www.atmel.com for detailed architectural and timing information.
Document #: 38-03039 Rev. *H
Page 40 of 86
Delta39K™ ISR™
CPLD Family
Package Diagrams
208-Lead Enhanced Quad Flat Pack (EQFP) NT208
51-85069-*B
Document #: 38-03039 Rev. *H
Page 41 of 86
Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
388-Lead Ball Grid Array MG388
51-85103-*C
Document #: 38-03039 Rev. *H
Page 42 of 86
Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
256-Ball FBGA (17 x 17 mm) BB256
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
PIN 1 CORNER
Ø0.45 0.05(256X)ꢀCPꢁD DEVICES (37K & 39K)
Ø0.50 0.05(256X)ꢀAꢁꢁ OTHER DEVICES
PIN 1 CORNER
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
A
B
C
D
E
F
F
G
H
J
G
H
J
K
ꢁ
K
ꢁ
M
N
P
R
T
M
N
P
R
T
1.00
B
7.50
15.00
A
17.00 0.10
A
SEATING PꢁANE
0.20(4X)
A1
C
REFERENCE JEDEC MOꢀ192
A1 0.36 0.56
1.40 MAX. 1.60 MAX.
A
51-85108-*D
Document #: 38-03039 Rev. *H
Page 43 of 86
Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
484-ball FBGA (23 mm x 23 mm x 1.6 mm) BB484
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
A1 CORNER
Ø0.25 M C A B
A1 CORNER
1
Ø0.60 0.10(4ꢀ4X)
21 19 17 15 13
11
11 13 15 17 19
9 10 12 14 16 1ꢀ
21
20 22
2
3
4
5
6
7
ꢀ
22 20 1ꢀ 16 14 12 10
9
ꢀ
7
6
5
4
3
2
1
A
B
A
B
C
C
D
E
D
E
F
F
G
H
J
G
H
J
K
K
L
L
M
N
P
M
N
P
R
R
T
T
U
V
U
V
W
Y
W
Y
AA
AB
AA
AB
1.00
A
10.50
21.00
B
23.00 0.10
0.10(4X)
SEATING PLANE
C
51-85124-*D
Document #: 38-03039 Rev. *H
Page 44 of 86
Delta39K™ ISR™
CPLD Family
Package Diagrams (continued)
676-Ball FBGA (27 x 27 x 1.6 mm) BB676/MB676
51-85125-*B
Pin Tables
Table 8. Pin Definition Table
Pin Name
GCLK0-3
GCTL0-3
GND
Function
Input
Description
Global Clock signals 0 through 3
Global Control signals 0 through 3
Ground
Input
Ground
IO/VREF0
IO/VREF1
IO/VREF2
IO/VREF3
IO/VREF4
IO/VREF5
IO/VREF6
IO/VREF7
IO
Input/Output Dual function pin: IO or Reference Voltage for Bank 0
Input/Output Dual function pin: IO or Reference Voltage for Bank 1
Input/Output Dual function pin: IO or Reference Voltage for Bank 2
Input/Output Dual function pin: IO or Reference Voltage for Bank 3
Input/Output Dual function pin: IO or Reference Voltage for Bank 4
Input/Output Dual function pin: IO or Reference Voltage for Bank 5
Input/Output Dual function pin: IO or Reference Voltage for Bank 6
Input/Output Dual function pin: IO or Reference Voltage for Bank 7
Input/Output Input or Output pin
IO6/Lock
MSEL
Input/Output Dual function pin: IO in Bank 6 or PLL lock output signal
Input
Mode Select Pin (see Table 9)
Document #: 38-03039 Rev. *H
Page 45 of 86
Delta39K™ ISR™
CPLD Family
Table 8. Pin Definition Table
Pin Name
Reconfig
TCLK
Function
Input
Description
Pin to start configuration of Delta39K
JTAG Test Clock
Input
TDI
Input
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Operating Voltage
VCC for I/O bank 0
VCC for I/O bank 1
VCC for I/O bank 2
VCC for I/O bank 3
VCC for I/O bank 4
VCC for I/O bank 5
VCC for I/O bank 6
VCC for I/O bank 7
VCC for JTAG pins
VCC for Configuration port
VCC for PLL
TDO
Output
Input
TMS
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Output
Output
Output
Input
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCJTAG
VCCCNFG
[18]
VCCPLL
VCCPRG
Config_Done
CCLK
VCC for programming the Self-Boot™ solution embedded boot PROM
Flag indicating that configuration is complete
Configuration Clock for serial interface with the external boot PROM
Chip select for the external boot PROM (active low)
CCE
Data
Pin to receive configuration data from the external boot PROM
Reset signal to interface with the external boot PROM
Reset
Output
Table 9. Mode Select (MSEL) Pin Connectivity Table
Table 10. I/O Banks for Global Clock and Global Control
Pins (in all densities and packages)
GND
Delta39K - Self-Boot™ Solution
GCLK[0]
GCTL[0]
GCLK[1]
GCTL[1]
GCLK[2]
GCTL[2]
GCLK[3]
GCTL[3]
VCCCNFG
Delta39K - with external boot PROM
Bank
0
5
6
7
Number
Table 11. 208 EQFP/PQFP Pin Table
Pin
1
CY39030
GCTL0
GND
CY39050
GCTL0
GND
CY39100
GCTL0
GND
CY39165
GCTL0
GND
CY39200
GCTL0
GND
GCLK0
GND
IO0
2
3
GCLK0
GND
GCLK0
GND
GCLK0
GND
GCLK0
GND
4
5
IO0
IO0
IO0
IO0
6
IO0
IO0
IO0
IO0
IO0
7
IO0
IO0
IO0
IO0
IO0
8
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
9
10
11
IO0
IO0
IO0
IO0
IO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
Note:
18. The PLL is available in Delta39K ‘V’ devices (2.5V/3.3V) and not in Delta39K ‘Z’ devices (1.8V). In Delta39K ‘Z’ devices, connect VCCPLL to VCC
.
Document #: 38-03039 Rev. *H
Page 46 of 86
Delta39K™ ISR™
CPLD Family
Table 11. 208 EQFP/PQFP Pin Table (continued)
Pin
12
CY39030
IO0
CY39050
IO0
CY39100
IO0
CY39165
CY39200
IO0
IO0
IO0
13
IO0
IO0
IO0
IO0
14
IO0
IO0
IO0
IO0
IO0
15
IO0
IO0
IO0
IO0
IO0
16
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
17
18
IO0
IO0
IO0
IO0
IO0
19
IO0
IO0
IO0
IO0
IO0
20
VCCIO0
IO0
VCCIO0
IO0
VCCIO0
IO0
VCCIO0
IO0
VCCIO0
IO0
21[19]
22[19]
23
IO0
IO0
IO0
IO0
IO0
VCC
VCC
VCC
VCC
VCC
24
GND
NC
GND
NC
GND
VCC
GND
VCC
GND
VCC
25
26
27[19]
NC
NC
GND
IO/VREF0
VCCIO0
VCCIO1
IO/VREF1
IO1
GND
IO/VREF0
VCCIO0
VCCIO1
IO/VREF1
IO1
GND
IO/VREF0
VCCIO0
VCCIO1
IO/VREF1
IO1
IO/VREF0
VCCIO0
VCCIO1
IO/VREF1
IO1
IO/VREF0
VCCIO0
VCCIO1
IO/VREF1
IO1
28
29
30[19]
31[19]
32[19]
33
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
34
IO1
IO1
IO1
IO1
IO1
35
VCCIO1
GND
IO1
VCCIO1
GND
IO1
VCCIO1
GND
IO1
VCCIO1
GND
IO1
VCCIO1
GND
IO1
36
37
38
IO1
IO1
IO1
IO1
IO1
39
IO1
IO1
IO1
IO1
IO1
40
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
41
42
IO1
IO1
IO1
IO1
IO1
43
IO1
IO1
IO1
IO1
IO1
44
IO1
IO1
IO1
IO1
IO1
45
VCCPRG
VCCIO1
GND
IO1
VCCPRG
VCCIO1
GND
IO1
VCCPRG
VCCIO1
GND
IO1
VCCPRG
VCCIO1
GND
IO1
VCCPRG
VCCIO1
GND
IO1
46
47
48
49
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
50
51
IO1
IO1
IO1
IO1
IO1
52
VCCCNFG
Data
VCCCNFG
Data
VCCCNFG
Data
VCCCNFG
Data
VCCCNFG
Data
53
54
Config_Done
Reset
Config_Done
Reset
Config_Done
Reset
Config_Done
Reset
Config_Done
Reset
55
Document #: 38-03039 Rev. *H
Page 47 of 86
Delta39K™ ISR™
CPLD Family
Table 11. 208 EQFP/PQFP Pin Table (continued)
Pin
56
CY39030
Reconfig
CCE
CY39050
Reconfig
CCE
CY39100
Reconfig
CCE
CY39165
CY39200
Reconfig
CCE
Reconfig
CCE
57
58
CCLK
VCCCNFG
MSEL
IO2
CCLK
VCCCNFG
MSEL
IO2
CCLK
VCCCNFG
MSEL
IO2
CCLK
VCCCNFG
MSEL
IO2
CCLK
VCCCNFG
MSEL
IO2
59
60
61
62
IO2
IO2
IO2
IO2
IO2
63
IO2
IO2
IO2
IO2
IO2
64
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
65
66
VCCIO2
GND
IO2
VCCIO2
GND
IO2
VCCIO2
GND
IO2
VCCIO2
GND
IO2
VCCIO2
GND
IO2
67
68
69
IO2
IO2
IO2
IO2
IO2
70
IO2
IO2
IO2
IO2
IO2
71
IO2
IO2
IO2
IO2
IO2
72
IO/VREF2
GND
VCCIO2
VCC
IO/VREF2
GND
VCCIO2
VCC
IO/VREF2
GND
VCCIO2
VCC
IO/VREF2
GND
VCCIO2
VCC
IO/VREF2
GND
VCCIO2
VCC
73
74
75
76
GND
NC
GND
NC
GND
VCC
GND
VCC
GND
VCC
77
78
NC
NC
GND
IO2
GND
IO2
GND
IO2
79
IO2
IO2
80
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
81[19]
82[19]
83[19]
84
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
VCCIO2
VCCIO3
IO3
VCCIO2
VCCIO3
IO3
VCCIO2
VCCIO3
IO3
VCCIO2
VCCIO3
IO3
VCCIO2
VCCIO3
IO3
85
86[19]
87[19]
88[19]
89
IO3
IO3
IO3
IO3
IO3
IO/VREF3
VCCIO3
GND
IO3
IO/VREF3
VCCIO3
GND
IO3
IO/VREF3
VCCIO3
GND
IO3
IO/VREF3
VCCIO3
GND
IO3
IO/VREF3
VCCIO3
GND
IO3
90
91
92
IO3
IO3
IO3
IO3
IO3
93
IO3
IO3
IO3
IO3
IO3
94
IO3
IO3
IO3
IO3
IO3
95
IO3
IO3
IO3
IO3
IO3
96
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
97
98
VCCIO3
IO3
VCCIO3
IO3
VCCIO3
IO3
VCCIO3
IO3
VCCIO3
IO3
99
Document #: 38-03039 Rev. *H
Page 48 of 86
Delta39K™ ISR™
CPLD Family
Table 11. 208 EQFP/PQFP Pin Table (continued)
Pin
100
CY39030
GND
IO3
CY39050
GND
IO3
CY39100
GND
IO3
CY39165
CY39200
GND
IO3
GND
IO3
101
102
103
104
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO/VREF3
IO4
IO/VREF3
IO4
IO/VREF3
IO4
IO/VREF3
IO4
IO/VREF3
IO4
105
106
107
108
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
109
110
IO4
IO4
IO4
IO4
IO4
111
VCCIO4
GND
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
112
113
114
VCCPRG
IO4
VCCPRG
IO4
VCCPRG
IO4
VCCPRG
IO4
VCCPRG
IO4
115
116
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
117
118
IO4
IO4
IO4
IO4
IO4
119
IO4
IO4
IO4
IO4
IO4
120
121
122[19]
123[19]
124
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
VCCIO4
GND
IO4
125
126[19]
127
VCC
VCC
VCC
VCC
VCC
128
GND
NC
GND
NC
GND
VCC
GND
VCC
GND
VCC
129
130
NC
NC
GND
VCCIO4
VCCIO5
IO5
GND
VCCIO4
VCCIO5
IO5
GND
VCCIO4
VCCIO5
IO5
131
VCCIO4
VCCIO5
IO5
VCCIO4
VCCIO5
IO5
132
133[19]
134[19]
135[19]
136
137
138
IO5
IO5
IO5
IO5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO5
IO5
IO5
IO5
IO5
VCCIO5
IO5
VCCIO5
IO5
VCCIO5
IO5
VCCIO5
IO5
VCCIO5
IO5
139
140
141
142
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
143
Document #: 38-03039 Rev. *H
Page 49 of 86
Delta39K™ ISR™
CPLD Family
Table 11. 208 EQFP/PQFP Pin Table (continued)
Pin
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183[19]
184[19]
185[19]
186
187
CY39030
IO5
CY39050
IO5
CY39100
IO5
CY39165
CY39200
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
VCCIO5
IO/VREF5
IO5
VCCIO5
IO/VREF5
IO5
VCCIO5
IO/VREF5
IO5
VCCIO5
IO/VREF5
IO5
VCCIO5
IO/VREF5
IO5
IO5
IO5
IO5
IO5
IO5
GND
GND
GND
GND
GND
GCLK1
GND
GCLK1
GND
GCLK1
GND
GCLK1
GND
GCLK1
GND
GCTL1
TDO
GCTL1
TDO
GCTL1
TDO
GCTL1
TDO
GCTL1
TDO
TCLK
TDI
TCLK
TDI
TCLK
TDI
TCLK
TDI
TCLK
TDI
VCCJTAG
GCLK2
GND
VCCJTAG
GCLK2
GND
VCCJTAG
GCLK2
GND
VCCJTAG
GCLK2
GND
VCCJTAG
GCLK2
GND
TMS
TMS
TMS
TMS
TMS
GCTL2
IO6
GCTL2
IO6
GCTL2
IO6
GCTL2
IO6
GCTL2
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
VCCIO6
IO6
VCCIO6
IO6
VCCIO6
IO6
VCCIO6
IO6
VCCIO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
GND
GND
GND
GND
GND
VCCIO6
VCCPLL
GND
VCCIO6
VCCPLL
GND
VCCIO6
VCCPLL
GND
VCCIO6
VCCPLL
GND
VCCIO6
VCCPLL
GND
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO6/Lock
VCCIO6
VCCIO7
IO6/Lock
VCCIO6
VCCIO7
IO6/Lock
VCCIO6
VCCIO7
IO6/Lock
VCCIO6
VCCIO7
IO6/Lock
VCCIO6
VCCIO7
Document #: 38-03039 Rev. *H
Page 50 of 86
Delta39K™ ISR™
CPLD Family
Table 11. 208 EQFP/PQFP Pin Table (continued)
Pin
188[19]
189[19]
190[19]
191
CY39030
IO7
CY39050
IO7
CY39100
IO7
CY39165
CY39200
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO/VREF7
VCCIO7
IO7
IO/VREF7
VCCIO7
IO7
IO/VREF7
VCCIO7
IO7
IO/VREF7
VCCIO7
IO7
IO/VREF7
VCCIO7
IO7
192
193
IO7
IO7
IO7
IO7
IO7
194
IO7
IO7
IO7
IO7
IO7
195
IO7
IO7
IO7
IO7
IO7
196
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
197
198
IO7
IO7
IO7
IO7
IO7
199
VCCIO7
IO7
VCCIO7
IO7
VCCIO7
IO7
VCCIO7
IO7
VCCIO7
IO7
200
201
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
202
203
IO7
IO7
IO7
IO7
IO7
204
IO7
IO7
IO7
IO7
IO7
205
GND
GCLK3
GND
GCTL3
GND
GCLK3
GND
GCTL3
GND
GCLK3
GND
GCTL3
GND
GCLK3
GND
GCTL3
GND
GCLK3
GND
GCTL3
206
207
208
Table 12. 388 BGA Pin Table
Pin
A1
CY39050
GND
NC
CY39100
CY39165
GND
IO7
CY39200
GND
IO7
GND
IO7
A2
A3
IO7
IO7
IO7
IO7
A4
IO7
IO7
IO7
IO7
A5
IO7
IO7
IO7
IO7
A6
IO7
IO7
IO7
IO7
A7
IO7
IO7
IO7
IO7
A8
NC
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
A9
IO7
A10
A11
A12
A13[19]
A14[19]
A15
A16
A17
A18
IO7
IO7
IO7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO7
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
GND
IO6
GND
IO6
GND
IO6
GND
IO6
IO6
IO6
IO6
IO6
Note:
19. Capacitance on these I/O pins meets the PCI spec (rev. 2.2), which requires IDSEL pin in a PCI design to have capacitance less than or equal to 8 pf. In the
document titled “Delta39K CPLD Family data sheet”, this spec is defined as CPCI. All other I/O pins have a capacitance less than or equal to 10 pf.
Document #: 38-03039 Rev. *H
Page 51 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
A19
A20
A21
A22
A23
A24
A25
A26
B1
CY39050
NC
CY39100
IO6
CY39165
IO6
CY39200
IO6
NC
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
GND
IO7
GND
IO7
GND
IO7
GND
IO7
B2
NC
IO7
IO7
IO7
B3
NC
IO7
IO7
IO7
B4
NC
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
B5
IO7
B6
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
B7
B8
IO7
IO7
IO7
IO7
B9
IO7
IO7
IO7
IO7
B10
B11
B12
B13[19]
B14[19]
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6/Lock
IO6
IO6/Lock
IO6
IO6/Lock
IO6
IO6/Lock
IO6
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
NC
IO6
IO6
IO6
NC
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO0
IO0
IO0
IO0
C2
IO/VREF7
NC
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
C3
C4
IO7
IO7
IO7
IO7
C5
IO7
IO7
IO7
IO7
C6
NC
IO7
IO7
IO7
C7
IO7
IO7
IO7
IO7
C8
IO7
IO7
IO7
IO7
C9
IO7
IO7
IO7
IO7
C10
IO7
IO7
IO7
IO7
Document #: 38-03039 Rev. *H
Page 52 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
C11
C12
C13[19]
C14[19]
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
CY39050
IO7
CY39100
IO7
CY39165
IO7
CY39200
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
NC
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
NC
IO6
IO6
IO6
NC
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO0
IO0
IO0
IO0
D2
IO0
IO0
IO0
IO0
D3
IO/VREF0
IO7
IO/VREF0
IO7
IO/VREF0
IO7
IO/VREF0
IO7
D4
D5
GCTL3
NC
GCTL3
IO7
GCTL3
IO7
GCTL3
IO7
D6
D7
GCLK3
VCCIO7
VCCIO7
VCCIO7
IO7
GCLK3
VCCIO7
VCCIO7
VCCIO7
IO7
GCLK3
VCCIO7
VCCIO7
VCCIO7
IO7
GCLK3
VCCIO7
VCCIO7
VCCIO7
IO7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
VCCIO7
VCC
VCCIO7
VCC
VCCIO7
VCC
VCCIO7
VCC
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
VCCPLL
VCCIO6
VCCIO6
GCLK2
NC
VCCPLL
VCCIO6
VCCIO6
GCLK2
IO/VREF6
GCTL2
IO6
VCCPLL
VCCIO6
VCCIO6
GCLK2
IO/VREF6
GCTL2
IO6
VCCPLL
VCCIO6
VCCIO6
GCLK2
IO/VREF6
GCTL2
IO6
GCTL2
NC
IO5
IO5
IO5
IO5
TMS
TCLK
IO0
TMS
TMS
TMS
TCLK
IO0
TCLK
IO0
TCLK
IO0
E2
IO0
IO0
IO0
IO0
Document #: 38-03039 Rev. *H
Page 53 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
E3
CY39050
IO0
CY39100
IO0
CY39165
IO0
CY39200
IO0
E4
GCTL0
GCLK1
IO5
GCTL0
GCLK1
IO5
GCTL0
GCLK1
IO5
GCTL0
GCLK1
IO5
E23
E24
E25
E26
F1
TDI
TDI
TDI
TDI
TDO
NC
TDO
IO0
TDO
IO0
TDO
IO0
F2
NC
IO0
IO0
IO0
F3
NC
IO0
IO0
IO0
F4
IO0
IO0
IO0
IO0
F23
F24
F25
F26
G1
NC
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO0
IO0
IO0
IO0
G2
IO0
IO0
IO0
IO0
G3
IO/VREF0
GCLK0
GCTL1
IO/VREF5
IO5
IO/VREF0
GCLK0
GCTL1
IO/VREF5
IO5
IO/VREF0
GCLK0
GCTL1
IO/VREF5
IO5
IO/VREF0
GCLK0
GCTL1
IO/VREF5
IO5
G4
G23
G24
G25
G26
H1
IO5
IO5
IO5
IO5
IO0
IO0
IO0
IO0
H2
NC
IO0
IO0
IO0
H3
NC
IO0
IO0
IO0
H4
VCCIO0
VCCJTAG
IO5
VCCIO0
VCCJTAG
IO5
VCCIO0
VCCJTAG
IO5
VCCIO0
VCCJTAG
IO5
H23
H24
H25
H26
J1
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
IO0
IO0
IO0
J2
NC
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
J3
NC
J4
VCCIO0
VCCIO5
NC
VCCIO0
VCCIO5
IO/VREF5
IO5
VCCIO0
VCCIO5
IO/VREF5
IO5
VCCIO0
VCCIO5
IO/VREF5
IO5
J23
J24
J25
J26
K1
IO5
IO5
IO5
IO5
IO5
NC
IO0
IO0
IO0
K2
NC
IO0
IO0
IO0
K3
NC
IO0
IO0
IO0
K4
VCC
VCC
VCC
VCC
K23
K24
VCCIO5
IO5
VCCIO5
IO5
VCCIO5
IO5
VCCIO5
IO5
Document #: 38-03039 Rev. *H
Page 54 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
K25
K26
L1
CY39050
NC
CY39100
IO5
CY39165
IO5
CY39200
IO5
NC
IO5
IO5
IO5
IO0
IO0
IO0
IO0
L2
IO0
IO0
IO0
IO0
L3
IO0
IO0
IO0
IO0
L4
IO0
IO0
IO0
IO0
L11
GND
GND
GND
GND
GND
GND
NC
GND
GND
GND
GND
GND
GND
IO5
GND
GND
GND
GND
GND
GND
IO5
GND
GND
GND
GND
GND
GND
IO5
L12
L13
L14
L15
L16
L23
L24
L25
L26
M1
IO/VREF5
NC
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
NC
IO5
IO5
IO5
IO0
IO0
IO0
IO0
M2[19]
M3[19]
M4
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
VCCIO0
GND
GND
GND
GND
GND
GND
VCCIO5
NC
VCCIO0
GND
GND
GND
GND
GND
GND
VCCIO5
IO5
VCCIO0
GND
GND
GND
GND
GND
GND
VCCIO5
IO5
VCCIO0
GND
GND
GND
GND
GND
GND
VCCIO5
IO5
M11
M12
M13
M14
M15
M16
M23
M24
M25
M26
N1
NC
IO5
IO5
IO5
NC
IO5
IO5
IO5
NC
VCC
IO/VREF0
IO0
VCC
IO/VREF0
IO0
VCC
IO/VREF0
IO0
N2
IO/VREF0
IO0
N3[19]
N4[19]
N11
N12
N13
N14
N15
N16
N23[19]
N24
N25
N26
IO1
IO1
IO1
IO1
GND
GND
GND
GND
GND
GND
IO5
GND
GND
GND
GND
GND
GND
IO5
GND
GND
GND
GND
GND
GND
IO5
GND
GND
GND
GND
GND
GND
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO/VREF5
IO/VREF5
IO/VREF5
IO/VREF5
Document #: 38-03039 Rev. *H
Page 55 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
P1
CY39050
IO1
CY39100
IO1
CY39165
IO1
CY39200
IO1
P2
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
P3[19]
P4[19]
P11
P12
P13
P14
P15
P16
P23
P24[19]
P25[19]
P26
R1
IO1
IO1
IO1
IO1
GND
GND
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
GND
GND
GND
GND
GND
VCC
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
VCC
VCC
VCC
IO1
IO1
IO1
IO1
R2
IO1
IO1
IO1
IO1
R3
NC
IO1
IO1
IO1
R4
VCCIO1
GND
GND
GND
GND
GND
GND
VCCIO4
IO4
VCCIO1
GND
GND
GND
GND
GND
GND
VCCIO4
IO4
VCCIO1
GND
GND
GND
GND
GND
GND
VCCIO4
IO4
VCCIO1
GND
GND
GND
GND
GND
GND
VCCIO4
IO4
R11
R12
R13
R14
R15
R16
R23
R24[19]
R25[19]
R26
T1
IO4
IO4
IO4
IO4
NC
IO5
IO5
IO5
NC
IO1
IO1
IO1
T2
NC
IO1
IO1
IO1
T3
NC
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
T4
NC
T11
GND
GND
GND
GND
GND
GND
IO4
GND
GND
GND
GND
GND
GND
IO4
GND
GND
GND
GND
GND
GND
IO4
GND
GND
GND
GND
GND
GND
IO4
T12
T13
T14
T15
T16
T23[19]
T24
T25
T26
U1
IO4
IO4
IO4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
NC
IO1
IO1
IO1
U2
NC
IO1
IO1
IO1
Document #: 38-03039 Rev. *H
Page 56 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
U3
CY39050
NC
CY39100
IO1
CY39165
IO1
CY39200
IO1
U4
VCCPRG
VCCPRG
IO4
VCCPRG
VCCPRG
IO4
VCCPRG
VCCPRG
IO4
VCCPRG
VCCPRG
IO4
U23
U24
U25
U26
V1
IO4
IO4
IO4
IO4
NC
IO4
IO4
IO4
NC
IO1
IO1
IO1
V2
NC
IO1
IO1
IO1
V3
IO1
IO1
IO1
IO1
V4
VCCIO1
VCCIO4
NC
VCCIO1
VCCIO4
IO4
VCCIO1
VCCIO4
IO4
VCCIO1
VCCIO4
IO4
V23
V24
V25
V26
W1
NC
IO4
IO4
IO4
NC
IO4
IO4
IO4
IO1
IO1
IO1
IO1
W2
IO1
IO1
IO1
IO1
W3
IO/VREF1
VCCIO1
VCCIO4
NC
IO/VREF1
VCCIO1
VCCIO4
IO4
IO/VREF1
VCCIO1
VCCIO4
IO4
IO/VREF1
VCCIO1
VCCIO4
IO4
W4
W23
W24
W25
W26
Y1
NC
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
NC
IO1
IO1
IO1
IO1
Y2
IO1
IO1
IO1
IO1
Y3
IO1
IO1
IO1
IO1
Y4
IO1
IO1
IO1
IO1
Y23
Y24
Y25
Y26
AA1
AA2
AA3
AA4
AA23
AA24
AA25
AA26
AB1
AB2
AB3
AB4
AB23
AB24
NC
IO4
IO4
IO4
NC
IO4
IO4
IO4
NC
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
VCCCNFG
Config_Done
IO1
VCCCNFG
Config_Done
IO1
VCCCNFG
Config_Done
IO1
VCCCNFG
Config_Done
IO1
IO1
IO1
IO1
IO1
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
Document #: 38-03039 Rev. *H
Page 57 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
AB25
AB26
AC1
CY39050
IO4
CY39100
IO4
CY39165
IO4
CY39200
IO4
IO4
IO4
IO4
IO4
Data
Data
Data
Data
AC2
Reconfig
IO2
Reconfig
IO2
Reconfig
IO2
Reconfig
IO2
AC3
AC4
IO2
IO2
IO2
IO2
AC5
IO2
IO2
IO2
IO2
AC6
IO2
IO2
IO2
IO2
AC7
NC
IO2
IO2
IO2
AC8
VCCIO2
VCCIO2
VCCCNFG
IO2
VCCIO2
VCCIO2
VCCCNFG
IO2
VCCIO2
VCCIO2
VCCCNFG
IO2
VCCIO2
VCCIO2
VCCCNFG
IO2
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
VCCIO2
VCCIO2
VCCIO3
VCCIO3
IO3
VCCIO2
VCCIO2
VCCIO3
VCCIO3
IO3
VCCIO2
VCCIO2
VCCIO3
VCCIO3
IO3
VCCIO2
VCCIO2
VCCIO3
VCCIO3
IO3
NC
VCC
VCC
VCC
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
Reset
CCLK
IO/VREF2
IO2
Reset
CCLK
IO/VREF2
IO2
Reset
CCLK
IO/VREF2
IO2
Reset
CCLK
IO/VREF2
IO2
AD2
AD3
AD4
AD5
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
AD6
AD7
NC
IO2
IO2
IO2
AD8
NC
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
AD9
IO2
AD10
AD11
AD12
AD13
AD14[19]
AD15[19]
AD16
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO2
IO2
IO2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
Document #: 38-03039 Rev. *H
Page 58 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
CY39050
IO3
CY39100
IO3
CY39165
IO3
CY39200
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO3
IO3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
CCE
MSEL
IO2
CCE
MSEL
IO2
CCE
MSEL
IO2
CCE
MSEL
IO2
AE2
AE3
AE4
IO2
IO2
IO2
IO2
AE5
IO2
IO2
IO2
IO2
AE6
NC
IO2
IO2
IO2
AE7
NC
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
AE8
IO2
AE9
IO2
IO2
IO2
IO2
AE10
AE11
AE12
AE13[19]
AE14[19]
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO/VREF3
NC
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO3
IO3
IO3
IO3
NC
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
NC
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
GND
IO2
GND
IO2
GND
IO2
GND
IO2
AF2
AF3
IO2
IO2
IO2
IO2
AF4
IO2
IO2
IO2
IO2
AF5
IO2
IO2
IO2
IO2
AF6
NC
IO2
IO2
IO2
AF7
NC
IO2
IO2
IO2
AF8
NC
IO2
IO2
IO2
Document #: 38-03039 Rev. *H
Page 59 of 86
Delta39K™ ISR™
CPLD Family
Table 12. 388 BGA Pin Table (continued)
Pin
AF9
CY39050
NC
CY39100
IO2
CY39165
IO2
CY39200
IO2
AF10
AF11
AF12
AF13
AF14[19]
AF15[19]
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
IO2
IO2
IO2
IO2
GND
IO2
GND
IO2
GND
IO2
GND
IO2
VCC
IO3
VCC
IO3
VCC
IO3
VCC
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO3
IO3
IO3
NC
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO3
NC
IO3
IO3
IO3
NC
IO3
IO3
IO3
GND
GND
GND
GND
Table 13. 256 FBGA Pin Table
Pin
A1
CY39030
GND
IO7
CY39050
GND
IO7
CY39100
GND
IO7
A2
A3
IO7
IO7
IO7
A4
IO7
IO7
IO7
A5
IO7
IO7
IO7
A6
IO/VREF7
NC
IO/VREF7
IO/VREF7
IO6/Lock
IO6
IO/VREF7
IO/VREF7
IO6/Lock
IO6
A7
A8
IO6/Lock
IO6
A9
A10
A11
A12
A13
A14
A15
A16
B1
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
GND
IO0
GND
IO0
GND
IO0
B2
GND
IO7
GND
IO7
GND
IO7
B3
B4
IO7
IO7
IO7
B5
IO7
IO7
IO7
B6
VCCIO7
VCC
VCCIO7
VCC
VCCIO7
VCC
B7
Document #: 38-03039 Rev. *H
Page 60 of 86
Delta39K™ ISR™
CPLD Family
Table 13. 256 FBGA Pin Table (continued)
Pin
B8
CY39030
IO/VREF7
NC
CY39050
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6
CY39100
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6
B9
B10
B11
B12
B13
B14
B15
B16
C1
VCCPLL
VCCIO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
GND
TDO
IO0
GND
TDO
IO0
GND
TDO
IO0
C2
IO0
IO0
IO0
C3
GND
IO7
GND
IO7
GND
IO7
C4
C5
IO7
IO7
IO7
C6
VCCIO7
VCCIO7
NC
VCCIO7
VCCIO7
IO7
VCCIO7
VCCIO7
IO7
C7
C8[19]
C9[19]
C10
C11
C12
C13
C14
C15
C16
D1
IO6
IO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
IO6
IO6
IO6
GND
TDI
GND
TDI
GND
TDI
IO5
IO5
IO5
IO0
IO0
IO0
D2
IO0
IO0
IO0
D3
IO0
IO0
IO0
D4
GND
IO7
GND
IO7
GND
IO7
D5
D6
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
D7
D8[19]
D9[19]
D10
D11
D12
D13
D14
D15
D16
E1
IO7
IO7
IO7
NC
IO6
IO6
IO6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
GND
TCLK
IO5
GND
TCLK
IO5
GND
TCLK
IO5
IO5
IO5
IO5
IO0
IO0
IO0
E2
IO0
IO0
IO0
E3
IO0
IO0
IO0
Document #: 38-03039 Rev. *H
Page 61 of 86
Delta39K™ ISR™
CPLD Family
Table 13. 256 FBGA Pin Table (continued)
Pin
E4
CY39030
IO0
CY39050
IO0
CY39100
IO0
E5
IO7
IO7
IO7
E6
IO7
IO7
IO7
E7
IO7
IO7
IO7
E8[19]
E9[19]
E10
E11
E12
E13
E14
E15
E16
F1
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
TMS
TMS
TMS
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO0
IO0
IO0
F2
VCC
VCC
VCC
F3
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
F4
F5
F6
IO7
IO7
IO7
F7
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
F8
F9
F10
F11
F12
F13
F14
F15
F16
G1
IO5
IO5
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO0
IO0
IO0
G2
NC
NC
VCC
G3
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
G4
G5
G6
GCTL0
GND
GND
GND
GND
GCTL1
IO5
GCTL0
GND
GND
GND
GND
GCTL1
IO5
GCTL0
GND
GND
GND
GND
GCTL1
IO5
G7
G8
G9
G10
G11
G12
G13
G14
G15
IO/VREF5
VCCIO5
NC
IO/VREF5
VCCIO5
NC
IO/VREF5
VCCIO5
VCC
Document #: 38-03039 Rev. *H
Page 62 of 86
Delta39K™ ISR™
CPLD Family
Table 13. 256 FBGA Pin Table (continued)
Pin
G16
H1[19]
H2[19]
H3[19]
H4
CY39030
IO5
CY39050
IO5
CY39100
IO5
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
H5
H6
GCLK0
GND
GND
GND
GND
GCLK1
IO5
GCLK0
GND
GND
GND
GND
GCLK1
IO5
GCLK0
GND
GND
GND
GND
GCLK1
IO5
H7
H8
H9
H10
H11
H12
H13
H14[19]
H15[19]
H16[19]
J1
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO1
IO1
IO1
J2
IO1
IO1
IO1
J3[19]
J4[19]
J5[19]
J6
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
J7
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
J8
J9
J10
J11
J12[19]
J13[19]
J14[19]
J15
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO5
IO5
IO5
J16
IO5
IO5
IO5
K1
IO1
IO1
IO1
K2
VCCPRG
VCCIO1
IO/VREF1
IO1
VCCPRG
VCCIO1
IO/VREF1
IO1
VCCPRG
VCCIO1
IO/VREF1
IO1
K3
K4
K5
K6
IO1
IO1
IO1
K7
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
K8
K9
K10
K11
Document #: 38-03039 Rev. *H
Page 63 of 86
Delta39K™ ISR™
CPLD Family
Table 13. 256 FBGA Pin Table (continued)
Pin
K12
K13
K14
K15
K16
L1
CY39030
IO4
CY39050
IO4
CY39100
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
IO1
IO1
IO1
L2
NC
NC
VCC
L3
VCCIO1
IO/VREF1
VCCCNFG
Config_Done
IO2
VCCIO1
IO/VREF1
VCCCNFG
Config_Done
IO2
VCCIO1
IO/VREF1
VCCCNFG
Config_Done
IO2
L4
L5
L6
L7
L8[19]
L9[19]
L10
L11
L12
L13
L14
L15
L16
M1
IO2
IO2
IO2
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO4
IO4
IO4
IO/VREF4
VCCIO4
VCC
IO/VREF4
VCCIO4
VCC
IO/VREF4
VCCIO4
VCC
IO4
IO4
IO4
IO1
IO1
IO1
M2
IO1
IO1
IO1
M3
IO1
IO1
IO1
M4
Data
Data
Data
M5
Reconfig
IO2
Reconfig
IO2
Reconfig
IO2
M6
M7
IO2
IO2
IO2
M8[19]
M9[19]
M10
M11
M12
M13
M14
M15
M16
N1
IO2
IO2
IO2
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
N2
N3
IO1
IO1
IO1
N4
GND
MSEL
IO/VREF2
IO/VREF2
GND
MSEL
IO/VREF2
IO/VREF2
GND
MSEL
IO/VREF2
IO/VREF2
N5
N6
N7
Document #: 38-03039 Rev. *H
Page 64 of 86
Delta39K™ ISR™
CPLD Family
Table 13. 256 FBGA Pin Table (continued)
Pin
N8[19]
N9[19]
N10
N11
N12
N13
N14
N15
N16
P1
CY39030
IO2
CY39050
IO2
CY39100
IO2
IO3
IO3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
GND
IO4
GND
IO4
GND
IO4
IO4
IO4
IO4
IO/VREF4
IO1
IO/VREF4
IO1
IO/VREF4
IO1
P2
IO1
IO1
IO1
P3
GND
CCE
IO2
GND
CCE
IO2
GND
CCE
IO2
P4
P5
P6
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
P7
P8
P9
IO2
IO2
IO2
P10
P11
P12
P13
P14
P15
P16
R1
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
IO3
IO3
IO3
GND
IO4
GND
IO4
GND
IO4
IO4
IO4
IO4
IO1
IO1
IO1
R2
GND
CCLK
IO2
GND
CCLK
IO2
GND
CCLK
IO2
R3
R4
R5
IO2
IO2
IO2
R6
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
R7
R8
R9
IO2
IO2
IO2
R10
R11
R12
R13
R14
R15
R16
T1
VCC
VCC
VCC
VCCIO3
IO3
VCCIO3
IO3
VCCIO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
GND
IO4
GND
IO4
GND
IO4
GND
Reset
IO2
GND
Reset
IO2
GND
Reset
IO2
T2
T3
Document #: 38-03039 Rev. *H
Page 65 of 86
Delta39K™ ISR™
CPLD Family
Table 13. 256 FBGA Pin Table (continued)
Pin
T4
CY39030
IO2
CY39050
IO2
CY39100
IO2
T5
IO2
IO2
IO2
T6
IO/VREF2
NC
IO/VREF2
IO/VREF2
IO2
IO/VREF2
IO/VREF2
IO2
T7
T8
IO2
T9
IO2
IO2
IO2
T10
T11
T12
T13
T14
T15
T16
NC
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
GND
GND
GND
Table 14. 484 FBGA Pin Table
Pin
A1
CY39050
GND
GND
NC
CY39100
GND
GND
NC
CY39165
GND
GND
IO/VREF7
IO/VREF7
IO7
CY39200
GND
GND
IO/VREF7
IO/VREF7
IO7
A2
A3
A4
NC
NC
A5
IO7
IO7
A6
IO7
IO7
IO7
IO7
A7
NC
IO7
IO7
IO7
A8
IO7
IO7
IO7
IO7
A9
IO7
IO7
IO7
IO7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
B1
IO7
IO7
IO7
IO7
GND
GND
IO6
GND
GND
IO6
GND
GND
IO6
GND
GND
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
NC
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
NC
NC
NC
IO/VREF6
IO6
NC
NC
NC
GND
GND
GND
GND
NC
GND
GND
GND
GND
NC
GND
GND
GND
GND
IO7
GND
GND
GND
GND
IO7
B2
B3
B4
VCCIO7
NC
VCCIO7
IO7
VCCIO7
IO7
VCCIO7
IO7
B5
B6
IO7
IO7
IO7
IO7
Document #: 38-03039 Rev. *H
Page 66 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
B7
CY39050
NC
CY39100
IO7
CY39165
IO7
CY39200
IO7
B8
IO/VREF7
NC
IO/VREF7
NC
IO/VREF7
VCCIO7
IO7
IO/VREF7
VCCIO7
IO7
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
C1
IO7
IO7
IO7
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
NC
NC
VCCIO6
IO/VREF6
IO6[20]
IO6
VCCIO6
IO/VREF6
IO6
IO/VREF6
NC
IO/VREF6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
VCCIO6
NC
VCCIO6
NC
VCCIO6
NC
VCCIO6
IO6
GND
GND
NC
GND
GND
NC
GND
GND
IO7
GND
GND
IO7
C2
NC
NC
IO7
IO7
C3
NC
NC
IO7
IO7
C4
NC
IO7
IO7
IO7
C5
NC
IO7
IO7
IO7
C6
IO7
IO7
IO7
IO7
C7
NC
IO7
IO7
IO7
C8
IO7
IO7
IO7
IO7
C9
IO7
IO7
IO7
IO7
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
D1
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
IO6
IO6
IO6
IO6
NC
IO/VREF6
IO6
IO/VREF6
IO6
IO6[20]
IO/VREF6
IO6
IO6
IO6
IO6
IO6
NC
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
NC
NC
NC
IO6
NC
NC
NC
IO6
NC
NC
NC
IO6
NC
NC
IO/VREF0
VCCIO0
IO0
IO/VREF0
VCCIO0
IO0
D2
VCCIO0
NC
VCCIO0
NC
D3
D4
GND
NC
GND
IO7
GND
IO7
GND
IO7
D5
D6
NC
IO7
IO7
IO7
Document #: 38-03039 Rev. *H
Page 67 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
D7
CY39050
IO7
CY39100
IO7
CY39165
IO7
CY39200
IO7
D8
IO7
IO7
IO7
IO7
D9
IO/VREF7
NC
IO/VREF7
IO/VREF7
IO6/Lock
IO6
IO/VREF7
IO/VREF7
IO6/Lock
IO6
IO/VREF7
IO/VREF7
IO6/Lock
IO6
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
E1
IO6/Lock
IO6
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
NC
IO6
IO6
IO6
NC
IO6
IO6
IO6
IO6
IO6
IO6
IO6
GND
NC
GND
NC
GND
IO5
GND
IO5
VCCIO5
NC
VCCIO5
NC
VCCIO5
IO/VREF5
IO0
VCCIO5
IO/VREF5
IO0
NC
NC
E2
NC
NC
IO0
IO0
E3
NC
NC
IO0
IO0
E4
IO0
IO0
IO0
IO0
E5
GND
IO7
GND
IO7
GND
IO7
GND
IO7
E6
E7
IO7
IO7
IO7
IO7
E8
IO7
IO7
IO7
IO7
E9
VCCIO7
VCC
VCCIO7
VCC
VCCIO7
VCC
VCCIO7
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
F1
IO/VREF7
NC
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6[19]
IO6
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6
VCCPLL
VCCIO6
NC
NC
IO6
IO6
NC
IO6
IO6
IO6
GND
TDO
NC
GND
TDO
NC
GND
TDO
GND
TDO
IO5
IO5
NC
NC
IO5
IO5
NC
NC
IO5
IO5
NC
NC
IO0
IO0
F2
NC
IO0
IO0
IO0
F3
IO0
IO0
IO0
IO0
F4
IO0
IO0
IO0
IO0
F5
IO0
IO0
IO0
IO0
F6
GND
GND
GND
GND
Document #: 38-03039 Rev. *H
Page 68 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
F7
CY39050
IO7
CY39100
IO7
CY39165
IO7
CY39200
IO7
F8
IO7
IO7
IO7
IO7
F9
VCCIO7
VCCIO7
IO7
VCCIO7
VCCIO7
IO7
VCCIO7
VCCIO7
IO7
VCCIO7
VCCIO7
IO7
F10
F11[19]
F12[19]
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
G1
IO6
IO6
IO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
NC
IO6
IO6
IO6
GND
TDI
GND
TDI
GND
TDI
GND
TDI
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
IO5
IO5
IO5
NC
NC
IO5
IO5
NC
NC
IO0
IO0
G2
IO0
IO0
IO0
IO0
G3
NC
IO0
IO0
IO0
G4
IO0
IO0
IO0
IO0
G5
IO0
IO0
IO0
IO0
G6
IO0
IO0
IO0
IO0
G7
GND
IO7
GND
IO7
GND
IO7
GND
IO7
G8
G9
NC
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
G10
G11[19]
G12[19]
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
H1
IO7
IO7
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO6
IO6
IO6[20]
IO/VREF6
IO6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
IO/VREF6
IO6
GND
TCLK
IO5
GND
TCLK
IO5
GND
TCLK
IO5
GND
TCLK
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
NC
IO5
IO5
NC
NC
IO0
IO0
H2
IO0
IO0
IO0
IO0
H3
IO0
IO0
IO0
IO0
H4
IO0
IO0
IO0
IO0
H5
NC
IO0
IO0
IO0
H6
NC
IO0
IO0
IO0
Document #: 38-03039 Rev. *H
Page 69 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
H7
CY39050
NC
CY39100
IO0
CY39165
IO0
CY39200
IO0
H8
IO7
IO7
IO7
IO7
H9
IO7
IO7
IO7
IO7
H10
H11[19]
H12[19]
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
J1
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO7
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
IO6
TMS
IO5
TMS
IO5
TMS
TMS
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
NC
IO5
IO5
NC
NC
IO/VREF0
VCCIO0
IO/VREF0
IO0
IO/VREF0
VCCIO0
IO/VREF0
IO0
J2
NC
NC
J3
NC
IO/VREF0
IO0
J4
NC
J5
NC
VCC
VCC
VCC
J6
VCCIO0
IO/VREF0
NC
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
J7
J8
J9
IO7
IO7
IO7
IO7
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
K1
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
IO5
IO5
IO5
IO5
IO/VREF5
VCCIO5
VCCJTAG
NC
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
NC
IO/VREF5
NC
IO/VREF5
VCCIO5
IO/VREF5
IO0
IO/VREF5
VCCIO5
IO/VREF5
IO0
NC
NC
NC
NC
NC
K2
IO0
IO0
IO0
IO0
K3
NC
IO0
IO0
IO0
K4
IO0
IO0
IO0
IO0
K5
VCC
VCC
VCC
VCC
K6
VCCIO0
VCCIO0
VCCIO0
VCCIO0
Document #: 38-03039 Rev. *H
Page 70 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
K7
CY39050
IO/VREF0
NC
CY39100
IO/VREF0
IO0
CY39165
IO/VREF0
IO0
CY39200
IO/VREF0
IO0
K8
K9
GCTL0
GND
GND
GND
GND
GCTL1
NC
GCTL0
GND
GND
GND
GND
GCTL1
IO5
GCTL0
GND
GND
GND
GND
GCTL1
IO5
GCTL0
GND
GND
GND
GND
GCTL1
IO5
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
L1
IO/VREF5
VCCIO5
NC
IO/VREF5
VCCIO5
VCC
IO/VREF5
VCCIO5
VCC
IO/VREF5
VCCIO5
VCC
NC
IO5
IO5
IO5
NC
IO5
IO5
IO5
NC
IO5
IO5
IO5
NC
NC
IO5
IO5
GND
IO0
GND
IO0
GND
IO0
GND
IO0
L2
L3
IO0
IO0
IO0
IO0
L4[19]
L5[19]
L6[19]
L7
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO0
IO/VREF0
NC
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
L8
L9
GCLK0
GND
GND
GND
GND
GCLK1
NC
GCLK0
GND
GND
GND
GND
GCLK1
IO5
GCLK0
GND
GND
GND
GND
GCLK1
IO5
GCLK0
GND
GND
GND
GND
GCLK1
IO5
L10
L11
L12
L13
L14
L15
L16
L17[19]
L18[19]
L19[19]
L20
L21
L22
M1
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
IO5
IO5
IO5
GND
GND
NC
GND
GND
IO1
GND
GND
IO1
GND
GND
IO1
M2
M3
IO1
IO1
IO1
IO1
M4
IO1
IO1
IO1
IO1
M5
NC
IO1
IO1
IO1
M6[19]
IO1
IO1
IO1
IO1
Document #: 38-03039 Rev. *H
Page 71 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
M7[19]
M8[19]
M9
CY39050
IO1
CY39100
IO1
CY39165
IO1
CY39200
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
IO1
M10
M11
M12
M13
M14
M15[19]
M16[19]
M17[19]
M18
M19
M20
M21
M22
N1
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
NC
IO5
IO5
IO5
NC
IO5
IO5
IO5
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
GND
NC
GND
NC
GND
IO1
GND
IO1
N2
NC
IO1
IO1
IO1
N3
NC
IO1
IO1
IO1
N4
NC
IO1
IO1
IO1
N5
VCCPRG
VCCIO1
IO/VREF1
NC
VCCPRG
VCCIO1
IO/VREF1
IO1
VCCPRG
VCCIO1
IO/VREF1
IO1
VCCPRG
VCCIO1
IO/VREF1
IO1
N6
N7
N8
N9
NC
IO1
IO1
IO1
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P1
GND
GND
GND
GND
NC
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
IO4
IO4
IO4
IO4
IO/VREF4
VCCIO4
VCCPRG
NC
IO/VREF4
VCCIO4
VCCPRG
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
NC
IO4
IO4
IO4
NC
IO4
IO4
IO4
NC
NC
IO4
IO4
NC
NC
IO/VREF1
VCCIO1
IO/VREF1
IO1
IO/VREF1
VCCIO1
IO/VREF1
IO1
P2
NC
NC
P3
IO/VREF1
NC
IO/VREF1
IO1
P4
P5
VCC
VCC
VCC
VCC
P6
VCCIO1
VCCIO1
VCCIO1
VCCIO1
Document #: 38-03039 Rev. *H
Page 72 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
P7
CY39050
NC
CY39100
IO/VREF1
VCCCNFG
Config_Done
IO2
CY39165
IO/VREF1
VCCCNFG
Config_Done
IO2
CY39200
IO/VREF1
VCCCNFG
Config_Done
IO2
P8
VCCCNFG
Config_Done
IO2
P9
P10
P11[19]
P12[19]
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R1
IO2
IO2
IO2
IO2
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO4
IO4
IO4
IO/VREF4
VCCIO4
VCC
NC
IO/VREF4
VCCIO4
VCC
IO/VREF4
VCCIO4
VCC
IO/VREF4
VCCIO4
VCC
IO4
IO4
IO4
NC
IO/VREF4
NC
IO/VREF4
VCCIO4
IO/VREF4
IO1
IO/VREF4
VCCIO4
IO/VREF4
IO1
NC
NC
NC
NC
NC
R2
NC
IO1
IO1
IO1
R3
IO1
IO1
IO1
IO1
R4
IO1
IO1
IO1
IO1
R5
IO1
IO1
IO1
IO1
R6
IO1
IO1
IO1
IO1
R7
Data
Reconfig
IO2
Data
Reconfig
IO2
Data
Reconfig
IO2
Data
Reconfig
IO2
R8
R9
R10
R11[19]
R12[19]
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
T1
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO2
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO3
IO3
IO3
NC
IO4
IO4
IO4
NC
IO4
IO4
IO4
NC
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
NC
NC
IO4
IO4
NC
NC
IO1
IO1
T2
IO1
IO1
IO1
IO1
T3
IO1
IO1
IO1
IO1
T4
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
T5
T6
IO1
IO1
IO1
IO1
Document #: 38-03039 Rev. *H
Page 73 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
T7
CY39050
GND
MSEL
IO/VREF2
IO/VREF2
IO2
CY39100
GND
MSEL
IO/VREF2
IO/VREF2
IO2
CY39165
GND
CY39200
GND
MSEL
IO/VREF2
IO/VREF2
IO2
T8
MSEL
IO/VREF2
IO/VREF2
IO2
T9
T10
T11[19]
T12[19]
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U1
IO3
IO3
IO3
IO3
[20]
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
GND
IO4
GND
IO4
GND
IO4
GND
IO4
IO4
IO4
IO4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
IO4
IO4
IO4
IO4
NC
NC
IO4
IO4
NC
NC
IO1
IO1
U2
IO1
IO1
IO1
IO1
U3
IO1
IO1
IO1
IO1
U4
IO1
IO1
IO1
IO1
U5
IO1
IO1
IO1
IO1
U6
GND
CCE
IO2
GND
CCE
IO2
GND
CCE
IO2
GND
CCE
IO2
U7
U8
U9
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V1
IO2
IO2
IO2
IO2
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3[20]
IO3
VCCIO3
VCCIO3
IO3
IO3
IO3
IO3
GND
IO4
GND
IO4
GND
IO4
GND
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
NC
NC
IO4
IO4
NC
NC
IO1
IO1
V2
NC
NC
IO1
IO1
V3
NC
NC
IO1
IO1
V4
NC
NC
IO1
IO1
V5
GND
CCLK
GND
CCLK
GND
CCLK
GND
CCLK
V6
Document #: 38-03039 Rev. *H
Page 74 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
V7
CY39050
IO2
CY39100
IO2
CY39165
IO2
CY39200
IO2
V8
NC
IO2
IO2
IO2
V9
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
W1
IO2
IO2
IO2
IO2
NC
VCC
VCC
VCC
VCCIO3
IO3
VCCIO3
IO3
VCCIO3
IO3
VCCIO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
GND
NC
GND
NC
GND
IO4
GND
IO4
NC
NC
IO4
IO4
NC
NC
IO4
IO4
NC
NC
IO4
IO4
NC
NC
IO/VREF1
VCCIO1
IO1
IO/VREF1
VCCIO1
IO1
W2
VCCIO1
NC
VCCIO1
NC
W3
W4
GND
Reset
IO2
GND
Reset
IO2
GND
Reset
IO2
GND
Reset
IO2
W5
W6
W7
NC
IO2
IO2
IO2
W8
IO2
IO2
IO2
IO2
W9
NC
IO/VREF2
IO/VREF2
IO2
IO/VREF2
IO/VREF2
IO2
IO/VREF2
IO/VREF2
IO2
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y1
NC
IO2
IO2
IO2
IO2
IO2
NC
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
NC
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO3
IO3
IO3
GND
NC
GND
NC
GND
IO4
GND
IO4
VCCIO4
NC
VCCIO4
NC
VCCIO4
IO/VREF4
IO2
VCCIO4
IO/VREF4
IO2
NC
NC
Y2
NC
NC
IO2
IO2
Y3
NC
NC
IO2
IO2
Y4
IO2
IO2
IO2
IO2
Y5
IO2
IO2
IO2
IO2
Y6
IO2
IO2
IO2
IO2
Document #: 38-03039 Rev. *H
Page 75 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
Y7
CY39050
IO2
CY39100
IO2
CY39165
IO2
CY39200
IO2
Y8
NC
IO2
IO2
IO2
Y9
NC
IO2
IO2
IO2
Y10
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
Y11
Y12
IO3
IO3
IO3
IO3
Y13
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
IO/VREF3
IO3
Y14
Y15
IO3
IO3
IO3
IO3
Y16
IO3
IO3
IO3
IO3
Y17
IO3
IO3
IO3
IO3
Y18
NC
IO3
IO3
IO3
Y19
NC
IO3
IO3
IO3
Y20
NC
NC
NC
IO3
Y21
NC
NC
NC
IO3
Y22
NC
NC
NC
IO3
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB1
AB2
AB3
AB4
GND
GND
NC
GND
GND
NC
GND
GND
IO2
GND
GND
IO2
VCCIO2
IO/VREF2
IO2
VCCIO2
IO/VREF2
IO2
VCCIO2
IO/VREF2
IO2
VCCIO2
IO/VREF2
IO2
NC
IO2
IO2
IO2
IO2
IO2
IO2
IO2
NC
NC
VCCIO2
IO2
VCCIO2
IO2
NC
IO2
IO2
IO2
IO2
IO2
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
NC
VCCIO3
IO3
VCCIO3
IO3
IO3
IO3
NC
IO3
IO3[20]
IO3[20]
IO/VREF3
VCCIO3
NC
IO3
NC
IO3
IO3
IO/VREF3
VCCIO3
NC
IO/VREF3
VCCIO3
NC
IO/VREF3
VCCIO3
IO3
GND
GND
GND
GND
NC
GND
GND
GND
GND
NC
GND
GND
GND
GND
IO/VREF2
IO/VREF2
GND
GND
GND
GND
IO/VREF2
IO/VREF2
NC
NC
Note:
20. These I/Os have a slightly higher tPD (propagation delay) than the rest of the pins. The use of these pins on the same packages of different densities or the
pins in the same relative position in smaller or larger FBGAs for signals with critical timing should be avoided. When first implementing a design in these
packages, the timing-driven routing of Warp 6.2 and later versions will ensure these pins are avoided when routing critical signal.
Document #: 38-03039 Rev. *H
Page 76 of 86
Delta39K™ ISR™
CPLD Family
Table 14. 484 FBGA Pin Table (continued)
Pin
CY39050
IO2
CY39100
IO2
CY39165
IO2
CY39200
IO2
AB5
AB6
IO2
IO2
IO2
IO2
AB7
IO2
IO2
IO2
IO2
AB8
NC
IO2
IO2
IO2
AB9
NC
IO2
IO2
IO2
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
NC
IO2
IO2
IO2
GND
GND
IO3
GND
GND
IO3
GND
GND
IO3
GND
GND
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO3
IO3
IO3
IO3
IO3
IO3
IO3
NC
IO3
IO3
IO3
NC
NC
NC
IO/VREF3
IO3
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table
Pin
A24
A25
A26
B1
CY39100
NC
CY39165
NC
CY39200
IO6
Pin
A1
CY39100
GND
NC
CY39165
GND
NC
CY39200
GND
NC
NC
NC
NC
A2
GND
NC
GND
NC
GND
NC
A3
NC
IO7
IO7
A4
NC
IO7
IO7
B2
GND
NC
GND
IO7
IO7
IO7
NC
GND
IO7
A5
NC
IO7
IO7
B3
A6
NC
VCCIO7
IO7
VCCIO7
IO7
B4
NC
IO7
A7
NC
B5
NC
IO7
A8
NC
IO7
IO7
B6
NC
NC
A9
NC
IO7
IO7
B7
NC
IO7
IO7
IO7
IO7
IO7
IO7
GND
GND
NC
IO7
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
NC
NC
NC
B8
NC
IO7
NC
VCCIO7
NC
VCCIO7
NC
B9
NC
IO7
NC
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
NC
IO7
GND
GND
NC
GND
GND
NC
GND
GND
NC
NC
IO7
NC
IO7
GND
GND
NC
GND
GND
IO6
NC
VCCIO6
NC
VCCIO6
NC
NC
NC
NC
IO6
NC
NC
IO6
NC
NC
IO6
NC
NC
IO6
NC
NC
IO6
NC
NC
IO6
NC
VCCIO6
NC
VCCIO6
IO6
NC
NC
IO6
NC
NC
NC
IO6
NC
NC
IO6
NC
NC
IO/VREF6
Document #: 38-03039 Rev. *H
Page 77 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
B22
B23
B24
B25
B26
C1
CY39100
NC
CY39165
NC
CY39200
IO6
Pin
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
CY39100
IO6
CY39165
IO6
CY39200
IO6
NC
NC
IO6
IO6
IO6
IO6
NC
NC
NC
NC
VCCIO6
IO/VREF6
IO6[20]
IO6
VCCIO6
IO/VREF6
IO6
GND
NC
GND
NC
GND
NC
IO/VREF6
IO6
NC
NC
NC
IO6
IO6
C2
NC
NC
NC
IO6
IO6
IO6
C3
GND
GND
NC
GND
GND
IO/VREF7
IO/VREF7
IO7
GND
GND
IO/VREF7
IO/VREF7
IO7
VCCIO6
NC
VCCIO6
NC
VCCIO6
IO6
C4
C5
GND
GND
NC
GND
GND
NC
GND
GND
NC
C6
NC
C7
IO7
C8
IO7
IO7
IO7
NC
NC
NC
C9
IO7
IO7
IO7
NC
NC
NC
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
IO7
IO7
IO7
E2
NC
NC
NC
IO7
IO7
IO7
E3
NC
IO7
IO7
IO7
IO7
IO7
E4
NC
IO7
IO7
GND
GND
IO6
GND
GND
IO6
GND
GND
IO6
E5
NC
IO7
IO7
E6
IO7
IO7
IO7
E7
IO7
IO7
IO7
IO6
IO6
IO6
E8
IO7
IO7
IO7
IO6
IO6[20]
IO6[20]
IO6
IO6
E9
IO7
IO7
IO7
IO6
IO6
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
F1
IO7
IO7
IO7
IO6
IO6
IO7
IO7
IO7
IO6
IO6
IO6
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
NC
NC
IO/VREF6
IO6
NC
NC
IO6
IO6
IO6
GND
GND
NC
GND
GND
NC
GND
GND
NC
IO/VREF6
IO6
IO/VREF6
IO6
IO6[20]
IO6[20]
IO6
IO/VREF6
IO6
IO6
IO6
NC
NC
NC
IO6
IO6
NC
NC
NC
IO6
IO6
D2
NC
NC
NC
IO6
IO6
IO6
D3
GND
GND
NC
GND
GND
IO7
GND
GND
IO7
IO6
IO6
IO6
D4
NC
NC
IO6
D5
NC
NC
IO6
D6
VCCIO7
IO7
VCCIO7
IO7
VCCIO7
IO7
NC
NC
IO6
D7
NC
NC
NC
D8
IO7
IO7
IO7
NC
NC
NC
D9
IO7
IO7
IO7
NC
NC
NC
D10
D11
D12
D13
IO/VREF7
NC
IO/VREF7
VCCIO7
IO7
IO/VREF7
VCCIO7
IO7
F2
NC
NC
NC
F3
NC
IO/VREF0
VCCIO0
IO0
IO/VREF0
VCCIO0
IO0
IO7
F4
VCCIO0
NC
IO7
IO7
IO7
F5
Document #: 38-03039 Rev. *H
Page 78 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
F6
CY39100
GND
IO7
CY39165
GND
IO7
CY39200
GND
IO7
Pin
G24
G25
G26
H1
CY39100
NC
CY39165
IO5
CY39200
IO5
F7
NC
NC
NC
F8
IO7
IO7
IO7
NC
NC
NC
F9
IO7
IO7
IO7
NC
NC
NC
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
IO7
IO7
IO7
H2
NC
NC
NC
IO/VREF7
IO/VREF7
IO6/Lock
IO6
IO/VREF7
IO/VREF7
IO6/Lock
IO6
IO/VREF7
IO/VREF7
IO6/Lock
IO6
H3
NC
IO0
IO0
H4
IO0
IO0
IO0
H5
IO0
IO0
IO0
H6
IO0
IO0
IO0
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
IO/VREF6
IO/VREF6
IO6
H7
IO0
IO0
IO0
H8
GND
IO7
GND
IO7
GND
IO7
H9
IO6
IO6
IO6
H10
H11
H12
H13[19]
H14[19]
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
J1
IO7
IO7
IO7
IO6
IO6
IO6
VCCIO7
VCCIO7
IO7
VCCIO7
VCCIO7
IO7
VCCIO7
VCCIO7
IO7
IO6
IO6
IO6
GND
NC
GND
IO5
GND
IO5
IO6
IO6
IO6
VCCIO5
NC
VCCIO5
IO/VREF5
NC
VCCIO5
IO/VREF5
NC
VCCIO6
VCCIO6
IO6
VCCIO6
VCCIO6
IO6
IO6[20]
GND
TDI
VCCIO6
VCCIO6
IO6
NC
NC
NC
NC
IO6
IO6
NC
NC
NC
GND
TDI
GND
TDI
G2
NC
NC
NC
G3
NC
IO0
IO0
IO5
IO5
IO5
G4
NC
IO0
IO0
IO5
IO5
IO5
G5
NC
IO0
IO0
IO5
IO5
IO5
G6
IO0
IO0
IO0
NC
IO5
IO5
G7
GND
IO7
GND
IO7
GND
IO7
NC
NC
NC
G8
NC
NC
NC
G9
IO7
IO7
IO7
NC
NC
NC
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
IO7
IO7
IO7
J2
NC
NC
NC
VCCIO7
VCC
VCCIO7
VCC
VCCIO7
VCC
J3
NC
IO0
IO0
J4
IO0
IO0
IO0
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6[20]
IO6
IO/VREF7
IO/VREF6
VCCPLL
VCCIO6
IO6
J5
IO0
IO0
IO0
J6
IO0
IO0
IO0
J7
IO0
IO0
IO0
J8
IO0
IO0
IO0
J9
GND
IO7
GND
IO7
GND
IO7
IO6
IO6
J10
J11
J12
J13[19]
J14[19]
J15
IO6
IO6
IO6
IO/VREF7
IO7
IO/VREF7
IO7
IO/VREF7
IO7
GND
TDO
NC
GND
TDO
GND
TDO
IO5
IO7
IO7
IO7
IO5
IO6
IO6
IO6
NC
IO5
IO5
IO6
IO6
IO6
Document #: 38-03039 Rev. *H
Page 79 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
J16
J17
J18
J19
J20
J21
J22
J23
J24
J25
J26
K1
CY39100
IO/VREF6
IO6
CY39165
IO/VREF6
IO6
CY39200
IO/VREF6
IO6
Pin
L8
CY39100
VCCIO0
IO/VREF0
IO0
CY39165
VCCIO0
IO/VREF0
IO0
CY39200
VCCIO0
IO/VREF0
IO0
L9
GND
TCLK
IO5
GND
TCLK
IO5
GND
TCLK
IO5
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
M1
IO7
IO7
IO7
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
GCTL3
GCLK3
GCTL2
GCLK2
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
NC
IO5
IO5
NC
NC
NC
IO5
IO5
IO5
NC
NC
NC
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
IO/VREF5
VCCIO5
VCCJTAG
IO5
NC
NC
NC
K2
NC
NC
NC
K3
NC
IO0
IO0
K4
IO0
IO0
IO0
IO/VREF5
NC
IO/VREF5
VCCIO5
IO/VREF5
NC
IO/VREF5
VCCIO5
IO/VREF5
NC
K5
IO0
IO0
IO0
K6
IO0
IO0
IO0
NC
K7
IO0
IO0
IO0
NC
K8
IO0
IO0
IO0
NC
NC
NC
K9
IO0
IO0
IO0
NC
NC
NC
K10
K11
K12
K13[19]
K14[19]
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
L1
IO7
IO7
IO7
M2
NC
NC
NC
IO7
IO7
IO7
M3
NC
IO0
IO0
IO7
IO7
IO7
M4
IO0
IO0
IO0
IO7
IO7
IO7
M5
IO0
IO0
IO0
IO6
IO6
IO6
M6
IO0
IO0
IO0
IO6
IO6
IO6
M7
VCC
VCC
VCC
IO6
IO6[20]
TMS
IO5
IO6
M8
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
VCCIO0
IO/VREF0
IO0
TMS
IO5
TMS
IO5
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
IO5
IO5
IO5
GCTL0
GND
GND
GND
GND
GCTL1
IO5
GCTL0
GND
GCTL0
GND
IO5
IO5
IO5
IO5
IO5
IO5
GND
GND
IO5
IO5
IO5
GND
GND
IO5
IO5
IO5
GND
GND
NC
IO5
IO5
GCTL1
IO5
GCTL1
IO5
NC
NC
NC
NC
NC
NC
IO/VREF5
VCCIO5
VCC
IO/VREF5
VCCIO5
VCC
IO/VREF5
VCCIO5
VCC
NC
NC
NC
L2
NC
NC
NC
L3
NC
IO/VREF0
VCCIO0
IO/VREF0
IO0
IO/VREF0
VCCIO0
IO/VREF0
IO0
IO5
IO5
IO5
L4
NC
IO5
IO5
IO5
L5
IO/VREF0
IO0
IO5
IO5
IO5
L6
NC
IO5
IO5
L7
VCC
VCC
VCC
NC
NC
NC
Document #: 38-03039 Rev. *H
Page 80 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
M26
N1
CY39100
NC
CY39165
NC
CY39200
NC
Pin
P18[19]
P19[19]
P20
P21
P22
P23
P24
P25
P26
R1
CY39100
IO4
CY39165
IO4
CY39200
IO4
GND
GND
GND
IO0
GND
GND
GND
IO0
GND
GND
GND
IO0
IO4
IO4
IO4
N2
IO5
IO5
IO5
N3
IO5
IO5
IO5
N4
IO4
IO4
IO4
N5
IO0
IO0
IO0
IO4
IO4
IO4
N6[19]
N7[19]
N8[19]
N9
IO0
IO0
IO0
GND
GND
GND
NC
GND
GND
GND
NC
GND
GND
GND
NC
IO0
IO0
IO0
IO0
IO0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
IO/VREF0
IO0
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19[19]
N20[19]
N21[19]
N22
N23
N24
N25
N26
P1
R2
NC
NC
NC
GCLK0
GND
GND
GND
GND
GCLK1
IO5
GCLK0
GND
GND
GND
GND
GCLK1
IO5
GCLK0
GND
GND
GND
GND
GCLK1
IO5
R3
NC
IO1
IO1
R4
IO1
IO1
IO1
R5
IO1
IO1
IO1
R6
IO1
IO1
IO1
R7
VCCPRG
VCCIO1
IO/VREF1
IO1
VCCPRG
VCCIO1
IO/VREF1
IO1
VCCPRG
VCCIO1
IO/VREF1
IO1
R8
R9
IO/VREF5
IO5
IO/VREF5
IO5
IO/VREF5
IO5
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
T1
IO1
IO1
IO1
IO5
IO5
IO5
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
IO5
GND
GND
GND
GND
GND
GND
IO1
GND
GND
GND
GND
GND
GND
IO1
GND
GND
GND
GND
GND
GND
IO1
IO4
IO4
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
IO/VREF4
VCCIO4
VCCPRG
IO4
P2
P3
P4
IO4
IO4
IO4
P5
IO1
IO1
IO1
IO4
IO4
IO4
P6
IO1
IO1
IO1
NC
IO4
IO4
P7
IO1
IO1
IO1
NC
NC
NC
P8[19]
P9[19]
P10[19]
P11
IO1
IO1
IO1
NC
NC
NC
IO1
IO1
IO1
NC
NC
NC
IO1
IO1
IO1
T2
NC
NC
NC
IO1
IO1
IO1
T3
NC
IO/VREF1
VCCIO1
IO/VREF1
IO1
IO/VREF1
VCCIO1
IO/VREF1
IO1
P12
P13
P14
P15
P16
P17[19]
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
GND
GND
GND
GND
IO4
T4
NC
T5
IO/VREF1
IO1
T6
T7
VCC
VCC
VCC
T8
VCCIO1
IO/VREF1
VCCIO1
IO/VREF1
VCCIO1
IO/VREF1
IO4
IO4
IO4
T9
Document #: 38-03039 Rev. *H
Page 81 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
T10
T11
T12
T13[19]
T14[19]
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
U1
CY39100
CY39165
CY39200
Pin
V2
CY39100
NC
CY39165
NC
CY39200
NC
VCCCNFG
VCCCNFG
VCCCNFG
Config_Done Config_Done Config_Done
V3
NC
IO1
IO1
IO2
IO2
IO2
IO2
IO2
IO2
V4
IO1
IO1
IO1
V5
IO1
IO1
IO1
IO3
IO3
IO3
V6
IO/VREF1
IO1
IO/VREF1
IO1
IO/VREF1
IO1
IO3
IO3
IO3
V7
IO3
IO3
IO3
V8
IO1
IO1
IO1
IO4
IO4
IO4
V9
GND
MSEL
IO/VREF2
IO/VREF2
IO2
GND
MSEL
IO/VREF2
IO/VREF2
IO2
GND
MSEL
IO/VREF2
IO/VREF2
IO2
IO/VREF4
VCCIO4
VCC
IO4
IO/VREF4
VCCIO4
VCC
IO4
IO/VREF4
VCCIO4
VCC
IO4
V10
V11
V12
V13[19]
V14[19]
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
W1
IO/VREF4
NC
IO/VREF4
VCCIO4
IO/VREF4
NC
IO/VREF4
VCCIO4
IO/VREF4
NC
IO3
IO3
IO3
[20]
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
NC
NC
NC
NC
NC
GND
IO4
GND
IO4
GND
IO4
NC
NC
NC
U2
NC
NC
NC
IO4
IO4
IO4
U3
NC
IO1
IO1
IO/VREF4
IO4
IO/VREF4
IO4
IO/VREF4
IO4
U4
NC
IO1
IO1
U5
IO1
IO1
IO1
IO4
IO4
IO4
U6
IO1
IO1
IO1
NC
IO4
IO4
U7
IO1
IO1
IO1
NC
NC
NC
U8
IO1
IO1
IO1
NC
NC
NC
U9
Data
Reconfig
IO2
Data
Reconfig
IO2
Data
Reconfig
IO2
NC
NC
NC
U10
U11
U12
U13[19]
U14[19]
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V1
W2
NC
NC
NC
W3
NC
IO1
IO1
IO2
IO2
IO2
W4
IO1
IO1
IO1
IO2
IO2
IO2
W5
IO1
IO1
IO1
IO3
IO3
IO3
W6
IO1
IO1
IO1
IO3
IO3
IO3
W7
IO1
IO1
IO1
IO3
IO3
IO3
W8
GND
CCE
IO2
GND
CCE
IO2
GND
CCE
IO2
IO3
IO3
IO3
W9
IO4
IO4
IO4
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
IO4
IO4
IO4
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
VCCIO2
VCCIO2
IO2
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO4
IO2
IO2
IO2
NC
IO4
IO4
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
VCCIO3
VCCIO3
IO3
NC
IO4
IO4
NC
NC
NC
NC
NC
NC
IO3
IO3
IO3
NC
NC
NC
GND
GND
GND
Document #: 38-03039 Rev. *H
Page 82 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
W20
W21
W22
W23
W24
W25
W26
Y1
CY39100
IO4
CY39165
IO4
CY39200
IO4
Pin
CY39100
IO/VREF2
IO2
CY39165
IO/VREF2
IO2
CY39200
IO/VREF2
IO2
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AB1
IO4
IO4
IO4
IO4
IO4
IO4
IO2
IO2
IO2
IO4
IO4
IO4
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
IO/VREF3
IO/VREF3
IO3
NC
IO4
IO4
NC
NC
NC
NC
NC
NC
IO3
IO3
IO3
NC
NC
NC
IO3
IO3
IO3
Y2
NC
NC
NC
IO3
IO3
IO3
Y3
NC
IO1
IO1
GND
NC
GND
IO4
GND
IO4
Y4
NC
IO1
IO1
Y5
NC
IO1
IO1
VCCIO4
NC
VCCIO4
IO/VREF4
NC
VCCIO4
IO/VREF4
NC
Y6
IO1
IO1
IO1
Y7
GND
CCLK
IO2
GND
CCLK
IO2
GND
CCLK
IO2
NC
Y8
NC
NC
NC
Y9
NC
NC
NC
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
IO2
IO2
IO2
AB2
NC
NC
NC
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
VCCCNFG
VCCIO2
IO2
AB3
NC
IO2
IO2
AB4
NC
IO2
IO2
AB5
NC
IO2
IO2
IO2
IO2
IO2
AB6
IO2
IO2
IO2
VCC
VCCIO3
IO3
VCC
VCCIO3
IO3
VCC
VCCIO3
IO3
AB7
IO2
IO2
IO2
AB8
IO2
IO2
IO2
AB9
IO2
IO2
IO2
IO3
IO3
IO3
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
IO2
IO2
IO2
IO3
IO3
IO3
IO2
IO2
IO2
GND
IO4
GND
IO4
GND
IO4
IO/VREF2
IO2
IO/VREF2
IO2
IO/VREF2
IO2
NC
IO4
IO4
IO3
IO3
IO3
NC
IO4
IO4
IO/VREF3
IO3
IO/VREF3
IO3
IO3[20]
IO/VREF3
IO3
NC
IO4
IO4
NC
NC
NC
IO3
IO3
NC
NC
NC
IO3
IO3
IO3
NC
NC
NC
IO3
IO3
IO3
NC
NC
NC
IO3
IO3
IO3
NC
IO/VREF1
VCCIO1
IO1
IO/VREF1
VCCIO1
IO1
IO3
IO3
IO3
VCCIO1
NC
NC
NC
IO3
NC
NC
IO3
GND
Reset
IO2
GND
Reset
IO2
GND
Reset
IO2
NC
NC
IO3
NC
NC
NC
NC
NC
NC
IO2
IO2
IO2
NC
NC
NC
IO2
IO2
IO2
AC2
NC
NC
NC
IO/VREF2
IO/VREF2
IO/VREF2
AC3
GND
GND
GND
Document #: 38-03039 Rev. *H
Page 83 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
GND
NC
CY39165
GND
CY39200
GND
IO2
Pin
AD22
AD23
AD24
AD25
AD26
AE1
CY39100
NC
CY39165
NC
CY39200
IO3
AC4
AC5
IO2
GND
GND
NC
GND
GND
NC
GND
GND
NC
AC6
VCCIO2
IO/VREF2
IO2
VCCIO2
IO/VREF2
IO2
VCCIO2
IO/VREF2
IO2
AC7
AC8
NC
NC
NC
AC9
IO2
IO2
IO2
NC
NC
NC
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
IO2
IO2
IO2
AE2
GND
NC
GND
IO2
GND
IO2
NC
VCCIO2
IO2
VCCIO2
IO2
AE3
IO2
AE4
NC
IO2
IO2
IO2
IO2
IO2
AE5
NC
IO2
IO2
IO3
IO3
IO3
AE6
NC
NC
NC
IO3
IO3
IO3
NC
VCCIO3
IO3[20]
IO3[20]
IO3[20]
VCCIO3
IO3
AE7
AE8
NC
NC
NC
NC
NC
NC
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IO2
IO2
IO2
IO2
IO2
IO2
GND
GND
NC
IO2
IO2
IO3
IO3
IO3
AE9
IO2
IO3
IO3
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
IO2
[20]
IO/VREF3
VCCIO3
NC
IO/VREF3
VCCIO3
NC
IO/VREF3
VCCIO3
IO3
IO2
IO2
GND
GND
IO3
GND
GND
NC
GND
GND
NC
GND
GND
NC
NC
IO3
NC
NC
NC
NC
IO3
NC
NC
NC
NC
IO3
AD2
NC
NC
NC
NC
IO3
AD3
GND
GND
NC
GND
GND
IO/VREF2
IO/VREF2
IO2
GND
GND
IO/VREF2
IO/VREF2
IO2
NC
IO3
AD4
NC
IO/VREF3
IO3
AD5
NC
AD6
NC
NC
IO3
AD7
IO2
NC
NC
AD8
IO2
IO2
IO2
GND
NC
GND
NC
AD9
IO2
IO2
IO2
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
IO2
IO2
IO2
GND
NC
GND
NC
IO2
IO2
IO2
AF2
IO2
IO2
IO2
AF3
IO2
IO2
IO2
VCCIO2
IO2
IO2
IO2
NC
IO2
GND
GND
IO3
GND
GND
IO3
GND
GND
IO3
AF4
IO2
AF5
IO2
AF6
VCCIO2
IO2
IO3
IO3
IO3
AF7
IO3
IO3[20]
IO3[20]
IO3
IO3
AF8
IO2
IO3
IO3
AF9
IO2
IO3
IO3
AF10
AF11
AF12
NC
IO3
IO3
IO3
VCCIO2
NC
VCCIO2
NC
NC
NC
IO/VREF3
Document #: 38-03039 Rev. *H
Page 84 of 86
Delta39K™ ISR™
CPLD Family
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
GND
GND
NC
CY39165
GND
GND
NC
CY39200
GND
GND
NC
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
NC
VCCIO3
NC
VCCIO3
NC
NC
NC
NC
IO3
NC
NC
IO3
NC
NC
IO3
NC
VCCIO3
NC
VCCIO3
IO3
NC
NC
NC
IO3
NC
NC
IO3
NC
NC
NC
GND
GND
GND
Windows 95, Windows 98, Windows 2000, Windows XP, and Windows NT are trademarks of Microsoft Corporation. ZBT is a
trademark of IDT. QDR is a trademark of Micron, IDT, and Cypress Semiconductor. Warp is a registered trademark, and NoBL,
Programmable Interconnect Matrix, PIM, Spread Aware, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, “CPLDs at FPGA
Densities,” True Vertical Migration, and Delta39K are trademarks, of Cypress Semiconductor. All product and company names
mentioned in this document are the trademarks of their respective holders.
Document #: 38-03039 Rev. *H
Page 85 of 86
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Delta39K™ ISR™
CPLD Family
Document History Page
Document Title: Delta39K™ ISR™ CPLD Family CPLDs at FPGA Densities™
Document Number: 38-03039
Issue
Date
Orig. of
Change
REV. ECN NO.
Description of Change
Change from Spec #: 38-00830 to 38-03039
**
106503
107625
05/30/01
07/11/01
SZV
RN
*A
Deleted 39K15 device and the associated -250-MHz bin specs
Deleted 144FBGA package and associated part numbers
Changed ESD spec from “MIL-STD-883” to “JEDEC EIA/JESD22-A114-A”
Changed the Prime bin for 39K50 and 39K30 from “MHz” to “233 MHz”
Changed the part ordering information accordingly
Updated the -233-MHz timing specs to match modified timing specs achieved by
design (main affected params: tPD, tMCCO, tIOS, tSCS, tSCS2, fMAX2, tCLMAA
,
tCLMCYC2, tCHMCYC2, tCHMCLK
)
Updated I/O standard Timing Delay Specs and changed the default I/O standard
from 3.3V PCI to LVCMOS
Added paragraph about Delta39K being CompactPCI hot swap Ready
Added X8 mode in the PLL description
Added Standby ICC spec
Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead
of CY3LV020
*B
109681
11/16/01
RN
Updated Delta39K family offering
Modified PLL timing parameters tDWSA, tDWOSA, tMCCJ, andtLOCK. AddedtINDUTY
parameter
Deleted exception to CompactPCI Hot Swap compliance regarding “PCI
buffers....”
Added reference to app note “Hot Socketing Delta39K”
Revised CompactPCI Hot Swap Specification R1.0 to be R2.0
*C
*D
112376
112946
12/21/01
04/04/02
RN
RN
Combined with spec# 38-03040
Updated pin tables for 39K30 (208PQFP, 256FBGA)
Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA)
Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL
Added PLL parameters (fPLLVCO, PSAPLLI, fMPPLI
)
Added and updated Storage Temperature for 39K200-208EQFP
Changed the Icc0 spec for 39K165 and 39K200
Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin
Updated Input and Output Standard Timing Delay Adjustment table
Removed Self Boot Industrial parts from the offering
Removed Delta39K165Z (1.8V) from the offering
Removed 144-FBGA package offering
Added self-boot Flash Memory endurance and data retention data
Added Family, Package, and Density Migration section
Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs
*E
117518
10/04/02
OOR
Changed data sheet status from Preliminary to Final
Added note 7 to DC Characteristics
*F
121063
122543
11/06/02
12/10/02
DSG
RN
Updated spec 51-85103 (MG388 package drawing) to rev. *C
*G
Changed the definition of following pins on CY39030 -256FBGA package:
Pin A10: From IO/Vref7 to IO/Vref6
Pin B7: From IO/Vref6 to VCC
Added Table to identify Bank Location of Global Clock and Global Control Pins
*H
128684
08/04/03
OOR
Removed all “Z” parts (1.8V)
Referenced EEPROM to ATMEL part number
Document #: 38-03039 Rev. *H
Page 86 of 86
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