CY39100V676A-200MBC [CYPRESS]

Loadable PLD, 7.5ns, 1536-Cell, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676;


型号：	CY39100V676A-200MBC
厂家：	CYPRESS
描述：	Loadable PLD, 7.5ns, 1536-Cell, CMOS, PBGA676, 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676 输入元件可编程逻辑
文件：	总3页 (文件大小：73K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY

Using the Delta39K™ ISR™ Prototype Board

Introduction

This application note is intended to provide instruction in the

use of the Delta39K™ ISR™ Prototype Board. This board

serves two major purposes. First, it provides a board with

Cypress Delta39K and Ultra37000™ CPLDs already con-

nected to take advantage of In-System Reprogrammability™

(ISR). This allows designers who are unfamiliar with ISR to

investigate it as a possible device programming solution.

Second, it permits designers who need custom logic to more

easily utilize Cypress CPLDs in prototype designs. After pro-

gramming the Delta39K and/or Ultra37000 devices on the

ISR Prototype Board, connections can be made between the

ISR Prototype Board and the designer’s board using the pro-

vided header strips. This gives a designer the ability to verify

the functionality of the CPLDs within a system before design-

ing them into that system.

D esign

Files

S ynthesis and Fitting

O utput D ata Files

(H E X / JE D )

This application note should familiarize the reader in the use

of the Delta39K ISR Prototype Board and highlight the

board’s features. Topics of discussion will include connecting

the programming cable, connecting power supplies to the

board, using the jumpers on the board, and making connec-

tions between the Delta39K ISR Prototype Board and other

systems.

S T AP L

C om poser

In-System Reprogrammability allows Complex Programma-

ble Logic Devices (CPLDs) to be reprogrammed after being

soldered in place on a printed circuit board. The Delta39K ISR

Prototype Board is designed to support one Delta39K and

Ultra37000 CPLD. The first device is a 100,000 gate 3.3V

Delta39K100 in a 208-pin PQFP package. The second device

is a 256 macrocell 3.3V Ultra37000 in a 160-pin TQFP pack-

age.

S T AP L P rogram m ing

Files

S T AP L

P layer

ISR programming of the CPLDs follows the IEEE 1149.1 stan-

dard Test Access Port and Boundary Scan architecture,

which supports chaining more than one IEEE1149.1/

JTAG -compliant devices together. ISR Programming Soft-

ware supports daisy-chain programming of multiple Cypress

CPLDs.

D elta39K / U ltra37000

D evice

Delta39K and Ultra37000 CPLDs support the STAPL stan-

dard as the solution for ISR programming. STAPL is an inter-

preted language that provides a standard for programming

PLDs through the JTAG interface. The CPLDs on the

Delta39K ISR Prototype Board are programmed through an

ISR cable using the Cypress ISR Programming Software. To

learn more about the ISR features of the Delta39K and

Ultra37000 family, refer to Cypress application notes at our

website (http://www.cypress.com/pld/pldappnotes.html)

Figure 1. Cypress CPLD Design Flow

synthesized into logic. Fitter software is responsible for map-

ping the logic into the targeted device. Both synthesis and

fitting are accomplished from the Warp™ environment. The

result of the fitting process is a compressed Intel Hex file

(Delta39K) or a JEDEC file (Ultra37000) that contains the in-

formation about how the logic of the design will be implement-

ed in the device. STAPL Composer software uses the output

files from Warp to produce STAPL standard programming

files. A STAPL file contains both the programming data and

programming algorithm for the device it targets. A STAPL

Player is then used to program the CPLDs using the STAPL

Design Flow

In order to use the Delta39K ISR Prototype Board, it is impor-

tant to understand how it fits into the ISR design flow. The

basic design flow for the Cypress CPLD is shown in Figure 1.

Designs are typically specified in VHDL or Verilog code. This

code can either be written by the designer or generated from

schematics. Once the code for the design is complete, it is

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

January 19, 2001

Using the Delta39K ISR Prototype Board

PRELIMINARY

ISR Programming Cable

To Parallel

Port

To 10-pin Connector (J2)

On Board

Device 2

J2 J3

Device 1

JP2

Figure 2. Connecting the ISR Programming Cable

files. The Cypress ISR Programming software includes a

STAPL Composer and a STAPL Player for programming de-

vices on a board through a programming cable attached to a

PC parallel port.

Pin 1

GND JTAG

ISR*

TDI

TDO

GND

The design flow shown in Figure 1 should be followed to pro-

totype designs with the Delta39K ISR Prototype Board. First,

design files need to be compiled to produce output files that

target either or both devices on the board. These output files

are then used to create STAPL programming files using the

STAPL Composer provided in the Cypress ISR Programming

Software. At this point the Delta39K ISR Prototype Board is

connected to a PC using an ISR programming cable. Then

the STAPL Player provided in the Cypress ISR Programming

Software programs the CPLDs on the board using the infor-

mation in the STAPL files.

TMS

N/C

TCK

Figure 3. View Looking into ISR Cable 10-pin Connector

Delta39K ISR Prototype Board. A wall transformer with the

appropriate female plug or a separate female power plug can

be obtained from an electronic components distributor. The

power jack is labeled V . The power LED labeled DS1 indi-

Using the Delta39K ISR Prototype Board

cates when power is applied to V . The Delta39K and

Connecting the Programming Cable

Ultra37K CPLDs on the board operate with a 3.3-volt supply

which must be supplied by V

The CPLDs on the Delta39K ISR Prototype Board are pro-

grammed using a PC as shown in Figure 2. The programming

cable connects the parallel port of the PC to the 10-pin con-

nector (J2) on the board. Cypress offers two cables for pro-

gramming the CPLDs on this board—the UltraISRPCCABLE

and the C3ISRPCCABLE. Either cable will be able to program

both devices.

Existing Board Connections

Connections necessary for ISR programming are already

provided on the Delta39K ISR Prototype Board. Power to the

board is supplied through the power jack at the edge of the

board. A 0.1-µF decoupling capacitor is connected to the

power supply to eliminate noise that may affect device oper-

Both of the cables have a female connector which plugs into

the 10-pin, 2 x 5, open header connector provided on the

Delta39K ISR Prototype Board. The view looking into the end

of the programming cable is shown in Figure 3. When plug-

ging the cable into the connector on the board, the key on the

cable should be at the top away from the board.

ation. Additionally, selected V

vice are connected to a 0.01-µF decoupling capacitor.

and V

pins of each de-

CCO

The JTAG interface used for ISR programming uses both par-

allel connections, for TCK, TMS, and JTAG , and serial con-

nections, for TDI and TDO. Device 1 does not have a JTAG

pin since its ISR pins are single-function and therefore does

not need JTAG to select between pin functions. Table 1

The programming cable should be disconnected from the

board before connecting the power supply.

also shows the parallel ISR connections made to each device

site. The serial ISR connections can be set to include either

or both CPLDs by configuring the Daisy Chain Jumpers.

Providing Board Power

The power jack accepts a 2.5-millimeter female plug. A

3.3-volt wall transformer can be used to provide power to the

Using the Delta39K ISR Prototype Board

PRELIMINARY

The three possible configurations are shown in Table 2. The

Cypress application notes, “Designing with Cypress In-Sys-

tem Reprogrammable (ISR) CPLDs for PC Cable Program-

ming” and “Cascading ISR Devices,” provide more informa-

tion about chaining together JTAG devices.

2.54 mm

Table 1. Parallel ISR Connections

Device 1 Pin

Number

Device 2 Pin

Number

JTAG Pin

TCK

157

TMS

162

JTAG

139

Table 2. Daisy Chain Jumper Configurations

Devices in Chain

Jumper Configuration

Device 1 only

A-B

C-E

Device 2 only

B-D

E-F

Device 1 and Device 2

A-B

C-D

E-F

0.64 mm SQ

Making Board Connections

Figure 4. Header Strip Dimensions

To facilitate making connections to the devices on the

Delta39K ISR Prototype Board, each device pin is connected

to one of the header strip sites surrounding each CPLD. The

header strips allow the Delta39K ISR Prototype Board to be

easily connected to another circuit board through a ribbon

cable. Other possible uses for the header strips include LEDs

and seven segment displays for monitoring outputs and

banks of DIP switches for providing inputs.

The 10-pin Header (J3) right next to the 10-pin ISR Header

will be used for future board’s features expansion.

For a complete list of pins information, please refer to each

device’s datasheet/pin list.

Conclusion

This application note highlights the features of the Delta39K

ISR Prototype Board. The board is designed to support one

Delta39K and one Ultra37000 CPLDs which may be pro-

grammed separately or together by configuring the board’s

jumpers. External logic or I/O devices may be connected to

the Delta39K ISR Prototype Board by using the header strips

that surround each device.

The Delta39K ISR Prototype Board provides designers with

a system already configured to take advantage of the ISR

capability of Delta39K CPLDs. The board allows designers

unfamiliar with In-System Reprogrammability to investigate

the Cypress ISR design flow without first designing a board

to support the JTAG interface. Designers may also use this

board to readily evaluate Cypress programmable logic in their

own prototype designs.

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY39100V676A-200MBC [CYPRESS]

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