CY39015Z144-125BBI [CYPRESS]
Loadable PLD, 10ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144;型号: | CY39015Z144-125BBI |
厂家: | CYPRESS |
描述: | Loadable PLD, 10ns, CMOS, PBGA144, 1 MM PITCH, FBGA-144 |
文件: | 总57页 (文件大小:1166K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Delta39K™ ISR™
CPLD Family
PRELIMINARY
CPLDs at FPGA Densities™
•Multiple I/O standards supported
Features
—LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2
•High density
(I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+
— 15K to 350K usable gates
— 256 to 5376 macrocells
— 92 to 520 maximum I/O pins
•Compatible with NOBL™, ZBT™, and QDR™ SRAMs
•Programmable slew rate control on each I/O pin
•User-Programmable Bus Hold capability on each I/O pin
•Fully PCI compliant (to 66 MHz 64-bit PCI spec rev2.2)
•Compact PCI hot swap compatible
•Multiple package/pinout offering across all densities
—144 to 676 pins in PQFP, BGA and FBGA packages
—Same pinout for 3.3V/2.5V and 1.8V devices
—Simplifies design migration across density
—Self-Boot™ solution in BGA and FBGA packages
•In-System Reprogrammable™ (ISR™)
— 12 Dedicated Inputs including 4 clock pins, 4 global
control signal pins and 4 JTAG interface pins for
reconfigurability
•Embedded Memory
— 40K to 840K bits embedded SRAM
• 32K to 672K bits of (single port) Cluster memory
• 8K to 168K bits of (dual port) Channel memory
•High speed - 250-MHz in-system operation
•AnyVolt™ interface
—JTAG-compliant on-board programming
— 3.3V, 2.5V and 1.8V VCC versions available
—Design changes don’t cause pinout changes
•IEEE1149.1 JTAG boundary scan
— 3.3V, 2.5V and 1.8V I/O capability on all versions
• Low Power Operation
— 0.18-µm 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
Development Software
— Standby current as low as 100 µA at 1.8V VCC
•Simple timing model
•Warp™
—IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing.
— Nopenaltyfor usingfull16product terms /macrocell
— No delay for single product term steering or sharing
•Flexible clocking
—Active-HDL FSM graphical finite state machine editor
—Active-HDL SIM post-synthesis timing simulator
—Architecture Explorer for detailed design analysis
—Static Timing Analyzer for critical path analysis
—Available on Windows 95, 98 & NT for $99
— 4 synchronous clocks per device
— 1 spread-aware PLL drives all 4 clock networks
— Locally generated Product Term clock
— Clock polarity control at each register
—Supports all Cypress Programmable Logic Products
•Carry-chain logic for fast and efficient arithmetic opera-
tions
Delta39K™ ISR CPLD Family Members
[2]
Standby ICC
Cluster Channel
memory memory Maximum
fMAX2 Speed-tPD
Pin-to-Pin
TA=25°C
Typical
Gates[1]
Device
39K15
Macrocells
256
(Kbits)
(Kbits)
I/O Pins
(MHz)
256
238
238
222
181
181
167
154
(ns)
6.5
7.0
7.0
7.5
8.5
8.5
8.5
9.0
3.3/2.5V
1.8V
8K–24K
16K–48K
32
8
134
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
10 mA
100 µA
200 µA
300 µA
600 µA
1250 µA
1250 µA
1500 µA
2100 µA
39K30
512
64
16
176
39K50
23K–72K
768
96
24
218
39K100
39K165
39K200
39K250
39K350
46K–144K
77K–241K
92K–288K
115K–361K
161K–505K
1536
2560
3072
3840
5376
192
320
384
480
672
48
302
80
386
96
428
120
168
470
520
Note:
1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used.
2. Standby ICC values are with PLL not utilized, no output load and stable inputs
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03039 Rev. **
Revised April 4, 2001
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Delta39K Speed Bins[3]
Device
39K15
250
222
200
181
167
154
125
X
83
X
X
X
X
X
X
X
X
X
39K30
X
X
X
39K50
X
39K100
39K165
39K200
39K250
39K350
X
X
X
X
X
X
X
X
X
X
Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs
Self-Boot Solution[4]
256-FBGA 388-BGA 484-FBGA
208-EQFP 144-FBGA 256-FBGA 484-FBGA 676-FBGA
676-FBGA
27x27 mm
1.0-mm
17x17 mm
1.0-mm
pitch
35x35 mm
1.27-mm
pitch
23x23 mm
28X28 mm
0.5-mm
pitch
13x13 mm
1.0-mm
pitch
17x17 mm
1.0-mm
pitch
23x23 mm
1.0-mm
pitch
27x27 mm
1.0-mm
pitch
1.0-mm pitch
Device
39K15
pitch
134
136
136
136
136
136
136
136
92
92
134
176
180
180
134
176
39K30
39K50
218
294
294
294
294
294
218
39K100
39K165
39K200
39K250
302
356
368
302
386
428
470
520
470
520
39K350
Notes:
3. Speed bins shown here are for Commercial operating range. Please refer to Delta39K Ordering Information on page 41 for Industrial range speed bins.
4. Self-Boot Solution integrates the boot PROM (Flash Memory) with Delta39K die inside the same package.
Document #: 38-03039 Rev. **
Page 2 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
PLL & Clock MUX
GCLK[3:0]
GCTL[3:0]
4
4
I/O Bank 7
I/O Bank 6
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
LB 0
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 6
LB 5
LB 4
LB 1
LB 2
LB 3
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
LB 2
PIM
LB 5
LB 3
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
LB 2
PIM
LB 5
LB 3
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
LB 2
PIM
LB 5
LB 3
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
I/O Bank 2
I/O Bank 3
Figure 1. Delta39K100 Block Diagram (3 Rows x 4 Columns) with I/O Bank Structure
Document #: 38-03039 Rev. **
Page 3 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
The Delta39KZ devices accept 1.8V on the VCC supply pins
directly. With Delta39K’s AnyVolt technology, the I/O pins can
be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devic-
es are 3.3V tolerant regardless of VCCIO or VCC settings.
General Description
The Delta39K family, based on a 0.18 µm, 6-layer metal
CMOS logic process, offers a wide range of high-density solu-
tions at unparalleled system performance. The Delta39K fam-
ily is designed to combine the high speed, predictable timing,
and ease of use of CPLDs with the high densities and low
power of FPGAs. With devices ranging from 15,000 to 350,000
usable gates, the family features devices ten times the size of
previously available CPLDs. Even at these large densities, the
Delta39K family is fast enough to implement a fully synthesiz-
able 64-bit, 66-MHz PCI core.
Device
39KV
39KZ
VCC
3.3V or 2.5V
1.8V
VCCIO
3.3V or 2.5V or 1.8V or 1.5V[5]
3.3V or 2.5V or 1.8V or 1.5V[5]
Global Routing Description
The routing architecture of the Delta39K is made up of hori-
zontal and vertical (H&V) routing channels. These routing
channels allow signals from each of the Delta39K architectural
components to communicate with one another. In addition to
the horizontal and vertical routing channels that interconnect
the I/O banks, channel memory blocks, and logic block clus-
ters, each LBC contains a Programmable Interconnect Matrix
(PIM™), which is used to route signals among the logic blocks
and the cluster memory blocks.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H&V) routing chan-
nels. Each LBC features eight individual Logic Blocks (LB) and
two cluster memory blocks. Adjacent to each LBC is a channel
memory block, which can be accessed directly from the I/O
pins. Both types of memory blocks are highly configurable and
can be cascaded in width and depth. See Figure 1 for a block
diagram of the Delta39K architecture.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby re-
ducing costs. The ISR feature provides the ability to reconfig-
ure the devices without having design changes cause pinout
or timing changes in most cases. The Cypress ISR function is
implemented through a JTAG-compliant serial interface. Data
is shifted in and out through the TDI and TDO pins respective-
ly. Superior routability, simple timing, and the ISR allows users
to change existing logic designs while simultaneously fixing
pinout assignments and maintaining system performance.
Figure 2 is a block diagram of the routing channels that inter-
face within the Delta39K architecture. The LBC is exactly the
same for every member of the Delta39K CPLD family.
Logic Block Cluster (LBC)
The Delta39K architecture consists of several logic block clus-
ters, each of which have 8 Logic Blocks (LB) and 2 cluster
memory blocks connected via a Programmable Interconnect
Matrix (PIM) as shown in Figure 3. Each cluster memory block
consists of 8-Kbit single-port RAM, which is configurable as
synchronous or asynchronous. The cluster memory blocks
can be cascaded with other cluster memory blocks within the
same LBC as well as other LBCs to implement larger memory
functions. If a cluster memory block is not specifically utilized
by the designer, Cypress’s Warp software can automatically
use it to implement large blocks of logic.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification, meet-
ing the electrical and timing requirements. The Delta39K fam-
ily also features user programmable bus-hold and slew rate
control capabilities on each I/O pin.
All LBCs interface with each other via horizontal and vertical
routing channels.
AnyVolt Interface
All Delta39KV devices feature an on-chip regulator, which ac-
cepts 3.3V or 2.5V on the VCC supply pins and steps it down
to 1.8V internally, the voltage level at which the core operates.
I/O Block
LB
LB
LB
LB
LB
LB
LB
LB
72
64
Cluster
PIM
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
Channel
Memory
Block
Cluster
Memory
Block
Cluster
Memory
Block
72
64
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
Figure 2. Delta39K Routing Interface
Note:
5. For HSTL only.
Document #: 38-03039 Rev. **
Page 4 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Clock Inputs
GCLK[3:0]
4
Logic
Block
0
Logic
Block
7
36
16
36
16
Logic
Block
1
Logic
Block
6
36
16
36
16
Logic
Block
2
Logic
Block
5
36
16
36
16
PIM
Logic
Block
3
Logic
Block
4
36
16
36
16
Cluster
Memory
0
Cluster
Memory
1
25
8
25
8
CC = Carry Chain
64 Inputs From
Vertical Routing
Channel
64 Inputs From
Horizontal Routing
Channel
144 Outputs to
Horizontal and Vertical
cluster-to-channel PIMs
Figure 3. Delta39K Logic Block Cluster Diagram
Logic Block (LB)
vides two important capabilities without affecting performance:
product term steering and product term sharing.
The logic block is the basic building block of the Delta39K ar-
chitecture. It consists of a product term array, an intelligent
product-term allocator, and 16 macrocells.
Product Term Steering
Product term steering is the process of assigning product
terms to macrocells as needed. For example, if one macrocell
requires ten product terms while another needs just three, the
product term allocator will “steer” ten product terms to one
macrocell and three to the other. On Delta39K devices, prod-
uct terms are steered on an individual basis. Any number be-
tween 1and 16 product terms can be steered to any macrocell.
Product Term Array
Each logic block features a 72 x 83 programmable product
term array. This array accepts 36 inputs from the PIM. These
inputs originate from device pins and macrocell feedbacks as
well as cluster memory and channel memory feedbacks. Ac-
tive LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 83 product
terms in the array can be created from any of the 72 inputs.
Product Term Sharing
Product term sharing is the process of using the same product
term among multiple macrocells. For example, if more than
one function has one or more product terms in its equation that
are common to other functions, those product terms are only
programmed once. The Delta39K product term allocator al-
lows sharing across groups of four macrocells in a variable
fashion. The software automatically takes advantage of this
capability so that the user does not have to intervene.
Of the 83 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Two of the remaining three
product terms in the logic block are used as asynchronous set
and asynchronous reset product terms. The final product term
is the Product Term clock (PTCLK) and is shared by all 16
macrocells within a logic block.
Product Term Allocator
Through the product term allocator, Warp software automati-
cally distributes the 80 product terms as needed among the 16
macrocells in the logic block. The product term allocator pro-
Note that neither product term sharing nor product term steer-
ing have any effect on the speed of the product. All steering
and sharing configurations have been incorporated in the tim-
ing specifications for the Delta39K devices.
.
Document #: 38-03039 Rev. **
Page 5 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Macrocell
tions are implemented through the use of carry-in arithmetic,
which drives through the circuit quickly. Figure 4 shows that
the carry chain logic within the macrocell consists of two prod-
uct terms (CPT0 and CPT1) from the PTA and an input carry-
in for carry logic. The inputs to the carry chain mux are con-
nected directly to the product terms in the PTA. The output of
the carry chain mux generates the carry-out for the next mac-
rocell in the logic block as well as the local carry input that is
connected to an input of the XOR input mux. Carry-in and a
configuration bit are inputs to an AND gate. This AND gate
provides a method of segmenting the carry chain in any mac-
rocell in the logic block.
Within each logic block there are 16 macrocells. Each
macrocell accepts a sum of up to 16 product terms from the
product term array. The sum of these 16 product terms can be
output in either registered or combinatorial mode. Figure 4
displays the block diagram of the macrocell. The register can
be asynchronously preset or asynchronously reset at the mac-
rocell level with the separate preset and reset product terms.
Each of these product terms features programmable polarity.
This allows the registers to be preset or reset based on an
AND expression or an OR expression.
An XOR gate in the Delta39K macrocell allows for many differ-
ent types of equations to be realized. It can be used as a po-
larity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows ad-
ditional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to imple-
ment adders, subtractors, magnitude comparators, parity tree,
or even generic XOR logic. The output of the macrocell is ei-
ther registered or combinatorial.
Macrocell Clocks
Clocking of the register is highly flexible. Four global synchro-
nous clocks (GCLK[3:0]) and a Product Term clock (PTCLK)
are available at each macrocell register. Furthermore, a clock
polarity mux within each macrocell allows the register to be
clocked on the rising or the falling edge (see macrocell dia-
gram in Figure 4).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and re-
set using the PRESET and RESET mux. Both signals are ac-
tive high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in Figure 4) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
Carry Chain Logic
The Delta39K macrocell features carry chain logic which is
used for fast and efficient implementation of arithmetic opera-
tions. The carry logic connects macrocells in up to 4 logic
blocks for a total of 64 macrocells. Effective data path opera-
Carry In
(from macrocell n-1)
PRESET
Mux
0
1
C
XOR Input
Mux
3
Carry Chain
Mux
C
CPT0
CPT1
Output Mux
C
2
To PIM
C
DPSET
C
Q
FROM PTM
Up To 16 PTs
Clock
Clock Mux
Polarity
RES Q
Mux
GCLK[3:0]
PTCLK
3
C
C
0
1
Carry Out
(to macrocell n+1)
3
C
RESET
Mux
Figure 4. Delta39K Macrocell
Document #: 38-03039 Rev. **
Page 6 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Embedded Memory
Cluster Memory Initialization
Each member of the Delta39K family contains two types of
embedded memory blocks. The channel memory block is
placed at the intersection of horizontal and vertical routing
channels. Each channel memory block is 4096 bits in size and
can be configured as asynchronous or synchronous Dual-Port
RAM, Single-Port RAM, Read-Only memory (ROM), or syn-
chronous FIFO memory. The memory organization is config-
urable as 4Kx1, 2Kx2, 1Kx4 and 512x8. The second type of
memory block is located within each LBC and is referred to as
a cluster memory block. Each LBC contains two cluster mem-
ory blocks that are 8192-bits in size. Similar to the channel
memory blocks, the cluster memory blocks can be configured
as 8Kx1, 4Kx2, 2Kx4 and 1Kx8 asynchronous or synchronous
Single-Port RAM or ROM.
The cluster memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To fa-
cilitate the use of look-up-table (LUT) logic and ROM applica-
tions, the cluster memory blocks can be initialized with a given
set of data when the device is configured at power up. For LUT
and ROM applications, the user cannot write to memory
blocks.
Channel Memory
The Delta39K architecture includes an embedded memory
block at each crossing point of horizontal and vertical routing
channels. The channel memory is a 4096-bit embedded mem-
ory block that can be configured as asynchronous or synchro-
nous Single-Port RAM, Dual-Port RAM, ROM, or synchronous
FIFO memory.
Cluster Memory
Data, address, and control inputs to the channel memory are
driven from horizontal and vertical routing channels. All data
and FIFO logic outputs drive dedicated tracks in the horizontal
and vertical routing channels. The clocks for the channel mem-
ory block are selected from four global clocks and pin inputs
from the horizontal and vertical channels. The clock muxes
also include a polarity mux for each clock so that the user can
choose an inverted clock.
Each logic block cluster of the Delta39K contains two 8192-bit
cluster memory blocks. Figure 5 is a block diagram of the clus-
ter memory block and the interface of the cluster memory block
to the cluster PIM.
The output of the cluster memory block can be optionally reg-
istered to perform synchronous pipelining or to register asyn-
chronous read and write operations. The output registers con-
tain an asynchronous RESET which can be used in any type
of sequential logic circuits (e.g., state machines).
Dual-Port (Channel Memory) Configuration
Each port has distinct address inputs, as well as separate data
and control inputs that can be accessed simultaneously. The
inputs to the Dual-Port memory are driven from the horizontal
and vertical routing channels. The data outputs drive dedicat-
ed tracks in the routing channels. The interface to the routing
is such that Port A of the Dual-Port interfaces primarily with the
horizontal routing channel and Port B interfaces primarily with
There are four global clocks (GCLK[3:0]) and one local clock
available for the input and the output registers. The local clock
for the input registers is independent of the one used for the
output registers. The local clock is generated in the user-de-
sign in a macrocell or comes from an I/O pin.
the vertical routing channel.
.
Write
Control
Logic
DIN[7:0]
ADDR[12:0]
WE
3
D
D
D
Q
Q
Q
C
C
2
8
C
1024x8
Asynchronous
SRAM
10
C
Cluster PIM
GCLK[3:0]
5:1
Local CLK
3
3
C
8
C
DOUT[7:0]
Read
Control
Logic
Q
D
C
R
RESET
2
C
GCLK[3:0]
Local CLK
5:1
3
C
C
Figure 5. Block Diagram of Cluster Memory Block
Document #: 38-03039 Rev. **
Page 7 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
The clocks for each port of the Dual-Port configuration are
selected from four global clocks and two local clocks. One lo-
cal clock is sourced from the horizontal channel and the other
from the vertical channel. The data outputs of the dual-port
memory can also be registered. Clocks for the output registers
are also selected from four global clocks and two local clocks.
One clock polarity mux per port allows the use of true or com-
plement polarity for input and output clocking purposes.
FIFO (Channel Memory) Configuration
The channel memory blocks are also configurable as synchro-
nous FIFO RAM. In the FIFO mode of operation, the channel
memory block supports all normal FIFO operations without the
use of any general-purpose logic resources in the device.
The FIFO block contains all of the necessary FIFO flag logic,
including the read and write address pointers. The FIFO flags
include an empty/full flag (EF), half-full flag (HF), and program-
mable almost-empty/full (PAEF) flag output. The FIFO config-
uration has the ability to perform simultaneous read and write
operations using two separate clocks. These clocks may be
tied together for a single operation or may run independently
for asynchronous Read/Write (w.r.t. each other) applications.
The data and control inputs to the FIFO block are driven from
the horizontal or vertical routing channels. The data and flag
outputs are driven onto dedicated routing tracks in both the
horizontal and vertical routing channels. This allows the FIFO
blocks to be expanded by using multiple FIFO blocks on the
same horizontal or vertical routing channel without any speed
penalty.
Arbitration
The Dual-Port configuration of the Channel Memory Block pro-
vides arbitration when both ports access the same address at
the same time. Depending on the memory operation being at-
tempted, one port always gets priority. See Table 1 for details
on which port gets priority for read and write operations. An
active-LOW ‘Address Match’ signal is generated when an ad-
dress collision occurs.
Table 1. Arbitration Result: Address Match Signal
Becomes Active
Result of
Port A Port B Arbitration
In FIFO mode, the write and read ports are controlled by sep-
arate clock and enable signals. The clocks for each port are
selected from four global clocks and two local clocks.
Comment
Read
Read No arbitration Both ports read at the
required
same time
One local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs from the read
port of the FIFO can also be registered. One clock polarity mux
per port allows using true or complement polarity for read and
write operations. The write operation is controlled by the clock
and the write enable pin. The read operation is controlled by
the clock and the read enable pin. The enable pins can be
sourced from horizontal or vertical channels.
Write
Read Port A gets
priority
If Port B requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port A
Read
Write
Write Port B gets
priority
If Port A requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port B
Write Port A gets
priority
Port B is blocked until
Port A is finished writing
All channel memory
inputs are driven from
the routing channels
4096-bit Dual Port
Array
Signals
Configurable as
Async/Sync Dual Port or
Sync FIFO
GCLK[3:0]
Configurable as
4Kx1, 2Kx2, 1Kx4 and
512x8 block sizes
All channel memory outputs
drive dedicated tracks in the
routing channels
Horizontal Channel
Figure 6. Block Diagram of Channel Memory Block
Document #: 38-03039 Rev. **
Page 8 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Channel Memory Initialization
note titled “Delta39K Family Device I/O Standards and Config-
urations” for details.
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To fa-
cilitate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a giv-
en set of data when the device is configured at power up. For
LUT and ROM applications, the user cannot write to memory
blocks.
bank 7
bank 6
Channel Memory Routing Interface
Similar to LBC outputs, the channel memory blocks feature
dedicated tracks in the horizontal and vertical routing channels
for the data outputs and the flag outputs, as shown in
Figure 6. This allows the channel memory blocks to be ex-
panded easily. These dedicated lines can be routed to I/O pins
as chip outputs or to other logic block clusters to be used in
logic equations.
Delta39K
bank 2
bank 3
I/O Banks
The Delta39K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are 8 I/O banks
per device as shown in Figure 7, and all I/Os from an I/O bank
are located in the same section of a package for PCB layout
convenience.
Figure 7. Delta39K I/O Bank Block Diagram
I/O Standards
For each package type, Delta39K devices of different densities
keep given pins in the same I/O banks. This supports and sim-
plifies design migration across densities.
I/O
Standard
Termination
VCCIO Voltage (VTT)
VREF (V)
Min. Max.
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
LVTTL
N/A
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.5
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
There are four dedicated inputs (GCTl[3:0]) that are used as
Global Control Signals available to every I/O cell. These global
control signals may be used as output enables, register resets
and register clock enables as shown in Figure 8.
0.9
1.3
1.1
1.7
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
1.5
Each I/O bank can use any supported I/O standard by supply-
ing appropriate VREF and VCCIO voltages. All the VREF and
1.3
1.7
1.5
V
CCIO pins in an I/O bank must be connected to the same VREF
1.15
1.15
0.68
0.68
0.68
0.68
1.35
1.35
0.9
1.25
1.25
0.75
0.75
1.5
and VCCIO voltage respectively. This requirement restricts the
number of I/O standards supported by an I/O bank at any given
time.
The number of I/Os which can be used in each I/O bank de-
pend on the type of I/O standards and the number of VCCIO
and GND pins being used. This restriction is derived from the
electromigration limit of the VCCIO and GND bussing on the
chip. Please refer to the note on page 17 and the application
HSTL II
0.9
HSTL III
HSTL IV
0.9
0.9
1.5
Document #: 38-03039 Rev. **
Page 9 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
.
Registered OE
Mux
OE Mux
D
Q
From
C
Output PIM
3
C
Input
Mux
RES
To Routing
Channel
Register Input
Mux
C
C
Output Mux
Bus
Hold
I/O
Register Enable
Mux
D
E
Q
Clock
C
C
Polarity
Mux
Slew
Rate
RES
3
C
C
Control
Clock Mux
C
C
2
Register Reset
Mux
3
C
Figure 8. Block Diagram of I/O Cell
I/O Cell
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-in-
terface applications. Bus-hold additionally allows unused de-
vice pins to remain unconnected on the board, which is partic-
ularly useful during prototyping as designers can route new
signals to the device without cutting trace connections to VCC
or GND. For more information, see the application note “Un-
derstanding Bus-Hold − A Feature of Cypress CPLDs.”
Figure 8 is a block diagram of the Delta39K I/O cell. The I/O
cell contains a three-state input buffer, an output buffer, and a
register that can be configured as an input or output register.
The output buffer has a slew rate control option that can be
used to configure the output for a slower slew rate. The input
of the device and the pin output can each be configured as
registered or combinatorial; however, only one path can be
configured as registered in a given design.
The output enable can be selected from one of the four global
control signals or from one of two Output Control Channel
(OCC) signals. The output enable can be configured as always
enabled or always disabled or it can be controlled by one of
the remaining inputs to the mux. The selection is done via a
mux that includes VCC and GND as inputs.
Clocks
Delta39K has four dedicated clock input pins (GCLK[3:0]) to
accept system clocks. One of these clocks (GCLK[0]) may be
selected to drive an on-chip Phase-Locked Loop (PLL) for fre-
quency modulation (see Figure 9 for details).
One of the global clocks can be selected as the clock for the
I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock.
The global clock tree for a Delta39K device can be driven by
a combination of the dedicated clock pins and/or the PLL-de-
rived clocks. The global clock tree consists of four global
clocks that go to every macrocell, memory block, and I/O cell.
Slew Rate Control
Clock Tree Distribution
The ouput buffer has a slew rate control option. This allows the
output buffer to slew at a fast rate (3 V/ns) or a slow rate (1
V/ns). All I/Os default to fast slew rate. For designs concerned
with meeting FCC emissions standards the slow edge pro-
vides for lower system noise. For designs requiring very high
performance the fast edge rate provides maximum system
performance.
The global clock tree performs two primary functions. First, the
clock tree generates the four global clocks by multiplexing four
dedicated clocks from the package pins and four PLL driven
clocks. Second, the clock tree distributes the four global clocks
to every cluster, channel memory, and I/O block on the die.
The global clock tree is designed such that the clock skew is
minimized while maintaining an acceptable clock delay.
Programmable Bus Hold
On each I/O pin, user-programmable-bus-hold is included.
Bus-hold, which is an improved version of the popular internal
Document #: 38-03039 Rev. **
Page 10 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
off-chip signal (external feedback)
INTCLK0, INTCLK1, INTCLK2, INTCLK3
Any Register
Send a global
clock off chip
GCLK1
Normal I/O signal path
Lock Detect/IO pin
C
Clock Tree
Delay
Phase selection
Divide
1-6,8,16
2
÷
C
INTCLK0
GCLK0
fb
fb
Lock
2
Phase selection
C
Divide
1-6,8,16
÷
÷
Clk 00
Clk 450
INTCLK1
INTCLK2
GCLK1
Clk 900
Clk 1350
Clk 1800
Clk 2250
Clk 2700
Clk 3150
Phase selection
2
GCLK0
Source
Clock
C
Divide
1-6,8,16
GCLK2
2
PLL
X1, X2, X4
C
Phase selection
Divide
1-6,8,16
÷
INTCLK3
GCLK3
2
C
Figure 9. Block Diagram of Spread Aware PLL
Spread Aware™ PLL
The Voltage Controlled Oscillator (VCO), the core of the
Delta39K PLL is designed to operate within the frequency
range of 100 MHz to 266 MHz. Hence, the multiply option com-
bined with input (GCLK[0]) frequency should be selected such
that this VCO operating frequency requirement is met. This is
demonstrated in Table 2 (columns 1, 2, and 3).
Each device in the Delta39K family features an on-chip PLL
designed using Spread Aware technology for low EMI applica-
tions. In general, PLLs are used to implement time-division-
multiplex circuits to achieve higher performance with fewer de-
vice resources.
Another feature of this PLL is the ability to drive the output
clock (INTCLK) off the Delta39K chip to clock other devices on
the board, as shown in Figure 9 above. This off-chip clock is
half the frequency of the output clock as it has to go through a
register (I/O register or a macrocell register).
For example, a system that operates on a 32-bit data path that
runs at 40 MHz can be implemented with 16-bit circuitry that
runs internally at 80 MHz. PLLs can also be used to take ad-
vantage of the positioning of the internally generated clock
edges to shift performance towards improved setup, hold or
clock-to-out times.
This PLL can also be used for board de-skewing purpose by
driving a PLL output clock off-chip, routing it to the other de-
vices on the board and feeding it back to the PLL’s external
feedback input (GCLK[1]). When this feature is used, only lim-
ited multiply, divide and phase shift options can be used.
There are several frequency multiply (X1, X2, X4) and divide
(/1, /2, /3, /4, /5, /6. /8, /16) options available to create a wide
range of clock frequencies from a single clock input (GCLK[0]).
For increased flexibility, there are seven phase shifting options
which allow clock skew/de-skew by 45°, 90°, 135°, 180°, 225°,
270° or 315°.
Table 2 describes the valid multiply and divide options that can
be used without an external feedback. Table 3 describes the
valid multiply & divide options that can be used with an exter-
nal feedback.
Table 2. PLL Multiply and Divide Options—without External Feedback
Valid Multiply Options
Input Frequency
Valid Divide Options
(GCLK[0])
VCO Output
Output Frequency (INTCLK[3:0]) Off-chip Clock
f
PLLI (MHz)
Value Frequency (MHz)
Value
fPLLO (MHz)
6.25–133
8.33–200
12.5–266
6.25–133
8.3–200
Frequency
25–33
4
4
4
2
2
2
1
100–133
133–200
200–266
100–133
133–200
200–266
100–133
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
3.12–66
33–50
4.16–100
6.25–133
3.12–66
50–66
66–100
4.16–100
6.25–133
3.12–66
12.5–266
6.25–133
100–133
Document #: 38-03039 Rev. **
Page 11 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Table 3. PLL Multiply and Divide Options—with External Feedback
Valid Multiply Options
Valid Divide Options
Input (GCLK) Frequency
fPLLI (MHz)
VCO Output
Frequency (MHz)
Output (INTCLK) Frequency
fPLLO (MHz)
Off-chip Clock
Frequency
Value
Value
50–66
66–100
100–133
1
1
1
100–133
133–200
200–266
1
1
1
100–133
133–200
200–266
50–66
66–100
100–133
Table 5 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift ap-
plies to the VCO output and not to the divided output.
Table 4 describes the valid phase shift options that can be used
with or without an external feedback.
Table 4. PLL Phase Shift Options—
with and without External Feedback
With External
Feedback
The Spread Aware PLL operates as specified for Delta39KV
devices (2.5V/3.3V), but not Delta39KZ devices (1.8V). For
more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree.”
Without External Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
0°
Table 5. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Duty
Divide
Factor
Period
(ns)
Cy-
0°
45°
90°
135°
180°
225°
270°
(ns)
315°
(ns)
cle%
(ns)
(ns)
(ns)
(ns)
(ns)
(ns)
1
2
4
40-60
50
0
0
0
0
0
0
0
0
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
8
3
12
16
20
24
32
64
33-67
50
4
5
40-60
50
6
8
50
16
50
Document #: 38-03039 Rev. **
Page 12 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Timing Model
shown in Figure 10. For synchronous systems, the input set-
up time to the output macrocell register and the clock to output
time are shown as the parameters tMCS and tMCCO shown in
the Figure 10. These measurements are for any output and
synchronous clock, regardless of the logic placement.
One important feature of the Delta39K family is the simplicity
of its timing. All combinatorial and registered/synchronous de-
lays are worst case and system performance is static (as
shown in the AC specs section) as long as data is routed
through the same horizontal and vertical channels. Figure 10
illustrates the true timing model for the 200-MHz devices. For
synchronous clocking of macrocells, a delay is incurred from
macrocell clock to macrocell clock of separate Logic Blocks
within the same cluster, as well as separate Logic Blocks with-
in different clusters. This is respectively shown as tSCS and
tSCS2 in Figure 10. For combinatorial paths, any input to any
output (from corner to corner on the device), incurs a worst-
case delay in the 39K100 regardless of the amount of logic or
which horizontal and vertical channels are used. This is the tPD
The Delta39K features:
• no dedicated vs. I/O pin delays
• no penalty for using 0–16 product terms
• no added delay for steering product terms
• no added delay for sharing product terms
• no output bypass delays
The simple timing model of the Delta39K family eliminates un-
expected performance penalties.
tSCS
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PI
PIM
tMCS
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
8 Kb
SRAM
8 Kb
SRAM
GCLK[3:0]
4
4
4
4
tSCS2
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 2
LB 3
tPD
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 7
LB 6
LB 5
LB 4
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 2
LB 3
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
tMCCO
Figure 10. Timing Model for 39K100 Device
Document #: 38-03039 Rev. **
Page 13 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
IEEE 1149.1 Compliant JTAG Operation
Delta39K to (re)configure according to data provided by other
sources such as a PC, automatic test equipment (ATE), or an
embedded micro-controller/processor via the JTAG interface.
For more information on configuring Delta39K devices, refer
The Delta39K family has an IEEE 1149.1 JTAG interface for
both Boundary Scan and ISR operations.
Four dedicated pins are reserved on each device for use by
the Test Access Port (TAP).
to
the
application
note
titled
“Configuring
note at
Delta39K/Quantum38K”
application
http://www.cypress.com.
Boundary Scan
There are two configuration options available for issuing the
IEEE std 1149.1 JTAG instructions to the Delta39K. The first
method is to use a PC with the C3ISR programming cable and
software. With this method, the ISR pins of the Delta39K de-
vices in the system are routed to a connector at the edge of
the printed circuit board. The C3ISR programming cable is
then connected between the PC and this connector. A simple
configuration file instructs the ISR software of the program-
ming operations to be performed on the Delta39K devices in
the system. The ISR software then automatically completes all
of the necessary data manipulations required to accomplish
configuration, reading, verifying, and other ISR functions. For
more information on the Cypress ISR interface, see the ISR
Programming Kit data sheet (CY3900i).
The Delta39K family supports Bypass, Sample/Preload, Ex-
test, Intest, Idcode and Usercode boundary scan instructions.
The JTAG interface is shown in Figure 11.
Instruction Register
TDI
TDO
Bypass Reg.
JTAG
TMS
TAP
CONTROLLER
Boundary Scan
TCLK
idcode
The second configuration option for the Delta39K is to utilize
the embedded controller or processor that already exists in the
system. The Delta39K ISR software assists in this method by
converting the device HEX file into the ISR serial stream that
contains the ISR instruction information and the addresses
and data of locations to be configured. The embedded control-
ler then simply directs this ISR stream to the chain of Delta39K
devices to complete the desired reconfiguration or diagnostic
operations. Contact your local sales office for information on
availability of this option.
Usercode
ISR Prog.
Data Registers
Figure 11. JTAG Interface
In-System Reprogramming (ISR)
Programming
In-System Reprogramming is the combination of the capability
to program or reprogram a device on-board, and the ability to
support design changes without changing the system timing
or device pinout. This combination means design changes
during debug or field upgrades do not cause board respins.
The Delta39K family implements ISR by providing a JTAG
compliant interface for on-board programming, robust routing
resources for pinout flexibility, and a simple timing model for
consistent system performance.
The on-chip FLASH device of the Delta39K Self-Boot package
is programmed by issuing the appropriate IEEE std 1149.1
JTAG instruction to the internal FLASH memory via the JTAG
interface. This can be done automatically using ISR/STAPL
software. The configuration bits are sent from a PC through
the JTAG port into the Delta39K via the C3ISR programming
cable. The data is then internally passed from Delta39K to the
on-chip FLASH. For more information on how to program the
Delta39K through ISR/STAPL, please refer to the ISR/STAPL
User Guide.
Configuration
Each device of the Delta39K family is available in a volatile and
a Self-Boot package. Cypress’s CPLD boot EEPROM is used
to store configuration data for the volatile solution and an em-
bedded on-chip FLASH memory device is used for the Self-
Boot solution.
The external CPLD boot EEPROM used to store configuration
data for the Delta39K volatile package is programmed through
Cypress’s CYDH2200E CPLD Boot PROM Programming Kit
via a two-wire interface. For more information on how to pro-
gram the CPLD boot EEPROM, please refer to the data sheet
titled “CYDH2200E CPLD Boot PROM Programming Kit.” For
more information on the architecture and timing specification
of the boot EEPROM, refer to the data sheet titled “CPLD Boot
EEPROM.”
For volatile Delta39K packages, programming is defined as
the loading of a user’s design into the external CPLD boot
EEPROM. For Self-Boot Delta39K packages, programming is
defined as the loading of a user’s design into the on-chip
FLASH internal to the Delta39K package. Configuration is de-
fined as the loading of a user’s design into the Delta39K die.
Third-Party Programmers
Cypress support is available on a wide variety of third-party
programmers. All major programmers (including BP Micro,
System General, Hi-Lo) support the Delta39K family.
Configuration can begin in two ways. It can be initiated by tog-
gling the Reconfig pin from LOW to HIGH, or by issuing the
appropriate IEEE std 1149.1 JTAG instruction to the Delta39K
device via the JTAG interface. There are two IEEE std 1149.1
JTAG instructions that initiate configuration of the Delta39K.
The Self Config instruction causes the Delta39K to (re)config-
ure with data stored in the serial boot PROM or the embedded
FLASH memory. The Load Config instruction causes the
Development Software Support
Warp
Warp is a state-of-the-art design environment for designing
with Cypress programmable logic. Warp utilizes a subset of
Document #: 38-03039 Rev. **
Page 14 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware De-
scription Language (HDL) for design entry. Warp accepts
VHDL or Verilog input, synthesizes and optimizes the entered
design, and outputs a configuration bitstream for the desired
Delta39K device. For simulation, Warp provides a graphical
waveform simulator as well as VHDL and Verilog Timing Mod-
els.
havioral design entry and simulation. HDL allows designers to
learn a single language that is useful for all facets of the design
process.
Third-Party Software
Cypress products are supported in a number of third-party de-
sign entry and simulation tools. Refer to the third-party soft-
ware data sheet or contact your local sales office for a list of
currently supported third party vendors.
VHDL and Verilog are open, powerful, non-proprietary Hard-
ware Description Languages (HDLs) that are standards for be-
Document #: 38-03039 Rev. **
Page 15 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
V
CC to Ground Potential (39KV device) ...........–0.5V to 4.6V
CCIO to Ground Potential................................–0.5V to 4.6V
Maximum Ratings
V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DC Voltage Applied to Outputs in High Z State –0.5V to 4.5V
DC Input voltage...............................................–0.5V to 4.5V
Storage Temperature..................................–65°C to +150°C
Soldering Temperature...................................................220°C
DC Current into Outputs.........................................................
...................±20 mA[6]
Ambient Temperature with
Power Applied...............................................–40°C to +85°C
Static Discharge Voltage (per MIL-STD-8883,
Method 3015)..............................................................>2001V
Latch-Up Current.......................................................>200 mA
Junction Temperature....................................................135°C
VCC to Ground Potential (39KZ device)........... –0.5V to 2.5V
Operating Range
Ambient
Temperature
Junction
Temperature
Output
Condition
VCCJTAG
/
Range
VCCIO
VCC
VCCCNFG VCCPLL VCCPRG
0°C to +70°C
0°C to +85°C
3.3V
2.5V
1.8V
1.5V
3.3V
2.5V
1.8V
1.5V
3.3V ± 0.3V
2.5V ± 0.2V
3.3V ± 0.3V
or
Same as
VCCIO
Same
as VCC
3.3V
±
0.3V
Commercial
1.8V ± 0.15V 2.5V ± 0.2V
1.5V ± 0.1V[5]
(39KV)
–40°C to +85°C –40°C to +100°C
3.3V ± 0.3V
1.8V± 0.15V
2.5V ± 0.2V
(39KZ)
Industrial
1.8V ± 0.15V
1.5V ± 0.1V[5]
DC Characteristics
VCCIO = 3.3 V VCCIO =2.5 V VCCIO =1.8V
Min. Max. Min. Max. Min. Max. Unit
Parameter Description
Test Conditions
Data Retention VCC Voltage
(config data may be lost below this)
1.5
1.2
–10
1.5
1.5
V
VDRINT
VDRIO
Data Retention VCCIO Voltage
(config data may be lost below this)
1.2
1.2
V
IIX
Input Leakage Current
Output Leakage Current
GND ≤ VI ≤ 3.6V
10
10
–10
–10
10
10
–10
–10
10
10
µA
µA
IOZ
GND ≤ VO ≤ VCCIO –10
VCCIO = Max.,
–160
–160
–160 mA
[7]
IOS
Output Short Circuit Current
VOUT = 0.5V
Input Bus Hold LOW Sustaining
Current
VCC = Min.,
VPIN = VIL
+40
+30
+25
µA
µA
IBHL
Input Bus Hold HIGH Sustaining
Current
VCC = Min.,
VPIN = VIH
–40
–30
–25
IBHH
IBHLO
Input Bus Hold LOW Overdrive Current VCC = Max.
Input Bus Hold HIGH Overdrive Current VCC = Max.
+250
+200
+150 µA
–150 µA
IBHHO
–250
–200
Notes:
6. DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV and 36 mA with GTL+ (with 25Ω pull-up resistor and VTT = 1.5
7. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03039 Rev. **
Page 16 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Capacitance
Parameter
CI/O
Description
Test Conditions
Min.
Max.
10
Unit
pF
Input/Output Capacitance
Clock Signal Capacitance
PCI Compliant[8] Capacitance
Vin=VCCIO @ f=1 MHz 25°C
Vin=VCCIO @ f=1 MHz 25°C
Vin=VCCIO @ f=1 MHz 25°C
CCLK
5
12
pF
CPCI
8
pF
[9]
DC Characteristics (IO)
VREF (V)
Input/
VOH (V)
VOL (V)
VOL
VIH (V)
VIL (V)
Output
VCCIO
Standard
(V)
3.3
3.3
3.0
2.5
@ IOH
=
VOH (min.) @ IOL
=
(max.)
Min.
2.0 V
2.0 V
2.0 V
1.7 V
Max.
Min.
Max.
0.8V
0.8V
0.8V
0.7V
LVTTL
N/A
–4 mA
2.4 4 mA
0.4
VCCIO+0.3 –0.3V
LVCMOS
LVCMOS3
–0.1 mA VCCIO–0.2v 0.1 mA
–0.1 mA VCCIO–0.2v 0.1mA
0.2
VCCIO+0.3 –0.3V
VCCIO+0.3 –0.3V
VCCIO+0.3 –0.3V
0.2
–0.1 mA
–1.0 mA
–2.0 mA
2.1
2.0
1.7
0.1 mA
1.0 mA
2.0 mA
0.2
LVCMOS2
0.4
0.7
1.8
3.3
–0.1 mA VCCIO–0.2v 0.1mA
– 2 mA VCCIO–0.45v 2.0 mA
0.2
0.65VCCIO VCCIO+0.3 –0.3V 0.35VCCIO
LVCMOS18
0.45
3.3V PCI
GTL+
–0.5 mA
0.9VCCIO
1.5 mA 0.1VCCIO 0.5VCCIO VCCIO+0.5 –0.5V 0.3VCCIO
0.9 1.1 Note 10
Note 11
8 mA
0.6
0.7
VREF+0.2
VREF–0.2
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
1.3 1.7
1.3 1.7
1.15 1.35
1.15 1.35
0.68 0.9
0.68 0.9
0.68 0.9
0.68 0.9
3.3
3.3
2.5
2.5
1.5
1.5
1.5
1.5
–8 mA
VCCIO–1.1v
VREF+0.2 VCCIO+0.3 –0.3V VREF–0.2
VREF+0.2 VCCIO+0.3 –0.3V VREF–0.2
VREF+1.8 VCCIO+0.3 –0.3V VREF–0.18
VREF+1.8 VCCIO+0.3 –0.3V VREF–0.18
VREF+1.0 VCCIO+0.3 –0.3V VREF–0.1
VREF+1.0 VCCIO+0.3 –0.3V VREF–0.1
VREF+1.0 VCCIO+0.3 –0.3V VREF–0.1
VREF+1.0 VCCIO+0.3 –0.3V VREF–0.1
–16 mA VCCIO–0.9v 16 mA
–7.6 mA VCCIO–0.62v 7.6 mA
–15.2 mA VCCIO–0.43v 15.2 mA
0.5
0.54
0.35
0.4
–8 mA
VCCIO–0.4v
8 mA
HSTL II
HSTL III
HSTL IV
–16 mA VCCIO–0.4v 16 mA
0.4
–8 mA
–8 mA
VCCIO–0.4v 24 mA
VCCIO–0.4v 48 mA
0.4
0.4
Notes:
8. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Document titled “Delta39K Pin Tables” identifies all the I/O pins, in a
given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
9. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer
to the application note titled “Delta39K Family Device I/O Standards and Configurations” for details.
•
•
The source current limit per I/O bank per Vccio pin is 165 mA
The sink current limit per I/O bank per GND pin is 230 mA
10. See “Power-up Sequence Requirements” below for VCCIO requirement.
11. 25Ω resistor terminated to termination voltage of 1.5V.
Document #: 38-03039 Rev. **
Page 17 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Configuration Parameters
Parameter
Description
Reconfig pin LOW time before it goes HIGH
Min.
200
Unit
ns
tRECONFIG
Power-up Sequence Requirements
• Upon power-up, all the outputs remain three-stated until all
the VCC pins have powered-up to the nominal voltage and
the part has completed configuration.
• All VCCIOs on a bank should be tied to the same potential
and powered up together.
• All VCCIOs (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
• Maximum ramp time for all VCCs should be 0V to nominal
voltage in 100 ms.
• The part will not start configuration until VCC, VCCIO
,
VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached
nominal voltage.
• VCC pins can be powered up in any order. This includes
VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG
.
Document #: 38-03039 Rev. **
Page 18 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Characteristics - Parameter Descriptions Over the Operating Range [12]
Parameter
Description
Combinatorial Mode Parameters
Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin
output on the horizontal or vertical channel associated with that cluster
tPD
tEA
tER
Global control to output enable
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical
channel associated with the cluster the macrocell is in
tPRR
tPRO
tPRW
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel
associated with the cluster that the macrocell is in to any pin output on those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in
the farthest cluster on the horizontal or vertical channel the pin is associated with
Synchronous Clocking Parameters
Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin,
relative to a global clock
tMCS
Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative
to a global clock
tMCH
tMCCO
Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated
with the cluster that macrocell is in
tIOS
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock
Clock to output of an I/O cell register to the output pin associated with that register
tIOH
tIOCO
tSCS
tSCS2
tICS
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster
that the macrocell is in
tOCS
tCHZ
tCLZ
fMAX
Clock to output disable (high-impedance)
Clock to output enable (low-impedance)
Maximum frequency with internal feedback—within the same cluster
Maximum frequency with internal feedback—within different clusters at the opposite ends of a horizontal
or vertical channel
fMAX2
Product Term Clock
tMCSPT
Set-up time for macrocell used as input register, from input to product term clock
Hold time of macrocell used as an input register
tMCHPT
tMCCOPT
Product term clock to output delay from input pin
Register to register delay through array logic in different clusters on the same channel using a product term
clock
tSCS2PT
Channel Interconnect Parameters
tCHSW
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
Cluster to Cluster delay adder (through channels and channel PIM)
tCL2CL
Note:
12. Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa.
Document #: 38-03039 Rev. **
Page 19 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Characteristics - Parameter Descriptions Over the Operating Range [12] (continued)
Parameter
Description
Miscellaneous Delays
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This
parameter can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array
required by a given signal path
tCPLD
tMCCD
tIOD
Adder for carry chain logic per macrocell
Delay from the input of the output buffer to the I/O pin
Delay from the I/O pin to the input of the channel buffer
Delay from the clock pin to the input of the clock driver
Delay from the I/O pin to the input of the I/O register
tIOIN
tCKIN
tIOREGPIN
PLL Parameters
tMCCJ
Maximum cycle to cycle jitter time
PLL delay with skew adjustment
PLL delay without any skew adjustment
Lock time for the PLL
tDWSA
tDWOSA
tLOCK
fPLLO
Output frequency of the PLL
Input frequency of the PLL
fPLLI
JTAG Parameters
tJCKH
TCLK HIGH time
tJCKL
TCLK LOW time
tJCP
TCLK clock period
tJSU
JTAG port setup time (TDI/TMS inputs)
JTAG port hold time (TDI/TMS inputs)
JTAG port clock to output time (TDO)
JTAG port valid output to high impedance (TDO)
JTAG port high impedance to valid output (TDO)
tJH
tJCO
tJXZ
tJZX
Document #: 38-03039 Rev. **
Page 20 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
tCLMPWE
tCLMSA
tCLMHA
tCLMSD
tCLMHD
Cluster memory access time. Delay from address change to read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Synchronous Mode Parameters
Clock cycle time for flow through read and write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
tCLMCYC1
tCLMCYC2
Clock cycle time for pipelined read and write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
tCLMH
tCLMDV1
tCLMDV2
tCLMMACS1
tCLMMACS2
tMACCLMS1
tMACCLMS2
Internal Parameters
tCLMCLAA
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
Macrocell clock to cluster memory output clock in the same cluster
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Document #: 38-03039 Rev. **
Page 21 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Channel Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Dual Port Asynchronous Mode Parameters
tCHMAA
tCHMPWE
tCHMSA
tCHMHA
tCHMSD
tCHMHD
tCHMBA
Channel memory access time. Delay from address change to read data out
Write enable pulse width
Address set-up to the beginning of write enable with both signals from the same I/O block
Address hold after the end of write enable with both signals from the same I/O block
Data set-up to the end of write enable
Data hold after the end of write enable
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
Clock cycle time for flow through read and write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
tCHMCYC1
tCHMCYC2
Clock cycle time for pipelined read and write operations (from channel memory input register through the
memory to channel memory output register)
tCHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
tCHMH
tCHMDV1
tCHMDV2
tCHMBDV
tCHMMACS1
tCHMMACS2
tMACCHMS1
tMACCHMS2
Global clock to data valid on output pins for pipelined data.
Channel memory synchronous dual-port address match (busy, clock to data valid)
Channel memory input clock to macrocell clock in the same cluster
Channel memory output clock to macrocell clock in the same cluster
Macrocell clock to channel memory input clock in the same cluster
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
tCHMCLK Read and write minimum clock cycle time
tCHMFS
Data, read enable, and write enable set-up time relative to pin inputs
Data, read enable, and write enable hold time relative to pin inputs
Data access time to output pins from rising edge of read clock (read clock to data valid)
Channel memory FIFO read clock to macrocell clock for read data
Macrocell clock to channel memory FIFO write clock for write data
tCHMFH
tCHMFRDV
tCHMMACS
tMACCHMS
Synchronous FIFO Flag Parameters
tCHMFO
Read or write clock to respective flag output at output pins
tCHMMACF
Read or write clock to macrocell clock with FIFO flag
Master Reset Pulse Width
tCHMFRS
tCHMFRSR
Master Reset Recovery Time
tCHMFRSF
Master Reset to Flag and Data Output Time
Read/Write Clock Skew Time for Full Flag
Read/Write Clock Skew Time for Empty Flag
Read/Write Clock Skew Time for Boundary Flags
tCHMSKEW1
tCHMSKEW2
tCHMSKEW3
Internal Parameters
tCHMCHAA
Asynchronous channel memory access time from input of channel memory to output of channel memory
Document #: 38-03039 Rev. **
Page 22 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Characteristics - Parameter Values Over the Operating Range
250
222
200
181
167
154
125
83
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
tPD
6.5
4.0
4.0
7.0
4.5
4.5
7.5
5.0
5.0
8.5
5.6
5.3
8.5
6.5
6.5
9.0
7.5
7.5
10
9.0
9.0
15
10
10
ns
ns
ns
ns
ns
ns
tEA
tER
tPRR
tPRO
tPRW
6.0
9.0
3.0
6.0
9.5
3.3
6.0
10
6.0
10.5
4.0
6.0
11
7.0
12
8.0
13
10
15
3.6
4.5
5.0
6.0
7.0
Synchronous Clocking Parameters
tMCS
tMCH
tMCCO
tIOS
2.5
0.0
2.7
0.0
3.0
0.0
3.5
0.0
3.5
0.0
4.0
0.0
5.0
0.0
6.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.0
3.2
5.5
3.6
6.0
4.0
7.0
4.5
7.5
5.0
8.5
6.0
10
12
0.8
0.8
0.9
0.9
1.0
1.0
1.2
1.2
1.4
1.4
1.7
1.7
2.0
2.0
2.5
2.5
tIOH
tIOCO
tSCS
tSCS2
tICS
7.0
8.0
3.0
3.9
4.0
4.0
3.2
4.2
4.5
4.5
3.5
4.5
5.0
5.0
3.6
5.5
5.5
5.5
3.7
5.7
6.0
6.0
3.9
6.2
6.5
6.5
6.4
8.0
8.0
8.0
9.6
12
12
12
tOCS
tCHZ
tCLZ
3.5
3.5
3.5
3.8
4.0
4.4
6.0
7.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
fMAX
fMAX2
333
256
313
238
286
222
278
181
270
167
256
154
156
125
104 MHz
83 MHz
Product Term Clocking Parameters
tMCSPT
tMCHPT
tMCCOPT
tSCS2PT
2.5
0.8
2.7
0.9
3.0
3.3
1.4
3.5
4.0
5.0
6.0
ns
ns
1.0
1.4
1.7
2.0
2.5
7.0
7.5
8.0
8.8
9.0
10.0
11.0
15.0
ns
ns
5.5
6.0
6.5
7.2
7.5
9.0
10.0
15.0
Channel Interconnect Parameters
tCHSW
tCL2CL
0.8
1.6
0.9
1.8
1.0
2.0
1.2
2.3
1.2
2.4
1.4
2.6
1.7
2.8
2.0
3.0
ns
ns
Miscellaneous Parameters
tCPLD
2.5
0.2
2.8
3.0
3.3
3.5
3.8
4.0
5.0
ns
ns
tMCCD
0.22
0.25
0.28
0.30
0.32
0.35
0.38
PLL Parameters
tMCCJ
0.45
±320
±320
3.0
0.48
±330
±330
3.0
0.50
±350
±350
3.0
0.50
±350
±350
3.0
0.55
±390
±390
3.0
0.58
±400
±400
3.0
0.60
±420
±420
3.0
0.65
ns
tDWSA
±460 ps
±460 ps
tDWOSA
tLOCK
3.0
ms
Document #: 38-03039 Rev. **
Page 23 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Characteristics - Parameter Values Over the Operating Range (continued)
250
222
200
181
167
154
125
83
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
[13]
fPLLO
6.2 266 6.2 266 6.2 266 6.2 266 6.2 266 6.2 266 6.2
200 6.2 200 MHz
[13]
fPLLI
25
133
25
133
25
133
25
133
25
133
25
133
25
100
25
100 MHz
JTAG Parameters
tJCKH
tJCKL
tJCP
tJSU
tJH
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
ns
ns
ns
ns
ns
tJCO
tJXZ
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
ns
ns
ns
tJZX
Note:
13. Refer to page 11 and the application note titled “Delta39K PLL and Clock Tree” for details on the PLL operation & specification
Document #: 38-03039 Rev. **
Page 24 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Input & Output Standard Timing Delay Adjustments
All the timing specifications in this data sheet are specified based on 3.3V PCI compliant inputs and outputs (fast slew rates).[14]
Apply following adjustments if the inputs and outputs are configured to operate at other standards.
Output Delay Adjustments
Input Delay Adjustments
tIOIN tCKIN
0 0
Input/Output
Standard
tIOD
2.6
2.0
2.0
1.2
1.0
0.5
0.2
0.2
0.3
0.5
2.1
tEA
0
tER
0
tIOREGPIN
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
LVCMOS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
0.05
0.1
0.7
0
0
0.1
0.2
0.5
0
0.1
0.2
0.4
0
0.2
0.4
0.3
0
0
0.1
0
0
GTL+
0.6[15]
–0.3
–0.4
–0.1
–0.2
0.6
0.4
0.6[15]
0.3
0.2
0.4
0.2
0.9
0.8
0.5
0.6
0.9[15]
0.1
0
0.5
0.5
0.5
0.9
0.9
0.5
0.5
0.5
0.5
0.4
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.2
0.3
0.3
0.6
0.6
0.3
0.3
0.3
0.3
SSTL3 I
SSTL3 II
SSTL2 I
0
SSTL2 II
0
HSTL I
0.5
0.5
0.1
0
HSTL II
HSTL III
0.6
HSTL IV
0.7
Notes:
14. For “slow slew rate” output delay adjustments, refer to Warp software’s static timing analyzer results.
15. These delays are based on falling edge output. The rising edge delay depends on the size of pull up resistor and termination voltage.
Document #: 38-03039 Rev. **
Page 25 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Cluster Memory Timing Parameter Values Over the Operating Range
250
222
200
181
167
154
125
83
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Asynchronous Mode Parameters
tCLMAA
tCLMPWE
tCLMSA
tCLMHA
tCLMSD
tCLMHD
9
10
11
12
13
15
17
20
ns
ns
ns
ns
ns
ns
5
5.5
1.8
0.9
5.5
0.4
6
6.5
2.2
1.1
6.5
0.6
7
8
10
3.2
1.8
10
12
4.0
2.0
12
1.6
0.8
5.0
0.3
2.0
1.0
6.0
0.5
2.5
1.2
7.0
0.7
2.8
1.5
8.0
0.8
0.9
1.0
Synchronous Mode Parameters
tCLMCYC1
tCLMCYC2
tCLMS
9.0
4.0
2.5
0.0
9.5
4.5
2.7
0.0
10
5.0
3.0
0.0
10.5
5.5
11
13
7.0
3.8
0.0
15
8.0
4.0
0.0
20
10.0
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6.0
3.5
0.0
3.8
tCLMH
0.0
0.0
tCLMDV1
tCLMDV2
9.0
6.5
10
11
12
13
15
17
10
20
15
7.0
7.5
8.0
8.5
9.0
tCLMMACS1 7.0
tCLMMACS2 4.0
tMACCLMS1 3.2
tMACCLMS2 5.5
7.5
4.5
3.6
6.0
8.0
5.0
4.0
6.5
8.5
5.5
4.4
7.0
9.0
6.0
4.8
7.5
10
7.0
5.5
8.5
12
8.0
6.6
10
15
10
8.0
12
Internal Parameters
tCLMCLAA
5
5.5
6
6.5
7
8
10
12
ns
Document #: 38-03039 Rev. **
Page 26 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Channel Memory Timing Parameter Values
250
222
200
181
167
154
125
83
Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Dual-Port Asynchronous Mode Parameters
tCHMAA
tCHMPWE
tCHMSA
tCHMHA
tCHMSD
tCHMHD
tCHMBA
9
10
11
12
13
15
17
20
ns
ns
ns
ns
ns
ns
5.0
1.6
0.8
5.0
0.3
5.5
1.8
0.9
5.5
0.4
6.0
2.0
1.0
6.0
0.5
6.5
2.2
1.1
6.5
0.6
7.0
2.5
1.2
7.0
0.7
8.0
2.8
1.5
8.0
0.8
10
3.2
1.8
10
12
4.0
2.0
12
0.9
1.0
8.0
8.5
9.0
10.0
11.0
12.0
14.0
16.0 ns
Dual-Port Synchronous Mode Parameters
tCHMCYC1
tCHMCYC2
tCHMS
9.0
4.2
2.7
0.0
9.5
4.6
3.0
0.0
10
5.0
3.3
0.0
10
5.4
3.9
0.0
11
13
6.2
4.5
0.0
15
7.4
5.0
0.0
20
10.6
6.0
ns
ns
ns
ns
5.8
4.0
0.0
tCHMH
0.0
tCHMDV1
9.0
6.5
8.0
10
7.0
8.5
11
7.5
9.0
12
8.0
13
8.5
15
9.0
17
10
20
15
ns
ns
tCHMDV2
tCHMBDV
tCHMMACS1
tCHMMACS2
tMACCHMS1
tMACCHMS2
10.0
11.0
12.0
14.0
16.0 ns
8.0
4.0
4.2
6.0
8.5
4.5
4.6
6.5
9.0
5.0
5.0
7.0
10.0
5.5
11.0
6.0
5.8
8.0
12.0
7.0
6.5
9.0
14.0
8.0
16.0
10
ns
ns
ns
ns
5.4
7.6
9.0
7.7
10.0
13.0
Synchronous FIFO Data Parameters
tCHMCLK
tCHMFS
4.2
3.5
0.0
6.0
4.2
4.2
4.6
3.7
0.0
6.5
4.6
4.6
5.0
4.0
0.0
7.0
5.0
5.0
5.4
4.3
0.0
7.5
5.4
5.4
5.8
4.5
0.0
8.0
5.8
5.8
6.2
5.0
0.0
9.0
6.2
6.2
7.4
6.0
10.6
7.0
ns
ns
ns
tCHMFH
0.0
0.0
tCHMFRDV
tCHMMACS
tMACCHMS
10.0
7.4
13.0
10.6
10.6
ns
ns
7.4
Synchronous FIFO Flag Parameters
tCHMFO
10.0
8.0
10.5
8.5
11
9
11.5
9.5
12
10
13
11
15
13
20
17
10
ns
ns
ns
tCHMMACF
tCHMFRS
4.0
4.5
5.0
5.5
6.0
7.0
8.0
tCHMFRSR
tCHMFRSF
tCHMSKEW1
tCHMSKEW2
tCHMSKEW3
3.2
9.0
1.6
1.6
4.2
3.6
9.5
1.8
1.8
4.6
4.0
10.0
2.0
4.4
11.0
2.2
4.8
12.0
2.4
5.5
13.0
2.6
6.6
15.0
3.2
8.0
ns
18.0 ns
4.0
4.0
ns
ns
2.0
2.2
2.4
2.6
3.2
5.0
5.4
5.8
6.2
7.4
10.6 ns
Internal Parameters
tCHMCHAA 6.0
6.5
7.0
7.5
8.0
9.0
10.0
13.0
ns
Document #: 38-03039 Rev. **
Page 27 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms
Combinatorial Output
INPUT
t
PD
COMBINATORIAL
OUTPUT
Delta39K-1
Registered Output with Synchronous Clocking (Macrocell)
INPUT
t
t
MCH
MCS
SYNCHRONOUS
CLOCK
REGISTERED
OUTPUT
t
MCCO
Delta39K-2
Registered Input in I/O Cell
DATA
INPUT
t
IOH
t
IOS
INPUT REGISTER
CLOCK
t
IOCO
REGISTERED
OUTPUT
Delta39K-3
Document #: 38-03039 Rev. **
Page 28 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Clock to Clock
INPUT REGISTER
CLOCK
t
t
ICS
SCS
MACROCELL
REGISTER CLOCK
Delta39K-4
PT Clock to PT Clock
DATA
INPUT
t
t
SCS2PT
MCSPT
PT CLOCK
Delta39K-5
Asynchronous Reset/Preset
t
PRW
RESET/PRESET
INPUT
t
PRO
REGISTERED
OUTPUT
t
PRR
CLOCK
Delta39K-6
Output Enable/Disable
GLOBAL CONTROL
INPUT
t
t
EA
ER
OUTPUTS
Delta39K-7
Document #: 38-03039 Rev. **
Page 29 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Cluster Memory Asynchronous Timing
WRITE
READ
READ
ADDRESS (AT
THE CLUSTER
INPUT)
WRITE ENABLE
tCLMPWE
INPUT
tCLMCLAA
tCLMCLAA
OUTPUT
Delta39K-8
Cluster Memory Asynchronous Timing 2
WRITE
READ
READ
ADDRESS (AT THE
I/O PIN)
tCLMHA
tCLMSA
WRITE ENABLE
tCLMPWE
INPUT
tCLMHD
tCLMSD
tCLMAA
tCLMAA
OUTPUT
Delta39K-9
Document #: 38-03039 Rev. **
Page 30 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Cluster Memory Synchronous Flow Through Timing
READ
WRITE
READ
GLOBAL
CLOCK
tCLMCYC1
tCLMS
tCLMH
ADDRESS
tCLMS
tCLMH
tCLMS
tCLMH
WRITE
ENABLE
REGISTERED
INPUT
tCLMDV1
tCLMDV1
tCLMDV1
REGISTERED
OUTPUT
Delta39K-10
Cluster Memory Internal Clocking
MACROCELL
INPUT CLOCK
tMACCLMS1
tCLMMACS1
CLUSTER MEMORY
INPUT CLOCK
tCLMMACS2
tMACCLMS2
CLUSTER MEMORY
OUTPUT CLOCK
Delta39K-11
Document #: 38-03039 Rev. **
Page 31 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Cluster Memory Output Register Timing (Asynchronous Inputs)
ADDRESS
WRITE
ENABLE
INPUT
tCLMCYC2
GLOBAL CLOCK
(OUTPUT REGISTER)
tCLMDV2
EGISTERED
OUTPUT
Delta39K-12
Cluster Memory Output Register Timing (Synchronous Inputs)
ADDRESS
WRITE
ENABLE
INPUT
tCLMCYC2
GLOBAL CLOCK
(INPUT REGISTER)
tCLMS
tCLMH
GLOBAL CLOCK
(OUTPUT REGISTER)
tCLMDV2
REGISTERED
OUTPUT
Delta39K-13
Document #: 38-03039 Rev. **
Page 32 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory DP Asynchronous Timing
An+1
An+2
ADDRESS
An-1
An
tCHMHA
tCHMSA
tCHMPWE
WRITE
ENABLE
tCHMSD
tCHMHD
DATA
INPUT
Dn
tCHMAA
tCHMAA
Dn-1
OUTPUT
Dn+1
Dn
Delta39K-14
Channel Memory Internal Clocking
MACROCELL INPUT
CLOCK
tMACCHMS1
tCHMMACS1
CHANNEL MEMORY
INPUT CLOCK
tCHMMACS2
tMACCHMS2
CHANNEL MEMORY
OUTPUT CLOCK
Delta39K-15
Document #: 38-03039 Rev. **
Page 33 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory Internal Clocking 2
MACROCELL INPUT
CLOCK
tCHMMACS
FIFO READ
CLOCK
tMACCHMS
FIFO WRITE
CLOCK
tCHMMACF
FIFO READ OR
WRITE CLOCK
Delta39K-16
Channel Memory DP SRAM Flow Through R/W Timing
CLOCK
tCHMCYC1
tCHMS
tCHMH
An+3
An+2
An-1
An
An+1
ADDRESS
WRITE
ENABLE
tCHMS
tCHMH
DATA
INPUT
Dn-1
Dn+1
Dn+3
tCHMDV1
tCHMDV1
tCHMDV1
tCHMDV1
Dn+1
Dn-1
Dn
Dn+2
Dn+3
OUTPUT
Delta39K-17
Document #: 38-03039 Rev. **
Page 34 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory DP SRAM Pipeline R/W Timing
CLOCK
tCHMCYC2
tCHMS
tCHMH
An-1
An
An+2
An+1
An+3
ADDRESS
tCHMH
tCHMS
WRITE
ENABLE
tCHMH
tCHMS
DATA
INPUT
Dn+3
Dn-1
Dn+1
tCHMDV2
tCHMDV2
tCHMDV2
Dn-1
Dn
Dn+1
OUTPUT
Dn+2
Delta38K-18
Dual-Port Asynchronous Address Match Busy Signal
Bn
An
ADDRESS A
ADDRESS B
An-1
An
An+1
tCHMBA
tCHMBA
ADDRESS
MATCH
Delta39K-19
Document #: 38-03039 Rev. **
Page 35 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Dual-Port Synchronous Address Match Busy Signal
CLOCK
An-1
An
ADDRESS A
ADDRESS B
An
Bn-1
Bn+1
tCHMS
tCHMS
ADDRESS
MATCH
tCHMBDV
tCHMBDV
Delta39K-20
Document #: 38-03039 Rev. **
Page 36 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Empty/Write Timing
PORT B CLOCK
tCHMCLK
tCHMFS
tCHMFH
WRITE ENABLE
REGISTERED
INPUT
Dn+1
EMPTY FLAG
(active low)
tCHMSKEW2
tCHMFO
tCHMFO
PORT A CLOCK
READ ENABLE
RE
tCHMFRDV
REGISTERED
OUTPUT
Delta39K-21
Document #: 38-03039 Rev. **
Page 37 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Full/Read Timing
PORT A CLOCK
tCHMCLK
tCHMFS
tCHMFH
READ ENABLE
tCHMFRDV
REGISTERED
OUTPUT
FULL FLAG
(active low)
tCHMFO
tCHMSKEW1 tCHMFO
PORT B CLOCK
WRITE ENABLE
tCHMS
tCHMH
REGISTERED
INPUT
Delta39K-22
Document #: 38-03039 Rev. **
Page 38 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Programmable Flag Timing
PORT B CLOCK
tCHMCLK
tCHMFH
tCHMFS
WRITE ENABLE
PROGRAMMABLE
ALMOST-EMPTY FLAG
(active LOW)
tCHMSKEW3
tCHMFO
tCHMFO
PORT A CLOCK
READ ENABLE
tCHMFH
tCHMFS
PORT B CLOCK
tCHMCLK
WRITE ENABLE
tCHMFO
tCHMFO
PROGRAMMABLE
ALMOST-FULL FLAG
(active LOW)
tCHMSKEW3
PORT A CLOCK
READ ENABLE
Delta39K-23
Document #: 38-03039 Rev. **
Page 39 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Switching Waveforms (continued)
Channel Memory Synchronous FIFO Master Reset Timing
tCHMFRS
MASTER
RESET INPUT
tCHMFRSR
READ ENABLE /
WRITE ENABLE
tCHMFRSF
EMPTY/FULL
PROGRAMMABLE
ALMOST EMPTY
FLAGS
tCHMFRSF
HALF-FULL/
PROGRAMMABLE
ALMOST FULL
FLAGS
tCHMFRSF
REGISTERED
OUTPUT
Delta39K-24
Document #: 38-03039 Rev. **
Page 40 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
C Y 3 9 1 0 0 V 6 7 6 - 2 0 0 M B C
Cypress Semiconductor ID
Family Type
39 = Delta39K Family
Operating Conditions
Commercial
Industrial
0°C to +70°C
-40°C to +85°C
Gate Density
15=15k Usable Gates
30=30k Usable Gates
50=50k Usable Gates
165=165k Usable Gates
200=200k Usable Gates
250=250k Usable Gates
Package Type
N
= Plastic Quad Flat Pack (PQFP)
NT = Thermally Enhanced Quad Flat Pack (EQFP)
BG = Ball Grid Array (BGA)
BB = Fine-Pitch Ball Grid Array (FBGA)
1.0-mm Lead Pitch
MG = Self-Boot Solution - Ball Grid Array
MB = Self-Boot Solution - Fine Pitch Ball Grid Array
1.0-mm Lead Pitch
100=100k Usable Gates 350=350k Usable Gates
Operating Reference Voltage
V = 3.3V or 2.5V Supply Voltage
Z = 1.8V
Supply Voltage
Pin Count
144 = 144 Balls
208 = 208 Leads
256 = 256 Balls
388 = 388 Balls
484 = 484 Balls
676 = 676 Balls
Speed
250 = 250 MHz 167 = 167 MHz
222 = 222 MHz 154 = 154 MHz
200 = 200 MH
181 = 181 MHz
125 = 125 MHz
83 = 83 MHz
Delta39K Pin Table
Please refer to document titled “Delta39K Pin Tables” for pinouts of all the packages of all Delta39K family members. You can
access this document on the internet at: http://www.cypress.com/pld/datasheets.html.
[16]
Delta39K Part Numbers
(Ordering Information)
Speed
Device (MHz)
Package
Name
Self-Boot
Solution
Operating
Range
Ordering Code
Package Type
39K15
250
CY39015V208-250NTC
CY39015Z208-250NC
CY39015V144-250BBC
CY39015Z144-250BBC
CY39015V256-250BBC
CY39015Z256-250BBC
CY39015V256-250MBC
CY39015Z256-250MBC
CY39015V208-125NTC
CY39015Z208-125NC
CY39015V144-125BBC
CY39015Z144-125BBC
CY39015V256-125BBC
CY39015Z256-125BBC
CY39015V256-125MBC
CY39015Z256-125MBC
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
Commercial
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
125
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
Document #: 38-03039 Rev. **
Page 41 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
CY39015V208-125NTI
CY39015Z208-125NI
CY39015V144-125BBI
CY39015Z144-125BBI
CY39015V256-125BBI
CY39015Z256-125BBI
CY39015V256-125MBI
CY39015Z256-125MBI
CY39015V208-83NTC
CY39015Z208-83NC
CY39015V144-83BBC
CY39015Z144-83BBC
CY39015V256-83BBC
CY39015Z256-83BBC
CY39015V256-83MBC
CY39015Z256-83MBC
CY39015V208-83NTI
CY39015Z208-83NI
Name
NT208
N208
Package Type
39K15
125
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
Industrial
Commercial
Industrial
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
83
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
NT208
N208
208-Lead Plastic Quad Flat Pack
208-Lead Enhanced Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
CY39015V144-83BBI
CY39015Z144-83BBI
CY39015V256-83BBI
CY39015Z256-83BBI
CY39015V256-83MBI
CY39015Z256-83MBI
CY39030V208-222NTC
CY39030Z208-222NC
CY39030V144-222BBC
CY39030Z144-222BBC
CY39030V256-222BBC
CY39030Z256-222BBC
CY39030V256-222MBC
CY39030Z256-222MBC
CY39030V208-125NTC
CY39030Z208-125NC
CY39030V144-125BBC
CY39030Z144-125BBC
CY39030V256-125BBC
CY39030Z256-125BBC
CY39030V256-125MBC
CY39030Z256-125MBC
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
39K30
222
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
Commercial
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
125
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
Document #: 38-03039 Rev. **
Page 42 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
CY39030V208-125NTI
CY39030Z208-125NI
CY39030V144-125BBI
CY39030Z144-125BBI
CY39030V256-125BBI
CY39030Z256-125BBI
CY39030V256-125MBI
CY39030Z256-125MBI
CY39030V208-83NTC
CY39030Z208-83NC
CY39030V144-83BBC
CY39030Z144-83BBC
CY39030V256-83BBC
CY39030Z256-83BBC
CY39030V256-83MBC
CY39030Z256-83MBC
CY39030V208-83NTI
CY39030Z208-83NI
Name
NT208
N208
Package Type
39K30
125
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
Industrial
Commercial
Industrial
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
83
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
NT208
N208
208-Lead Plastic Quad Flat Pack
208-Lead Enhanced Quad Flat Pack
144-Lead Fine Pitch Ball Grid Array
144-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
CY39030V144-83BBI
CY39030Z144-83BBI
CY39030V256-83BBI
CY39030Z256-83BBI
CY39030V256-83MBI
CY39030Z256-83MBI
CY39050V208-222NTC
CY39050Z208-222NC
CY39050V256-222BBC
CY39050Z256-222BBC
CY39050V388-222MGC
CY39050Z388-222MGC
CY39050V484-222MBC
CY39050Z484-222MBC
CY39050V208-125NTC
CY39050Z208-125NC
CY39050V256-125BBC
CY39050Z256-125BBC
CY39050V388-125MGC
CY39050Z388-125MGC
CY39050V484-125MBC
CY39050Z484-125MBC
BB144
BB144
BB256
BB256
MB256 256-Lead Fine Pitch Ball Grid Array
MB256 256-Lead Fine Pitch Ball Grid Array
√
√
39K50
222
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
Commercial
BB256
BB256
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
125
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
BB256
BB256
MG388 388-Lead Pitch Ball Grid Array
MG388 388-Lead Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
√
√
√
√
Document #: 38-03039 Rev. **
Page 43 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
CY39050V208-125NTI
CY39050Z208-125NI
CY39050V256-125BBI
CY39050Z256-125BBI
CY39050V388-125MBI
CY39050Z388-125MBI
CY39050V484-125MBI
CY39050Z484-125MBI
CY39050V208-83NTC
CY39050Z208-83NC
CY39050V256-83BBC
CY39050Z256-83BBC
CY39050V388-83MGC
CY39050Z388-83MGC
CY39050V484-83MBC
CY39050Z484-83MBC
CY39050V208-83NTI
CY39050Z208-83NI
Name
NT208
N208
Package Type
39K50
125
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
Industrial
Commercial
Industrial
BB256
BB256
MG388 388-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Fine Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
√
√
√
√
83
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
BB256
BB256
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Plastic Quad Flat Pack
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
CY39050V256-83BBI
CY39050Z256-83BBI
CY39050V388-83MGI
CY39050Z388-83MGI
CY39050V484-83MBI
CY39050Z484-83MBI
BB256
BB256
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
MB484 484-Lead Fine Pitch Ball Grid Array
Document #: 38-03039 Rev. **
Page 44 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
Name
NT208
BB256
BB484
Package Type
39K100
200
CY39100V208-200NTC
CY39100V256-200BBC
CY39100V484-200BBC
CY39100V388-200MGC
CY39100V676-200MBC
CY39100V208A-200NTC
CY39100V256A-200BBC
CY39100V484A-200BBC
CY39100V388A-200MGC
CY39100V676A-200MBC
CY39100V208B-200NTC
CY39100Z208B-200NC
CY39100V256B-200BBC
CY39100Z256B-200BBC
CY39100V484B-200BBC
CY39100Z484B-200BBC
CY39100V388B-200MGC
CY39100Z388B-200MGC
CY39100V676B-200MBC
CY39100Z676B-200MBC
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
[17]
MG388 388-Lead Ball Grid Array
√
√
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
BB256
BB484
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
√
√
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB256
BB256
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
Document #: 38-03039 Rev. **
Page 45 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
Name
NT208
BB256
BB484
Package Type
39K100
125
CY39100V208-125NTC
CY39100V256-125BBC
CY39100V484-125BBC
CY39100V388-125MGC
CY39100V676-125MBC
CY39100V208A-125NTC
CY39100V256A-125BBC
CY39100V484A-125BBC
CY39100V388A-125MGC
CY39100V676A-125MBC
CY39100V208B-125NTC
CY39100Z208B-125NC
CY39100V256B-125BBC
CY39100Z256B-125BBC
CY39100V484B-125BBC
CY39100Z484B-125BBC
CY39100V388B-125MGC
CY39100Z388B-125MGC
CY39100V676B-125MBC
CY39100Z676B-125MBC
CY39100V208B-125NTI
CY39100Z208B-125NI
CY39100V256B-125BBI
CY39100Z256B-125BBI
CY39100V484B-125BBI
CY39100Z484B-125BBI
CY39100V388B-125MGI
CY39100Z388B-125MGI
CY39100V676B-125MBI
CY39100Z676B-125MBI
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
[17]
MG388 388-Lead Ball Grid Array
√
√
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
BB256
BB484
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
√
√
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB256
BB256
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Industrial
BB256
BB256
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
Document #: 38-03039 Rev. **
Page 46 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
Name
NT208
BB256
BB484
Package Type
39K100
83
CY39100V208-83NTC
CY39100V256-83BBC
CY39100V484-83BBC
CY39100V388-83MGC
CY39100V676-83MBC
CY39100V208A-83NTC
CY39100V256A-83BBC
CY39100V484A-83BBC
CY39100V388A-83MGC
CY39100V676A-83MBC
CY39100V208B-83NTC
CY39100Z208B-83NC
CY39100V256B-83BBC
CY39100Z256B-83BBC
CY39100V484B-83BBC
CY39100Z484B-83BBC
CY39100V388B-83MGC
CY39100Z388B-83MGC
CY39100V676B-83MBC
CY39100Z676B-83MBC
CY39100V208B-83NTI
CY39100Z208B-83NI
CY39100V256B-83BBI
CY39100Z256B-83BBI
CY39100V484B-83BBI
CY39100Z484B-83BBI
CY39100V388B-83MGI
CY39100Z388B-83MGI
CY39100V676B-83MBI
CY39100Z676B-83MBI
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
[17]
MG388 388-Lead Ball Grid Array
√
√
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
BB256
BB484
208-Lead Enhanced Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
MG388 388-Lead Ball Grid Array
√
√
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB256
BB256
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
256-Lead Fine Pitch Ball Grid Array
256-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Industrial
BB256
BB256
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
Document #: 38-03039 Rev. **
Page 47 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
CY39165V208-181NTC
CY39165Z208-181NC
CY39165V484-181BBC
CY39165Z484-181BBC
CY39165V388-181MGC
CY39165Z388-181MGC
CY39165V676-181MBC
CY39165Z676-181MBC
CY39165V208-125NTC
CY39165Z208-125NC
CY39165V484-125BBC
CY39165Z484-125BBC
CY39165V388-125MGC
CY39165Z388-125MGC
CY39165V676-125MBC
CY39165Z676-125MBC
CY39165V208-125NTI
CY39165Z208-125NI
CY39165V484-125BBI
CY39165Z484-125BBI
CY39165V388-125MGI
CY39165Z388-125MGI
CY39165V676-125MBI
CY39165Z676-125MBI
CY39165V208-83NTC
CY39165Z208-83NC
CY39165V484-83BBC
CY39165Z484-83BBC
CY39165V388-83MGC
CY39165Z388-83MGC
CY39165V676-83MBC
CY39165Z676-83MBC
CY39165V208-83NTI
CY39165Z208-83NI
Name
NT208
N208
Package Type
39K165
181
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
Commercial
Industrial
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
125
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
83
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Industrial
CY39165V484-83BBI
CY39165Z484-83BBI
CY39165V388-83MGI
CY39165Z388-83MGI
CY39165V676-83MBI
CY39165Z676-83MBI
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
Document #: 38-03039 Rev. **
Page 48 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[16]
Delta39K Part Numbers
(Ordering Information) (continued)
Speed
Package
Self-Boot
Solution
Operating
Range
Device (MHz)
Ordering Code
CY39200V208-167NTC
CY39200Z208-167NC
CY39200V484-167BBC
CY39200Z484-167BBC
CY39200V388-167MGC
CY39200Z388-167MGC
CY39200V676-167MBC
CY39200Z676-167MBC
CY39200V208-125NTC
CY39200Z208-125NC
CY39200V484-125BBC
CY39200Z484-125BBC
CY39200V388-125MGC
CY39200Z388-125MGC
CY39200V676-125MBC
CY39200Z676-125MBC
CY39200V208-125NTI
CY39200Z208-125NI
CY39200V484-125BBI
CY39200Z484-125BBI
CY39200V388-125MGI
CY39200V388-125MGI
CY39200V676-125MBI
CY39200Z676-125MBI
CY39200V208-83NTC
CY39200Z208-83NC
CY39200V484-83BBC
CY39200Z484-83BBC
CY39200V388-83MGC
CY39200Z388-83MGC
CY39200V676-83MBC
CY39200Z676-83MBC
CY39200V208-83NTI
CY39200Z208-83NI
Name
NT208
N208
Package Type
39K200
167
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
Commercial
Industrial
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
125
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
83
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Commercial
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
NT208
N208
208-Lead Enhanced Quad Flat Pack
208-Lead Plastic Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
484-Lead Fine Pitch Ball Grid Array
Industrial
CY39200V484-83BBI
CY39200Z484-83BBI
CY39200V388-83MGI
CY39200Z388-83MGI
CY39200V676-83MBI
CY39200Z676-83MBI
BB484
BB484
MG388 388-Lead Ball Grid Array
√
√
√
√
MG388 388-Lead Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
MB676 676-Lead Fine Pitch Ball Grid Array
16. For the availability of Delta39KZ devices (1.8V), please contact your local sales office
17. Refer to the section titled “Delta39K100 Revisions/Errata” on page 50
Document #: 38-03039 Rev. **
Page 49 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
4. An ESD failure is very unlikely. CDM ESD passes 1000V.
HBM ESD passes 3300V with all I/O bank’s VCCIO shorted
together. If VCCIOs in a bank are tested separately a per-
centage of parts will fail HBM ESD over 500V.
Delta39K100 Revisions/Errata
Three revisions of Delta39K100, in 3.3V version, are currently
offered which are marked as CY39100Vxxx, CY39100VxxxA
and CY39100VxxxB. CY39100VxxxB devices operate exactly
as specified in this datasheet. Following paragraphs explain
the operation of the CY39100Vxxx and CY39100VxxxA parts
as different from this datasheet:
CY39100VxxxA
1. The part always configures on power-up and will reconfig-
ure on HIGH to LOW edge of the Reconfig pin. Please refer
to the application note titled “Configuring
Delta39K/Quantum38K” at http://www.cypress.com for
more details.
CY39100Vxxx
1. The internal regulator takes several seconds to power
down. Hence, cycling the power supply (within 8 seconds)
may cause a high standby current (200 mA to 1A) until the
part is configured.
2. The Self Config instruction starts reconfiguring the CPLD
upon execution of the Update-IR state of the JTAG TAP
controller state machine. In CY39100VxxxB parts, Self
Config instruction is executed upon execution of Test-Log-
ic-Reset state of the TAP controller.
2. The part always configures on power-up and will reconfig-
ure on HIGH to LOW edge of the Reconfig pin. Please refer
to the application note titled “Configuring
Delta39K/Quantum38K” at http://www.cypress.com for
more details.
3. An ESD failure is very unlikely. CDM ESD passes 1000V.
HBM ESD passes 3300V with all I/O bank’s VCCIO shorted
together. If VCCIOs in a bank are tested separately a per-
centage of parts will fail HBM ESD over 500V.
3. The Self Config instruction starts reconfiguring the CPLD
upon execution of the Update-IR state of the JTAG TAP
controller state machine. In CY39100VxxxB parts, Self
Config instruction is executed upon execution of Test-Log-
ic-Reset state of the TAP controller.
Document #: 38-03039 Rev. **
Page 50 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
[18]
CPLD Boot EEPROM
Part Numbers (Ordering Information)
Speed
(MHz)
Package
Name
Operating
Device
Ordering Code
CY3LV010-10JC
CY3LV010-10JI
CY3LV512-10JC
CY3LV512-10JI
Package Type
Range
1Mbit
15
10
15
10
20J
20J
20J
20J
20-Lead Plastic Leaded Chip Carrier Commercial
20-Lead Plastic Leaded Chip Carrier
Industrial
512Kbit
20-Lead Plastic Leaded Chip Carrier Commercial
20-Lead Plastic Leaded Chip Carrier
Industrial
Recommended CPLD Boot EEPROM for corresponding Delta39K CPLDs
CPLD Device
39K15
Recommended boot EEPROM
CY3LV256
39K30
CY3LV512
39K50
CY3LV512
39K100
39K165
39K200
CY3LV010
CY3LV020
CY3LV020
Note:
18. See the data sheet titled “CPLD Boot EEPROM” for detailed architectural and timing information.
Document #: 38-03039 Rev. **
Page 51 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Package Diagrams
208-Lead Plastic Quad Flatpack (PQFP) N208
208-Lead Enhanced Quad Flat Pack (EQFP) NT208
51-85069-B
Document #: 38-03039 Rev. **
Page 52 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Package Diagrams (continued)
388-Lead Ball Grid Array MG388
51-85103
Document #: 38-03039 Rev. **
Page 53 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Package Diagrams (continued)
256-Ball Thin Ball Grid Array (17 x 17 x 1.6 mm) BB256/MB256
51-85108-A
Document #: 38-03039 Rev. **
Page 54 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Package Diagrams (continued)
484-Ball Thin Ball Grid Array (23 x 23 x 1.6 mm) BB484/MB484
51-85124
Document #: 38-03039 Rev. **
Page 55 of 57
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Package Diagrams (continued)
676-Ball FBGA (27 x 27 x 1.6 mm) BB676
51-85125
Mechanical drawings of 144FBGA will be available soon.
For package sizes and ball pitch see page 2.
NoBL, PIM, Spread Aware, Warp, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, and Delta39K are trademarks of
Cypress Semiconductor Corporation.
ZBT is a trademark of IDT. QDR is a trademark of Micron, IDT, and Cypress Semiconductor Corporation.
SpeedWave, and ViewDraw are trademarks of ViewLogic.
Document #: 38-03039 Rev. **
Page 56 of 57
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Delta39K™ ISR™
CPLD Family
PRELIMINARY
Document Title: DELTA39K™ ISR™ CPLD FAMILY
Document Number: 38-03039
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
Change from Spec #: 38-00830 to 38-03039
**
106503
05/30/01
SZV
Document #: 38-03039 Rev. **
Page 57 of 57
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