CY2AVC16835ZCT [CYPRESS]
Bus Driver, 1-Func, 18-Bit, True Output, PDSO56, 6 X 12 MM, TSSOP2-56;
| 型号： | CY2AVC16835ZCT |
| 厂家： | 
CYPRESS |
| 描述： | Bus Driver, 1-Func, 18-Bit, True Output, PDSO56, 6 X 12 MM, TSSOP2-56 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总10页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY2AVC16835
18-Bit Universal Bus/Driver with Three-State Outputs
Features
Description
• Lessthan2.8-nSmaximuminputtooutputdelayat 3.3V.
• Wide supply voltage range of 1.2V to 3.6 V
• Over voltage- tolerant inputs/outputs allow
mixed-voltage-mode data communications
• Output circuitry with VOI™ control minimizes
over/undershoot and maximizes output drive
• Configurable as latch or register
• Extended temp range of –40° to + 85° C
• 2KV ESD
The CY2AVC16835 is a high performance, low voltage 18-bit
universal bus driver. It is operational from 1.2V to 3.6V VDD
,
but is designed specifically for 1.5V to 3.6V VDD operation.
Data flow from A to Y is controlled by the output-enable (OE).
The device operates in the transparent mode when the
latch-enable (LE) input is high. The A data is latched if the
clock (CLK) input is held at a high or low logic level. If LE is
low, the A data is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is high, the outputs are in the
high-impedance state.
• 56-pin TSSOP package
To ensure the high-impedance state during power up or power
down, OE should be tied VDD through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the OE driving device.
The output circuitry is dynamically controlled via Variable
Output Impedance (VOI), which, during output transitions,
initially lowers the output impedance to effectively drive the
load and, subsequently, raises the impedance to reduce noise.
Figure 1 shows typical VOL vs. IOL and VOH vs IOH curves
to illustrate the output impedance and drive capability of the
circuit.
Block Diagram
Pin Configuration
NC
NC
Y1
VSS
Y2
Y3
VDD
Y4
Y5
Y6
VSS
Y7
VSS
NC
A1
VSS
A2
A3
VDD
A4
A5
A6
VSS
A7
1
2
3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
4
5
6
7
8
9
27
OE
30
CLK
28
LE
54
A1
D
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3
LE
CLK
Y1
Y8
Y9
A8
A9
Y10
Y11
Y12
VSS
Y13
Y14
Y15
VDD
Y16
Y17
VSS
Y18
OE
LE
A10
A11
A12
VSS
A13
A14
A15
VDD
A16
A17
VSS
A18
CLK
VSS
To 17 Other Channels
Cypress Semiconductor Corporation
Document #: 38-07462 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 16, 2003
CY2AVC16835
Pin Description
Pin No.
Name
NC
Description
1,2,55
No Connect
3, 5, 6, 8, 9, 10, 12,13, 14, 15,16, 17, 19,
20, 21, 23, 24, 26
Y(1:18)
Data Outputs
4, 11, 18, 25, 29, 32, 39, 46, 53, 56
VSS
VDD
Ground
7, 22, 35, 50
Positive Supply Voltage
27
28
30
OE
Output Enable Pin (Active LOW)
Latch Enable (Transparent High)
Clock
LE
CLK
A (1:18)
54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41,
40, 38, 37, 36, 34, 33, 31
Data Inputs
Table 1. Function Table
Inputs
Outputs[1]
OE
H
L
LE
X
H
H
L
CLK
X
A
X
L
Y
Z
L
X
L
X
H
L
H
L
L
↑
L
L
↑
H
X
H
Y
L
L
L/H
Table 2. Capacitance Table[2]
Parameter
Description
Conditions
Vin = 0V
Typ.
Max.
Unit
pF
Cin
Input Capacitance
2.5
6.5
6.5
7
9
9
Cout
Output Capacitance
I/O Port Capacitance
Vout = 0V
Vin = 0V
pF
CI/O
pF
Notes:
1. Output level before the indicated steady_state input conditions were established, provided that CLK is high before LE goes low.
2. As applicable to device type.
Document #: 38-07462 Rev. *A
Page 2 of 10
CY2AVC16835
Absolute Maximum Conditions[3, 4]
Parameter
Description
Terminal Voltage with respect to VSS
Terminal Voltage with respect to VSS
Max.
–0.5 to + 4.6
–0.5 to VDD + 0.5
–65° to + 150°C
–50 to + 50
±100
Unit
V
[5]
VTERM
VTERM
TSTG
IOUT
IIK
[6]
V
Storage Temperature
°C
DC Output Current
mA
mA
mA
mA
Continuous Clamp Current, VI<0 or VI>VDD
Continuous Clamp Current, Vo<0
Continuous Current through each VDD or VSS
IOK
–50
IDD
ISS
±100
Variable Output Impedance Control
Pull Down
Pull Up
3.5
3.5
3
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0.5
0
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
-0.18
-0.16
-0.14
-0.12
-0.1
-0.08
-0.06
-0.04
-0.02
0
Iol (A)
Ioh (A)
Vdd=3.3 V
Vdd=2.5V
Vdd=1.8V
Vdd = 3 . 3 V
Vdd=2.5V
Vdd=1.8 V
Figure 1. Output Voltage vs. Output Current (TA = 25°C)
DC Electrical Specifications (TAMB = –40°C to +85°C)
Parameter
Description
Conditions
Min.
Typ.[7]
Max.
Unit
VIH
High-level input voltage
VDD = 1.2V
VDD
–
–
–
–
–
–
–
–
–
–
–
–
V
V
V
V
V
V
V
V
V
V
VDD = 1.4V to 1.65V
VDD = 1.65V to 1.95V
VDD = 2.3V to 2.7V
VDD = 3.0V to 3.6V
VDD = 1.2V
0.65 × VDD
0.65 VDD
–
1.7
2.0
–
–
–
VIL
Low-level input voltage
VSS
VDD = 1.4V to 1.65V
VDD = 1.65V to 1.95V
VDD = 2.3V to 2.7V
VDD = 3.0V to 3.6V
–
0.35 VDD
0.35 VDD
0.7
–
–
–
0.8
Notes:
3. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Stresses greater that those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended period may affect reliability.
5. VDD terminals.
6. All terminals except VDD.
Document #: 38-07462 Rev. *A
Page 3 of 10
CY2AVC16835
DC Electrical Specifications (TAMB = –40°C to +85°C) (continued)
Parameter
Description
Conditions
VDD = 1.4V to 3.6V IO = –100 µA
DD = 1.4V
Min.
Typ.[7]
Max.
–
Unit
V
[8]
VOH
High-level output voltage
VDD -0.20
–
–
–
–
–
–
–
–
–
–
–
–
–
–
V
IO = –2 µA
IO = –4 mA
IO = –8 mA
IO = –12 mA
IO = 100 µA
IO = 2 mA
1.05
1.2
1.75
2.3
–
–
V
VDD = 1.65V
VDD = 2.3V
–
V
–
V
VDD = 3.0V
–
V
VDD = 1.4V to 3.6V
VDD = 1.4V
0.20
0.40
0.45
0.55
0.70
±2.5
±10
40
V
[8]
VOL
Low-level output voltage
–
V
V
DD = 1.65V
VDD = 2.3V
DD = 3.0V
IO = 4 mA
–
V
IO = 8 mA
–
V
V
IO = 12 mA
–
V
II
Input leakage current per pin VDD = 1.65V to 3.6V Vin = VDD or VSS
–
µA
µA
µA
µA
IOFF
IDD
IOZ
Power off leakage current
Quiescent supply Current
VI or VO = 3.6V
VDD = 3.6V
VDD = 0V
–
IO = 0
–
Three-state output OFF-state VDD = 3.6V
current
VO= VDD or VSs
–
±10
AC Electrical Specifications
VDD =1.5V
+ 0.1V
VDD =1.8V
+ 0.15V
VDD =2.5V
+ 0.2V
VDD =3.3V
+ 0.3V
VDD = 1.2V
Parameters
Min.
–
Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Fclock Clock Frequency
–
–
–
–
–
–
–
–
–
–
–
150
–
–
150
–
–
150 MHz
tw
Pulse
LE high
–
3.3
3.3
0.7
3.3
3.3
0.7
3.3
1.0
0.7
–
–
–
ns
ns
ns
Duration
CLK High or Low
–
–
–
3.3
–
tsu
Set-up
Time
Data Before CLK
HIGH
1.0
0.9
–
Data
CLK High 1.7
–
1.6
–
1.2
–
0.8
–
0.8
–
–
BeforeLE
LOW
CLK Low
2.0
–
–
–
–
0.9
1.3
2.4
2.1
–
–
–
0.7
1.0
2.0
1.7
–
–
–
0.5
0.9
1.7
1.5
–
–
–
–
0.5
1.3
1.6
1.4
–
–
–
–
ns
ns
–
th
Hold time Data after CLK HIGH 1.5
DataAfter CLK High 3.2
–
–
–
LE LOW Or Low
2.8
–
–
–
From
To
Typ.
4.5
6.2
5.2
7.1
6.9
–
–
–
–
–
tpd
An
LE
Yn
1.2
1.6
1.6
2.4
2.2
6.2
9.4
7.8
10.2
10.3
1.3
1.3
1.5
2.2
2
5.5
7.2
6
1.0
1.1
1
3.1
4.7
3.7
6.7
5.3
0.9
0.9
0.8
1.2
1.1
2.5
3.8
3.1
6.2
5.3
ns
CLK
OE
ten
Yn
Yn
8.8
8.4
1.5
1.2
ns
ns
tdis
OE
Notes:
7. All typical values are measured at TAMB = 25°C.
8. VIN = VIL or VIH
.
Document #: 38-07462 Rev. *A
Page 4 of 10
CY2AVC16835
Parameter Measurement
VDD = 1.2V and 1.5V ± 0.1V
Timing Diagrams
2x VDD
Open
2 k ohm
S1
tw
VDD/2
From Output
Under Test
VSS
VDD
CL = 15 pF
Input
2 k ohm
VDD/2
0 V
Voltage Waveforms
Pulse Duration
Load Circuit
Waveform 1
Waveform 4
VDD
0 V
Output
Control
(low-level
enabling)
Output
VD
VDD/2
th
Timing Input
Data Input
VDD/2
VDD/2
D
0 V
tsu
tPZL
tPLZ
VD
Waveform 1
S1 at 2 x VDD
VDD
0 V
OL + 0.1 VD
VOL
V
DD/2
V
VDD/2
VDD/2
tPZH
tPHZ
Voltage Waveforms
Setup and Hold Times
VOH
0 V
Output
Waveform 2
S1 at GND
VOH- 0.1 V
VDD/2
Waveform 2
Voltage Waveforms
Enable and Disable Times
VDD
Waveform 5
VDD/2
VDD/2
Input
tPLH
0 V
tPHL
Test
S1
Open
V
VDD/2
VDD/2 OH
VOL
t
t
t
/t
PLH PHL
Output
/t
2 x V
PLZ PZL
DD
/t
Voltage Waveforms
Propagation Delay Times
PHZ PZH
VSS
Waveform 3
Figure 2. Load Circuit and Voltage Waveforms for VDD = 1.2V and 1.5V ± 0.1V[9,10,11,12,13,14,15,16]
Notes:
9. CL includes probe and jig capacitance.
10. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
11. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
12. All input pulses are supplied by generators having the following characteristics: PRR≤ 10MHz, Z0 = 50Ω, tR ≤2ns, tF≤ 2 ns.
13. The outputs are measured one at a time with on transition per measurement.
14. tPLZ snf tPHZ are the same as tDIS
15. tPZl and tPZH are the same as ten
16. tPLH and tPHL are the same as tPD
.
.
.
Document #: 38-07462 Rev. *A
Page 5 of 10
CY2AVC16835
Parameter Measurement
VDD = 1.8V ± 0.15V
Timing Diagrams
2x VDD
Open
1 k ohm
S1
tw
VDD/2
From Output
Under Test
VSS
VDD
Input
1 k ohm
VDD/2
CL = 15 pF
0 V
Voltage Waveforms
Pulse Duration
Load Circuit
Waveform 1
Waveform 4
VDD
0 V
Output
Control
(low-level
enabling)
Output
VD
VDD/2
th
Timing Input
Data Input
VDD/2
VDD/2
D
0 V
tsu
tPZL
tPLZ
VDD
Waveform 1
S1 at 2 x VDD
VDD
0 V
V
DD/2
V
OL + 0.15 V
VDD/2
VDD/2
VOL
tPZH
tPHZ
Voltage Waveforms
Setup and Hold Times
VOH
Output
Waveform 2
S1 at GND
VOH- 0.15 V
VDD/2
0 V
Waveform 2
Voltage Waveforms
Enable and Disable Times
VDD
Waveform 5
VDD/2
VDD/2
Input
tPLH
0 V
tPHL
Test
S1
Open
V
VDD/2
VDD/2 OH
VOL
t
t
t
/t
PLH PHL
Output
/t
2 x V
PLZ PZL
DD
/t
Voltage Waveforms
Propagation Delay Times
PHZ PZH
VSS
Waveform 3
Figure 3. Load Circuit and Voltage Waveforms for VDD = 1.8V ± 0.15V[9,10,11,12,13,14,15,16]
Document #: 38-07462 Rev. *A
Page 6 of 10
CY2AVC16835
Parameter Measurement
VDD =2.5V ± 0.2V
Timing Diagrams
2x VDD
Open
500 ohm
S1
tw
VDD/2
From Output
Under Test
VSS
VDD
CL = 15 pF
Input
500 ohm
VDD/2
0 V
Voltage Waveforms
Pulse Duration
Load Circuit
Waveform 1
Waveform 4
VDD
0 V
Output
Control
(low-level
enabling)
Output
VD
VDD/2
th
Timing Input
Data Input
VDD/2
VDD/2
D
0 V
tsu
tPZL
tPLZ
VD
Waveform 1
S1 at 2 x VDD
VDD
0 V
OL + 0.2 VD
VOL
V
DD/2
V
VDD/2
VDD/2
tPZH
tPHZ
Voltage Waveforms
Setup and Hold Times
VOH
0 V
Output
Waveform 2
S1 at GND
VOH- 0.2 V
VDD/2
Voltage Waveforms
Enable and Disable Times
Waveform 2
VDD
Waveform 5
VDD/2
VDD/2
Input
tPLH
0 V
tPHL
Test
S1
Open
V
VDD/2
VDD/2 OH
VOL
t
t
t
/t
PLH PHL
Output
/t
2 x V
PLZ PZL
DD
/t
Voltage Waveforms
Propagation Delay Times
PHZ PZH
VSS
Waveform 3
Figure 4. Load Circuit and Voltage Waveforms for VDD =2.5V ± 0.2V[9,10,11,12,13,14,15,16]
Document #: 38-07462 Rev. *A
Page 7 of 10
CY2AVC16835
Parameter Measurement
VDD = 3.3V ± 0.3V
Timing Diagrams
2x VDD
Open
500 ohm
S1
tw
VDD/2
From Output
Under Test
VSS
VDD
VDD/2
CL = 15 pF
Input
500 ohm
0 V
Voltage Waveforms
Pulse Duration
Load Circuit
Waveform 1
Waveform 4
VDD
0 V
Output
Control
(low-level
enabling)
Output
VD
VDD/2
th
Timing Input
Data Input
VDD/2
V
DD/2
D
0 V
tsu
tPZL
tPLZ
VD
Waveform 1
S1 at 2 x VDD
VDD
0 V
VOL + 0.3 VD
VOL
VDD/2
VDD/2
VDD/2
tPZH
tPHZ
Voltage Waveforms
Setup and Hold Times
VOH
0 V
Output
Waveform 2
S1 at GND
VOH- 0.3 V
VDD/2
Voltage Waveforms
Enable and Disable Times
Waveform 2
VDD
Waveform 5
VDD/2
VDD/2
Input
tPLH
0 V
tPHL
Test
S1
Open
2 x V
V
VDD/2
VDD/2 OH
VOL
t
/t
PLH PHL
Output
t
t
/t
PLZ PZL
DD
/t
PHZ PZH
VSS
Voltage Waveforms
Propagation Delay Times
Waveform 3
Figure 5. Load Circuit and Voltage Waveforms for VDD = 3.3V ± 0.3V[9,10,11,12,13,14,15,16]
Ordering Information
Part Number
CY2AVC16835ZI
Package Type
56-pin TSSOP
Product Flow
Industrial, –40° to 85°C
CY2AVC16835ZIT
CY2AVC16835ZC
CY2AVC16835ZCT
56-pin TSSOP – Tape and Reel
56-pin TSSOP
Industrial, –40° to 85°C
Commercial, 0° to 70°C
Commercial, 0° to 70°C
56-pin TSSOP – Tape and Reel
Document #: 38-07462 Rev. *A
Page 8 of 10
CY2AVC16835
Package Drawing and Dimension
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
51-85060-*B
VOI is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks
of their respective holders.
Document #: 38-07462 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2AVC16835
Document History Page
Document Title: CY2AVC16835 18-Bit Universal Bus/Driver with Three-State Outputs
Document Number: 38-07462
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
123625
126278
Description of Change
04/14/03
04/21/03
RGL
KKV
New Data Sheet
*A
Addedcommercialinformation to ordering informationtable, was notadded
in previous rev **.
Document #: 38-07462 Rev. *A
Page 10 of 10
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