CY25562_08_技术文档

CY25562

Spread Spectrum Clock Generator

Features

Applications

■ 50 to 200 MHz Operating Frequency Range

■ Wide range of spread selections: 9

■ Accepts Clock and Crystal Inputs

■ High resolution VGA controllers

■ LCD panels and monitors

■ Workstations and servers

■ Low Power Dissipation

❐ 70 mW Typ (Fin = 65 MHz)

Benefits

■ Peak EMI reduction by 8 to 16 dB

■ Fast time to market

■ Frequency Spread Disable Function

■ Center Spread Modulation

■ Low Cycle-to-cycle Jitter

■ 8-pin SOIC Package

■ Cost reduction

Logic Block Diagram

300K

REFERENCE

DIVIDER

Xin/

CLK

1

Loop

Filter

PD

CP

Xout

8

MODULATION

CONTROL

FEEDBACK

DIVIDER

vco

VDD

VSS

2

3

INPUT

DECODER

LOGIC

DIVIDER

&

MUX

4

SSCLK

VDD

20 K

VSS

20 K

VSS

7

5

6

SSCC

S1

S0

Cypress Semiconductor Corporation

Document Number: 38-07392 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 15, 2008

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CY25562

Pinout

Figure 1. Pin Configuration

1

2

3

4

8

XIN/CLK

VDD

XOUT

7 S0

CY25562

6

5

S1

VSS

SSCC

SSCLK

Pin Description

Pin #

Pin Name

Xin/CLK

VDD

Type

Pin Description

1

2

3

4

5

I

P

O

I

Clock or crystal connection input. Refer to Table 1 for input frequency range selection.

Positive power supply

GND

Power supply ground

SSCLK

SSCC

SSCG modulated clock output

Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input

is high and disabled when input is low. This pin is pulled high internally.

6

7

8

S1

S0

I

Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth

selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider

network to V_DDand V_SS. Refer to Logic Block Diagram on page 1.

Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth

selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider

network to V_DDand V_SS. Refer to Logic Block Diagram on page 1.

Xout

O

Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives

Xin/CLK.

General Description

CY25562 is a spread spectrum clock generator (SSCG) IC used

to reduce electromagnetic interference (EMI) found in today’s

high speed digital electronic systems.

CY25562 is intended for applications with a reference frequency

in the range of 50 to 200 MHz.

A wide range of digitally selectable spread percentages is made

possible by using tri-level (high, low, and middle) logic at the S0

and S1 digital control inputs.

CY25562 uses a Cypress proprietary Phase Locked Loop (PLL)

and Spread Spectrum Clock (SSC) technology to synthesize and

frequency modulate the input frequency of the reference clock.

By doing this, the measured EMI at the fundamental and

harmonic frequencies of clock (SSCLK) is greatly reduced.

The output spread (frequency modulation) is symmetrically

centered on the input frequency.

Spread spectrum clock control (SSCC) function enables or

disables the frequency spread and is provided for easy

comparison of system performance during EMI testing.

This reduction in radiated energy can significantly reduce the

cost of complying with regulatory requirements and time to

market without degrading system performance.

CY25562 is available in an eight-pin SOIC package with a 0 to

70°C operating temperature range.

CY25562 is a very simple and versatile device to use. The

frequency and spread percentage range is selected by

programming S0 and S1 digital inputs. These inputs use three

logic states including high (H), low (L), and middle (M) logic

levels to select one of the nine available spread percentage

ranges. Refer to Table 1 for programming details.

Refer to CY25561 for applications with lower drive requirements,

and CY25560 with lower drive and frequency requirements.

Document Number: 38-07392 Rev. *C

Page 2 of 8

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CY25562

Table 1. Frequency and Spread Percentage Selection (Center Spread)

5 0 – 1 0 0 M H z (L o w R a n g e )

In p u t

F re q u e n c y

(M H z )

5 0 - 6 0

6 0 - 7 0

S 1 = M

S 0 = M

(% )

4 .3

S 1 = M

S 0 = 0

(% )

3 .9

S 1 = 1

S 0 = 0

(% )

3 .3

S 1 = 0

S 0 = 0

(% )

2 .9

S 1 = 0

S 0 = M

(% )

2 .7

S e le c t th e

F re q u e n c y a n d

C e n te r S p re a d

d e s ire d a n d th e n

s e t S 1 , S 0 a s

in d ic a te d .

%

4 .0

3 .6

3 .1

2 .6

2 .5

7 0 - 8 0

3 .8

3 .4

2 .9

2 .5

2 .4

8 0 - 1 0 0

3 .5

3 .1

2 .7

2 .2

2 .1

1 0 0 – 2 0 0 M H z (H ig h R a n g e )

In p u t

F re q u e n c y

(M H z )

S 1 = 1

S 0 = M

(% )

3 .0

2 .7

2 .6

2 .5

2 .4

S 1 = 0

S 0 = 1

(% )

2 .4

2 .1

2 .0

1 .8

S 1 = 1

S 0 = 1

(% )

1 .6

1 .4

1 .3

1 .2

S 1 = M

S 0 = 1

(% )

1 .3

1 .1

1 .0

S e le c t th e

F re q u e n c y a n d

C e n te r S p re a d

d e s ire d a n d th e n

s e t S 1 , S 0 a s

in d ic a te d .

%

1 0 0 – 1 2 0

1 2 0 -1 3 0

1 3 0 - 1 4 0

1 4 0 - 1 5 0

1 5 0 - 1 6 0

1 6 0 - 1 7 0

1 7 0 - 1 8 0

1 8 0 - 1 9 0

1 9 0 - 2 0 0

2 .3

1 .7

1 .6

1 .1

0 .9

Tri-level Logic

With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using

two control lines. Tri-level logic in CY25562 is implemented by defining a third logic state in addition to the standard logic “1” and “0.”

Pins six and seven of CY25562 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0”

(low), “M” (middle), and “1” (one). Each of these states have a defined voltage range that is interpreted by CY25562 as “0”, “M,” or “1”

logic state. Refer to Table 2 for voltage ranges for each logic state. CY25562 has two equal value resistors connected internally to pin

6 and pin 7, which produce the default “M” state. Pins six and/or seven can be tied directly to ground or V_DDto program a logic “0” or

“1” state, respectively. See the following examples:

Figure 2. Tri-level Logic Example

VDD

CY25562

S0 = "1"

CY25562

S0

S1

S0 = "M" (N/C)

7

6

7

6

5

S0 = "1"

S1 = "0" (GND)

SSCC = "1"

S1

S1 = "0" (GND)

SSCC = "1"

S1 = "1"

6

5

VDD

5

SSCC = "1"

harmonics, that is; third, fifth, seventh, etc. The amount of energy

contained in the fundamental and odd harmonics can be reduced

by increasing the bandwidth of the fundamental clock frequency.

Conventional digital clocks have a very high Q factor; all the

energy at that frequency is concentrated in a very narrow

bandwidth, and consequently, higher energy peaks. Regulatory

agencies test electronic equipment by the amount of peak

energy radiated from the equipment. By reducing the peak

energy at the fundamental and harmonic frequencies, the

equipment under test satisfies agency requirements for EMI.

Conventional methods of reducing EMI use shielding, filtering,

multi-layer PCBs, etc. CY25562 reduces the peak energy in the

clock by increasing the clock bandwidth, thus lowering the Q.

SSCG Theory of Operation

CY25562 is a PLL-type clock generator using a proprietary

Cypress design to modulate the reference clock. By precisely

controlling the bandwidth of the output clock, CY25562 becomes

a low-EMI clock generator. The theory and detailed operation of

CY25562 is discussed in the following sections.

EMI

All digital clocks generate unwanted energy in their harmonics.

Conventional digital clocks are square waves with a duty cycle

that is very close to 50 percent. Because of this 50/50 duty cycle,

digital clocks generate most of their harmonic energy in the odd

Document Number: 38-07392 Rev. *C

Page 3 of 8

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CY25562

important factor in the amount of EMI reduction realized from an

SSCG clock.

SSCG

SSCG uses a patented technology of modulating the clock over

a very narrow bandwidth and controlled rate of change, both

peak and cycle-to-cycle. CY25562 takes a narrow band digital

reference clock in the range of 50 to 200 MHz and produces a

clock that sweeps between a controlled start (F1) and stop (F2)

frequency at a precise rate of change. To understand what

happens to a clock when SSCG is applied, consider a 200 MHz

clock with a 50 percent duty cycle, as shown in this figure.

The modulation domain analyzer is used to visualize the sweep

waveform and sweep period. Figure 3 shows the modulation

profile of a 200 MHz SSCG clock. Notice that the actual sweep

waveform is not a simple sine or sawtooth waveform. Figure 3

also shows a scan of the same SSCG clock using a spectrum

analyzer. The spectrum analyzer scan shows a 10 dB reduction

in the peak RF energy when using CY25562 SSCG clock.

Modulation Rate

50 %

Tc = 5.0 ns

Clock frequency = fc = 200 MHz

50 %

Spread spectrum clock generators use frequency modulation

(FM) to distribute energy over a specific band of frequencies. The

maximum frequency of the clock (Fmax) and minimum

frequency of the clock (Fmin) determine this band of frequencies.

The time required to transition from Fmin to Fmax and back to

Fmin is the period of the modulation rate, Tmod. Modulation

rates of SSCG clocks are generally referred to in terms of

frequency or Fmod = 1/Tmod.

Clock period = Tc = 1/200 MHz

If this clock is applied to the Xin/CLK pin of CY25562, the output

clock at pin 4 (SSCLK) sweeps back and forth between two

frequencies. These two frequencies, F1 and F2, calculate total

amount of spread or bandwidth applied to the reference clock at

pin 1. As the clock is making the transition, sweep, from F1 to

F2, the amount of time and sweep waveform become a very

The input clock frequency, Fin, and the internal divider count,

Cdiv, determine the modulation rate. In some SSCG clock gener-

ators, the selected range determines the internal divider count.

In other SSCG clocks, the internal divider count is fixed over the

operating range of the part. CY25562 has a fixed divider count

of 2332.

Figure 3. SSCG Clock, Part Number, Fin = 200 MHz

Device

Cdiv

CY25562

2332 (All Ranges)

Example:

Device =

Fin

Range =

CY25562

200 MHz

S1 = 1, S0 = 1

=

Then;

Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.

Modulation Profile

Spectrum Analyzer

Document Number: 38-07392 Rev. *C

Page 4 of 8

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CY25562

Part Number Application Schematic

Figure 4. Application Schematic

VDD

C3

0.1 uF

2

VDD

1

XIN/CLK

XOUT

4

200 MHz Reference Clock

SSCLK

8

CY25562

6

7

VDD

S1

S0

5

VDD

SSCC

VSS

3

The schematic in Figure 4 demonstrates how CY25562 is configured in a typical application. This application is using a 200 MHz

reference clock connected to pin 1. Because an external reference clock is used, pin 8 (Xout) is left unconnected.

This configuration depicts the profile and spectrum scans shown in Figure 3. Note that S0=S1=1, for a spread of approximately 1.1

percent.

Document Number: 38-07392 Rev. *C

Page 5 of 8

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CY25562

Absolute Maximum Ratings^{[1, 2]}

Supply voltage (V ) ......................................–0.5V to +6.0V

Operating temperature ....................................... 0°C to 70°C

Storage temperature................................... –65°C to +150°C

Static discharge voltage (ESD)............................ 2,000V Min

DD

DC input voltage....................................–0.5V to V + 0.5V

DD

Junction temperature.................................. –40°C to +140°C

Table 2. Electrical Characteristics V = 3.3V, T = 25°C, and C (Pin 4) = 15 pF unless otherwise noted

DD

A

L

Parameter

Description

Power supply range

Input high voltage

Input middle voltage

Input low voltage

Conditions

Min

Typ

Max

Unit

V

±10%

2.97

3.3

3.63

DD

S0 and S1 only

0.85V

0.40V

0.0

V

DD

V

INH

INM

INL

DD

0.50V

0.0

0.60V

0.15V

V

DD

V

Output high voltage

Output low voltage

Input capacitance

Power supply current

I

= 6 mA

= 20 mA

= 6 mA

= 20 mA

2.4

V

OH1

OH2

OL1

OL2

OH

2.0

V

0.4

1.2

5

V

C

Xin/CLK (pin 1)

3

6

3

4

8

pF

mA

in1

Xout (pin 8)

10

5

in2

S0, S1, SSCC (pins 7, 6, 5)

Fin = 65 MHz, CL = 15 pF

Fin = 200 MHz, CL =15 pF

Fin = 200 MHz, no load

4

in2

I

23

53

48

30

66

60

DD1

DD2

DD3

Table 3. Electrical Timing Characteristics V = 3.3V, T = 25°C, and C = 15 pF unless otherwise noted. Rise/Fall at 0.4 to 2.4V,

DD

A

L

Duty at 1.5V

Parameter

Description

Input clock frequency range

Clock rise time (pin 4)

Clock fall time (pin 4)

Clock rise time (pin 4)

Clock fall time (pin 4)

Input clock duty cycle

Output clock duty cycle

Frequency modulation

Cycle-to-Cycle jitter

Conditions

Pk–Pk = 3.3 volts

Min

50

Typ

Max

200

1.0

1.8

1.9

70

Unit

MHz

ns

I

t

CLKFR

RISE

FALL

RISE

FALL

SSCLK, CL = 15 pF, 200 MHz

SSCLK, CL = 33 pF, 200 MHz

XIN/CLK (pin 1)

0.8

1.1

30

0.9

ns

1.45

1.5

ns

D

50

%

TYin

SSCLK1 (pin 4)

45

50

55

%

TYout

FM1

FM2

Fin = 70 MHz

29.5

85.0

30.0

85.4

150

175

250

30.5

86

kHz

ps

Fin = 200 MHz

C

Fin = 50 MHz, mod ON

Fin = 120 MHz, mod ON

Fin = 200 MHz, mod ON

175

200

300

CJ1

CJ2

CJ3

Cycle-to-Cycle jitter

ps

Cycle-to-Cycle jitter

ps

Ordering Information

Part Number

CY25562SXC

Package Type

Product Flow

8-pin SOIC, Pb-free

Commercial, 0° to 70°C

CY25562SXCT

8-pin SOIC – tape and reel, Pb-free

Notes

1. Operation at any absolute maximum rating is not implied.

2. Single power supply: The voltage on any input or I/O pin cannot exceed the power pine during power-up.

Document Number: 38-07392 Rev. *C

Page 6 of 8

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CY25562

Package Drawing and Dimensions

Figure 5. 8 Lead (150 Mil) SOIC-SO8

51-85066 *C

Document Number: 38-07392 Rev. *C

Page 7 of 8

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CY25562

Document History Page

Document Title: CY25562 Spread Spectrum Clock Generator

Document Number: 38-07392

Submission Orig. of

Rev.

ECN No.

Description of Change

Date

Change

**

115526

119444

122703

2567245

07/08/02

10/17/02

12/28/02

09/16/08

OXC

New Data Sheet

*A

*B

*C

RGL

Corrected the values in the Absolute Maximum Ratings to match the device.

Added power up requirements to maximum ratings information.

RBI

PYG/KVM/ Replaced CY25562SC w/ CY25562SXC, CY255652SCT w/ CY25562SXCT.

AESA

Package changed from S8 to SZ8.

Updated template.

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 38-07392 Rev. *C

Revised September 15, 2008

Page 8 of 8

All products and company names mentioned in this document may be the trademarks of their respective holders.

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型号：	CY25562_08
厂家：	CYPRESS
描述：	Spread Spectrum Clock Generator 扩频时钟发生器时钟发生器
文件：	总8页 (文件大小：599K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY25562_08 [CYPRESS]

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