CY25402FSXC [CYPRESS]
Two PLL Programmable Clock Generator with Spread Spectrum; 两个PLL可编程时钟发生器，带有扩频
| 型号： | CY25402FSXC |
| 厂家： | 
CYPRESS |
| 描述： | Two PLL Programmable Clock Generator with Spread Spectrum |
| 文件： | 总8页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY25402
CY25422
PRELIMINARY
Two PLL Programmable Clock Generator
with Spread Spectrum
Benefits
Features
• Two fully integrated phase-locked loops (PLLs)
• Input Frequency range:
• Multiple high-performance PLLs allow synthesis of
unrelated frequencies
• Nonvolatile programming for customized PLL frequencies,
spreadspectrumcharacteristics, drivestrength,crystalload
capacitance, and output frequencies
— External crystal: 8 to 48 MHz
— External reference: 8 to 166 MHz clock
• Wide operating output frequency range
— 3 to 166 MHz
• Two Spread Spectrum capable PLLs with Lexmark profile
for maximum for EMI reduction
• Spread Spectrum PLLs can be disabled or enabled
separately
• Programmable Spread Spectrum modulation frequency
range of 30 to 120 kHz with Lexmark profile
• PLLs can be programmed for system frequency margin
tests
• Center Spread: ±0.125% to ±2.5%
• Down Spread: –0.25% to –5%
• Meets critical timing requirements in complex system
designs
• Frequency select feature with option to select four different
frequencies
• Suitable for PC, consumer, and networking applications
• Ability to synthesize standard frequencies with ease
• Low-jitter, high-accuracy outputs
• Up to three clock outputs
• Application compatibility in standard and low-power
systems
• Programmable output drive strength
• Glitch-free outputs while frequency switching
• Four independent output voltages: 3.3V, 3.0V, 2.5V, and
1.8V
• 8-pin SOIC package
• Commercial and Industrial temperature range
Block Diagram
XIN
OSC
XOUT
Output
CLK1
Dividers
and
Drive
Strength
Control
PLL1
MUX
and
Control
Logic
CLK2
CLK3
(SS)
FS0
FS1
PLL2
(SS)
SSON
PD#/OE
Cypress Semiconductor Corporation
Document #: 001-12565 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 02, 2007
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CY25402
CY25422
PRELIMINARY
Pin Configuration
XIN
XOUT
8
1
VDD
CLK1
GND
7
6
5
2
3
4
8 LDSOIC
CLK3/SSON
PD#/OE/FS1
CLK2/FS0
Pin Description - Memory Programmable 2-PLL device with 2 Spread Spectrum PLLs
Pin Number
Name
I/O
Description
1
2
3
4
5
6
7
8
XIN
Input
Crystal or Clock Input
Power Supply
VDD
Power
Output
CLK1
CLK2/FS0
Programmable Clock Output
Programmable Clock Output or FS0
Power Down, Output Enable or FS1
Programmable Clock Output or SSON
Power Supply Ground
Output/input
Input
PD#/OE/FS1
CLK3/SSON
GND
Output/Input
Power
XOUT
Output
Crystal Output
for center spread is from ±0.125% to ±2.50%. The range for
down spread is from –0.25% to –5.0%. Contact the factory for
smaller or larger spread percentage amounts, if required.
General Description
The CY25402 and CY25422 are two PLL programmable
Spread Spectrum Clock Generators used to reduce EMI found
in high-speed digital electronic systems. Both PLLs have
Spread Spectrum capability. The spread spectrum feature are
turned on or off using the control pin SSON.
The input to the CY25402 and CY25422 is either a crystal or
a clock signal. The input frequency range for crystals is 8 MHz
to 48 MHz, and for clock signals is 8 MHz to 166 MHz.
The CY25402 and CY25422 have up to three clock outputs
and each output has three possible input sources.There are
two frequency select lines FS(1:0) that provide an option to
select four different sets of frequencies among the two PLLs.
Each output has programmable output divider options. Output
1 has eight possible divider values and outputs 2–3 have four
possible divider values for maximum flexibility. The 2 bit or 3
bit output dividers are programmable providing a wide output
frequency range.
The advantage of having two PLLs is that a single device can
generate up to two independent frequencies from a single
crystal or reference input frequency. Generally, a design
requires up to two oscillators to achieve the same result with
a single CY25402 or CY25422.
The device uses Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy significantly reduces the cost of complying with
regulatory agency (EMC) requirements and improves
time-to-market without degrading the system performance.
The outputs are glitch-free when frequency is switched using
output dividers. The outputs have a predictable phase
relationship if the clock source is the same PLL and divider
values are 2, 3, 4, or 6.
The CY25402 and CY25422 are available in an 8-pin SOIC
package with commercial and industrial operating temperature
ranges.
The CY25402 and CY25422 use a factory/field-programmable
configuration memory array to provide customization for
output frequencies, frequency select options, spread charac-
teristics like spread percentage and modulation frequency,
output drive strength and crystal load capacitance. A
customized device are configured using CyberclocksTM
software or by contacting the factory.
Table 1. Supply Voltage Options
Device
VDD Supply Voltage
CY25402
CY25422
2.5V, 3.0V or 3.3V
1.8V
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range
Document #: 001-12565 Rev. *A
Page 2 of 8
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CY25402
CY25422
PRELIMINARY
Absolute Maximum Conditions
Parameter
Description
Supply Voltage
Condition
Min.
–0.5
–0.5
–65
Max.
Unit
V
4.5
V
DD
IN
S
V
Input Voltage
Relative to V
V
+ 0.5 VDC
DD
SS
T
Temperature, Storage
Non Functional
+150
°C
ESD
ESD Protection (Human
Body Model)
MIL-STD-883, Method 3015
2000
Volts
–
HBM
UL-94
MSL
Flammability Rating
@1/8 in.
V-0
Moisture Sensitivity Level SOIC package
1
Recommended Operating Conditions
Parameter
Description
Min. Typ. Max. Unit
V
V
V
V
Operating Voltage, 3.3V
3.0
2.7
2.25
1.65
0
–
–
–
–
–
–
–
–
3.6
3.3
V
V
V
V
DD1
DD2
DD3
DD4
Operating Voltage, 3.0V
Operating Voltage, 2.5V
2.75
1.95
Operating Voltage, 1.8V
T
Commercial Ambient Temperature
Industrial Ambient Temperature
Max. Load Capacitance
+70 °C
+85 °C
AC
T
–40
–
AI
C
15
pF
LOAD
t
Power-up time for all V pins to reach minimum specified voltage (power ramps must 0.05
500 ms
PU
DD
be monotonic)
DC Electrical Specifications
Parameter
Description
Conditions
All VDD levels, IOL = 8 mA
All VDD levels, IOH = –8 mA
All VDD levels
Min.
0
Typ.
–
Max.
Unit
V
V
V
V
V
V
V
Output Low Voltage, All CLK pins
Output High Voltage, All CLK pins
All Inputs except XIN
0.4
OL
OH
IL
VDD – 0.4
–0.3
–
VDD
V
–
0.2 * VDD
VDD + 0.3
0.36
V
All Inputs except XIN
All VDD levels
0.8 * VDD
–0.3
–
V
IH
Input Low Voltage, clock input to XIN pin
Input High Voltage, clock input to XIN pin
All VDD levels
–
V
ILX
IHX
All VDD levels
1.44
–
2.0
V
IILPDOE
IIHPDOE
IILSR
Input Low Current, PD#/OE and FS0,1 pins VIN = VSS
(Internal pull up = 100k typical)
–
–
10
μA
Input High Current, PD#/OE and FS0,1 pins VIN = VDD
(Internal pull up = 100k typical)
–
–
–
–
–
–
1
1
μA
μA
μA
Input Low Current, SSON pin
VIN = VSS
(Internal pull down = 100k typical)
IIHSR
Input High Current, SSON pin
VIN = VDD
(Internal pull down = 100k typical)
10
[1]
I
Supply Current
All clocks running, CL = 0
–
–
–
–
12
7
mA
pF
DD
C
Input Capacitance - All inputs except XIN
SSON, OE, PD# or FS inputs
IN
Note
1. Configuration dependent.
Document #: 001-12565 Rev. *A
Page 3 of 8
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CY25402
CY25422
PRELIMINARY
AC Electrical Specifications
Parameter
Description
Conditions
Min. Typ. Max. Unit
F
F
F
(crystal) Crystal Frequency
8
8
–
–
48 MHz
166 MHz
166 MHz
IN
IN
(clock)
Input Clock Frequency (XIN)
Output Clock Frequency
Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2; t /t ,
3
–
OUT
DC
45
50
55
%
1
2
50% of V
DD
DC
Ref Out Duty Cycle
CLK1-3 Rising Edge Rate
CLK1-3 Falling Edge Rate
Cycle-to-cycle Jitter
Long Term Jitter
Ref In Min 45%, Max 55%
VDD = All, 20% to 80% VDD
VDD = All, 20% to 80% VDD
40
0.8
0.8
–
60
–
%
V/ns
V/ns
ps
ER
–
–
-
EF
–
TCCJ1
TLTJ
T10
Configuration dependent. See Table 2
Configuration dependent. See Table 2
–
–
-
–
ns
PLL Lock Time
–
–
3
ms
Table 2. Configuration Example for Jitter
Max Jitter (ps) on
Output 1(48MHz)
Max Jitter (ps) on Output 2
(27 MHz)
Max Jitter (ps) on
Output 3 (166 MHz)
Reference
Description
TCCJ1
27MHz
27MHz
48 MHz
48 MHz
155
770
135
535
255
580
225
575
170
630
100
520
TLTJ
TCCJ1
TLTJ
Recommended Crystal Specification for SMD Package
Parameter
Fmin
Description
Range 1 Range 2 Range 3 Unit
Minimum Frequency
Maximum Frequency
8
14
135
4
14
28
50
4
28
48
30
2
MHz
MHz
Ω
Fmax
R1(max)
C0(max)
CL(max)
DL(max)
Maximum Motional Resistance (ESR)
Maximum Shunt Capacitance
pF
Maximum Parallel Load Capacitance
Maximum Crystal Drive Level
18
300
14
300
12
300
pF
μW
Recommended Crystal Specification for Thru-Hole Package
Parameter
Fmin
Description
Range 1 Range 2 Range 3 Unit
Minimum Frequency
Maximum Frequency
8
14
14
24
24
32
MHz
MHz
Ω
Fmax
R1(max)
C0(max)
CL(max)
DL(max)
Maximum Motional Resistance (ESR)
Maximum Shunt Capacitance
90
50
30
7
7
7
pF
Maximum Parallel Load Capacitance
Maximum Crystal Drive Level
18
12
12
pF
1000
1000
1000
μW
Document #: 001-12565 Rev. *A
Page 4 of 8
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CY25402
CY25422
PRELIMINARY
Test and Measurement Setup
Figure 1. Test and Measurement Setup
VDDs
Outputs
CLOAD
0.1 μF
DUT
GND
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
t1
t2
VDD
50% of VDD
0V
Clock
Output
Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
t4
t3
VDD
80% of VDD
20% of VDD
0V
Clock
Output
Document #: 001-12565 Rev. *A
Page 5 of 8
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CY25402
CY25422
PRELIMINARY
Ordering Information
Part Number[2]
Type
VDD(V)
Temperature Range
Lead-free
CY25402SXC-xxx
CY25402SXC-xxxT
CY25402FSXC
CY25402FSXC
CY25422SXC-xxx
CY25422SXC-xxxT
CY25422FSXC
CY25422FSXCT
CY25402SXI-xxx
CY25402SXI-xxxT
CY25402FSXI
8-pin SOIC
3.3, 3.0 or 2.5
3.3, 3.0 or 2.5
3.3, 3.0 or 2.5
3.3, 3.0 or 2.5
1.8
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Commercial, 0°C to 70°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
Industrial, -40°C to +85°C
8-pin SOIC-Tape & Reel
8-pin SOIC
8-pin SOIC-Tape & Reel
8-pin SOIC
8-pin SOIC-Tape & Reel
8-pin SOIC
1.8
1.8
8-pin SOIC-Tape & Reel
8-pin SOIC
1.8
3.3, 3.0 or 2.5
3.3, 3.0 or 2.5
3.3, 3.0 or 2.5
3.3, 3.0 or 2.5
1.8
8-pin SOIC-Tape & Reel
8-pin SOIC
CY25402FSXIT
CY25422SXI-xxx
CY25422SXI-xxxT
CY25422FSXI
8-pin SOIC-Tape & Reel
8-pin SOIC
8-pin SOIC-Tape & Reel
8-pin SOIC
1.8
1.8
CY25422FSXIT
8-pin SOIC-Tape & Reel
1.8
Note
2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
F in the part number indicates field programmable using CyberClocks Online software.
Document #: 001-12565 Rev. *A
Page 6 of 8
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CY25402
CY25422
PRELIMINARY
Package Drawing and Dimensions
Figure 4. 8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
0.150[3.810]
0.157[3.987]
RECTANGULAR ON MATRIX LEADFRAME
3. REFERENCE JEDEC MS-012
4. PACKAGE WEIGHT 0.07gms
0.230[5.842]
0.244[6.197]
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
5
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
X 45°
SEATING PLANE
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.0075[0.190]
0.0098[0.249]
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
51-85066-*C
0.0138[0.350]
0.0192[0.487]
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-12565 Rev. *A
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY25402
CY25422
PRELIMINARY
Document History Page
Document Title: CY25402/CY25422 Two PLL Programmable Clock Generator
with Spread Spectrum
Document Number: 001-12565
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
690296
815788
See ECN
See ECN
RGL
RGL
New Data Sheet
Minor Change: To post on web
*A
Document #: 001-12565 Rev. *A
Page 8 of 8
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