CY25200KFZXIT [CYPRESS]
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| 型号： | CY25200KFZXIT |
| 厂家： | 
CYPRESS |
| 描述： | 暂无描述 时钟发生器 PC |
| 文件： | 总8页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22800
Universal Programmable Clock Generator
(UPCG)
Features
Benefits
• Spread Spectrum, VCXO, and Frequency Select
• Input frequency range:
• Make inventory of only one device, CY22800, to use in
various applications such as HDTV, STB, DVDR, etc.
• Multiple predefined configurations that can be programmed
into a single chip
— Crystal: 8–30 MHz
— CLKIN: 0.5–100 MHz
• Eliminates the need for expensive and difficult to use
higher-order crystal
• Output frequency:
— LVCMOS: 1–200 MHz
• Integrated phase-locked loop
• Low jitter, high accuracy outputs
• 3.3V operation
• High-performance PLL tailored for multiple applications
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
• Allows up to three different frequency selects
• 8-pin SOIC package
Logic Block Diagram
Pin Configuration
CY22800
8-pin SOIC
CLKC
XIN/CLKIN
OSC
Q
Φ
XOUT
1
2
3
4
XIN/CLKIN
8
7
6
5
OUTPUT
DIVIDER
XOUT
VCXO
VCO
CLKB
CLKA
CLKC/FS2/VSS
CLKA/FS0
VDD
FS0/VCXO
VSS
P
FS2
FS1
FS0
CLKB/FS1
PLL
(with modulation control)
VSS
VDD
Pin Description
Name
Pin Number Description
XIN
1
2
3
4
5
6
7
8
Reference Input; Crystal or External Clock
3.3V Voltage Supply
Frequency Select 0/VCXO Analog Control Voltage[1]
VDD
FS0/VCXO
VSS
Ground
CLKB/FS1
CLKA/FS0
CLKC/FS2/VSS
XOUT
Clock Output B/Frequency Select 1[1]
Clock Output A/Frequency Select 0[1]
Clock Output C/Frequency Select 2/VSS[1]
Reference Output (No Connect when the reference is a clock)
Note
1. Pin definition changes for different configurations. Refer to the specific one-page data sheet for more details.
Cypress Semiconductor Corporation
Document #: 001-07704 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 14, 2006
CY22800
General Description
VCXO
The CY22800 is a multi-function clock generator that supports
various applications in consumer and communications
markets. The device uses the Cypress proprietary PLL along
with Spread Spectrum and VCXO technology to make it one of
the most versatile clock synthesizer in the market place. The
CY22800 is a field-programmable synthesizer that can be
programmed using an easy-to-use programmer dongle,
CY36800, with one of many predefined configuration files for
fast sample generation of prototype builds. The CY22800 is a
reprogrammable device that can be programmed up to five
thousand times. The latest configurations available for this
device are summarized in Table 1.
One of the key components of the CY22800 device is the
VCXO. The VCXO is used to “pull” the reference crystal higher
or lower in order to lock the system frequency to an external
source. This is ideal for applications where the output
frequency needs to track along with an external reference
frequency that is constantly shifting.
A special pullable crystal must be used in order to have
adequate VCXO pull range. Pullable Crystal specifications are
included in this data sheet.
VCXO Profile
Figure 1 shows an example of what a VCXO profile looks like.
The analog voltage input is on the X-axis and the PPM range
is on the Y-axis. An increase in the VCXO input voltage results
in a corresponding increase in the output frequency. This has
the effect of moving the PPM from a negative to positive offset.
Spread Spectrum Clock Generation (SSCG)
The CY22800 is capable of generating Spread Spectrum
Clocks (SSCG) for the purpose of reducing EMI found in
today’s high-speed digital electronic systems.
Figure 1. VCXO Profile
The device uses proprietary Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the
input clock. By modulating the frequency of the clock, the
measured EMI at the fundamental and harmonic frequencies
is greatly reduced. This reduction in radiated energy can
significantly reduce the cost of complying with regulatory
agency (EMC) requirements and improve time-to-market
without degrading system performance.
200
150
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
-50
-100
-150
-200
The CY22800 uses a preprogrammed configuration of
memory arrays to synthesize output frequency and offers eight
different spread percentages (refer to Table 1 – Code numbers
-015 to -022), and an additional option to turn the spread on
and off.
VCXOinput [V]
For the above-mentioned configurations, the modulation
frequency varies with the reference frequency as follows:
f
ref
f
mod
=
1000
Document #: 001-07704 Rev. **
Page 2 of 8
CY22800
Table 1. CY22800 Configurations
Document #: 001-07704 Rev. **
Page 3 of 8
CY22800
Cypress offers a wide range of programmable clock synthesizers that can be used to generate any other frequencies not covered
by the CY22800. Table 2 summarizes all Cypress programmable devices including CY22800.
Table 2. Cypress Programmable Clocks[2]
Output
Freq.
No. of
Spread
Part #
CY22800
No. of PLL Input Freq.
Package
VCXO
I2C
Outputs Spectrum
1
1
1
1
1
1
3
3
3
3
4
0.5–100
1–133
1–133
8–166
3–166
27/13.5
1–166
1–166
1–166
1–166
1–100
1–200
0.08–200
0.08–200
3–200
8-SOIC
up to 3
up to 6
up to 6
Yes
No
No
Yes
Yes
No
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
No
No
Yes
No
No
No
No
No
Yes
No
No
CY22050
16-TSSOP
16-TSSOP
CY22150
CY25100
8-SOIC/TSSOP up to 2
CY25200
3–200
16-TSSOP
8-SOIC
up to 6
up to 2
up to 6
up to 3
up to 6
up to 5
up to 8
CY241V08
CY22392
27/13.5
1–200
16-TSSOP
8-SOIC
CY22381
1–200
CY22393
1–200
16-TSSOP
16-TSSOP
CY22394/5
CY22388/89/91
1–200
4.2–166
16/20-TSSOP,
32-QFN
Note
2. The CY3672 programmer can be used to program all Cypress chips. Refer to the CY3672 data sheet for programming procedures.
Document #: 001-07704 Rev. **
Page 4 of 8
CY22800
Absolute Maximum Conditions
Parameter
Description
Min.
–0.5
–65
–
Max.
4.6
Unit
V
VDD
TS
Supply Voltage
Storage Temperature
Junction Temperature
Digital Inputs
125
125
°C
°C
V
TJ
V
SS – 0.3 VDD + 0.3
Digital Outputs referred to VDD
Electro-Static Discharge
VSS – 0.3 VDD + 0.3
V
2
–
kV
Recommended Operating Conditions
Parameter
Description
Min.
Typ.
3.3
–
Max. Unit
VDD
TA
Operating Voltage
3.14
0
3.47
70
V
Ambient Temperature
°C
pF
CLOAD
Max. Load Capacitance on the CLK output
Reference Frequency
–
–
15
[3]
fREF
0.5
–
100 MHz
500 ms
tPU
Power-up time for all VDDs to reach minimum specified voltage (power ramps 0.05
must be monotonic)
–
Pullable Crystal Specifications for VCXO Application ONLY
Parameter
CLNOM
Name
Min.
Typ.
14
–
Max. Unit
Crystal Load Capacitance
–
–
3
–
25
–
pF
Ω
–
R1
Equivalent Series Resistance
R3/R1
Ratio of Third Overtone Mode ESR to Fundamental Mode ESR. Ratio used
because typical R1 values are much less than the maximum spec
–
DL
Crystal Drive Level. No external series resistor assumed
Third overtone separation from 3*FNOM (High Side)
Third overtone separation from 3*FNOM (Low Side)
Crystal shunt capacitance
–
300
–
0.5
–
2
–
mW
ppm
F3SEPHI
F3SEPLO
C0
–
–150 ppm
7
pF
pF
C0/C1
C1
Ratio of Shunt to motional capacitance
Crystal motional capacitance
180
–
250
21.6
14.4
18
Recommended Crystal Specifications for ALL other Applications
Parameter
FNOM
Name
Description
Min.
Typ.
Max. Unit
Nominal Crystal Frequency
Parallelresonance,fundamentalmode,and
AT cut
8
–
30
MHz
CLNOM
R1
Nominal Load Capacitance
–
–
12
35
–
pF
Equivalent Series Resistance
(ESR)
Fundamental mode
50
Ω
DL
Crystal Drive Level
No external series resistor assumed
–
0.5
2
mW
Note
3. Configuration dependent, see the one-page document.
Document #: 001-07704 Rev. **
Page 5 of 8
CY22800
DC Electrical Specifications
Parameter
IOH
Name
Output High Current
Output Low Current
Input Capacitance
Input Capacitance
Input High Current
Input Low Current
VCXO Pullability Range
VCXO Input Range
Input High Voltage
Input Low Voltage
Description
VOH = VDD – 0.5, VDD = 3.3V (source)
VOL = 0.5, VDD = 3.3V (sink)
All input pins except XIN and XOUT
XIN and XOUT pins
Min.
12
12
–
Typ. Max. Unit
24
24
–
–
–
mA
mA
pF
IOL
CIN1
CIN2
IIH
7
–
24
5
–
pF
VIH = VDD
–
10
50
µA
IIL
VIL = 0V
–
–
µA
f∆XO
VVCXO
VIH
±150
0
–
ppm
V
–
VDD
–
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
0.7
–
–
VDD
VDD
VIL
–
0.3
AC Electrical Characteristics (V = 3.3V)
DD
Parameter
DC
Name
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
PLL Lock Time
Description
Min.
45
Typ. Max. Unit
Duty Cycle is defined in Figure 3, 50% of VDD
Output Clock Rise Time, 20% - 80% of VDD
Output Clock Fall Time, 80% - 20% of VDD
50
1.4
1.4
–
55
–
%
t3
0.8
0.8
–
V/ns
V/ns
ms
t4
–
t10
3
Test Circuit
Figure 2. Test Circuit Diagram
Figure 4. Rise and Fall Time Definitions
t3 t4
VDD
CLKout
CLOAD
0.1µF
80%
OUTPUTS
CLK
20%
GND
Figure 3. Duty Cycle Definition; DC = t2/t1
t1
t2
50%
CLK
50%
Document #: 001-07704 Rev. **
Page 6 of 8
CY22800
Ordering Information
Ordering Code
Package Type
8-Pin SOIC
Operating Range
Operating Voltage
CY22800FXC
Commercial
3.3V
Package Diagram
Figure 5. 8-Lead (150-Mil) SOIC S8
51-85066-*C
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-07704 Rev. **
Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY22800
Document History Page
Document Title: CY22800 Universal Programmable Clock Generator
(UPCG)
Document Number: 001-07704
Orig. of
REV.
ECN NO. Issue Date
478688
Description of Change
Change
**
See ECN KKVTMP New data sheet
Document #: 001-07704 Rev. **
Page 8 of 8
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