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CY24206ZC-1T [CYPRESS]

MediaClock - TM DTV, STB Clock Generator; MediaClock - TM DTV ， STB时钟发生器
CY24206ZC-1T
型号： CY24206ZC-1T
厂家： CYPRESS    CYPRESS
描述：

MediaClock - TM DTV, STB Clock Generator
MediaClock - TM DTV ， STB时钟发生器

时钟发生器 电视
文件： 总6页 (文件大小：132K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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CY24206  
MediaClock™ DTV, STB Clock Generator  
Features  
Benefits  
• Integrated phase-locked loop (PLL)  
• Low-jitter, high-accuracy outputs  
• 3.3V operation  
• Internal PLL with up to 400-MHz internal operation  
• Meets critical timing requirements in complex system  
designs  
• Enables application compatibility  
Output Frequency Range  
• Available in 16-pin TSSOP Package  
Part Number Outputs Input Frequency  
CY24206-1  
3
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
CY24206-2  
4
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
CY24206-3  
CY24206-4  
4
4
27 MHz  
27 MHz  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
1 copy 27-MHz reference clock output  
1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable)  
1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable)  
1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable)  
Logic Block Diagram  
XIN  
Q
OSC.  
Φ
VCO  
OUTPUT  
XOUT  
MULTIPLEXER  
CLK1  
CLK2  
AND  
P
DIVIDERS  
PLL  
REFCLK  
FS0  
CLK3 (-2, -3,-4)  
FS1  
FS2  
OE  
VSS  
AVDD AVSS  
VDDL  
VDD  
VSSL  
Pin Configurations  
CY24206-2,3,4  
16-pin TSSOP  
CY24206-1  
16-pin TSSOP  
XOUT  
XOUT  
1
1
16  
16  
XIN  
VDD  
AVDD  
OE  
AVSS  
VSSL  
XIN  
15  
14  
13  
12  
15  
14  
13  
12  
2
3
4
5
6
7
8
2
3
4
5
6
FS2  
FS1  
VSS  
VDD  
AVDD  
OE  
AVSS  
VSSL  
FS2  
FS1  
VSS  
CLK3  
VDDL  
N/C  
VDDL  
11  
10  
11  
10  
7
8
FS0  
REFCLK  
FS0  
REFCLK  
CLK1  
CLK2  
CLK1  
CLK2  
9
9
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07451 Rev. *B  
Revised September 27, 2004  
CY24206  
Frequency Select Options  
FS2  
0
0
0
0
1
1
1
FS1  
0
0
1
1
0
0
1
FS0  
0
1
0
1
0
1
0
CLK1 (-1,-2)  
CLK1 (-3,-4)  
81  
81.081  
74.17582  
74.25  
CLK2  
27 (CLK1/3)  
27.027 (CLK1/3) 27.027 (CLK1/3)  
24.725 (CLK1/3) 74.17582 (CLK1)  
24.75 (CLK1/3)  
CLK3 (-2, -3,-4)  
27 (CLK1/3)  
REFCLK  
Units  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
81  
27  
27  
27  
27  
27  
27  
27  
27  
81.081  
74.175  
74.250  
81  
81.081  
74.175  
74.250  
74.25 (CLK1)  
27 (CLK1/3)  
27.027 (CLK1/3)  
74.175 (CLK1)  
74.25 (CLK1)  
81  
27  
27  
27  
27  
81.081  
74.1758  
74.25  
1
1
1
Pin Description  
Name  
Pin Number  
Description  
XIN  
VDD  
1
2
Reference Crystal Input.  
Voltage Supply.  
AVDD  
3
Analog Voltage Supply.  
OE  
AVSS  
4
5
Output Enable, weak internal pull-up. 0 = outputs off, 1 = outputs on.  
Analog Ground.  
VSSL  
6
VDDL Ground.  
CLK1 (-1,-2)  
CLK1 (-3,-4)  
CLK2  
REFCLK  
FS0  
7
7
8
9
10  
11  
12  
12  
13  
14  
15  
16  
81-/81.081-/74.175-/74.250-MHz Clock Output (frequency selectable).  
81-/81.081-/74.17582-/74.25-MHz Clock Output (frequency selectable).  
27-/27.027-/24.725-/24.75-MHz Clock Output (frequency selectable).  
Reference Clock Output.  
Frequency Select 0, weak internal pull-up.  
Voltage Supply.  
VDDL  
N/C (-1)  
CLK3 (-2,-3,-4)  
VSS  
FS1  
FS2  
No Connect.  
27-/27.027-/74.175-/74.25-MHz Clock Output (frequency selectable).  
Ground.  
Frequency Select 1, weak internal pull-up.  
Frequency Select 2, weak internal pull-up.  
Reference Crystal Output.  
XOUT  
Document #: 38-07451 Rev. *B  
Page 2 of 6  
CY24206  
Absolute Maximum Conditions  
Parameter  
Description  
Supply Voltage  
Min.  
–0.5  
Max.  
7.0  
Unit  
V
VDD  
VDDL  
TJ  
I/O Supply Voltage  
Junction Temperature  
Digital Inputs  
7.0  
125  
AVDD + 0.3  
V
°C  
V
AVSS – 0.3  
2
Electrostatic Discharge  
kV  
Recommended Operating Conditions  
Parameter  
DD/AVDDL/VDDL Operating Voltage  
Description  
Min.  
3.135  
0
Typ.  
3.3  
Max.  
3.465  
70  
15  
Unit  
V
°C  
pF  
MHz  
V
TA  
Ambient Temperature  
Max. Load Capacitance  
Reference Frequency  
CLOAD  
fREF  
27  
DC Electrical Specifications  
Parameter[1]  
IOH  
IOL  
IIH  
IIL  
VIH  
VIL  
IVDD  
IVDDL  
RUP  
Name  
Output High Current  
Output Low Current  
Input High Current  
Input Low Current  
Input High Voltage  
Input Low Voltage  
Supply Current  
Description  
VOH = VDD – 0.5, VDD/VDDL = 3.3V  
VOL = 0.5, VDD/VDDL = 3.3V  
VIH = VDD  
Min.  
12  
12  
–
–
0.7  
Typ.  
24  
24  
5
Max.  
Unit  
mA  
mA  
µA  
10  
50  
VIL = 0V  
–
µA  
CMOS levels, 70% of VDD  
CMOS levels, 30% of VDD  
AVDD/VDD Current  
VDD  
VDD  
mA  
mA  
kΩ  
0.3  
25  
20  
Supply Current  
VDDL Current  
Pull-up resistor on Inputs VDD = 3.14 to 3.47V, measured VIN = 0V  
100  
150  
AC Electrical Specifications  
Parameter[1]  
Name  
Description  
Min.  
Typ.  
Max.  
Unit  
DC  
Output Duty Cycle  
Duty Cycle is defined in Figure 1; t1/t2, 50% of  
45  
50  
55  
%
VDD  
ER  
EF  
Rising Edge Rate  
Falling Edge Rate  
Output Clock Edge Rate, Measured from 20% to  
0.8  
0.8  
1.4  
1.4  
200  
V/ns  
V/ns  
80% of VDD, CLOAD = 15 pF. See Figure 2.  
Output Clock Edge Rate, Measured from 80% to  
20% of VDD, CLOAD = 15 pF. See Figure 2.  
t9  
Clock Jitter  
CLK1, CLK2 Peak-Peak period jitter  
ps  
t10  
PLL Lock Time  
3
ms  
Test and Measurement Set-up  
VDDs  
Outputs  
CLOAD  
0.1 µF  
DUT  
GND  
Note:  
1. Not 100% tested.  
Document #: 38-07451 Rev. *B  
Page 3 of 6  
CY24206  
Voltage and Timing Definitions  
t1  
t2  
VDD  
50% of VDD  
0V  
Clock  
Output  
Figure 1. Duty Cycle Definitions  
t4  
t3  
V DD  
80% of VDD  
20% of VDD  
0V  
Clock  
Output  
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4  
Ordering Information  
Ordering Code  
CY24206ZC-2  
CY24206ZC-2T  
CY24206ZC-3  
CY24206ZC-3T  
CY24206ZC-4  
CY24206ZC-4T  
Lead Free  
Package Name  
Package Type  
16-Pin TSSOP  
Operating Range  
Commercial  
Operating Voltage  
Z16  
Z16  
Z16  
Z16  
Z16  
Z16  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
3.3V  
16-Pin TSSOP – Tape and Reel Commercial  
16-Pin TSSOP Commercial  
16-Pin TSSOP – Tape and Reel Commercial  
16-Pin TSSOP Commercial  
16-Pin TSSOP – Tape and Reel Commercial  
CY24206ZXC-4  
CY24206ZXC-4T  
Z16  
Z16  
16-Pin TSSOP  
16-Pin TSSOP – Tape and Reel Commercial  
Commercial  
3.3V  
3.3V  
Document #: 38-07451 Rev. *B  
Page 4 of 6  
CY24206  
Package Drawing and Dimensions  
16-lead TSSOP 4.40 MM Body Z16.173  
PIN 1 ID  
DIMENSIONS IN MM[INCHES] MIN.  
MAX.  
1
REFERENCE JEDEC MO-153  
PACKAGE WEIGHT 0.05 gms  
6.25[0.246]  
6.50[0.256]  
4.30[0.169]  
4.50[0.177]  
PART #  
Z16.173 STANDARD PKG.  
ZZ16.173 LEAD FREE PKG.  
16  
0.65[0.025]  
BSC.  
0.25[0.010]  
BSC  
0.19[0.007]  
0.30[0.012]  
1.10[0.043] MAX.  
GAUGE  
PLANE  
0°-8°  
0.076[0.003]  
0.50[0.020]  
0.70[0.027]  
0.05[0.002]  
0.15[0.006]  
0.85[0.033]  
0.95[0.037]  
0.09[[0.003]  
0.20[0.008]  
SEATING  
PLANE  
4.90[0.193]  
5.10[0.200]  
51-85091-*A  
MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document  
may be the trademarks of their respective holders.  
Document #: 38-07451 Rev. *B  
Page 5 of 6  
CY24206  
Document History Page  
Document Title: CY24206 MediaClock™ DTV, STB Clock Generator  
Document Number: 38-07451  
Orig. of  
REV.  
**  
*A  
ECN NO. Issue Date Change  
Description of Change  
120901  
123046  
270029  
12/10/02  
03/03/03  
See ECN  
CKN  
CKN  
RGL  
New data sheet  
Added –4 to data sheet  
Removed Preliminary  
*B  
Added Lead-free devices for -4  
Document #: 38-07451 Rev. *B  
Page 6 of 6  

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