CY2254A [CYPRESS]

Pentium Processor Compatible Clock Synthesizer/Driver; 奔腾处理器兼容的时钟合成器/驱动器


型号：	CY2254A
厂家：	CYPRESS
描述：	Pentium Processor Compatible Clock Synthesizer/Driver 奔腾处理器兼容的时钟合成器/驱动器驱动器时钟
文件：	总8页 (文件大小：97K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY2254A

Pentium^®Processor Compatible

Clock Synthesizer/Driver

• Freq. stability = 0.01% (max.)

Features

• Output duty cycle 45% min. to 55% max.

• Test mode support (−1 option only)

• 3.3V or 5.0V operation

• Multiple clock outputs to meet requirements of most

Pentium^®motherboards

— Four pin-selectable CPU clocks @ 66.66 MHz, 60.0

MHz, and50.0MHz forsupport ofIntel Triton^™PCIset

based PC

• Internal pull-up resistors on S0, S1, and OE inputs

Functional Description

— 55.0 MHz pin-selectable CPU clock also available (−2

The CY2254A is a Clock Synthesizer/Driver that provides the

multiple clocks required for a Pentium-based PC. The

CY2254A has low-skew outputs (< 250 ps between the CPU

Clocks, < 250 ps between the PCI Clocks). In addition, the

CY2254A CPU clock outputs have less than 200 ps cy-

cle-to-cycle jitter. Finally, both the PCI and CPU clock outputs

meet the 1 V/ns slew rate requirement of a Pentium proces-

sor-based system.

option only)

— Six PCI clocks at 1/2 CPU Clock frequency

— One I/O clock @ 24 MHz

— OneKeyboardControllerclock@ 12MHz(−1 option)

or one Universal Serial Bus clock @ 48 MHz

(−2 option)

— Two Ref. clocks @ 14.318 MHz

The CY2254A accepts a 14.318 MHz reference signal as its

input. The CY2254A has 2 PLLs, one of which generates the

CPU and PCI clocks, and the other generates the I/O and Key-

board Controller or USB clocks. The CY2254A runs off either

a 3.3V or 5V supply.

— Ref. 14.318 MHz Xtal oscillator input

• CPU clock jitter < 200 ps cycle-to-cycle

• Low skew outputs

— < 250 ps between CPU clocks

The CY2254A is available in two options. The −1 option sup-

ports the Intel Triton PCIset and provides a 12 MHz keyboard

clock on pin 25. The −2 option provides a 48 MHz USB clock

on pin 25 and supports the Cyrix^®M1 processor.

— < 250 ps between PCI clocks

— < 500 ps between CPU and PCI clocks (−2 option)

— CPU clock leads PCI clock by +1 ns min. to +4 ns

max. (−1 option)

Pin Configuration

Logic Block Diagram

REF0 (14.318 MHz)

Top View

REF1 (14.318 MHz)

KBDCLK (12 MHz)

SOIC

SYS

÷2

PLL

REF0

REF1

14.318

MHz

OSC.

XTALIN

IOCLK (24 MHz)

XTALOUT

USBCLK (48 MHz)

SEEBELOW

IOCLK

CPUCLK0

CPUCLK1

CPU

PLL

CPUCLK0

CPUCLK1

CPUCLK2

CPUCLK3

PCICLK2

PCICLK3

ROM

CPUCLK2

CPUCLK3

PCICLK4

PCICLK5

÷2

DELAY

PCICLK1

PCICLK0

−1 option only

PCICLK0

PCICLK1

PCICLK2

PCICLK3

PIN 25

OPTION

KBDCLK

12 MHz

USBCLK

48 MHz

−1

−2

PCICLK4

PCICLK5

Intel and Pentium are registered trademarks of Intel Corporation.

Triton is a trademark of Intel Corporation.

Cyrix is a registered trademark of Cyrix Corporation.

Cypress Semiconductor Corporation

Document #: 38-07203 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised December 14, 2002

CY2254A

Pin Summary

Name

−1

−2

Description

V_DD

Voltage supply

XTALIN^[1]

XTALOUT^[1]

V_SS

Reference crystal input

Reference crystal feedback

Ground

Output Enable, Active HIGH (internal pull-up resistor to V_DD

CPU clock output

)

CPUCLK0

CPUCLK1

V_DD

CPU clock output

Voltage supply

CPUCLK2

CPUCLK3

V_SS

CPU clock output

Ground

CPU clock select input, bit 1 (internal pull-up resistor to V_DD

CPU clock select input, bit 0 (internal pull-up resistor to V_DD

Voltage supply

)

V_DD

PCICLK0

PCICLK1

V_SS

PCI clock output

Ground

PCICLK5

PCICLK4

V_DD

PCI clock output

Voltage supply

PCICLK3

PCICLK2

V_SS

PCI clock output

Ground

IOCLK

KBDCLK

USBCLK

V_DD

I/O clock output (24 MHz)

Keyboard controller clock output (12 MHz)

Universal Serial Bus clock output (48 MHz)

Voltage supply

REF1

Reference clock output (14.318 MHz)

REF0

Function Table

Ref. Clock

Output

KBDCLK

−1 only

USBCLK

Option

−1,−2

−1

OE S0 S1

XTALIN

CPUCLK

PCICLK

High-Z

IOCLK

High-Z

−2 only

14.318 MHz High-Z

14.318 MHz 50.0 MHz

14.318 MHz 60.0 MHz

High-Z

25.0 MHz

30.0 MHz

14.318 MHz 24 MHz

12 MHz

TCLK/8

48 MHz

14.318 MHz 66.66 MHz 33.33 MHz 14.318 MHz 24 MHz

TCLK^[2]

TCLK/2

TCLK/4

TCLK

TCLK/4

−2

14.318 MHz 55.0 MHz

27.5 MHz

14.318 MHz 24 MHz

48 MHz

Notes:

1. For best accuracy, use a parallel-resonant crystal, C_LOAD= 17 pF.

2. TCLK is a test clock on XTALIN (pin 2) during test mode.

Document #: 38-07203 Rev. *A

Page 2 of 8

CY2254A

PCI Clock Driver Strength Requirements

Maximum Ratings

• Matched impedances on both rising and falling edges on

the output drivers

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

• Output impedance: 25Ω (typical) measured at 1.5V

• Maximum output impedance: 40Ω measured at 1.5V

Supply Voltage........................................................−0.5 to +7.0V

Input Voltage................................................. −0.5V to V_DD+ 0.5

Storage Temperature (Non-Condensing).... −65°C to +150°C

Junction Temperature............................................... +150°C

Package Power Dissipation.............................................. 1W

CPU Clock Driver Strength Requirements

• Matched impedances on both rising and falling edges on

the output drivers

• Output impedance: 25Ω (typical) measured at 1.5V

• Maximum output impedance: 40Ω measured at 1.5V

Static Discharge Voltage............................................ >2000V

(per MIL-STD-883, Method 3015)

Operating Conditions^[3]

Parameter

V_DD

Description

Min.

Max.

Unit

Supply Voltage 3.3V

Supply Voltage 5.0V

3.135

4.5

3.6

5.5

T_A

C_L

Operating Ambient Temperature

°C

Max. Capacitive Load on

CPUCLK

PCICLK

IOCLK

KBDCLK / USBCLK

REF0

REF1

f_(REF)

t_PU

Reference Frequency, Oscillator Nominal Value

14.318

0.05

14.318

MHz

Power-up time for all VDD's to reach minimum specified voltage (power

ramps must be monotonic)

Electrical Characteristics V_DD= 3.135V − 3.6V, or 5.0V ±10%, T_A= 0°C to +70°C

Parameter

V_IH

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Low-level Input Voltage

Except Crystal Inputs

2.0

V_IL

0.8

[4]

V_OH

High-level Output Voltage V_DD= V_DDMin.

I_OH= 6 mA

I_OH= 12 mA

I_OH= 4 mA

I_OH= 8 mA

I_OL= 6 mA

I_OL= 12 mA

I_OL= 4 mA

I_OL= 8 mA

CPUCLK

PCICLK, REF0

2.4

KBDCLK, USBCLK

REF1

[4]

V_OL

Low-level Output Voltage

V_DD= V_DDMin.

CPUCLK

0.4

PCICLK, REF0

KBDCLK, USBCLK

REF1

I_IH

Input High Current

Input Low Current

V_IH= V_DD,V_DD= 3.3V

V_IH= V_DD,V_DD= 5.0V

V_IL= 0 V, V_DD= 3.3V

V_IL= 0 V, V_DD= 5.0V

Three-state

µA

I_IL

100

250

+10

I_OZ

I_DD

Output Leakage Current

Power Supply Current

−10

V_DD= 3.6V, V_IN= 0 or V_DD

V_DD= 5.5V, V_IN= 0 or V_DD

150

Document #: 38-07203 Rev. *A

Page 3 of 8

CY2254A

Electrical Characteristics V_DD= 3.135V − 3.6V, or 5.0V ±10%, T_A= 0°C to +70°C (continued)

Parameter

Description

Test Conditions

Min. Max. Unit

Notes:

3. Electrical parameters are guaranteed with these operating conditions.

4. Guaranteed by design, not tested.

Switching Characteristics^[5]

Parameter

Output

Name

Description

t₁= t_1A÷ t_1B

Min. Max. Unit

t₁

All

Output Duty Cycle^[6]

45% 55%

[4]

t₂

CPUCLK, PCICLK

Output Rising and Fall- Measured between 0.4 and 2.4V

ing Edge Rate

V/ns

[4]

t₃

REF, KBDCLK, USBCLK

CPUCLK

Rise Time

Fall Time

Measured between 0.4 and 2.4V

Measured between 2.4 and 0.4V

[4]

t₄

[4]

t₅

CPU-CPU Clock Skew Measured at 1.5V

250

[4]

t₆

PCICLK

PCI-PCI Clock Skew

CPU-PCI Skew

Measured at 1.5V

[4]

t₇

CPUCLK, PCICLK

Measured at 1.5V (−1 option)

Measured at 1.5V (−2 option)

500

200

[4]

t₈

CPUCLK

Cycle-Cycle Clock Jitter CPU Clock Jitter

Switching Waveforms

Duty Cycle Timing

1.5V

All Outputs Rise/Fall Time

3.3V

2.4V

0.4V

OUTPUT

0.4V

Document #: 38-07203 Rev. *A

Page 4 of 8

CY2254A

Switching Waveforms (continued)

Clock Skew

1.5V

CPUCLK/

PCICLK

1.5V

Notes:

5. All parameters specified with outputs fully loaded.

6. Duty cycle is measured at 1.5V.

Document #: 38-07203 Rev. *A

Page 5 of 8

CY2254A

Switching Waveforms (continued)

CPU-PCI Clock Skew

1.5V

CPUCLK

1.5V

PCICLK

Test Circuit

V_DD

0.1 µF

V_DD

14 OUTPUTS

C_LOAD

0.1 µF

Note:All capacitors should be placed as close to each pin as possible.

Ordering Information

Package

Operating

Range

Ordering Code

CY2254ASC−1

CY2254ASC−2

Name

Package Type

28-Pin SOIC

S21

Commercial

S21

Document #: 38-07203 Rev. *A

Page 6 of 8

CY2254A

Package Diagram

28-Lead (300-Mil) Molded SOIC S21

51-85026-A

Document #: 38-07203 Rev. *A

Page 7 of 8

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY2254A

Document Title: CY2254A Pentium^®Processor Compatible Clock Synthesizer/Driver

Document Number: 38-07203

Issue

Date

Orig. of

Change

REV.

ECN NO.

111723

Description of Change

12/15/01

12/14/02

DSG

RBI

Change from Spec number: 38-00504 to 38-07203

121838

Power up requirements added to Operating Conditions Information

Document #: 38-07203 Rev. *A

Page 8 of 8

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