CY22393_09 [CYPRESS]
Three-PLL Serial-Programmable Flash-Programmable Clock Generator; 三锁相环串行可编程闪存的可编程时钟发生器
| 型号： | CY22393_09 |
| 厂家： | 
CYPRESS |
| 描述： | Three-PLL Serial-Programmable Flash-Programmable Clock Generator |
| 文件： | 总19页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY22393, CY223931, CY22394, CY22395
Three-PLL Serial-Programmable
Flash-Programmable Clock Generator
Features
Benefits
■ Three integrated phase-locked loops (PLLs)
■ Generates up to three unique frequencies on up to six
outputs from an external source.
■ Ultra wide divide counters (8-bit Q, 11-bit P, and 7-bit post
divide)
■ Allows for 0 ppm frequency generation and frequency
conversion in the most demanding applications.
■ Improved linear crystal load capacitors
■ Flash programmability with external programmer
■ Field-programmable
■ Improves frequency accuracy over temperature, age,
process, and initial ppm offset.
■ Nonvolatile programming enables easy customization,
ultra-fast turnaround, performance tweaking, design timing
margin testing, inventory control, lower part count, and more
secure product supply. In addition, any part in the family can
be programmed multiple times, which reduces programming
errors and provides an easy upgrade path for existing
designs.
■ Low jitter, high accuracy outputs
■ Power management options (Shutdown, OE, Suspend)
■ Configurable crystal drive strength
■ Frequency select through three external LVTTL inputs
■ 3.3V operation
■ In-house programming of samples and prototype quantities
is available using the CY3672 FTG Development Kit.
Production quantities are available through Cypress
Semiconductor’s value-added distribution partners or by
using third-party programmers from BP Microsystems, HiLo
Systems, and others.
■ 16-pin TSSOP package
■ CyClocksRT™ software support
Advanced Features
■ Performance suitable for high-end multimedia, communica-
tions, industrial, A/D converters, and consumer applications.
■ 2-wire serial interface for in-system configurability
■ Configurable output buffer
■ Supports numerous low power application schemes and
reduces electromagnetic interference (EMI) by allowing
unused outputs to be turned off.
■ Digital VCXO
■ High frequency LVPECL output (CY22394 only)
■ 3.3/2.5V outputs (CY22395 only)
■ NiPdAu lead finish (CY223931)
■ Adjust crystal drive strength for compatibility with virtually all
crystals.
■ 3-bit external frequency select options for PLL1, CLKA, and
CLKB.
■ Industry standard packaging saves on board space.
■ Easy to use software support for design entry.
■ 2-wire serial interface allows in-system programming into
volatile configuration memory. All frequency settings can be
changed, providing literally millions of frequency options.
■ Adjust output buffer strength to lower EMI or improve timing
margin.
■ Fine tune crystal oscillator frequency by changing load
capacitance.
■ Differential output up to 400 MHz.
■ Provides interfacing option for low voltage parts.
Cypress Semiconductor Corporation
Document #: 38-07186 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 9, 2009
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Selector Guide
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifics
CY22393_C
6 CMOS
8 MHz–30 MHz (external crystal) Up to 200 MHz
1 MHz–166 MHz (reference clock)
Commercial Temperature
CY22393_I
6 CMOS
8 MHz–30 MHz (external crystal) Up to 166 MHz
1 MHz–166 MHz (reference clock)
Industrial Temperature
Industrial Temperature
Commercial Temperature
Industrial Temperature
Commercial Temperature
Industrial Temperature
CY223931_I 6 CMOS
8 MHz–30 MHz (external crystal) Up to 166 MHz
1 MHz–166 MHz (reference clock)
CY22394_C
CY22394_I
CY22395_C
CY22395_I
1 PECL/
4 CMOS
8 MHz–30 MHz (external crystal) 100 MHz–400 MHz (PECL)
1 MHz–166 MHz (reference clock) Up to 200 MHz (CMOS)
1 PECL/
4 CMOS
8 MHz–30 MHz (external crystal) 125 MHz–375 MHz (PECL)
1 MHz–150 MHz (reference clock) Up to 166 MHz (CMOS)
4 LVCMOS/ 8 MHz–30 MHz (external crystal) Up to 200 MHz (3.3V)
1 CMOS 1 MHz–166 MHz (reference clock) Up to 133 MHz (2.5V)
4 LVCMOS/ 8 MHz–30 MHz (external crystal) Up to 166 MHz (3.3V)
1 CMOS 1 MHz–150 MHz (reference clock) Up to 133 MHz (2.5V)
Logic Block Diagram - CY22393 and CY223931
XTALIN
XBUF
OSC.
XTALOUT
CONFIGURATION
PLL1
FLASH
Divider
/2, /3, or /4
CLKE
11-Bit P
8-Bit Q
SHUTDOWN/OE
PLL2
Divider
7-Bit
SCLK
CLKD
CLKC
11-Bit P
8-Bit Q
4x4
Crosspoint
SDAT
Switch
S2/SUSPEND
Divider
7-Bit
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
CLKB
CLKA
Divider
7-Bit
Document #: 38-07186 Rev. *E
Page 2 of 19
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CY22393, CY223931, CY22394, CY22395
Logic Block Diagram - CY22394
XTALIN
XBUF
OSC.
XTALOUT
CONFIGURATION
FLASH
0º
PLL1
P+CLK
PECL
OUTPUT
11-Bit P
8-Bit Q
180º
P-CLK
SHUTDOWN/OE
SCLK
PLL2
Divider
7-Bit
4x4
Crosspoint
Switch
CLKC
SDAT
11-Bit P
8-Bit Q
S2/SUSPEND
Divider
7-Bit
CLKB
CLKA
PLL3
11-Bit P
8-Bit Q
Divider
7-Bit
Logic Block Diagram - CY22395
XTALIN
OSC.
XTALOUT
Divider
/2, /3, or /4
LCLKE
CONFIGURATION
FLASH
PLL1
11-Bit P
8-Bit Q
Divider
7-Bit
LCLKD
CLKC
SHUTDOWN/OE
SCLK
4x4
Crosspoint
Switch
SDAT
Divider
7-Bit
S2/SUSPEND
PLL2
11-Bit P
8-Bit Q
Divider
7-Bit
LCLKB
LCLKA
PLL3
Divider
7-Bit
11-Bit P
8-Bit Q
LCLKA, LCLKB, LCLKD, LCLKE referenced to LVDD
Document #: 38-07186 Rev. *E
Page 3 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Pinouts
Figure 1. Pin diagram - 16-Pin TSSOP CY22393/CY223931/CY22394/CY22394
CY22393
CY223931
CY22395
CY22394
CL KC
VDD
1
SHUTDOWN/OE
S2/SUSPEND
AVDD
CLKC
1
SHUTDOWN/OE
S2/SUSPEND
AVDD
16
15
14
13
12
CLKC
VDD
1
SHUTDOWN/OE
S2/SUSPEND
AVD D
16
15
14
13
12
16
15
14
13
12
2
3
VDD
2
3
2
AGND
AGND
AGND
3
4
4
4
XTALIN
XTALOUT
XBUF
SCLK (S1)
SDAT (S0)
GND
XTALIN
SCLK (S1)
SDAT (S0)
GND/LGND
XTALIN
XTALOUT
XBUF
SCLK(S1)
SDAT (S0)
GND
5
6
XTALOUT
LVDD
5
6
5
6
11
10
9
11
10
9
11
10
9
CLKD
CLKE
CLKA
CLKB
LCL KD
LCL KE
LCLKA
LCLKB
7
8
P–CLK
CLKA
CLKB
7
8
7
8
P+ CLK
Pin Definitions
Pin Number
CY22393
CY223931
Pin Number Pin Number
Name
Description
CY22394
CY22395
CLKC
1
2
1
2
1
2
Configurable clock output C
Power supply
VDD
AGND
3
3
3
Analog Ground
XTALIN
4
4
4
Reference crystal input or external reference clock input
Reference crystal feedback
XTALOUT
XBUF
5
5
5
6
6
N/A
6
Buffered reference clock output
LVDD
N/A
7
N/A
N/A
7
Low voltage clock output power supply
Configurable clock output D; LCLKD referenced to LVDD
LV PECL output[1]
CLKD or LCLKD
P– CLK
7
N/A
8
N/A
8
CLKE or LCLKE
P+ CLK
N/A
8
Configurable clock output E; LCLKE referenced to LVDD
LV PECL output[1]
N/A
9
N/A
9
CLKB or LCLKB
CLKA or LCLKA
GND/LGND
SDAT (S0)
SCLK (S1)
AVDD
9
Configurable clock output B; LCLKB referenced to LVDD
Configurable clock output A; LCLKA referenced to LVDD
Ground
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
15
Serial Port Data. S0 value latched during start up
Serial Port Clock. S1 value latched during start up
Analog Power Supply
S2/
SUSPEND
General purpose input for frequency control; bit 2. Optionally,
Suspend mode control input
SHUTDOWN/
OE
16
16
16
Places outputs in tri-state condition and shuts down chip when
LOW. Optionally, only places outputs in tri-state condition and
does not shut down chip when LOW
Note
1. LVPECL outputs require an external termination network.
Document #: 38-07186 Rev. *E
Page 4 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Crystal Input
Operation
The input crystal oscillator is an important feature of this family
of parts because of its flexibility and performance features.
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, process, performance, and quality.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when nonlinear load
capacitance interacts with load, bias, supply, and temperature
changes. Nonlinear (FET gate) crystal load capacitors must not
be used for MPEG, POTS dial tone, communications, or other
applications that are sensitive to absolute frequency
requirements.
The clock family has three PLLs which, when combined with the
reference, allow up to four independent frequencies to be output
on up to six pins. These three PLLs are completely
programmable.
The CY223931 is the CY22393 with NiPdAu lead finish.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL1 is sent to two
locations: the cross point switch and the PECL output
(CY22394). The output of PLL1 is also sent to a /2, /3, or /4
synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed using serial programming or
by external CMOS inputs, S0, S1, and S2. See the following
section on General Purpose Inputs for more detail.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with a
resolution of 0.375pF for a total crystal load range of 6pF to 30pF.
For driven clock inputs, the input load capacitors can be
completely bypassed. This allows the clock chip to accept driven
frequency inputs up to 166 MHz. If the application requires a
driven input, leave XTALOUT floating.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL2 is sent to the
cross point switch. The frequency of PLL2 is changed using
serial programming.
Digital VCXO
The serial programming interface is used to dynamically change
the capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit divider
in the PLL feedback loop (P). The output of PLL3 is sent to the
cross point switch. The frequency of PLL3 is changed using
serial programming.
For special pullable crystals specified by Cypress, the
capacitance pull range is +150 ppm to –150 ppm from midrange.
Be aware that adjusting the frequency of the reference affects all
frequencies on all PLLs in a similar manner since all frequencies
are derived from the single reference.
General Purpose Inputs
Output Configuration
S2 is a general purpose input that is programmed to allow for two
different frequency settings. Options that switches with this
general purpose input are as follows: the frequency of PLL1, the
output divider of CLKB, and the output divider of CLKA.
Under normal operation there are four internal frequency
sources that are routed through a programmable cross point
switch to any of the four programmable 7-bit output dividers. The
four sources are: reference, PLL1, PLL2, and PLL3. The
following is a description of each output.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start up and used as the other two indexes
into this array.
CLKA’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one of the two programmable registers.
See the section on “General Purpose Inputs” on page 5 for more
information.
CLKA and CLKB have seven-bit dividers that point to one of the
two programmable settings (register 0 and register 1). Both
clocks share a single register control and both must be set to
register 0, or both must be set to register 1.
CLKB’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one of the two programmable registers.
See the section on “General Purpose Inputs” on page 5 for more
information.
For example, the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q on
PLL1. For each PLL1 P and Q setting, one of the two CLKA and
CLKB divider registers can be chosen. Any divider change as a
result of switching S0, S1, or S2 is guaranteed to be glitch free.
CLKC’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one programmable register.
CLKD’s output originates from the cross point switch and goes
through a programmable 7-bit post divider. The 7-bit post divider
derives its value from one programmable register. For the
CY22394, CLKD is brought out as the complimentary version of
Document #: 38-07186 Rev. *E
Page 5 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
a LV PECL Clock referenced to CLKE, bypassing both the cross
point switch and 7-bit post divider.
CyClocksRT is used to generate P, Q, and divider values used
in serial programming. There are many internal frequency rules
that are not documented in this data sheet, but are required for
proper operation of the device. Check these rules by using the
latest version of CyClocksRT.
CLKE’s output originates from PLL1 and goes through a post
divider that may be programmed to /2, /3, or /4. For the CY22394,
CLKE is brought out as a low voltage PECL Clock, bypassing the
post divider.
Junction Temperature Limitations
XBUF is the buffered reference.
It is possible to program this family such that the maximum
Junction Temperature rating is exceeded. The package θJA is
115 °C/W. Use the CyClocksRT power estimation feature to
verify that the programmed configuration meets the Junction
Temperature and Package Power Dissipation maximum ratings.
The Clock outputs have been designed to drive a single point
load with a total lumped load capacitance of 15 pF. While driving
multiple loads is possible with the proper termination it is
generally not recommended.
Power-Saving Features
Dynamic Updates
The SHUTDOWN/OE input tri-states the outputs when pulled
LOW. If system shutdown is enabled, a LOW on this pin also
shuts off the PLLs, counters, reference oscillator, and all other
active components. The resulting current on the VDD pins is less
than 5 mA (typical). Relock the PLLs after leaving shutdown
mode.
The output divider registers are not synchronized with the output
clocks. Changing the divider value of an active output is likely
cause a glitch on that output.
PLL P and Q data is spread between three bytes. Each byte
becomes active on the acknowledge for that byte, so changing
P and Q data for an active PLL is likely cause the PLL to try to
lock on an out-of-bounds condition. For this reason, turn off the
PLL being programmed during the update. Do this by setting the
PLL*_En bit LOW.
The S2/SUSPEND input is configured to shut down a
customizable set of outputs and/or PLLs, when LOW. All PLLs
and any of the outputs are shut off in nearly any combination.
The only limitation is that if a PLL is shut off, all outputs derived
from it must also be shut off. Suspending a PLL shuts off all
associated logic, while suspending an output simply forces a
tri-state condition.
PLL1, CLKA, and CLKB each have multiple registers supplying
data. To program these resources safely, always program an
inactive register, and then transition to that register. This allows
these resources to stay active during programming.
With the serial interface, each PLL and/or output is individually
disabled. This provides total control over the power savings.
The serial interface is active even with the SHUTDOWN/OE pin
LOW as the serial interface logic uses static components and is
completely self timed. The part does not meet the IDDS current
limit with transitioning inputs.
Improving Jitter
Jitter Optimization Control is useful for mitigating problems
related to similar clocks switching at the same moment, causing
excess jitter. If one PLL is driving more than one output, the
negative phase of the PLL can be selected for one of the outputs
(CLKA–CLKD). This prevents the output edges from aligning,
allowing superior jitter performance.
Memory Bitmap Definitions
Clk{A–D}_Div[6:0]
Each of the four main output clocks (CLKA–CLKD) features a
7-bit linear output divider. Any divider setting between 1 and 127
may be used by programming the value of the desired divider
into this register. Odd divide values are automatically duty cycle
corrected. Setting a divide value of zero powers down the divider
and forces the output to a tri-state condition.
Power Supply Sequencing
For parts with multiple VDD pins, there are no power supply
sequencing requirements. The part is not fully operational until
all VDD pins have been brought up to the voltages specified in
the Operating Conditions Table on page 13.
CLKA and CLKB have two divider registers, selected by the
DivSel bit (which in turn is selected by S2, S1, and S0). This
allows the output divider value to change dynamically. For the
CY22394 device, ClkD_Div = 000001.
All grounds must be connected to the same ground plane.
CyClocksRT Software
ClkE_Div[1:0]
CyClocksRT is our second generation software application that
allows users to configure this family of devices. The easy-to-use
interface offers complete control of the many features of this
family including, but not limited to, input frequency, PLL and
output frequencies, and different functional options. It checks
data sheet frequency range limitations and automatically applies
performance tuning. CyClocksRT also has a power estimation
feature that allows the user to see the power consumption of a
specific configuration. You can download a free copy of
CyberClocks that includes CyClocksRT for free on Cypress’s
web site at www.cypress.com.
CLKE has a simpler divider (see Table 1). For the CY22394, set
ClkE_Div = 01.
Table 1. ClkE Divider
ClkE_Div[1:0]
ClkE Output
Off
00
01
10
11
PLL1 0° Phase/4
PLL1 0° Phase/2
PLL1 0° Phase/3
Document #: 38-07186 Rev. *E
Page 6 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Clk*_FS[2:0]
PLL*_Q[7:0]
PLL*_P[9:0]
PLL*_P0
Each of the four main output clocks (CLKA–CLKD) has a
three-bit code that determines the clock sources for the output
divider. The available clock sources are: Reference, PLL1, PLL2,
and PLL3. Each PLL provides both positive and negative phased
outputs, for a total of seven clock sources (see Table 2). Note
that the phase is a relative measure of the PLL output phases.
No absolute phase relation exists at the outputs.
These are the 8-bit Q value and 11-bit P values that determine
the PLL frequency. The formula is:
PT
⎛
⎝
⎞
⎠
------
FPLL = FREF
×
Table 2. Clock Source
QT
Equation 1
Clk*_FS[2:0]
000
Clock Source
Reference Clock
PT = (2 × (P + 3)) + PO
QT = Q + 2
001
Reserved
PLL*_LF[2:0]
010
PLL1 0° Phase
PLL1 180° Phase
PLL2 0° Phase
PLL2 180° Phase
PLL3 0° Phase
PLL3 180° Phase
These bits adjust the loop filter to optimize the stability of the PLL.
Table 4 can be used to guarantee stability. However,
CyClocksRT uses a more complicated algorithm to set the loop
filter for enhanced jitter performance. Use the Print Preview
function in CyClocksRT to determine the charge pump settings
for optimal jitter performance.
011
100
101
110
111
Table 4. Loop Filter Settings
Xbuf_OE
PLL*_LF[2:0]
PT Min
16
PT Max
231
This bit enables the XBUF output when HIGH. For the CY22395,
Xbuf_OE = 0.
000
001
010
011
100
232
626
PdnEn
627
834
This bit selects the function of the SHUTDOWN/OE pin. When
this bit is HIGH, the pin is an active LOW shutdown control. When
this bit is LOW, this pin is an active HIGH output enable control.
835
1043
1600
1044
PLL*_En
Clk*_ACAdj[1:0]
This bit enables the PLL when HIGH. If PLL2 or PLL3 are not
enabled, then any output selecting the disabled PLL must have
a divider setting of zero (off). Since the PLL1_En bit is dynamic,
internal logic automatically turns off dependent outputs when
PLL1_En goes LOW.
These bits modify the output predrivers, changing the duty cycle
through the pads. These are nominally set to 01, with a higher
value shifting the duty cycle higher. The performance of the
nominal setting is guaranteed.
Clk*_DCAdj[1:0]
DivSel
These bits modify the DC drive of the outputs. The performance
of the nominal setting is guaranteed.
This bit controls which register is used for the CLKA and CLKB
dividers.
Table 3. Output Drive Strength
OscCap[5:0]
Clk*_DCAdj[1:0]
Output Drive Strength
–30% of nominal
This controls the internal capacitive load of the oscillator. The
approximate effective crystal load capacitance is:
00
01
10
11
Nominal
Equation 2
CLOAD = 6pF + (OscCap × 0.375pF)
+15% of nominal
+50% of nominal
Set to zero for external reference clock.
Document #: 38-07186 Rev. *E
Page 7 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
For external reference, the use Table 6.
OscDrv[1:0]
These bits control the crystal oscillator gain setting. These must
always be set according to Table 5. The parameters are the
Crystal Frequency, Internal Crystal Parasitic Resistance
(available from the manufacturer), and the OscCap setting
during crystal start up, which occurs when power is applied, or
after shutdown is released. If in doubt, use the next higher
setting.
Table 6. Osc Drv for External Reference
External Freq (MHz) 1–25 25–50 50–90 90–166
OscDrv[1:0]
00
01
10
11
Reserved
These bits must be programmed LOW for proper operation of the
device.
Table 5. Crystal Oscillator Gain Settings
OscCap
00H–20H
20H–30H
30H–40H
Crystal Freq\ R 30Ω 60Ω 30Ω 60Ω 30Ω 60Ω
8–15 MHz
15–20 MHz
20–25 MHz
25–30 MHz
00
01
01
10
01
10
10
10
01
01
10
10
10
10
10
11
01
10
10
11
10
10
11
NA
Serial Programming Bitmaps — Summary Tables
Addr DivSel
b7
b6
b5
b4
b3
b2
b1
b0
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
–
ClkA_FS[0]
ClkA_FS[0]
ClkB_FS[0]
ClkB_FS[0]
ClkC_FS[0]
ClkD_FS[0]
ClkA_Div[6:0]
ClkA_Div[6:0]
ClkB_Div[6:0]
ClkB_Div[6:0]
ClkC_Div[6:0]
ClkD_Div[6:0]
ClkD_FS[2:1]
ClkC_FS[2:1]
ClkB_FS[2:1]
ClkA_FS[2:1]
Clk{C,X}_ACAdj[1:0]
ClkX_DCAdj[1]
Clk{A,B,D,E}_ACAdj[1:0]
Clk{D,E}_DCAdj[1]
PdnEn
Xbuf_OE
ClkE_Div[1:0]
ClkC_DCAdj[1]
Clk{A,B}_DCAdj[1]
PLL2_Q[7:0]
PLL2_P[7:0]
PLL2_LF[2:0]
Reserved
PLL2_En
PLL2_PO
PLL2_P[9:8]
PLL3_Q[7:0]
PLL3_P[7:0]
Reserved
PLL3_En
PLL3_LF[2:0]
Osc_Cap[5:0]
PLL3_PO
PLL3_P[9:8]
Osc_Drv[1:0]
Addr S2 (1,0)
b7
b6
b5
b4
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b3
b2
b1
b0
40H
41H
42H
43H
44H
45H
46H
47H
48H
000
001
010
DivSel
DivSel
DivSel
PLL1_En
PLL1_En
PLL1_En
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_P[9:8]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
Document #: 38-07186 Rev. *E
Page 8 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Addr S2 (1,0)
b7
b6
b5
b4
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
b3
b2
b1
b0
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
011
100
101
110
111
DivSel
DivSel
DivSel
DivSel
DivSel
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_En
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_PO
PLL1_P[9:8]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_P[9:8]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
PLL1_Q[7:0]
PLL1_P[7:0]
PLL1_LF[2:0]
Data Valid
SerialBusProgrammingProtocolandTiming
Data is valid when the clock is HIGH, and can only be transi-
tioned when the clock is LOW as illustrated in Figure 4 on page
11.
The CY22393, CY22394 and CY22395 have a 2-wire serial
interface for in-system programming. They use the SDAT and
SCLK pins, and operate up to 400 kbit/s in Read or Write mode.
Except for the data hold time, it is compliant with the I2C bus
standard. The basic Write serial format is as follows:
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 5 on page 11.
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-
trated in Figure 3 on page 11.
Start Sequence - Start Frame is indicated by SDAT going LOW
when SCLK is HIGH. Every time a start signal is given, the next
8-bit data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Default Startup Condition for the CY22393/931/94/95
Stop Sequence - Stop Frame is indicated by SDAT going HIGH
when SCLK is HIGH. A Stop Frame frees the bus for writing to
another part on the same bus or writing to another random
register address.
The default (programmed) condition of each device is generally
set by the distributor, who programs the device using a customer
specified JEDEC file produced by CyClocksRT, Cypress’s propri-
etary development software. Parts shipped by the factory are
blank and unprogrammed. In this condition, all bits are set to 0,
all outputs are tri-stated, and the crystal oscillator circuit is active.
Acknowledge Pulse
During Write Mode the CY22393, CY22394, and CY22395
respond with an Acknowledge pulse after every eight bits. To do
this, they pull the SDAT line LOW during the N*9th clock cycle,
as illustrated in Figure 6 on page 12. (N = the number of bytes
transmitted). During Read Mode, the master generates the
acknowledge pulse after the data packet is read.
While users can develop their own subroutine to program any or
all of the individual registers as described in the following pages,
it may be easier to simply use CyClocksRT to produce the
required register setting file.
Device Address
The device address is a 7-bit value that is configured during Field
Programming. By programming different device addresses, two
or more parts are connected to the serial interface and can be
independently controlled. The device address is combined with
a read/write bit as the LSB and is sent after each start bit.
The default serial interface address is 69H, but must there be a
conflict with any other devices in your system, this can also be
changed using CyClocksRT.
Document #: 38-07186 Rev. *E
Page 9 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Random Read
Write Operations
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. Do this by sending the address to the
CY22393, CY22394 and CY22395 as part of a write operation.
After the word address is sent, the master generates a START
condition following the acknowledge. This terminates the write
operation before any data is stored in the address, but not before
setting the internal address pointer. Next, the master reissues
the control byte with the R/W byte set to ‘1’. The CY22393,
CY22394 and CY22395 then issue an acknowledge and transmit
the 8-bit word. The master device does not acknowledge the
transfer, but generates a STOP condition which causes the
CY22393, CY22394 and CY22395 to stop transmission.
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the data word is received, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition. Instead, the master
sends multiple contiguous bytes of data to be stored. After each
byte, the slave responds with an acknowledge bit, the same as
after the first byte, and accepts data until the STOP condition
responds to the acknowledge bit. When receiving multiple bytes,
the CY22393, CY223931, CY22394, and CY22395 internally
increment the register address.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmitting the first 8-bit data word. This
action increments the internal address pointer, and subsequently
outputs the next 8-bit data word. By continuing to issue acknowl-
edges instead of STOP conditions, the master serially reads the
entire contents of the slave device memory. Note that register
addresses outside of 08H to 1BH and 40H to 57H can be read
from but are not real registers and do not contain configuration
information. When the internal address pointer points to the FFH
register, after the next increment, the pointer points to the 00H
register.
Read Operations
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Current Address Read
The CY22393, CY22394 and CY22395 have an onboard
address counter that retains “1” more than the address of the last
word access. If the last word written or read was word ‘n’, then a
current address read operation returns the value stored in
location ‘n+1’. When the CY22393, CY22394 and CY22395
receive the slave address with the R/W bit set to a ‘1’, they issue
an acknowledge and transmit the 8-bit word. The master device
does not acknowledge the transfer, but generates a STOP
condition, which causes the CY22393, CY22394 and CY22395
to stop transmission.
Figure 2. Data Transfer Sequence on the Serial Bus
SCLK
SDAT
STOP
Address or
Acknowledge
Valid
Data may
be changed
Condition
START
Condition
Document #: 38-07186 Rev. *E
Page 10 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Figure 3. Data Frame Architecture
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
R/W = 0
SDAT Write
Multiple
Contiguous
Registers
7-bit
8-bit
8-bit
8-bit
8-bit
Register
Data
(XXH+2)
8-bit
Register
Data
8-bit
Register
Data
(00H)
Device
Address
Register Register Register
Address Data
Data
(XXH+1)
(XXH)
(XXH)
(FFH)
Stop Signal
Start Signal
1 Bit
Slave
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
R/W = 1
SDAT Read
7-bit
Device
Address
Current
Address
Read
8-bit
Register
Data
Stop Signal
Start Signal
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Master
ACK
1 Bit
Slave
ACK
1 Bit
Master
ACK
1 Bit
R/W = 0
SDAT Read
Multiple
Contiguous
Registers
7-bit
8-bit
7-bit
8-bit
Register
Data
8-bit
Register
Data
(XXH+1)
8-bit
Register
Data
8-bit
Register
Data
(00H)
Device
Address
Register Device
Address
(XXH)
Address
+R/W=1
(XXH)
(FFH)
Stop Signal
Start Signal
Repeated
Start bit
Figure 4. Data Valid and Data Transition Periods
Transition
to next Bit
Data Valid
SDAT
tDH
tSU
CLKHIGH
VIH
VIL
SCLK
CLKLOW
Serial Programming Interface Timing
Figure 5. Start and Stop Frame
SDAT
SCLK
Transition
START
to next Bit
STOP
Document #: 38-07186 Rev. *E
Page 11 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Figure 6. Frame Format (Device Address, R/W, Register Address, Register Data)
SDAT
+
+
+
START
D7
D6
D1
D0
DA6
DA5 DA0
R/W
ACK
RA7
RA6 RA1
RA0
ACK
ACK
STOP
+
+
+
SCLK
Serial Programming Interface Timing Specifications
Parameter
fSCLK
Description
Frequency of SCLK
Min
Max
Unit
kHz
μs
–
400
–
Start mode time from SDA LOW to SCL LOW
SCLK LOW period
0.6
1.3
0.6
100
100
–
CLKLOW
CLKHIGH
tSU
–
μs
SCLK HIGH period
–
μs
Data transition to SCLK HIGH
Data hold (SCLK LOW to data transition)
Rise time of SCLK and SDAT
Fall time of SCLK and SDAT
–
ns
tDH
–
ns
300
300
–
ns
–
ns
Stop mode time from SCLK HIGH to SDAT HIGH
Stop mode to Start mode
0.6
1.3
μs
–
μs
Document #: 38-07186 Rev. *E
Page 12 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Absolute Maximum Conditions
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ........................... –0.5V to + (AVDD + 0.5V)
Storage Temperature.................................. –65°C to +125°C
Junction Temperature.................................................. 125°C
Data Retention at Tj=125×C..................................> 10 years
Maximum Programming Cycles....................................... 100
Package Power Dissipation...................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2000V
Latch up (per JEDEC 17) .................................... > ±200 mA
Stresses exceeding Absolute Maximum Conditions may cause
permanent damage to the device. These conditions are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in the operation
sections of this data sheet is not implied. Extended exposure to
Absolute Maximum Conditions may affect reliability.
Operating Conditions
Parameter
Description
Part Numbers
Min
Typ
3.3
2.5
–
Max Unit
V
DD/AVDD/LVDD Supply Voltage
All
CY22395
Commercial Operating Temperature, Ambient All
3.135
3.465
2.625
+70
+85
15
V
V
LVDD
TA
2.5V Output Supply Voltage
2.375
0
–40
–
°C
Industrial Operating Temperature, Ambient
Maximum Load Capacitance
All
All
All
All
All
–
°C
CLOAD_OUT
fREF
–
pF
External Reference Crystal
8
–
30
MHz
MHz
MHz
External Reference Clock,[3] Commercial
External Reference Clock,[3] Industrial
1
–
166
150
1
–
3.3V Electrical Characteristics
Parameter
IOH
Description
Output High Current[4]
Output Low Current[4]
Conditions[2]
VOH = (L)VDD – 0.5, (L)VDD = 3.3V
VOL = 0.5, (L)VDD = 3.3V
Min
12
12
–
Typ
24
24
6
Max Unit
–
–
–
–
–
–
mA
mA
pF
IOL
CXTAL_MIN
Crystal Load Capacitance[4] Capload at minimum setting
Crystal Load Capacitance[3] Capload at maximum setting
CXTAL_MAX
–
30
7
pF
CIN
VIH
VIL
IIH
Input Pin Capacitance[4]
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input HIGH Current
Except crystal pins
CMOS levels,% of AVDD
CMOS levels,% of AVDD
VIN = AVDD – 0.3 V
VIN = +0.3 V
–
pF
70%
–
–
AVDD
30% AVDD
–
<1
<1
10
10
10
–
μA
μA
μA
mA
IIL
Input LOW Current
–
IOZ
IDD
Output Leakage Current
Three-state outputs
–
Total Power Supply Current 3.3V Power Supply;
2 outputs at 20 MHz; 4 outputs at 40 MHz
–
50
100
5
3.3V Power Supply;
2 outputs at 166 MHz; 4 outputs at 83 MHz
–
–
–
mA
IDDS
Total Power Supply Current in Shutdown active
Shutdown Mode
20
μA
2.5V Electrical Characteristics (CY22395 only)[5]
Parameter
IOH_2.5
Description
Output High Current[4]
Output Low Current[4]
Conditions
VOH = LVDD – 0.5, LVDD = 2.5 V
VOL = 0.5, LVDD = 2.5 V
Min
8
Typ
16
Max Unit
–
–
mA
mA
IOL_2.5
8
16
Notes
2. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
3. External input reference clock must have a duty cycle between 40% and 60%, measured at V /2.
DD
4. Guaranteed by design, not 100% tested.
5.
V
is only specified and characterized at 3.3V ± 5% and 2.5V ± 5%. V
may be powered at any value between 3.465 and 2.375.
DDL
DDL
Document #: 38-07186 Rev. *E
Page 13 of 19
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CY22393, CY223931, CY22394, CY22395
3.3V Switching Characteristics
Parameter
1/t1
Description
Output Frequency[4, 6]
Conditions
Min
–
Typ
–
Max Unit
Clock output limit, CMOS, Commercial
Clock output limit, CMOS, Industrial
200
166
400
MHz
MHz
MHz
–
–
Clock output limit, PECL, Commercial
(CY22394 only)
100
–
Clock output limit, PECL, Industrial
(CY22394 only)
125
–
375
MHz
t2
Output Duty Cycle[4, 7]
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2,
measured at VDD/2
45%
50%
55%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1,
measured at VDD/2
40%
50%
60%
t3
t4
t5
Rising Edge Slew Rate[4]
Falling Edge Slew Rate[4]
Output three-state Timing[4]
Output clock rise time, 20% to 80% of VDD 0.75
1.4
1.4
150
V/ns
V/ns
ns
Output clock fall time, 20% to 80% of VDD
0.75
–
Time for output to enter or leave three-state
mode after SHUTDOWN/OE switches
300
0.2
3
t6
v7
t8
t9
Clock Jitter[4, 8]
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–
–0.2
–
400
0
ps
V
P+/P– Crossing Point[4]
P+/P– Jitter[4, 8]
Lock Time[4]
Crossing point referenced to Vdd/2,
balanced resistor network (CY22394 only)
Peak-to-peak period jitter, P+/P– outputs
measured at crossing point (CY22394 only)
200
1.0
ps
ms
PLL Lock Time from Power up
–
2.5V Switching Characteristics (CY22395 only)[5]
Parameter
1/t1_2.5
Description
Output Frequency[4, 6]
Output Duty Cycle[4, 7]
Conditions
Min
Typ
Max Unit
Clock output limit, LVCMOS
133
MHz
t2_2.5
Duty cycle for outputs, defined as t2 ÷ t1
measured at LVDD/2
40%
50%
60%
t3_2.5
t4_2.5
Rising Edge Slew Rate[4]
Falling Edge Slew Rate[4]
Output clock rise time, 20% to 80% of LVDD
Output clock fall time, 20% to 80% of LVDD
0.5
0.5
1.0
1.0
V/ns
V/ns
Notes
6. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
7. Reference Output duty cycle depends on XTALIN duty cycle.
8. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
Document #: 38-07186 Rev. *E
Page 14 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Switching Waveforms
Figure 7. All Outputs, Duty Cycle and Rise and Fall Time
t
1
t
2
OUTPUT
t
3
t
4
Figure 8. Output Tri-state Timing
OE
t
5
t
5
ALL
TRI-STATE
OUTPUTS
Figure 9. CLK Output Jitter
t6
CLK
OUTPUT
Figure 10. P+/P– Crossing Point and Jitter
t8
P–
v7
V
/2
DD
P+
Figure 11. CPU Frequency Change
SELECT
CPU
OLD SELECT
NEW SELECT STABLE
t
9
F
new
F
old
Document #: 38-07186 Rev. *E
Page 15 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Test Circuit
Figure 12. Test Circuit
AV DD
0.1 μF
CLK out
CLOAD
VDD
P+/P- out
(L)V
DD
0.1 μF
GND
Document #: 38-07186 Rev. *E
Page 16 of 19
[+] Feedback
CY22393, CY223931, CY22394, CY22395
Ordering Information
Ordering Code
CY22393ZC-xxx[9]
CY22393ZC-xxxT[9]
CY22393FC[9]
CY22393FCT[9]
CY22394FC[9]
CY22394FCT[9]
CY22395FC[9]
CY3672-USB
Package Type
Product Flow
16-pin TSSOP
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
16-pin TSSOP
FTG Programmer
CY3698
CY22392F, CY22393F, CY22394F, and
CY22395F Adapter for CY3672-USB
Pb-Free
CY22393ZXC-xxx
CY22393ZXC-xxxT
CY22393ZXI-xxx
CY22393ZXI-xxxT
CY22393FXC
16-pin TSSOP
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
Commercial, 0 to 70°C
Commercial, 0 to 70°C
Industrial, –40 to 85°C
Industrial, –40 to 85°C
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22393FXCT
CY22393FXI
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22393FXIT
16-pin TSSOP - Tape and Reel
16-pin TSSOP with NiPdAu lead finish
16-pin TSSOP
CY223931FXI
CY22394ZXC-xxx
CY22394ZXC-xxxT
CY22394ZXI-xxx
CY22394ZXI-xxxT
CY22394FXC
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22394FXCT
CY22394FXI
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22394FXIT
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22395ZXC-xxx
CY22395ZXC-xxxT
CY22395ZXI-xxx
CY22395ZXI-xxxT
CY22395FXC
16-pin TSSOP - Tape and Reel
16-pin TSSOP
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22395FXCT
CY22395FXI
16-pin TSSOP - Tape and Reel
16-pin TSSOP
CY22395FXIT
16-pin TSSOP - Tape and Reel
Note
9. Not recommended for new designs.
Document #: 38-07186 Rev. *E
Page 17 of 19
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CY22393, CY223931, CY22394, CY22395
Package Diagram
Figure 13. 16-Pin TSSOP 4.40 MM Body Z16.173
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
MAX.
1
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05 gms
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
16
0.65[0.025]
BSC.
0.25[0.010]
BSC
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
GAUGE
PLANE
0°-8°
0.076[0.003]
0.50[0.020]
0.70[0.027]
0.05[0.002]
0.15[0.006]
0.85[0.033]
0.95[0.037]
0.09[[0.003]
0.20[0.008]
SEATING
PLANE
4.90[0.193]
5.10[0.200]
51-85091-*A
Document #: 38-07186 Rev. *E
Page 18 of 19
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CY22393, CY223931, CY22394, CY22395
Document History Page
Document Title: CY22393, CY223931, CY22394, CY22395 Three-PLL Serial-Programmable Flash-Programmable Clock
Generator
Document Number: 38-07186
Orig. of
Change
Submission
Date
REV.
ECN
Description of Change
**
111984
129388
237755
848580
DSG
RGL
RGL
RGL
12/09/01
10/13/03
See ECN
See ECN
10/10/08
Change from Spec number: 38-01144 to 38-07186
Added timing information
*A
*B
*C
*D
Added Lead-Free Devices
Added references to I2C; removed all references to SPI
2584052 AESA/KVM
Updated template. Added Note “Not recommended for new designs.”
Added part number CY22393FC, and CY22393FCT in Ordering
Information table. Removed part number CY22393FI, CY22393FIT,
CY22393ZI-XXX, CY22393ZI-XXXT, CY22393FC, CY22393FCT,
CY22392FI, CY22392FIT, CY22394ZC-XXX, CY22394ZC-XXXT,
CY22394ZI-XXX, CY22394ZI-XXXT, CY22394FI, CY22394FIT,
CY22395ZC-XXX, CY22395ZC-XXXT, CY22395ZI-XXX,
CY22395ZI-XXXT, CY22395FC, CY22395FCT, and CY22395FI in
Ordering Information table. Changed Lead-Free to Pb-Free.
Changed serial interface hold time (TDH) from 0ns to 100ns.
Replaced I2C references with “2-wire serial interface”
*E
2634202 KVM/AESA
01/09/09
Changed title to include CY223931. Added CY223931 to page 1 features
list. Added part number CY223931FXI. Added CY22393_I to the Selector
Guide (p.2), and changed the format of the part numbers. Added overbar
to SUSPEND in Pin Definitions table
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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psoc.cypress.com/precision-analog
psoc.cypress.com/lcd-drive
psoc.cypress.com/can
Clocks & Buffers
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© Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07186 Rev. *E
Revised January 9, 2009
Page 19 of 19
CyClocksRT is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
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