CY14MC256J [CYPRESS]
256-Kbit (32 K x 8) Serial (I2C) nvSRAM; 256千位（是32K ×8 ）串行（ I2C ）的nvSRAM
| 型号： | CY14MC256J |
| 厂家： | 
CYPRESS |
| 描述： | 256-Kbit (32 K x 8) Serial (I2C) nvSRAM |
| 文件： | 总30页 (文件大小：1168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY14MC256J
CY14MB256J
CY14ME256J
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
256-Kbit (32
K × 8) Serial (I2C) nvSRAM
■ Industry standard configurations
❐ Operating voltages:
Features
■ 256-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 32 K × 8
• CY14MC256J: VCC = 2.4 V to 2.6 V
• CY14MB256J: VCC = 2.7 V to 3.6 V
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (SoftwareSTORE) orHSBpin(HardwareSTORE)
• CY14ME256J: VCC = 4.5 V to 5.5 V
❐ Industrial temperature
❐ 8- and 16-pin small outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by I2C command (Software RECALL)
Overview
❐ Automatic STORE on power-down with a small capacitor
(except for CY14MX256J1)
The
Cypress
CY14MC256J/CY14MB256J/CY14ME256J
combines a 256-Kbit nvSRAM[2] with a nonvolatile element in
each memory cell. The memory is organized as 32 K words of
8 bits each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14MX256J1). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
■ High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years at 85 C
■ High speed I2C interface[1]
❐ Industry standard 100 kHz and 400 kHz speed
❐ Fast-mode Plus: 1 MHz speed
❐ High speed: 3.4 MHz
❐ Zero cycle delay reads and writes
■ Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software block protection for one quarter, half, or entire array
■ I2C access to special functions
❐ Nonvolatile STORE/RECALL
❐ 8 byte serial number
❐ Manufacturer ID and Product ID
❐ Sleep mode
Configuration
Feature
AutoStore
CY14MX256J1 CY14MX256J2 CY14MX256J3
No
Yes
Yes
Yes
Yes
Software
STORE
Yes
Hardware
STORE
No
No
Yes
■ Low power consumption
❐ Average active current of 1 mA at 3.4-MHz operation
❐ Average standby mode current of 150 µA
❐ Sleep mode current of 8 µA
Slave Address
pins
A2, A1, A0
A2, A1
A2, A1, A0
Logic Block Diagram
Serial Number
8 x 8
VCC VCAP
Manufacturer ID /
Product ID
Power Control
Memory Control Register
Command Register
Block
QuantumTrap
32 K x 8
Sleep
STORE
SRAM
32 K x 8
Control Registers Slave
Memory Slave
SDA
SCL
A2, A1, A0
WP
I2C Control Logic
Slave Address
Decoder
Memory
Address and Data
Control
RECALL
Notes
2
1. The I C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on chips
which support only one mode of operation. Refer to AN87209 for more details.
2
2. Serial (I C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation
Document Number: 001-65233 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 29, 2013
CY14MC256J
CY14MB256J
CY14ME256J
Contents
Pinouts ..............................................................................3
Pin Definitions ..................................................................3
I2C Interface ......................................................................4
Protocol Overview ............................................................4
I2C Protocol – Data Transfer .......................................4
Data Validity ................................................................5
START Condition (S) ...................................................5
STOP Condition (P) .....................................................5
Repeated START (Sr) .................................................5
Byte Format .................................................................5
Acknowledge / No-acknowledge .................................5
High Speed Mode (Hs-mode) ......................................6
Slave Device Address .................................................7
Write Protection (WP) ..................................................9
AutoStore Operation ....................................................9
Hardware STORE and HSB pin Operation .................9
Hardware RECALL (Power-Up) ..................................9
Write Operation .........................................................10
Read Operation .........................................................10
Memory Slave Access ...............................................10
Control Registers Slave .............................................14
Serial Number .................................................................16
Serial Number Write ..................................................16
Serial Number Lock ...................................................16
Serial Number Read ..................................................16
Device ID .........................................................................17
Executing Commands Using Command Register .....17
Maximum Ratings ...........................................................18
Operating Range .............................................................18
DC Electrical Characteristics ........................................18
Data Retention and Endurance .....................................19
Thermal Resistance ........................................................19
AC Test Loads and Waveforms .....................................20
AC Test Conditions ........................................................20
AC Switching Characteristics .......................................21
Switching Waveforms ....................................................21
nvSRAM Specifications .................................................22
Switching Waveforms ....................................................22
Software Controlled STORE/RECALL Cycles ..............23
Switching Waveforms ....................................................23
Hardware STORE Cycle .................................................24
Switching Waveforms ....................................................24
Ordering Information ......................................................25
Ordering Code Definitions .........................................25
Package Diagrams ..........................................................26
Acronyms ........................................................................28
Document Conventions .................................................28
Units of Measure .......................................................28
Document History Page .................................................29
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support .......................30
Products ....................................................................30
PSoC Solutions .........................................................30
Document Number: 001-65233 Rev. *G
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Pinouts
Figure 1. 8-pin SOIC pinout [3]
V
8
7
6
5
V
A0
A1
A2
8
7
6
5
1
2
3
V
CC
CAP
1
2
3
CC
WP
A1
CY14MX256J1
Top View
not to scale
WP
CY14MX256J2
Top View
not to scale
SCL
SDA
A2
SCL
SDA
V
V
4
4
SS
SS
Figure 2. 16-pin SOIC pinout
V
16
15
14
13
12
NC
NC
NC
NC
1
2
CC
NC
V
3
4
5
6
7
8
CAP
CY14MX256J3
Top View
A2
not to scale
SDA
SCL
A1
WP
A0
11
10
NC
SS
V
9
HSB
Pin Definitions
Pin Name
SCL
I/O Type
Description
Clock. Runs at speeds up to a maximum of fSCL
Input
.
SDA
Input/Output I/O. Input/Output of data through I2C interface.
Output: Is open-drain and requires an external pull-up resistor.
WP
A2–A0 [3]
HSB
Input
Write Protect. Protects the memory from all writes. This pin is internally pulled LOW and hence can be
left open if not connected.
Slave Address. Defines the slave address for I2C. This pin is internally pulled LOW and hence can be
left open if not connected.
Input
Input/Output Hardware STORE Busy
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a
weak internal pull-up resistor keeps this pin HIGH (External pull up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If not required, AutoStore must be disabled and this pin left as no connect. It
must never be connected to ground.
NC
VSS
VCC
No connect No connect. This pin is not connected to the die.
Power supply Ground.
Power supply Power supply.
Note
3. A0 pin is not available in CY14MX256J2.
Document Number: 001-65233 Rev. *G
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CY14MB256J
CY14ME256J
2
bit slave address and eighth bit (R/W) indicating a read (1) or a
write (0) operation. All signals are transmitted on the open-drain
SDA line and are synchronized with the clock on SCL line. Each
byte of data transmitted on the I2C bus is acknowledged by the
receiver by holding the SDA line LOW on the ninth clock pulse.
The request for write by the master is followed by the memory
address and data bytes on the SDA line. The writes can be
performed in burst-mode by sending multiple bytes of data. The
memory address increments automatically after receiving
/transmitting of each byte on the falling edge of 9th clock cycle.
The new address is latched just prior to sending/receiving the
acknowledgment bit. This allows the next sequential byte to be
accessed with no additional addressing. On reaching the last
memory location, the address rolls back to 0x0000 and writes
continue. The slave responds to each byte sent by the master
during a write operation with an ACK. A write sequence can be
terminated by the master generating a STOP or Repeated
START condition.
I C Interface
I2C bus consists of two lines – serial clock line (SCL) and serial
data line (SDA) that carry information between multiple devices
on the bus. I2C supports multi-master and multi-slave
configurations. The data is transmitted from the transmitter to the
receiver on the SDA line and is synchronized with the clock SCL
generated by the master.
The SCL and SDA lines are open-drain lines and are pulled up
to VCC using resistors. The choice of pull-up resistor on the
system depends on the bus capacitance and the intended speed
of operation. The master generates the clock and all the data
I/Os are transmitted in synchronization with this clock. The
CY14MX256J supports up to 3.4 MHz clock speed on SCL line.
Protocol Overview
This device supports only a 7-bit addressable scheme. The
master generates
a
START condition to initiate the
A read request is performed at the current address location
(address next to the last location accessed for read or write). The
memory slave device responds to a read request by transmitting
the data on the current address location to the master. A random
address read may also be performed by first sending a write
request with the intended address of read. The master must
abort the write immediately after the last address byte and issue
a Repeated START or STOP signal to prevent any write
operation. The following read operation starts from this address.
The master acknowledges the receipt of one byte of data by
holding the SDA pin LOW for the ninth clock pulse. The reads
can be terminated by the master sending a no-acknowledge
(NACK) signal on the SDA line after the last data byte. The
no-acknowledge signal causes the CY14MX256J to release the
SDA line and the master can then generate a STOP or a
Repeated START condition to initiate a new operation.
communication followed by broadcasting a slave select byte.
The slave select byte consists of a seven bit address of the slave
that the master intends to communicate with and R/W bit
indicating a read or a write operation. The selected slave
responds to this with an acknowledgement (ACK). After a slave
is selected, the remaining part of the communication takes place
between the master and the selected slave device. The other
devices on the bus ignore the signals on the SDA line till a STOP
or Repeated START condition is detected. The data transfer is
done between the master and the selected slave device through
the SDA pin synchronized with the SCL clock generated by the
master.
2
I C Protocol – Data Transfer
Each transaction in I2C protocol starts with the master
generating a START condition on the bus, followed by a seven
Figure 3. System Configuration using Serial (I2C) nvSRAM
Vcc
R
R
= (V - V max) / I
CC OL OL
Pmin
= t / (0.8473 * C )
Pmax
r
b
SDA
SCL
Microcontroller
Vcc
Vcc
A0
SCL
SDA
A0
A1
SCL
A0
A1
A2
SCL
SDA
A1
A2
SDA
WP
A2
WP
WP
CY14MX256J
#1
CY14MX256J
#0
CY14MX256J
#7
Document Number: 001-65233 Rev. *G
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Data Validity
STOP Condition (P)
The data on the SDA line must be stable during the HIGH period
of the clock. The state of the data line can only change when the
clock on the SCL line is LOW for the data to be valid. There are
only two conditions under which the SDA line may change state
with SCL line held HIGH, that is, START and STOP condition.
The START and STOP conditions are generated by the master
to signal the beginning and end of a communication sequence
on the I2C bus.
A LOW to HIGH transition on the SDA line while SCL is HIGH
indicates a STOP condition. This condition indicates the end of
the ongoing transaction.
START and STOP conditions are always generated by the
master. The bus is considered to be busy after the START
condition. The bus is considered to be free again after the STOP
condition.
Repeated START (Sr)
START Condition (S)
If an Repeated START condition is generated instead of a STOP
condition the bus continues to be busy. The ongoing transaction
on the I2C lines is stopped and the bus waits for the master to
send a slave ID for communication to restart.
A HIGH to LOW transition on the SDA line while SCL is HIGH
indicates a START condition. Every transaction in I2C begins
with the master generating a START condition.
Figure 4. START and STOP Conditions
SDA
SCL
SDA
SCL
S
P
STOP Condition
START Condition
Figure 5. Data Transfer on the I2C Bus
handbook, full pagewidth
P
SDA
Sr
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
MSB
S
Sr
or
P
SCL
1
2
7
8
9
ACK
1
2
3 - 8
9
or
Sr
ACK
START or
STOP or
Repeated START
condition
Repeated START
condition
Byte complete,
interrupt within slave
Clock line held LOW while
interrupts are serviced
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
Byte Format
Each operation in I2C is done using 8 bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
■ The master did not receive valid data due to noise.
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
■ The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
Acknowledge / No-acknowledge
NACK can be generated by nvSRAM slave during a WRITE
operation in following cases:
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data
transferred on the I2C bus needs to be responded with an ACK
signal by the receiver to continue the operation. Failing to do so
is considered as a NACK state. NACK is the state where receiver
■ nvSRAM did not receive valid data due to noise.
■ The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Document Number: 001-65233 Rev. *G
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Figure 6. Acknowledge on the I2C Bus
DATA OUTPUT
BY MASTER
not acknowledge (A)
DATA OUTPUT
BY SLAVE
acknowledge (A)
8
SCL FROM
MASTER
1
2
9
S
clock pulse for
START
acknowledgement
condition
Serial Data Format in Hs-mode
High Speed Mode (Hs-mode)
Serial data transfer format in Hs-mode meets the standard-mode
I2C-bus specification. Hs-mode can only commence after the
following conditions (all of which are in F/S-modes):
In Hs-mode, nvSRAM can transfer data at bit rates of up to
3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place
the device into high speed mode. This enables master slave
communication for speed upto 3.4 MHz. A stop condition exits
Hs-mode.
1. START condition (S)
2. 8-bit master code (0000 1XXXb)
3. No-acknowledge bit (A)
Figure 7. Data transfer format in Hs-mode
Hs-mode
F/S-mode
F/S-mode
S
P
A/A
MASTER CODE
A
Sr SLAVE ADD. R/W
A
DATA
n (bytes+ack.)
Hs-mode continues
SLAVE ADD.
Sr
Single and multiple-byte reads and writes are supported. After
the device enters into Hs-mode, data transfer continues in
Hs-mode until stop condition is sent by master device. The slave
switches back to F/S-mode after a STOP condition (P). To
continue data transfer in Hs-mode, the master sends Repeated
START (Sr).
See Figure 13 on page 11 and Figure 16 on page 12 for Hs-mode
timings for read and write operation.
Document Number: 001-65233 Rev. *G
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address field for accessing Memory and Control Registers. The
accessing mechanism is described in Memory Slave Device.
Slave Device Address
Every slave device on an I2C bus has a device select address.
The first byte after START condition contains the slave device
address with which the master intends to communicate. The
seven MSBs are the device address and the LSB (R/W bit) is
used for indicating Read or Write operation. The CY14MX256J
reserves two sets of upper four MSBs [7:4] in the slave device
The nvSRAM product provides two different functionalities:
Memory and Control Registers functions (such as serial number
and product ID). The two functions of the device are accessed
through different slave device addresses. The first four most
significant bits [7:4] in the device address register are used to
select between the nvSRAM functions.
Table 1. Slave device Addressing
nvSRAM
Function Select
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
CY14MX256J Slave Devices
1
0
0
0
1
1
0
1
Device Select ID
R/W Selects Memory
Memory, 32 K × 8
Control Registers
- Memory Control Register, 1 × 8
- Serial Number, 8 × 8
- Device ID, 4 × 8
Selects Control
Registers
Device Select ID
R/W
- Command Register, 1 × 8
Memory Slave Device
Control Registers Slave Device
The nvSRAM device is selected for Read/Write if the master
issues the slave address as 1010b followed by two/three bits of
device select. For CY14MX256J1/J3, the device select is three
bits and for CY14MX256J2, it is two bits with the third bit don’t
care. If the slave address sent by the master matches with the
Memory Slave device address then depending on the R/W bit of
the slave address, data is either read from (R/W = ‘1’) or written
to (R/W = ‘0’) the nvSRAM.
The Control Registers Slave device includes the Serial Number,
Product ID, Memory Control, and Command Register.
The nvSRAM Control Register Slave device is selected for
Read/Write if the master issues the Slave address as 0011b
followed by two/three bits of device select. For
CY14MX256J1/J3 device select is three bits and for
CY14MX256J2 it is two bits with third bit don’t care. If the slave
address sent by the master matches with the Memory Slave
device address, then depending on the R/W bit of the slave
address, data is either read from (R/W = ‘1’) or written to
(R/W = ‘0’) the nvSRAM.
The address length for CY14MX256J is 15 bits and thus it
requires two address bytes to map the entire memory address
location. The dedicated two address bytes represent bit A0 to
A14. However, since the address is only 15-bits, it implies that
the first MSB bit that is fed in is ignored by the device. Although
this bit is ‘don’t care’, Cypress recommends that this bit is treated
as 0 to enable seamless transition to higher memory densities.
Figure 9. Control Registers Slave Device Address
handbook, halfpMagSe B
LSB
R/W
0
0
1
1
A2 A1 A0/X
Figure 8. Memory Slave Device Address
Device Select
Slave ID
handbook, halfpMagSe B
LSB
1
0
1
A2 A1
A0/X R/W
0
Device Select
Slave ID
Document Number: 001-65233 Rev. *G
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performed, the serial number lock bit will not survive the power
cycle. The default value shipped from the factory for SNL is ‘0’.
Table 2. Control Registers map
Address Description Read/Write
Details
Command Register
0x00
Memory
Control
Register
Read/Write Contains
Block
The Command Register resides at address “AA” of the Control
Registers Slave device. This is a write only register. The byte
written to this register initiates a STORE, RECALL, AutoStore
Enable, AutoStore Disable and sleep mode operation as listed in
Table 5. Refer to Serial Number on page 16 for details on how to
execute a command register byte.
Protect Bits and Serial
Number Lock bit
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0xAA
Serial Number Read/Write Programmable Serial
8 Bytes
(Read only Number. Locked by
when SNL setting the Serial
is set)
Number lock bit in
Table 5. Command Register bytes
Memory
Control
Register to ‘1’.
Data Byte
Command
Description
[7:0]
0011 1100
STORE
STORE SRAM data to nonvolatile
memory
0110 0000
RECALL RECALL data from nonvolatile
memory to SRAM
Device ID
Reserved
Read only Device ID is factory
programmed
0101 1001
0001 1001
1011 1001
ASENB
ASDISB
SLEEP
Enable AutoStore
Disable AutoStore
Enter Sleep Mode for low power
consumption
Reserved Reserved
Command
Register
Write only Allows commands for
■ STORE: Initiates nvSRAM Software STORE. The nvSRAM
cannot be accessed for tSTORE time after this instruction has
been executed. When initiated, the device performs a STORE
operation regardless of whether a write has been performed
since the last NV operation. After the tSTORE cycle time is
completed, the SRAM is activated again for read and write
operations.
STORE,
RECALL,
AutoStore
Enable/Disable,
SLEEP Mode
Memory Control Register
The Memory Control Register contains the following bits:
Table 3. Memory Control Register Bits
■ RECALL: Initiates nvSRAM Software RECALL. The nvSRAM
cannot be accessed for tRECALL time after this instruction has
been executed. The RECALL operation does not alter the data
in the nonvolatile elements. A RECALL may be initiated in two
ways: Hardware RECALL, initiated on power-up; and Software
RECALL, initiated by a I2C RECALL instruction.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
SNL
(0)
0
0
BP1
(0)
BP0
(0)
0
0
■ ASENB: Enables nvSRAM AutoStore. The nvSRAM cannot be
accessed for tSS time after this instruction has been executed.
This setting is not nonvolatile and needs to be followed by a
manual STORE sequence if this is desired to survive power
cycle. The part comes from the factory with AutoStore Enabled
and 0x00 written in all cells.
■ BP1:BP0: Block Protect bits are used to protect one-quarter,
one-half, orfullmemoryarray. Thesebitscanbewrittenthrough
a write instruction to the 0x00 location of the Control Register
Slave device. However, any STORE cycle causes transfer of
SRAM data into a nonvolatile cell regardless of whether or not
the block is protected. The default value shipped from the
factory for BP0 and BP1 is ‘0’.
■ ASDISB: Disables nvSRAM AutoStore. The nvSRAM cannot
be accessed for tSS time after this instruction has been
executed. This setting is not nonvolatile and needs to be
followed by a manual STORE sequence if this is desired to
survive power cycle.
Table 4. Block Protection
Level
0
BP1:BP0
Block Protection
00
01
10
11
None
Note If AutoStore is disabled and VCAP is not required, it is
required that the VCAP pin is left open. VCAP pin must never be
connected to ground. Power-Up RECALL operation cannot be
disabled in any case.
1/4
1/2
1
0x6000–0x7FFF
0x4000–0x7FFF
0x0000–0x7FFF
■ SLEEP: SLEEP instruction puts the nvSRAM in a sleep mode.
When the SLEEP instruction is registered, the nvSRAM takes
tSS time to process the SLEEP request. Once the SLEEP
command is successfully registered and processed, the
nvSRAM toggles HSB LOW, performs a STORE operation to
secure the data to nonvolatile memory and then enters into
SLEEP mode. Whenever nvSRAM enters into sleep mode, it
initiates non volatile STORE cycle which results in losing an
SNL (S/N Lock) Bit: Serial Number Lock bit (SNL) is used to lock
the serial number. Once the bit is set to ‘1’, the serial number
registers are locked and no modification is allowed. This bit
cannot be cleared to ‘0’. The serial number is secured on the next
STORE operation (Software STORE or AutoStore). If AutoStore
is not enabled, user must perform the Software STORE
operation to secure the lock bit status. If a STORE was not
Document Number: 001-65233 Rev. *G
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endurance cycle per sleep command execution. A STORE
cycle starts only if a write to the SRAM has been performed
since the last STORE or RECALL cycle.
Store. This will corrupt the data stored in nvSRAM as well as the
serial number and it will unlock the SNL bit.
Figure 10 shows the proper connection of the storage capacitor
The nvSRAM enters into sleep mode as follows:
1. The Master sends a START command
(VCAP
) for AutoStore operation. Refer to DC Electrical
Characteristics on page 18 for the size of the VCAP
.
2. The Master sends Control Registers Slave device ID with I2C
Write bit set (R/W = ’0’)
Figure 10. AutoStore Mode
VCC
3. The Slave (nvSRAM) sends an ACK back to the Master
4. The Master sends Command Register address (0xAA)
5. The Slave (nvSRAM) sends an ACK back to the Master
0.1 uF
VCC
6. The Master sends Command Register byte for entering into
Sleep mode
7. The Slave (nvSRAM) sends an ACK back to the Master
8. The Master generates a STOP condition.
VCAP
Once in Sleep mode the device starts consuming IZZ current,
tSLEEP time after SLEEP instruction is registered. The device is
not accessible for normal operations until it is out of sleep mode.
The nvSRAM wakes up after tWAKE duration after the device
slave address is transmitted by the master.
VCAP
VSS
Transmitting any of the two slave addresses wakes the nvSRAM
from Sleep mode. The nvSRAM device is not accessible during
tSLEEP and tWAKE interval, and any attempt to access the
nvSRAM device by the master is ignored and nvSRAM sends
NACK to the master. As an alternative method of determining
when the device is ready, the master can send read or write
commands and look for an ACK.
Hardware STORE and HSB pin Operation
The HSB pin in CY14MX256J is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, the device conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for tSTORE duration or as long
as HSB pin is LOW.
Write Protection (WP)
The WP pin is an active high pin and protects entire memory and
all registers from write operations. To inhibit all the write
operations, this pin must be held high. When this pin is high, all
memory and register writes are prohibited and address counter
is not incremented. This pin is internally pulled LOW and hence
can be left open if not used.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
AutoStore Operation
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
STORE or RECALL.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB pin unconnected if not used.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in Command Register on page 8. If AutoStore is
enabled without a capacitor on VCAP pin, the device attempts an
AutoStore operation without sufficient charge to complete the
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the Ready status of the device.
Document Number: 001-65233 Rev. *G
Page 9 of 30
CY14MC256J
CY14MB256J
CY14ME256J
immediately after the slave device address byte is sent out by
the master. The read operation starts from the current address
location (the location following the previous successful write or
read operation). When the last address is reached, the address
counter loops back to the first address.
Write Operation
The last bit of the slave device address indicates a read or a write
operation. In case of a write operation, the slave device address
is followed by the memory or register address and data. A write
operation continues as long as a STOP or Repeated START
condition is generated by the master or if a NACK is issued by
the nvSRAM.
In case of the Control Register Slave, whenever a burst read is
performed such that it flows to a non-existent address, the reads
operation will loop back to 0x00. This is applicable, in particular
for the Command Register.
A NACK is issued from the nvSRAM under the following
conditions:
There are the following ways to end a read operation:
1. A valid Device ID is not received.
1. The Master issues a NACK on the 9th clock cycle followed by
a STOP or a Repeated START condition on the 10th clock
cycle.
2. A write (burst write) access to a protected memory block
address returns a NACK from nvSRAM after the data byte is
received. However, the address counter is set to this address
and the following current read operation starts from this
address.
2. Master generates a STOP or Repeated START condition on
the 9th clock cycle.
3. A write/random read access to an invalid or out-of-bound
memory address returns a NACK from the nvSRAM after the
address is received. The address counter remains unchanged
in such a case.
More details on write instruction are provided in Section Memory
Slave Access.
Memory Slave Access
The following sections describe the data transfer sequence
required to perform Read or Write operations from nvSRAM.
After a NACK is sent out from the nvSRAM, the write operation
is terminated and any data on the SDA line is ignored till a STOP
or a Repeated START condition is generated by the master.
Write nvSRAM
For example, consider a case where the burst write access is
performed on Control Register Slave address 0x01 for writing the
serial number and continued to the address 0x09, which is a read
only register. The device returns a NACK and address counter
will not be incremented. A following read operation will be started
from the address 0x09. Further, any write operation which starts
from a write protected address (say, 0x09) will be responded by
the nvSRAM with a NACK after the data byte is sent and set the
address counter to this address. A following read operation will
start from the address 0x09 in this case also.
Each write operation consists of a slave address being
transmitted after the start condition. The last bit of slave address
must be set as ‘0’ to indicate a Write operation. The master may
write one byte of data or continue writing multiple consecutive
address locations while the internal address counter keeps
incrementing automatically. The address register is reset to
0x0000 after the last address in memory is accessed. The write
operation continues till a STOP or Repeated START condition is
generated by the master or a NACK is issued by the nvSRAM.
A write operation is executed only after all the 8 data bits have
been received by the nvSRAM. The nvSRAM sends an ACK
signal after a successful write operation. A write operation may
be terminated by the master by generating a STOP condition or
a Repeated START operation. If the master desires to abort the
current write operation without altering the memory contents, this
should be done using a START/STOP condition prior to the 8th
data bit.
Note In case the user tries to read/write access an address that
does not exist (for example 0x0D in Control Register Slave),
nvSRAM responds with
a NACK immediately after the
out-of-bound address is transmitted. The address counter
remains unchanged and holds the previous successful read or
write operation address.
A write operation is performed internally with no delay after the
eighth bit of data is transmitted. If a write operation is not
intended, the master must terminate the write operation before
the eighth clock cycle by generating a STOP or Repeated
START condition.
If the master tries to access a write protected memory address
on the nvSRAM, a NACK is returned after the data byte intended
to write the protected address is transmitted and address counter
will not be incremented. Similarly, in a burst mode write
operation, a NACK is returned when the data byte that attempts
to write a protected memory location and address counter will not
be incremented.
More details on write instruction are provided in Section Memory
Slave Access.
Read Operation
If the last bit of the slave device address is ‘1’, a read operation
is assumed and the nvSRAM takes control of the SDA line
Document Number: 001-65233 Rev. *G
Page 10 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Figure 11. Single-Byte Write into nvSRAM (except Hs-mode)
S
T
A
R
T
S
T
By Master
SDA Line
By nvSRAM
Memory Slave Address
Most Significant Address Byte
Least Significant Address Byte
Data Byte
0
P
P
1
A2 A1
A0
S
1
0
0
0
X
A
A
A
A
Figure 12. Multi-Byte Write into nvSRAM (except Hs-mode)
S
T
A
R
T
S
T
Least Significant Address
Byte
Most Significant Address
Byte
0
By Master
Memory Slave Address
Data Byte 1
Data Byte N
P
P
SDA Line
1
A2 A1 A0
S
1
0
0
0
X
By nvSRAM
A
A
A
A
A
Figure 13. Single-Byte Write into nvSRAM (Hs-mode)
S
T
A
R
T
S
T
Most Significant Address
Byte
Least Significant Address
Byte
By Master
0
Hs-mode command
Memory Slave Address
A2 A1 A0
Data Byte
P
SDA Line
P
0
1
X
X
X
1
Sr
0
1 0
S
0
0
0
0
X
By nvSRAM
A
A
A
A
A
Figure 14. Multi-Byte Write into nvSRAM (Hs-mode)
S
T
A
R
T
Most Significant Address
Byte
Least Significant Address
Byte
By Master
Hs-mode command
Memory Slave Address
Data Byte 1
0
1
X
X
X
1
0
1 0
A2 A1
A0
X
S
0
0
0
Sr
0
SDA Line
By nvSRAM
A
A
A
A
A
S
T
0
Data Byte N
Data Byte 3
Data Byte 2
By Master
P
SDA Line
P
By nvSRAM
A
A
A
Document Number: 001-65233 Rev. *G
Page 11 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Current nvSRAM Read
terminate a read operation after reading 1 byte or continue
reading addresses sequentially till the last address in the
memory after which the address counter rolls back to the
address 0x0000. The valid methods of terminating read access
are described in Section Read Operation on page 10.
Each read operation starts with the master transmitting the
nvSRAM slave address with the LSB set to ‘1’ to indicate “Read”.
The reads start from the address on the address counter. The
address counter is set to the address location next to the last
accessed with a “Write” or “Read” operation. The master may
Figure 15. Current Location Single-Byte nvSRAM Read (except Hs-mode)
S
T
A
R
T
S
T
0
P
A
Memory Slave Address
By Master
P
SDA Line
1
A2 A1
A0
S
1
0
0
1
By nvSRAM
Data Byte
A
Figure 16. Current Location Multi-Byte nvSRAM Read (except Hs-mode)
S
T
A
R
T
S
T
0
A
A
Memory Slave Address
By Master
SDA Line
By nvSRAM
P
P
1
A2 A1 A0
1
S
1
0
0
Data Byte N
Data Byte
A
Figure 17. Current Location Single-Byte nvSRAM Read (Hs-mode)
S
T
A
R
T
S
T
A
By Master
0
P
Hs-mode command
Memory Slave Address
SDA Line
1
1 0 A2 A1 A0
P
0
1
X
X
X
1
Sr
0
S
0
0
0
By nvSRAM
Data Byte
A
A
Figure 18. Current Location Multi-Byte nvSRAM Read (Hs-mode)
S
T
A
R
T
S
T
0
A
A
By Master
Hs-mode command
Memory Slave Address
P
1
1 0 A2 A1 A0
P
SDA Line
0
1
X
X
X
1
Sr
0
S
0
0
0
Data Byte N
Data Byte
By nvSRAM
A
A
Document Number: 001-65233 Rev. *G
Page 12 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Random Address Read
initiate read operation from here. The master may terminate a
read operation after reading 1 byte or continue reading
addresses sequentially till the last address in the memory after
which the address counter rolls back to the start address 0x0000.
A random address read is performed by first initiating a write
operation and generating a Repeated START immediately after
the last address byte is acknowledged. The address counter is
set to this address and the next read access to this slave will
Figure 19. Random Address Single-Byte Read (except Hs-mode)
S
T
A
R
T
S
T
0
P
A
Most Significant Address
Byte
Least Significant Address
Byte
By Master
Memory Slave Address
Memory Slave Address
P
SDA Line
1
A2 A1
Sr
0
1
A2 A1 A0
1
S
1
0
0
A0
X
1
0
0
By nvSRAM
Data Byte
A
A
A
A
Figure 20. Random Address Multi-Byte Read (except Hs-mode)
S
T
A
R
T
Least Significant Address
Byte
Most Significant Address
Byte
A
By Master
Memory Slave Address
Memory Slave Address
1
A2 A1
Sr
0
1
A2 A1 A0
1
A0
X
S
1
0
0
1
0
0
SDA Line
By nvSRAM
Data Byte 1
A
A
A
A
S
T
0
A
P
P
Data Byte N
Figure 21. Random Address Single-Byte Read (Hs-mode)
S
T
A
R
T
Most Significant Address
Byte
Least Significant Address
Byte
By Master
Hs-mode command
Memory Slave Address
Memory Slave Address
1
1 0 A2 A1 A0
0
1
Sr
0
SDA Line
0
1
X
X
X
1
0
1
0
A2 A1 A0
X
S
0
0
0
Sr
A
By nvSRAM
A
A
A
A
A
S
T
0
P
P
Data Byte
Document Number: 001-65233 Rev. *G
Page 13 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Figure 22. Random Address Multi-Byte Read (Hs-mode)
S
T
A
R
T
Most ignificant Address
Byte
Least Significant Address
Byte
By Master
Hs-mode command
Memory Slave Address
A2 A1 A0
0
Memory Slave Address
SDA Line
1
1 0 A2 A1 A0
1
Sr
0
0
1
X
X
X
1
0
1
0
S
0
0
0
Sr
X
By nvSRAM
A
A
A
A
A
S
T
0
A
A
P
P
Data Byte
Data Byte N
first address (0x00) as in this case, the current address is an
out-of-bound address. The address is not incremented and the
next current read operation begins from this address location. If
a write operation is attempted on an out-of-bound address
location, the nvSRAM sends a NACK immediately after the
address byte is sent.
Control Registers Slave
The following sections describes the data transfer sequence
required to perform Read or Write operations from Control
Registers Slave.
Write Control Registers
Further, if the serial number is locked, only two addresses (0xAA
or Command Register, and 0x00 or Memory Control Register)
are writable in the Control Registers Slave. On a write operation
to any other address location, the device will acknowledge
command byte and address bytes but it returns a NACK from the
Control Registers Slave for data bytes. In this case, the address
will not be incremented and a current read will happen from the
last acknowledged address.
To write the Control Registers Slave, the master transmits the
Control Registers Slave address after generating the START
condition. The write sequence continues from the address
location specified by the master till the master generates a STOP
condition or the last writable address location.
If a non writable address location is accessed for write operation
during a normal write or a burst, the slave generates a NACK
after the data byte is sent and the write sequence terminates.
Any following data bytes are ignored and the address counter is
not incremented.
The nvSRAM Control Registers Slave sends a NACK when an
out of bound memory address is accessed for write operation, by
the master. In such a case, a following current read operation
begins from the last acknowledged address.
If a write operation is performed on the Command Register
(0xAA), the following current read operation also begins from the
Figure 23. Single-Byte Write into Control Registers
S
T
A
R
T
S
T
Control Registers
Slave Address
Control Register Address
Data Byte
By Master
0
P
P
1
A2 A1 A0
0
SDA Line
S
0
0
1
By nvSRAM
A
A
A
Figure 24. Multi-Byte Write into Control Registers
S
T
A
R
T
S
T
0
Control Registers
Slave Address
Control Register Address
Data Byte
Data Byte N
By Master
P
P
1
A2 A1 A0
0
SDA Line
S
0
0
1
By nvSRAM
A
A
A
A
Document Number: 001-65233 Rev. *G
Page 14 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Current Control Registers Read
address location and loops back to the first location (0x00). Note
that the Command Register is a write only register and is not
accessible through the sequential read operations. If a burst read
operation begins from the Command Register (0xAA), the
address counter wraps around to the first address in the register
map (0x00).
A read of Control Registers Slave is started with master sending
the Control Registers Slave address after the START condition
with the LSB set to ‘1’. The reads begin from the current address
which is the next address to the last accessed location. The
reads to Control Registers Slave continues till the last readable
Figure 25. Control Registers Single-Byte Read
S
T
A
R
T
S
Control Registers
Slave Address
T
A
By Master
0
P
P
SDA Line
1
A2 A1
A0
S
0
0
1
1
By nvSRAM
Data Byte
A
Figure 26. Current Control Registers Multi-Byte Read
S
T
A
R
T
S
T
0
Control Registers
Slave Address
A
A
By Master
P
P
1
A2 A1 A0
1
SDA Line
S
0
0
1
By nvSRAM
Data Byte
Data Byte N
A
Random Control Registers Read
Command Register is a write only register and is not accessible
through the sequential read operations. A random read starting
at the Command Register (0xAA) loops back to the first address
in the Control Registers map (0x00). If a random read operation
is initiated from an out-of-bound memory address, the nvSRAM
sends a NACK after the address byte is sent.
A read of random address may be performed by initiating a write
operation to the intended location of read and immediately
following with a Repeated START operation. The reads to
Control Registers Slave continues till the last readable address
location and loops back to the first location (0x00). Note that the
.
Figure 27. Random Control Registers Single-Byte Read
S
T
A
R
T
S
T
Control Registers
Slave Address
A
Control Register Address
Control Registers Slave Address
By Master
0
P
Sr
0
1
A2
A0
1
P
1
A1
SDA Line
0
1
A2 A1
A0
S
0
0
1
0
By nvSRAM
Data Byte
A
A
A
Document Number: 001-65233 Rev. *G
Page 15 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Figure 28. Random Control Registers Multi-Byte Read
S
T
A
R
T
Control Registers
Slave Address
A
Control Register Address
Control Registers Slave Address
By Master
Sr
1
A2
A1 A0
0
1
1
0
1
A2 A1
A0
SDA Line
S
0
0
1
0
By nvSRAM
Data Byte
A
A
A
S
T
0
A
P
P
Data Byte N
when the lock bit is set, a NACK is returned and write will not be
performed.
Serial Number
Serial number is an 8 byte memory space provided to the user
to uniquely identify this device. It typically consists of a two byte
customer ID, followed by five bytes of unique serial number and
one byte of CRC check. However, nvSRAM does not calculate
the CRC and it is up to the user to utilize the eight byte memory
space in the desired format. The default values for the eight byte
locations are set to ‘0x00’.
Serial Number Lock
After writes to Serial Number registers is complete, master is
responsible for locking the serial number by setting the serial
number lock bit to ‘1’ in the Memory Control Register (0x00). The
content of Memory Control Register and serial number are
secured on the next STORE operation (STORE or AutoStore). If
AutoStore is not enabled, user must perform STORE operation
to secure the lock bit status.
Serial Number Write
The serial number can be accessed through the Control
Registers Slave Device. To write the serial number, master
transmits the Control Registers Slave address after the START
condition and writes to the address location from 0x01 to 0x08.
The content of Serial Number registers is secured to nonvolatile
memory on the next STORE operation. If AutoStore is enabled,
nvSRAM automatically stores the Serial number in the
nonvolatile memory on power-down. However, if AutoStore is
disabled, user must perform a STORE operation to secure the
contents of Serial Number registers.
If a STORE was not performed, the serial number lock bit will not
survive power cycle. The serial number lock bit and 8 - byte serial
number is defaults to ‘0’ at power-up.
Serial Number Read
Serial number can be read back by a read operation of the
intended address of the Control Registers Slave. The Control
Registers Device loops back from the last address (excluding the
Command Register) to 0x00 address location while performing
burst read operation. The serial number resides in the locations
from 0x01 to 0x08. Even if the serial number is not locked, a
serial number read operation will return the current values written
to the serial number registers. Master may perform a serial
number read operation to confirm if the correct serial number is
written to the registers before setting the lock bit.
Note If the serial number lock (SNL) bit is not set, the serial
number registers can be re-written regardless of whether or not
a STORE has happened. Once the serial number lock bit is set,
no writes to the serial number registers are allowed. If the master
tries to perform a write operation to the serial number registers
Document Number: 001-65233 Rev. *G
Page 16 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Device ID
Device ID is a 4 byte code consisting of JEDEC assigned manufacturer ID, product ID, density ID, and die revision. These registers
are set in the factory and are read only registers for the user.
Table 6. Device ID
Device ID Description
Device ID
(4 bytes)
31–21
(11 bits)
20–7
(14 bits)
6–3
(4 bits)
2–0
(3 bits)
Device
Manufacture ID
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
00000110100
Product ID
Density ID
0010
Die Rev
000
CY14MC256J1
CY14MC256J2
CY14MC256J3
CY14MB256J1
CY14MB256J2
CY14MB256J3
CY14ME256J1
CY14ME256J2
CY14ME256J3
0x06812090
0x0681A090
0x0681A290
0x06812890
0x0681A890
0x0681AA90
0x06813090
0x0681B090
0x0681B290
00001001000001
00001101000001
00001101000101
00001001010001
00001101010001
00001101010101
00001001100001
00001101100001
00001101100101
0010
000
0010
000
0010
000
0010
000
0010
000
0010
000
0010
000
0010
000
The device ID is divided into four parts as shown in Table 6:
1. Manufacturer ID (11 bits)
4. Die Rev (3 bits)
This is used to represent any major change in the design of the
product. The initial setting of this is always 0x0.
This is the JEDEC assigned manufacturer ID for Cypress.
JEDEC assigns the manufacturer ID in different banks. The first
three bits of the manufacturer ID represent the bank in which ID
is assigned. The next eight bits represent the manufacturer ID.
Executing Commands Using Command Register
The Control Registers Slave allows different commands to be
executed by writing the specific command byte in the Command
Register (0xAA). The command byte codes for each command
are specified in Table 5 on page 8. During the execution of these
commands the device is not accessible and returns a NACK if
any of the three slave devices is selected. If an invalid command
is sent by the master, the nvSRAM responds with an ACK
indicating that the command has been acknowledged with NOP
(No Operation). The address will rollover to 0x00 location.
Cypress manufacturer ID is 0x34 in bank 0. Therefore the
manufacturer ID for all Cypress nvSRAM products is given as:
Cypress ID - 000_0011_0100
2. Product ID (14 bits)
The product ID for device is shown in the Table 6.
3. Density ID (4 bits)
The 4 bit density ID is used as shown in Table 6 for indicating the
256 Kb density of the product.
Figure 29. Command Execution using Command Register
S
T
A
R
T
S
T
O
P
Control Register
Slave Address
Command Register Address
Command Byte
By Master
SDA Line
1
A2 A1
A0
S
0
0
1
P
0
1
1
0
1
0
1
0
0
By nvSRAM
A
A
A
Document Number: 001-65233 Rev. *G
Page 17 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Storage temperature ................................ –65 C to +150 C
Maximum accumulated storage time
Surface mount lead soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration). .... 15 mA
At 150 C ambient temperature ...................... 1000 h
At 85 C ambient temperature .................... 20 Years
Maximum junction temperature ................................. 150 C
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2001 V
Latch up current .....................................................> 140 mA
Supply voltage on VCC relative to VSS
CY14MC256J: ..................................–0.5 V to +3.1 V
CY14MB256J: ...................................–0.5 V to +4.1 V
CY14ME256J: ...................................–0.5 V to +7.0 V
DC voltage applied to outputs
Operating Range
Ambient
Temperature
Product
Range
VCC
in High Z state ....................................–0.5 V to VCC + 0.5 V
CY14MC256J Industrial –40 C to +85 C 2.4 V to 2.6 V
Input voltage .......................................–0.5 V to VCC + 0.5 V
CY14MB256J
CY14ME256J
2.7 V to 3.6 V
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
CY14MC256J
Min
2.4
2.7
4.5
–
Typ [4]
2.5
3.0
5.0
–
Max
2.6
3.6
5.5
1
Unit
V
VCC
Power supply
CY14MB256J
CY14ME256J
V
V
ICC1
Average VCC current
fSCL = 3.4 MHz;
mA
Values obtained without output loads
(IOUT = 0 mA)
f
SCL = 1 MHz;
CY14MC256J
CY14MB256J
–
–
400
A
Values obtained
without output loads
(IOUT = 0 mA)
CY14ME256J
–
–
–
–
450
3
A
ICC2
ICC4
ISB
Average VCC current during
STORE
All inputs don’t care, VCC = Max
mA
Average current for duration tSTORE
Average VCAP current during
AutoStore cycle
All inputs don't care. Average current
for duration tSTORE
–
–
–
–
3
mA
VCC standby current
SCL > (VCC – 0.2 V).
150
A
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after nonvolatile
cycle is complete. Inputs are static.
f
SCL = 0 MHz.
IZZ
Sleep mode current
tSLEEP time after SLEEP Instruction is
Issued. All inputs are static and
configured at CMOS logic level.
–
–
8
A
[5]
IIX
Input current in each I/O pin
(except HSB)
–1
–100
–1
–
–
–
+1
+1
+1
A
A
A
0.1 VCC < Vi < 0.9 VCC(max)
Input current in each I/O pin (for
HSB)
IOZ
Output leakage current
Notes
4. Typical values are at 25 °C, V = V
. Not 100% tested.
CC(Typ)
CC
5. Not applicable to WP, A2, A1 and A0 pins.
Document Number: 001-65233 Rev. *G
Page 18 of 30
CY14MC256J
CY14MB256J
CY14ME256J
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [4]
Max
Unit
Ci
Capacitance for each I/O pin
Capacitancemeasuredacrossallinput
–
–
7
pF
and output signal pin and VSS
.
VIH
VIL
Input HIGH voltage
Input LOW voltage
Output LOW voltage
0.7 × Vcc
–
–
–
–
–
–
–
VCC + 0.5
V
V
– 0.5
0.3 × Vcc
VOL
IOL = 3 mA
OL = 6 mA
0
0.4
0.6
–
V
I
0
V
[6]
Rin
Input resistance (WP, A2, A1, A0) For VIN = VIL (Max)
For VIN = VIH (Min)
50
1
k
M
V
–
Vhys
Hysteresis of Schmitt trigger
inputs
0.05 × VCC
–
[7]
VCAP
Storage capacitor
Between VCAP pin and CY14MC256J
170
42
220
47
270
180
F
F
VSS
CY14MB256J
CY14ME256J
[8, 9]
VVCAP
Maximum voltage driven on VCAP VCC = Max
pin by the device
CY14MC256J
CY14MB256J
–
–
–
–
VCC
V
V
CY14ME256J
VCC– 0.5
Data Retention and Endurance
Over the Operating Range
Parameter
Description
Min
20
Unit
Years
K
DATAR
NVC
Data retention
Nonvolatile STORE operations
1,000
Thermal Resistance
Parameter [9]
Description
Test Conditions
8-pin SOIC
16-pin SOIC Unit
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
101.08
56.68
C/W
JC
Thermal resistance
(junction to case)
37.86
32.11
C/W
Notes
6. The input pull-down circuit is stronger (50 k) when the input voltage is below V and weak (1 M) when the input voltage is above V
.
IH
IL
7. Min V
value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max V
value guarantees that the capacitor
CAP
CAP
on V
is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore
CAP
it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on V
options.
CAP
8. Maximum voltage on V
pin (V
) is provided for guidance when choosing the V
capacitor. The voltage rating of the V capacitor across the operating
CAP
VCAP
CAP
CAP
temperature range should be higher than the V
voltage.
VCAP
9. These parameters are guaranteed by design and are not tested.
Document Number: 001-65233 Rev. *G
Page 19 of 30
CY14MC256J
CY14MB256J
CY14ME256J
AC Test Loads and Waveforms
Figure 30. AC Test Loads and Waveforms
For 3.0 V (CY14MB256J)
For 5.0 V (CY14ME256J)
5.0 V
For 2.5 V (CY14MC256J)
2.5 V
3.0 V
867
1.6 K
700
OUTPUT
OUTPUT
OUTPUT
100 pF
50 pF
100 pF
AC Test Conditions
Description
Input pulse levels
Input rise and fall times (10%–90%)
Input and output timing reference levels
CY14MC256J
0 V to 2.5 V
10 ns
CY14MB256J
0 V to 3 V
10 ns
CY14ME256J
0 V to 5 V
10 ns
1.25 V
1.5 V
2.5 V
Document Number: 001-65233 Rev. *G
Page 20 of 30
CY14MC256J
CY14MB256J
CY14ME256J
AC Switching Characteristics
Over the Operating Range
Parameter
3.4 MHz [11]
1 MHz [11]
400 kHz [11]
Unit
Description
[10]
Min
Max
3400
–
Min
Max
1000
–
Min
Max
400
–
fSCL
Clock frequency, SCL
–
–
–
kHz
ns
tSU; STA
Setup time for Repeated START
condition
160
250
600
tHD;STA
tLOW
Hold time for START condition
LOW period of the SCL
HIGH period of the SCL
Data in setup time
160
160
60
10
0
–
–
250
500
260
100
0
–
–
600
1300
600
100
0
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHIGH
–
–
–
tSU;DATA
tHD;DATA
tDH
tr[12]
tf[12]
–
–
–
Data hold time (In/Out)
Data out hold time
–
–
–
0
–
0
–
0
–
Rise time of SDA and SCL
Fall time of SDA and SCL
Setup time for STOP condition
Data output valid time
ACK output valid time
–
80
80
–
–
120
120
–
–
300
300
–
–
–
–
tSU;STO
tVD;DATA
tVD;ACK
160
–
250
–
600
–
130
130
80
400
400
120
900
900
250
–
–
–
[12]
tOF
Output fall time from VIH min to
VILmax
–
–
–
tBUF
tSP
Bus free time between STOP and
next START condition
0.3
–
–
0.5
–
–
1.3
–
–
us
ns
Pulse width ofspikesthatmustbe
suppressed by input filter
10
50
50
Switching Waveforms
Figure 31. Timing Diagram
SDA
t
r
t
f
t
SP
t
t
VD;DAT
BUF
t
t
HIGH
SU;DATA
t
t
t
HD;STA
SU;STO
t
VD;ACK
LOW
SCL
t
t
t
9th clock
(ACK)
f
r
HD;STA
t
t
SU;STA
HD;DATA
S
S
Sr
P
START condition
STOP condition START condition
Repeated START condition
Notes
10. Test conditions assume signal transition time of 10 ns or less, timing reference levels of V /2, input pulse levels of 0 to V
, and output loading of the specified
CC(typ)
CC
I
and load capacitance shown in Figure 30.
OL
2
11. Bus Load (Cb) considerations; Cb < 500 pF for I C clock frequency (SCL) 100/400 KHz; Cb < 550 pF for SCL at 1000 kHz; Cb < 100 pF for SCL at 3.4 MHz.
12. These parameters are guaranteed by design and are not tested.
Document Number: 001-65233 Rev. *G
Page 21 of 30
CY14MC256J
CY14MB256J
CY14ME256J
nvSRAM Specifications
Over the Operating Range
Parameter
Description
Min
–
–
–
–
–
150
–
–
–
Max
40
20
20
8
Unit
ms
ms
ms
ms
ns
µs
V
V
V
µs
V
[13]
tFA
Power-Up RECALL duration
CY14MC256J
CY14MB256J
CY14ME256J
[14]
tSTORE
STORE cycle duration
[15]
tDELAY
tVCCRISE
VSWITCH
Time allowed to complete SRAM write cycle
VCC rise time
25
–
[16]
Low voltage trigger level
CY14MC256J
CY14MB256J
CY14ME256J
2.35
2.65
4.40
5
1.9
500
40
20
20
8
100
[16]
tLZHSB
HSB high to nvSRAM active time
HSB output disable voltage
–
–
[16]
VHDIS
tHHHD
tWAKE
[16]
HSB HIGH active time
–
–
–
–
–
–
ns
ms
ms
ms
ms
µs
Time for nvSRAM to wake up from SLEEP mode
CY14MC256J
CY14MB256J
CY14ME256J
tSLEEP
Time to enter low power mode after issuing SLEEP instruction
Time to enter into standby mode after issuing STOP condition
[16]
tSB
Switching Waveforms
Figure 32. AutoStore or Power-Up RECALL [17]
VCC
VSWITCH
VHDIS
14
14
tVCCRISE
tSTORE
tSTORE
Note
Note
tHHHD
tHHHD
18
18
Note
Note
HSB OUT
AutoStore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
AutoStore
POWER
DOWN
AutoStore
POWER-UP
RECALL
Notes
13. t starts from the time V rises above V
SWITCH.
FA
CC
14. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
15. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t
16. These parameters are guaranteed by design and are not tested.
.
DELAY
17. Read and Write cycles are ignored during STORE, RECALL, and while V is below V
CC
SWITCH.
18. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document Number: 001-65233 Rev. *G
Page 22 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Software Controlled STORE/RECALL Cycles
Over the Operating Range
CY14MX256J
Parameter
tRECALL
Description
Unit
Min
–
Max
600
500
RECALL duration
Software sequence processing time
µs
µs
[19, 20]
–
tSS
Switching Waveforms
Figure 33. Software STORE/RECALL Cycle
DATA OUTPUT
Command Reg Address
acknowledge (A) by Slave
Command Byte (STORE/RECALL)
nvSRAM Control Slave Address
BY MASTER
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM
MASTER
2
8
9
1
2
8
9
1
2
8
9
1
P
S
START
condition
RWI
t
t
STORE / RECALL
Figure 34. AutoStore Enable/Disable Cycle
DATA OUTPUT
BY MASTER
Command Reg Address
acknowledge (A) by Slave
Command Byte (ASENB/ASDISB)
nvSRAM Control Slave Address
acknowledge (A) by Slave
acknowledge (A) by Slave
SCL FROM
MASTER
2
8
9
1
2
8
9
1
2
8
9
1
P
S
START
condition
RWI
t
SS
Notes
19. This is the amount of time it takes to take action on a soft sequence command. V power must remain HIGH to effectively register command.
CC
20. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
Document Number: 001-65233 Rev. *G
Page 23 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Hardware STORE Cycle
Over the Operating Range
CY14MX256J
Parameter
Description
Unit
Min
Max
tPHSB
Hardware STORE pulse width
15
–
ns
Switching Waveforms
Figure 35. Hardware STORE Cycle [21]
Write Latch set
t
PHSB
HSB (IN)
t
STORE
t
t
HHHD
DELAY
HSB (OUT)
RWI
t
LZHSB
Write Latch not set
t
PHSB
HSB (IN)
HSB pin is driven HIGH to V
only by Internal
CC
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
HSB (OUT)
RWI
t
DELAY
Note
21. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
Document Number: 001-65233 Rev. *G
Page 24 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Ordering Information
Ordering Code
CY14MB256J1-SXIT
CY14MB256J1-SXI
CY14MB256J2-SXIT
CY14MB256J2-SXI
CY14ME256J2-SXIT
CY14ME256J2-SXI
Package Diagram
Package Type
8-pin SOIC (without VCAP
Operating Range
51-85066
)
Industrial
8-pin SOIC (with VCAP
)
All these parts are Pb-free. This table contains Final information. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 M B 256 J 2 - S X I T
Option:
T - Tape and Reel
Blank - Std.
Temperature:
I - Industrial (–40 to 85 °C)
Pb-free
Package:
SX - 8-pin SOIC
1 - Without VCAP
2 - With VCAP
SF - 16-pin SOIC
3 - With VCAP and HSB
J - Serial (I2C) nvSRAM
Density:
256 - 256 Kb
Voltage:
C - 2.5 V
B - 3.0 V
E - 5.0 V
Metering
14 - nvSRAM
Cypress
Document Number: 001-65233 Rev. *G
Page 25 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Package Diagrams
Figure 36. 8-pin SOIC (150 mils) Package Outline, 51-85066
51-85066 *F
Document Number: 001-65233 Rev. *G
Page 26 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Package Diagrams (continued)
Figure 37. 16-pin SOIC (0.413 × 0.299 × 0.0932 Inches) Package Outline, 51-85022
51-85022 *E
Document Number: 001-65233 Rev. *G
Page 27 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Acronyms
Document Conventions
Units of Measure
Acronym
Description
ACK
CMOS
CRC
EIA
Acknowledge
Symbol
°C
Unit of Measure
Complementary Metal Oxide Semiconductor
Cyclic Redundancy Check
Electronic Industries Alliance
Inter-Integrated Circuit
degree Celsius
hertz
Hz
kHz
k
Mbit
MHz
M
A
F
s
kilohertz
kilohm
I2C
I/O
Input/Output
megabit
JEDEC
LSB
Joint Electron Devices Engineering Council
Least Significant Bit
megahertz
megaohm
microampere
microfarad
microsecond
milliampere
millisecond
nanosecond
ohm
MSB
nvSRAM
NACK
RoHS
R/W
Most Significant Bit
Non-volatile Static Random Access Memory
No Acknowledge
Restriction of Hazardous Substances
Read/Write
mA
ms
ns
RWI
Read and Write Inhibit
SCL
Serial Clock Line
SDA
SNL
Serial Data Access
%
percent
Serial Number Lock
pF
V
picofarad
volt
SOIC
SRAM
WP
Small Outline Integrated Circuit
Static Random Access Memory
Write Protect
W
watt
Document Number: 001-65233 Rev. *G
Page 28 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Document History Page
Document Title: CY14MC256J, CY14MB256J, CY14ME256J, 256-Kbit (32 K × 8) Serial (I2C) nvSRAM
Document Number: 001-65233
Submission
Date
Orig. of
Change
Rev.
ECN No.
Description of Change
**
3089747
3198492
11/18/2010
03/21/2011
GVCH
GVCH
New datasheet
*A
Updated Configuration (Added Slave Address information).
Updated AutoStore Operation (description).
Updated Hardware STORE and HSB pin Operation (Added more clarity on
HSB pin operation).
Updated Table 6 (Product ID column).
Updated nvSRAM Specifications (description of tLZHSB parameter).
Fixed typo error in Figure 32.
Updated Ordering Code Definitions.
Updated in new template.
*B
*C
3248609
3394987
05/05/2011
11/28/2011
GVCH
GVCH
Datasheet status changed from “Preliminary” to “Final”
Updated Ordering Information
Updated Pin Definitions (SDA pin description).
Updated Command Register (SLEEP description on page 8).
Updated Device ID (Added device ID (4 bytes) column in Table 6).
Updated Executing Commands Using Command Register (description).
Updated DC Electrical Characteristics (Added ICC1 parameter value for 1 MHz
frequency, changed ICC2 parameter value from 2 mA to 3 mA, removed ICC3
parameter, added Note 7 and referred the note in the VCAP parameter).
Updated AC Switching Characteristics (Added Note 10 and referred the note
in the Parameter column, updated tSP max value from 5 ns to 10 ns for 3.4
MHz).
Updated Software Controlled STORE/RECALL Cycles (Updated Figure 33
and Figure 34).
Updated Ordering Information.
Updated Package Diagrams.
*D
3676259
07/25/2012
GVCH
Updated DC Electrical Characteristics (Added VVCAP parameter and its details,
added Note 8 and referred the same note in VVCAP parameter, also referred
Note 9 in VVCAP parameter).
*E
*F
*G
3757434
3905097
3985313
09/27/2012
02/15/2013
04/29/2013
GVCH
GVCH
GVCH
Updated Maximum Ratings (Removed “Ambient temperature with power
applied” and included “Maximum junction temperature”).
Updated Features:
Added Note 1 and referred the same note in “High speed I2C interface”.
Updated Features:
Updated Note 1.
Updated DC Electrical Characteristics:
Added one more condition “IOL = 6 mA” for VOL parameter and added
respective values.
Updated AC Switching Characteristics:
Updated Note 11.
Changed value of tOF parameter from 300 ns to 250 ns for 400 kHz frequency.
Updated Package Diagrams:
spec 51-85066 – Changed revision from *E to *F.
spec 51-85022 – Changed revision from *D to *E.
Document Number: 001-65233 Rev. *G
Page 29 of 30
CY14MC256J
CY14MB256J
CY14ME256J
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC Solutions
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2010-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-65233 Rev. *G
Revised April 29, 2013
Page 30 of 30
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