CY14B512P_技术文档

CY14B512P

512-Kbit (64 K × 8) Serial (SPI) nvSRAM

with Real Time Clock

512-Kbit (64

K × 8) Serial (SPI) nvSRAM with Real Time Clock

■ Write protection

❐ Hardware protection using Write Protect (WP) pin

Features

■ 512-Kbit nonvolatile static random access memory (nvSRAM)

❐ Internally organized as 64 K × 8

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4, 1/2, or entire array

❐ STORE to QuantumTrap nonvolatile elements initiated

automatically on power-down (AutoStore) or by the user

using HSB pin (Hardware STORE) or SPI instruction

(Software STORE)

■ Low power consumption

❐ Single 3 V + 20%, –10% operation

❐ Average active current of 10 mA at 40 MHz operation

❐ RECALL to SRAM initiated on power-up (Power-Up

RECALL) or by serial peripheral interface (SPI) instruction

(Software RECALL)

■ Industry standard configurations

❐ Industrial temperature

❐ 16-pin small outline integrated circuit (SOIC) package

❐ Restriction of hazardous substances (RoHS) compliant

❐ Automatic STORE on power-down with a small capacitor

■ High reliability

Overview

❐ Infinite read, write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ Data retention: 20 years

The Cypress CY14B512P combines a 512-Kbit nvSRAM^[1]with

a full-featured real time clock in a monolithic integrated circuit

with serial SPI interface. The memory is organized as 64 K words

of 8 bits each. The embedded nonvolatile elements incorporate

the QuantumTrap technology, creating the world’s most reliable

nonvolatile memory. The SRAM provides infinite read and write

cycles, while the QuantumTrap cells provide highly reliable

nonvolatile storage of data. Data transfers from SRAM to the

nonvolatile elements (STORE operation) takes place

automatically at power-down. On power-up, data is restored to

the SRAM from the nonvolatile memory (RECALL operation).

The STORE and RECALL operations can also be initiated by the

user through SPI instruction.

■ Real time clock (RTC)

❐ Full featured RTC

❐ Watchdog timer

❐ Clock alarm with programmable interrupts

❐ Capacitor or battery backup for RTC

❐ Backup current of 0.35 µA (typical)

■ High-speed SPI

❐ 40 MHz clock rate – SRAM memory access

❐ 25 MHz clock rate – RTC memory access

❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)

Logic Block Diagram

V_CC

V_CAP

QuantumTrap

64 K X 8

Power Control

CS

WP

SCK

Instruction decode

Write protect

Control logic

STORE/RECALL

Control

STORE

HSB

SRAM Array

HOLD

RECALL

64 K X 8

Instruction

register

D0-D7

A0-A15

X

out

in

Address

Decoder

RTC

X

INT

MUX

Data I/O register

Status Register

SO

SI

Note

1. This device is referred to as nvSRAM throughout the document.

Cypress Semiconductor Corporation

Document #: 001-53872 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 12, 2011

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CY14B512P

Contents

Pinouts .............................................................................. 3

Device Operation.............................................................. 4

SRAM Write................................................................. 4

SRAM Read ................................................................ 4

STORE Operation ....................................................... 4

AutoStore Operation.................................................... 4

Software STORE Operation........................................ 5

Hardware STORE and HSB Pin Operation................. 5

RECALL Operation...................................................... 5

Hardware RECALL (Power-Up) .................................. 5

Software RECALL ....................................................... 5

Disabling and Enabling AutoStore............................... 5

Serial Peripheral Interface ............................................... 6

SPI Overview............................................................... 6

SPI Modes ......................................................................... 7

SPI Operating Features.................................................... 8

Power-Up .................................................................... 8

Power On Reset.......................................................... 8

Power-Down................................................................ 8

Active Power and Standby Power Modes ................... 8

SPI Functional Description.............................................. 8

Status Register ................................................................. 9

Read Status Register (RDSR) Instruction................... 9

Write Status Register (WRSR) Instruction .................. 9

Write Protection and Block Protection......................... 10

Write Enable (WREN) Instruction.............................. 10

Write Disable (WRDI) Instruction .............................. 10

Block Protection ........................................................ 10

Hardware Write Protection (WP Pin)......................... 11

Memory Access .............................................................. 11

Read Sequence (READ) instruction.......................... 11

Write Sequence (WRITE) instruction ........................ 11

RTC Access..................................................................... 12

READ RTC (RDRTC) Instruction .............................. 13

WRITE RTC (WRTC) Instruction............................... 13

Software STORE (STORE) instruction...................... 14

Software RECALL (RECALL) instruction .................. 14

AutoStore Enable (ASENB) instruction ..................... 14

AutoStore Disable (ASDISB) instruction ................... 14

HOLD Pin Operation ................................................. 15

Real Time Clock Operation............................................ 16

nvTIME Operation ..................................................... 16

Clock Operations....................................................... 16

Reading the Clock..................................................... 16

Setting the Clock....................................................... 16

Backup Power ........................................................... 16

Stopping and Starting the Oscillator.......................... 16

Calibrating the Clock ................................................. 17

Alarm......................................................................... 17

Watchdog Timer........................................................ 17

Power Monitor ........................................................... 18

Interrupts ................................................................... 18

Interrupt Register....................................................... 18

Flags Register ........................................................... 18

Accessing the Real Time Clock through SPI............. 19

Best Practices................................................................. 24

Maximum Ratings........................................................... 25

DC Electrical Characteristics ........................................ 25

Data Retention and Endurance .................................... 26

Capacitance .................................................................... 26

Thermal Resistance........................................................ 26

AC Test Conditions ........................................................ 26

RTC Characteristics ....................................................... 27

AC Switching Characteristics ....................................... 27

AutoStore or Power-Up RECALL .................................. 29

Software Controlled STORE/RECALL Cycles.............. 30

Hardware STORE Cycle ................................................. 31

Ordering Information...................................................... 32

Ordering Code Definition........................................... 32

Package Diagram............................................................ 33

Acronyms........................................................................ 34

Document Conventions ................................................. 34

Units of Measure ....................................................... 34

Document History Page ................................................ 35

Sales, Solutions, and Legal Information ...................... 36

Worldwide Sales and Design Support....................... 36

Products .................................................................... 36

PSoC Solutions......................................................... 36

Document #: 001-53872 Rev. *E

Page 2 of 36

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CY14B512P

Pinouts

Figure 1. Pin Diagram - 16-pin SOIC

V

16

15

14

13

12

NC

1

2

CC

V

INT

V

RTCbat

X

out

3

4

5

6

7

8

CAP

Top View

X

SO

SI

in

not to scale

WP

HOLD

SCK

CS

11

10

V

RTCcap

V

SS

9

HSB

Table 1. Pin Definitions

Pin Name

I/O Type

Description

CS

Input

Chip select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low

power standby mode.

SCK

Input

Serial clock. Runs at speeds up to maximum of f_SCK. Serial input is latched at the rising edge of

this clock. Serial output is driven at the falling edge of the clock.

SI

SO

Input

Output

Serial input. Pin for input of all SPI instructions and data.

Serial output. Pin for output of data through SPI.

Write protect. Implements hardware write protection in SPI.

HOLD pin. Suspends serial operation.

WP

Input

HOLD

HSB

Input

Input/Output

Hardware STORE busy:

Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE

operation HSB is driven HIGH for a short time (t_HHHD) with standard output high current and then

a weak internal pull-up resistor keeps this pin HIGH (an external pull-up resistor connection is

optional).

Input: Hardware STORE implemented by pulling this pin LOW externally.

V_CAP

Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the

SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as ‘no connect’. It

must never be connected to ground.

V_RTCcap

V_RTCbat

Xout

Power supply Capacitor backup for RTC. Left unconnected if V_RTCbatis used.

Power supply Battery backup for RTC. Left unconnected if V_RTCcapis used.

Output

Input

Crystal output connection. Drives crystal on start up.

Crystal input connection. For 32.768 kHz crystal.

Xin

Output

Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power

monitor. It is also programmable to either active HIGH (push or pull) or LOW (open drain).

INT

NC

V_SS

V_CC

No connect

No connect. This pin is not connected to the die.

Power supply Ground.

Power supply Power supply (2.7 V to 3.6 V).

Document #: 001-53872 Rev. *E

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CY14B512P

SRAM Read

Device Operation

A read cycle in CY14B512P is performed at the SPI bus speed

and the data is read out with zero cycle delay after the READ

instruction is executed. The READ instruction is issued through

the serial input (SI) pin of the nvSRAM and consists of the READ

opcode and two bytes of address. The data is read out on the

serial output (SO) pin.

CY14B512P is a 512-Kbit nvSRAM memory with integrated RTC

and SPI interface. All the reads and writes to nvSRAM happen

to the SRAM, which gives nvSRAM the unique capability to

handle infinite writes to the memory. The data in SRAM is

secured by a STORE sequence that transfers the data in parallel

to the nonvolatile QuantumTrap cells. A small capacitor (V_CAP

)

CY14B512P allows burst mode reads to be performed through

SPI. This enables reads on consecutive addresses without

issuing a new READ instruction. When the last address in

memory is reached in burst mode read, the address rolls over to

0x0000 and the device continues to read.

is used to AutoStore the SRAM data in nonvolatile cells when

power goes down, providing power-down data security. The

QuantumTrap nonvolatile elements built in the reliable SONOS

technology make nvSRAM the ideal choice for secure data

storage.

The SPI read cycle sequence is defined in the memory access

section of SPI protocol description.

In CY14B512P, the 512-Kbit memory array is organized as

64 K words × 8 bits. The memory is accessed through a standard

SPI interface that enables very high clock speeds up to 40 MHz

with zero cycle delay read and write cycles. CY14B512P

supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and

operates as a SPI slave. The device is enabled using the chip

select (CS) pin and accessed through serial input (SI), serial

output (SO), and serial clock (SCK) pins.

STORE Operation

STORE operation transfers the data from the SRAM to the

nonvolatile QuantumTrap cells. The CY14B512P STOREs data

to the nonvolatile cells using one of the three STORE operations:

AutoStore, activated on device power-down; Software STORE,

activated by a STORE instruction; and Hardware STORE,

activated by the HSB. During the STORE cycle, an erase of the

previous nonvolatile data is first performed, followed by a

program of the nonvolatile elements. After a STORE cycle is

initiated, read/write to CY14B512P is inhibited until the cycle is

completed.

CY14B512P provides the feature for hardware and software

write protection through the WP pin and WRDI instruction.

CY14B512P also provides mechanisms for block write

protection (quarter, half, or full array) using BP0 and BP1 pins in

the Status Register. Further, the HOLD pin is used to suspend

any serial communication without resetting the serial sequence.

The HSB signal or the RDY bit in the Status Register can be

monitored by the system to detect if a STORE or Software

RECALL cycle is in progress. The busy status of nvSRAM is

indicated by HSB being pulled LOW or the RDY bit being set to

‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore and

Hardware STORE operations are ignored unless at least one

write operation takes place since the most recent STORE or

RECALL cycle. However, software initiated STORE cycles are

performed regardless of whether a write operation has taken

place.

CY14B512P uses the standard SPI opcodes for memory access.

In addition to the general SPI instructions for read and write,

CY14B512P provides four special instructions that allow access

to four nvSRAM specific functions: STORE, RECALL, AutoStore

Disable (ASDISB), and AutoStore Enable (ASENB).

The major benefit of nvSRAM over serial EEPROMs is that all

reads and writes to nvSRAM are performed at the speed of SPI

bus with zero cycle delay. Therefore, no wait time is required

after any of the memory accesses. The STORE and RECALL

operations need finite time to complete and all memory accesses

are inhibited during this time. While a STORE or RECALL

operation is in progress, the busy status of the device is indicated

by the Hardware STORE Busy (HSB) pin and also reflected on

the RDY bit of the Status Register.

AutoStore Operation

The AutoStore operation is a unique feature of nvSRAM which

automatically stores the SRAM data to QuantumTrap cells

during power-down. This STORE makes use of an external

capacitor (V_CAP) and enables the device to safely STORE the

data in the nonvolatile memory when power goes down.

SRAM Write

All writes to nvSRAM are carried out on the SRAM and do not

use up any endurance cycles of the nonvolatile memory. This

enables the user to perform infinite write operations. A write cycle

is performed through the WRITE instruction. The WRITE

instruction is issued through the SI pin of the nvSRAM and

consists of the WRITE opcode, two bytes of address, and one

byte of data. Write to nvSRAM is done at SPI bus speed with zero

cycle delay.

During normal operation, the device draws current from V_CCto

charge the capacitor connected to the V_CAPpin. When the

voltage on the V_CCpin drops below V_SWITCHduring power-down,

the device inhibits all memory accesses to nvSRAM and

automatically performs a conditional STORE operation using the

charge from the V_CAPcapacitor. The AutoStore operation is not

initiated if no write cycle was performed since the last RECALL.

Note If a capacitor is not connected to V_CAPpin, AutoStore must

be disabled by issuing the AutoStore Disable instruction

specified in AutoStore Disable (ASDISB) instruction on page 14.

If AutoStore is enabled without a capacitor on V_CAPpin, the

device attempts an AutoStore operation without sufficient charge

to complete the Store. This corrupts the data stored in nvSRAM

and Status Register. To resume normal functionality, the WRSR

instruction must be issued to update the nonvolatile bits BP0,

BP1 and WPEN in the Status Register.

CY14B512P allows burst mode writes to be performed through

SPI. This enables write operations on consecutive addresses

without issuing a new WRITE instruction. When the last address

in memory is reached in burst mode, the address rolls over to

0x0000 and the device continues to write.

The SPI write cycle sequence is defined in the memory access

section of SPI protocol description.

Document #: 001-53872 Rev. *E

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CY14B512P

Figure 2 shows the proper connection of the storage capacitor

(V_CAPfor AutoStore operation. Refer to DC Electrical

Characteristics on page 25 for the size of the V_CAP

Upon completion of the STORE operation, the nvSRAM memory

access is inhibited for t_LZHSBtime after HSB pin returns HIGH.

The HSB pin must be left unconnected if not used.

)

.

RECALL Operation

Figure 2. AutoStore Mode

V_CC

A RECALL operation transfers the data stored in the nonvolatile

QuantumTrap elements to the SRAM. In CY14B512P, a

RECALL may be initiated in two ways: Hardware RECALL,

initiated on power-up; and Software RECALL, initiated by a SPI

RECALL instruction.

0.1 uF

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared. Next, the nonvolatile information is transferred into the

SRAM cells. All memory accesses are inhibited while a RECALL

cycle is in progress. The RECALL operation does not alter the

data in the nonvolatile elements.

V_CC

CS

V_CAP

Hardware RECALL (Power-Up)

During power-up, when V_CCcrosses V_SWITCH, an automatic

RECALL sequence is initiated, which transfers the content of

nonvolatile memory on to the SRAM.

V_CAP

V_SS

A Power-Up RECALL cycle takes t_FAtime to complete and the

memory access is disabled during this time. HSB pin is used to

detect the Ready status of the device.

Software RECALL

Software STORE Operation

Software RECALL allows the user to initiate a RECALL operation

to restore the content of nonvolatile memory on to the SRAM. In

CY14B512P, this can be done by issuing a RECALL instruction

in SPI.

Software STORE allows the user to trigger a STORE operation

through a special SPI instruction. The STORE operation is

initiated by executing a STORE instruction regardless of whether

a write has been performed since the last NV operation.

A Software RECALL takes t_RECALLtime to complete during

which all memory accesses to nvSRAM are inhibited. The

controller must provide sufficient delay for the RECALL operation

to complete before issuing any memory access instructions.

A STORE cycle takes t_STOREtime to complete, during which all

the memory accesses to nvSRAM are inhibited. The RDY bit of

the Status Register or the HSB pin may be polled to find the

Ready / Busy status of the nvSRAM. After the t_STOREcycle time

is completed, the SRAM is activated again for read and write

operations.

Disabling and Enabling AutoStore

If the application does not require the AutoStore feature, it can

be disabled in CY14B512P by using the ASDISB instruction. If

this is done, the nvSRAM does not perform a STORE operation

at power-down.

Hardware STORE and HSB Pin Operation

The HSB pin in CY14B512P is used to control and acknowledge

STORE operations. If no STORE/RECALL is in progress, this pin

can be used to request a Hardware STORE cycle. When the

HSB pin is driven LOW, the CY14B512P conditionally initiates a

STORE operation after t_DELAYduration. A STORE cycle starts

only if a write to the SRAM was performed since the last STORE

or RECALL cycle. Reads and writes to the memory are inhibited

for t_STOREduration or as long as HSB pin is LOW.

AutoStore can be re-enabled by using the ASENB instruction.

However, these operations are not nonvolatile and if the user

needs this setting to survive the power cycle, a STORE operation

must be performed following AutoStore Disable or Enable

operation.

Note CY14B512P comes from the factory with AutoStore

Enabled.

The HSB pin also acts as an open drain driver (internal 100-kΩ

weak pull-up resistor) that is internally driven LOW to indicate a

busy condition when the STORE (initiated by any means) is in

progress.

Note If AutoStore is disabled and V_CAPis not required, then the

V_CAPpin must be left open. The V_CAPpin must never be

connected to ground. The Power-Up RECALL operation cannot

be disabled in any case.

Note After each Hardware and Software STORE operation HSB

is driven HIGH for a short time (t_HHHD) with standard output high

current and then remains HIGH by an internal 100-kΩ pull-up

resistor.

Note For successfull last data byte STORE, a hardware store

should be initiated atleast one clock cycle after the last data bit

D0 is recieved.

Document #: 001-53872 Rev. *E

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CY14B512P

Serial Clock (SCK)

Serial Peripheral Interface

Serial clock is generated by the SPI master and the

communication is synchronized with this clock after CS goes

LOW.

SPI Overview

The SPI is a four-pin interface with chip select (CS), serial input

(SI), serial output (SO), and serial clock (SCK) pins. CY14B512P

provides serial access to nvSRAM through SPI interface. The

SPI bus on CY14B512P can run at speeds up to 40 MHz for all

instructions except RDRTC which runs at 25 MHz.

CY14B512P allows SPI modes 0 and 3 for data communication.

In both these modes, the inputs are latched by the slave device

on the rising edge of SCK and outputs are issued on the falling

edge. Therefore, the first rising edge of SCK signifies the arrival

of the first bit (MSB) of SPI instruction on the SI pin. Further, all

data inputs and outputs are synchronized with SCK.

The SPI is a synchronous serial interface which uses clock and

data pins for memory access and supports multiple devices on

the data bus. A device on SPI bus is activated using the CS pin.

Data Transmission SI/SO

The relationship between chip select, clock, and data is dictated

by the SPI mode. CY14B512P supports SPI modes 0 and 3. In

both these modes, data is clocked into the nvSRAM on the rising

edge of SCK starting from the first rising edge after CS goes

active.

SPI data bus consists of two lines, SI and SO, for serial data

communication. The SI is also referred to as Master Out Slave

In (MOSI) and SO is referred to as Master In Slave Out (MISO).

The master issues instructions to the slave through the SI pin,

while the slave responds through the SO pin. Multiple slave

devices may share the SI and SO lines as described earlier.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave device.

After CS is activated the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS must go inactive after an

operation is complete and before a new opcode can be issued.

CY14B512P has two separate pins for SI and SO which can be

connected with the master as shown in Figure 3 on page 7.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

most significant bit (MSB). This is valid for both address and data

transmission.

The commonly used terms used in SPI protocol are as follows.

SPI Master

CY14B512P requires a 2-byte address for any read or write

operation.

The SPI master device controls the operations on a SPI bus. A

SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and the

master may select any of the slave devices using the CS pin. All

the operations must be initiated by the master activating a slave

device by pulling the CS pin of the slave LOW. The master also

generates the SCK and all the data transmission on SI and SO

lines are synchronized with this clock.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

CY14B512P uses the standard opcodes for memory accesses.

In addition to the memory accesses, CY14B512P provides

additional opcodes for the nvSRAM specific functions: STORE,

RECALL, AutoStore Enable, and AutoStore Disable. Refer to

Table 2 on page 8 for details on opcodes.

SPI Slave

The SPI slave device is activated by the master through the chip

select line. A slave device gets the SCK as an input from the SPI

master and all the communication is synchronized with this

clock. SPI slave never initiates a communication on the SPI bus

and acts on the instruction from the master.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin till the next

falling edge of CS and the SO pin remains tristated.

CY14B512P operates as a slave device and may share the SPI

bus with multiple CY14B512P devices or other SPI devices.

Status Register

Chip Select (CS)

CY14B512P has an 8-bit Status Register. The bits in the Status

Register are used to configure the SPI bus. These bits are

described in the Table 4 on page 9.

For selecting any slave device, the master needs to pull down

the corresponding CS pin. Any instruction can be issued to a

slave device only when the CS pin is LOW.

The CY14B512P is selected when the CS pin is LOW. When the

device is not selected, data through the SI pin is ignored and the

serial output pin (SO) remains in a high-impedance state.

Note A new instruction must begin with the falling edge of CS.

Therefore, only one opcode can be issued for each active Chip

Select cycle.

Document #: 001-53872 Rev. *E

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CY14B512P

Figure 3. System Configuration using SPI nvSRAM

S C K

M O SI

M IS O

SC K

S I

S O

SC K

SI

S O

uC ontroller

C Y 14B 512P

C S

H O LD

C S

H O LD

C S 1

H O LD 1

C S 2

H O LD 2

The two SPI modes are shown in Figure 4 and Figure 5. The

status of clock when the bus master is in standby mode and not

transferring data is:

SPI Modes

CY14B512P device may be driven by a microcontroller with its

SPI peripheral running in either of these two modes:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

■ SPI Mode 0 (CPOL=0, CPHA=0)

■ SPI Mode 3 (CPOL=1, CPHA=1)

CPOL and CPHA bits must be set in the SPI controller for the

either Mode 0 or Mode 3. CY14B512P detects the SPI mode

from the status of SCK pin when the device is selected by

bringing the CS pin LOW. If SCK pin is LOW when the device is

selected, SPI Mode 0 is assumed and if SCK pin is HIGH,

CY14B512P works in SPI Mode 3.

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

Figure 4. SPI Mode 0

Figure 5. SPI Mode 3

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

SCK

SI

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

MSB

LSB

Document #: 001-53872 Rev. *E

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CY14B512P

Active Power and Standby Power Modes

SPI Operating Features

When CS is LOW, the device is selected and is in the active

power mode. The device consumes I_CCcurrent, as specified in

DC Electrical Characteristics on page 25. When CS is HIGH, the

device is deselected and the device goes into the standby power

mode if a STORE or RECALL cycle is not in progress. If a

STORE/RECALL cycle is in progress, the device goes into the

standby power mode after the STORE/RECALL cycle is

completed. In the standby power mode, the current drawn by the

Power-Up

Power-up is defined as the condition when the power supply is

turned on and V_CCcrosses Vswitch voltage. During this time, the

CS must be enabled to follow the V_CCvoltage. Therefore, CS

must be connected to V_CCthrough a suitable pull-up resistor. As

a built in safety feature, CS is both edge-sensitive and

level-sensitive. After power-up, the device is not selected until a

falling edge is detected on CS. This ensures that CS is HIGH,

before going LOW to start the first operation.

device drops to I_SB

.

SPI Functional Description

As described earlier, nvSRAM performs a Power-Up RECALL

operation after power-up and therefore, all memory accesses are

disabled for t_FAduration after power-up. The HSB pin can be

probed to check the Ready/Busy status of nvSRAM after

power- up.

The CY14B512P uses an 8-bit instruction register. Instructions

and their operation codes are listed in Table 2. All instructions,

addresses, and data are transferred with the MSB first and start

with a HIGH to LOW CS transition. There are, in all, 12 SPI

instructions that provide access to most of the functions in

nvSRAM. Further, the WP, HOLD and HSB pins provide

additional functionality driven through hardware.

Power On Reset

A power on reset (POR) circuit is included to prevent inadvertent

writes. At power-up, the device does not respond to any

instruction until the V_CCreaches the POR threshold voltage

(V_SWITCH). After V_CCtransitions the POR threshold, the device

is internally reset and performs an Power-Up RECALL operation.

During Power-Up RECALL all device accesses are inhibited.

The device is in the following state after POR:

Table 2. Instruction Set

Instruction Instruction

Opcode

Operation

Category

Name

WREN

0000 0110

Set Write Enable

latch

■ Deselected (after power-up, a falling edge is required on CS

before any instructions are started).

WRDI

RDSR

WRSR

READ

0000 0100 Reset Write

Enable latch

Status

Register

instructions

■ Standby power mode

0000 0101 Read Status

Register

■ Not in the HOLD condition

0000 0001 Write Status

Register

■ Status Register state:

❐ Write Enable (WEN) bit is reset to ‘0’.

❐ WPEN, BP1, BP0 unchanged from previous STORE opera-

tion

0000 0011

Read data from

memory array

SRAM

Read/Write

instructions

❐ Don’t care bits 4-6 are reset to 0.

WRITE

RDRTC

WRTC

0000 0010 Write data to

memory array

The WPEN, BP1, and BP0 bits of the Status Register are

nonvolatile bits and remain unchanged from the previous

STOERE operation.

0001 0011

Read RTC

registers

RTC

Read/Write

instructions

Before selecting and issuing instructions to the memory, a valid

and stable V_CCvoltage must be applied. This voltage must

remain valid until the end of the instruction transmission.

0001 0010 Write RTC

registers

STORE

0011 1100

0110 0000

Software STORE

RECALL

Software

RECALL

Power-Down

Special NV

instructions

At power-down (continuous decay of V_CC), when V_CCdrops from

the normal operating voltage and below the V_SWITCHthreshold

voltage, the device stops responding to any instruction sent to it.

If a write cycle is in progress and the last data bit D0 has been

received when the power goes down, it is allowed t_DELAYtime to

complete the write. After this, all memory accesses are inhibited

and a conditional AutoStore operation is performed (AutoStore is

not performed if no writes have happened since last RECALL

cycle). This feature prevents inadvertent writes to nvSRAM from

happening during power-down.

ASENB

ASDISB

0101 1001 AutoStore Enable

0001 1001 AutoStore Disable

0001 1110

Reserved

- Reserved -

The SPI instructions in CY14B512P are divided based on their

functionality in the following types:

❐ Status Register access: RDSR and WRSR instructions

❐ Write protection functions: WREN and WRDI instructions

along with WP pin and WEN, BP0, and BP1 bits

However, to avoid the possibility of inadvertent writes during

power-down, ensure that the device is deselected and is in

standby power mode, and the CS follows the voltage applied on

❐ SRAM memory access: READ and WRITE instructions

❐ RTC access: RDRTC and WRTC instructions

❐ nvSRAM special instructions: STORE, RECALL, ASENB,

and ASDISB

V_CC

.

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CY14B512P

Status Register

The Status Register bits are listed in Table 3. The Status Register consists of a Ready bit (RDY) and data protection bits WEN, BP0,

BP1 and WPEN. The RDY bit can be polled to check the Ready / Busy status while a nvSRAM STORE or Software RECALL cycle

is in progress. The Status Register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN,

BP1, and BP0 bits of the Status Register can be modified by using the WRSR instruction. The WRSR instruction has no effect on

WEN and RDY bits. The default value shipped from the factory for BP1, BP0, bits 4-6 and WPEN bits is ‘0’.

Table 3. Status Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WPEN (0)

X (0)

BP1 (0)

BP0 (0)

WEN (0)

RDY

Table 4. Status Register Bit Definition

Bit

Definition

Description

Bit 0 (RDY)

Ready

Read only bit indicates the Ready status of device to perform a memory access. This

bit is set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.

Bit 1 (WEN)

Write Enable

WEN indicates if the device is Write Enabled. This bit defaults to ‘0’ (disabled) on

power-up.

WEN = '1' --> Write Enabled

WEN = '0' --> Write Disabled

Bit 2 (BP0)

Bit 3 (BP1)

Bit 4-6

Block protect bit ‘0’

Block protect bit ‘1’

Don’t care

Used for block protection. For details see Table 5 on page 10.

Bits are writable and volatile. On power-up, bits are written with ‘0’.

Bit 7(WPEN)

Write protect enable bit

Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on

page 11.

to select one of four levels of block protection. Further, WPEN bit

must be set to ‘1’ to enable the use of Write Protect (WP) pin.

Read Status Register (RDSR) Instruction

The RDSR instruction provides access to the Status Register.

This instruction is used to probe the Write Enable status of the

device or the Ready status of the device. RDY bit is set by the

device to ‘1’ whenever a STORE or Software RECALL cycle is

in progress. The block protection and WPEN bits indicate the

extent of protection employed.

WRSR instruction is a write instruction and needs writes to be

enabled (WEN bit set to ‘1’) using the WREN instruction before

it is issued. The instruction is issued after the falling edge of CS

using the opcode for WRSR followed by eight bits of data to be

stored in the Status Register. Only bits 2, 3, and 7 can be

modified by WRSR instruction; therefore, it is recommended to

leave the bits 4-6 as ‘0’ while writing to the Status Register.

This instruction is issued after the falling edge of CS using the

opcode for RDSR.

Note In CY14B512P, the values written to Status Register are

saved to nonvolatile memory only after a STORE operation. If

AutoStore is disabled, any modifications to the Status Register

must be secured by performing a Software STORE operation.

Write Status Register (WRSR) Instruction

The WRSR instruction enables the user to write to the Status

Register. However, this instruction cannot be used to modify bit

0 and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used

Figure 6. Read Status Register (RDSR) Instruction Timing

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

SI

0

1

0

1

0

MSB

LSB

HI-Z

SO

D4

D2

D7 D6 D5

MSB

D3

D1 D0

LSB

Data

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CY14B512P

Figure 7. Write Status Register (WRSR) Instruction Timing

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

Data in

Opcode

D2

D7

1

D3

X

SI

0

X

MSB

LSB

HI-Z

SO

Write Disable (WRDI) Instruction

Write Protection and Block Protection

Write Disable instruction disables the write by clearing the WEN

bit to ‘0’ in order to protect the device against inadvertent writes.

This instruction is issued following the falling edge of CS followed

by opcode for WRDI instruction. The WEN bit is cleared on the

rising edge of CS following a WRDI instruction.

CY14B512P provides features for both software and hardware

write protection using WRDI instruction and WP. Additionally, this

device also provides block protection mechanism through BP0

and BP1 pins of the Status Register.

The Write Enable and Disable status of the device is indicated

by WEN bit of the Status Register. The write instructions (WRSR,

WRITE, and WRTC) and nvSRAM special instruction (STORE,

RECALL, ASENB, ASDISB) need the write to be enabled (WEN

bit = ‘1’) before they can be issued.

Figure 9. WRDI Instruction

CS

0

1

2

3

4

5

6

7

Write Enable (WREN) Instruction

SCK

SI

On power-up, the device is always in the write disable state. The

following WRITE, WRSR, WRTC, or nvSRAM special instruction

must therefore be preceded by a Write Enable instruction. If the

device is not Write Enabled (WEN = ‘0’), it ignores the write

instructions and returns to the standby state when CS is brought

HIGH. A new CS falling edge is required to re-initiate serial

communication. The instruction is issued following the falling

edge of CS. When this instruction is used, the WEN bit of Status

Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.

0

1

0

HI-Z

SO

Block Protection

Block protection is provided using the BP0 and BP1 pins of the

Status Register. These bits can be set using WRSR instruction

and probed using the RDSR instruction. The nvSRAM is divided

into four array segments. one-quarter, one-half, or all of the

memory segments can be protected. Any data within the

protected segment is read only. Table 5 shows the function of

block protect bits.

Note After completion of a write instruction (WRSR, WRITE, or

WRTC) or nvSRAM special instruction (STORE, RECALL,

ASENB, ASDISB) instruction, WEN bit is cleared to ‘0’. This is

done to provide protection from any inadvertent writes.

Therefore, WREN instruction must be used before a new write

instruction is issued.

Table 5. Block Write Protect Bits

Status Register Bits

Figure 8. WREN Instruction

Level

Array Addresses Protected

BP1

BP0

CS

0

1

0

1

0

1

None

0

1

2

3

4

5

6

7

1 (1/4)

2 (1/2)

3 (All)

0xC000-0xFFFF

0x8000-0xFFFF

0x0000-0xFFFF

SCK

SI

0

1

0

HI-Z

SO

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CY14B512P

After the CS line is pulled LOW to select a device, the read

opcode is transmitted through the SI line followed by two bytes

of address. After the last address bit is transmitted on the SI pin,

the data (D7-D0) at the specific address is shifted out on the SO

line on the falling edge of SCK starting with D7. Any other data

on SI line after the last address bit is ignored.

Hardware Write Protection (WP Pin)

The write protect pin (WP) is used to provide hardware write

protection. WP pin allows all normal read and write operations

when held HIGH. When the WP pin is brought LOW and WPEN

bit is ‘1’ all write operations to the Status Register are inhibited.

The hardware write protection function is blocked when the

WPEN bit is ‘0’. This allows the user to install the CY14B512P in

a system with the WP pin tied to ground, and still write to the

Status Register.

CY14B512P allows reads to be performed in bursts through SPI

which can be used to read consecutive addresses without

issuing a new READ instruction. If only one byte is to be read,

the CS line must be driven HIGH after one byte of data comes

out. However, the read sequence may be continued by holding

the CS line LOW and the address is automatically incremented

and data continues to shift out on SO pin. When the last data

memory address (0xFFFF) is reached, the address rolls over to

0x0000 and the device continues to read.

WP pin can be used along with WPEN and block protect bits

(BP1 and BP0) of the Status Register to inhibit writes to memory.

When WP pin is LOW and WPEN is set to ‘1’, any modifications

to the Status Register are disabled. Therefore, the memory is

protected by setting the BP0 and BP1 bits and the WP pin inhibits

any modification of the Status Register bits, providing hardware

write protection.

Write Sequence (WRITE) instruction

Note WP going LOW when CS is still LOW has no effect on any

of the ongoing write operations to the Status Register.

The write operations on CY14B512P are performed through the

SI pin. To perform a write operation CY14B512P, if the device is

write disabled, then the device must first be Write Enabled

through the WREN instruction. When the writes are enabled

(WEN = ‘1’), WRITE instruction is issued after the falling edge of

CS. A WRITE instruction constitutes transmitting the WRITE

opcode on SI line followed by 2 bytes of address and the data

(D7-D0) which is to be written.

Table 6 summarizes all the protection features provided in the

CY14B512P.

Table 6. Write Protection Operation

Protected Unprotected Status

WPEN WP

WEN

Blocks

Protected

Writable

Register

Protected

Writable

X

0

1

X

0

1

Protected

CY14B512P allows writes to be performed in bursts through SPI

which can be used to write consecutive addresses without

issuing a new WRITE instruction. If only one byte is to be written,

the CS line must be driven HIGH after the D0 (LSB of data) is

transmitted. However, if more bytes are to be written, CS line

must be held LOW and address incremented automatically. The

following bytes on the SI line are treated as data bytes and

written in the successive addresses. When the last data memory

address (0xFFFF) is reached, the address rolls over to 0x0000

and the device continues to write. The WEN bit is reset to ‘0’ on

completion of a WRITE sequence.

X

LOW

HIGH

Protected

Writable

Memory Access

All memory accesses are done using the READ and WRITE

instructions. These instructions cannot be used while a STORE

or RECALL cycle is in progress. A STORE cycle in progress is

indicated by the RDY bit of the Status Register and the HSB pin.

Note When a burst write reaches a protected block address, it

continues the address increment into the protected space but

does not write any data to the protected memory. If the address

roll over takes the burst write to unprotected space, it resumes

writes. The same operation is true if a burst write is initiated

within a write protected block.

Read Sequence (READ) instruction

The read operations on CY14B512P are performed by giving the

instruction on the SI pin and reading the output on SO pin. The

following sequence needs to be followed for a read operation:

Figure 10. Read Instruction Timing

CS

0

1

0

1

2

3

4

5

6

7

2

3

4

5

6

7

12 13 14 15

0

1

2

3

4

5

6

7

SCK

16-bit Address

11 10

Op-Code

SI

9

8

0

1

3

2

1

0

LSB

15 14 13 12

MSB

HI-Z

SO

D7 D6 D5 D4 D3

D2

D1

D0

MSB

LSB

Data

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CY14B512P

Figure 11. Burst Mode Read Instruction Timing

CS

12 13 14 15

0

1

0

1

2

3

4

5

6

7

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

Op-Code

16-bit Address

8

1

15 14 13 12 11 10

9

3

2

1

0

SI

0

MSB

LSB

Data Byte N

Data Byte 1

HI-Z

SO

D7 D6 D5 D4

D0

D3 D2 D1 D0

D3 D2

D7 D0 D7 D6 D5 D4

D1

MSB

LSB

Figure 12. Write Instruction Timing

CS

0

1

0

1

2

3

4

5

7

2

3

4

5

6

7

12 13 14 15

0

1

2

3

4

5

6

7

6

SCK

Op-Code

16-bit Address

11 10

D4

D2

D1 D0

SI

D7 D6 D5

MSB

D3

0

1

0

8

3

2

1

0

15 14 13 12

MSB

9

LSB

Data

HI-Z

SO

Figure 13. Burst Mode Write Instruction Timing

CS

14 15

12 13

0

1

0

1

2

3

4

5

6

7

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

SCK

Data Byte N

Data Byte 1

Op-Code

16-bit Address

8

D7 D6 D5 D4

MSB

D7 D0 D7 D6 D5 D4

D3 D2

1

0

15 14 13 12 11 10

MSB

9

3

2

1

0

D1 D0

0

SI

LSB

HI-Z

SO

timekeeping registers to ensure that transitional values of time

are not read.

RTC Access

CY14B512P uses 16 registers for RTC. These registers can be

read out or written to by accessing all 16 registers in burst mode

or accessing each register, one at a time. The RDRTC and

WRTC instructions are used to access the RTC.

Writes to the RTC register are performed using the WRTC

instruction. Writing RTC timekeeping registers and control

registers, except for the flags register needs the ‘W’ bit of the

flags register to be set to ‘1’. The internal counters are updated

with the new date and time setting when the ‘W’ bit is cleared to

‘0’. All the RTC registers can also be written in burst mode using

the WRTC instruction.

All the RTC registers can be read in burst mode by issuing the

RDRTC instruction and reading all 16 bytes without bringing the

CS pin HIGH. The ‘R’ bit must be set while reading the RTC

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CY14B512P

The ‘R’ bit in RTC flags register must be set to '1' before reading

RTC time keeping registers to avoid reading transitional data.

Modifying the RTC flags register requires a Write RTC cycle. The

R bit must be cleared to '0' after completion of the read operation.

READ RTC (RDRTC) Instruction

Read RTC (RDRTC) instruction allows the user to read the

contents of RTC registers. Reading the RTC registers through

the SO pin requires the following sequence: After the CS line is

pulled LOW to select a device, the RDRTC opcode is transmitted

through the SI line followed by eight address bits for selecting the

register. Any data on the SI line after the address bits is ignored.

The data (D7-D0) at the specified address is then shifted out onto

the SO line. RDRTC also allows burst mode read operation.

When reading multiple bytes from RTC registers, the address

rolls over to 0x00 after the last RTC register address (0x0F) is

reached.

The easiest way to read RTC registers is to perform RDRTC in

burst mode. The read may start from the first RTC register (0x00)

and the CS must be held LOW to allow the data from all 16 RTC

registers to be transmitted through the SO pin.

Note Read RTC (RDRTC) instruction operates at a maximum

clock frequency of 25 MHz. The opcode cycles, address cycles

and data out cycles need to run at 25 MHz for the instruction to

work properly.

Figure 14. Read RTC (RDRTC) Instruction Timing

CS

0

1

0

1

2

3

4

5

6

7

2

4

5

6

7

0

1

2

3

4

5

6

7

3

SCK

Op-Code

1

0

SI

0

1

0

MSB

0

A3

A2 A1

A0

LSB

SO

D4 D3 D2

Data

D0

D7 D6

D1

D5

MSB

LSB

bytes of data. WRTC allows burst mode write operation. When

writing more than one registers in burst mode, the address rolls

over to 0x00 after the last RTC address (0x0F) is reached.

WRITE RTC (WRTC) Instruction

WRITE RTC (WRTC) instruction allows the user to modify the

contents of RTC registers. The WRTC instruction requires the

WEN bit to be set to '1' before it can be issued. If WEN bit is '0',

a WREN instruction needs to be issued before using WRTC.

Writing RTC registers requires the following sequence: After the

CS line is pulled LOW to select a device, WRTC opcode is

transmitted through the SI line followed by eight address bits

identifying the register which is to be written to and one or more

Note that writing to RTC timekeeping and control registers

require the W bit to be set to '1'. The values in these RTC

registers take effect only after the ‘W’ bit is cleared to '0'. Write

Enable bit (WEN) is automatically cleared to ‘0’ after completion

of the WRTC instruction.

Figure 15. Write RTC (WRTC) Instruction Timing

CS

0

1

0

1

2

3

4

5

6

7

2

4

5

6

7

0

1

2

3

4

5

6

7

3

SCK

Op-Code

1

4-bit Address

A0

0

SI

0

1

0

A3

A2 A1

D7 D6

MSB

D4

D2 D1 D0

LSB

D5

D3

MSB

LSB

Data

HI-Z

SO

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CY14B512P

AutoStore Enable (ASENB) instruction

nvSRAM Special Instructions

The AutoStore Enable instruction enables the AutoStore on

CY14B512P. This setting is not nonvolatile and needs to be

followed by a STORE sequence if this is desired to survive the

power cycle.

CY14B512P provides four special instructions that allow access

to the nvSRAM specific functions: STORE, RECALL, ASDISB,

and ASENB. Table 7 lists these instructions.

Table 7. nvSRAM Special Instructions

To issue this instruction, the device must be Write Enabled

(WEN = ‘1’). The instruction is performed by transmitting the

ASENB opcode on the SI pin following the falling edge of CS.

The WEN bit is cleared on the positive edge of CS following the

ASENB instruction.

Function Name

STORE

Opcode

0011 1100

0110 0000

Operation

Software STORE

Software RECALL

RECALL

ASENB

0101 1001 AutoStore Enable

0001 1001 AutoStore Disable

Figure 18. AutoStore Enable Operation

ASDISB

CS

Software STORE (STORE) instruction

0

1

2

3

4

5

6

7

When a STORE instruction is executed, CY14B512P performs a

Software STORE operation. The STORE operation is performed

irrespective of whether a write has taken place since the last

STORE or RECALL operation.

SCK

SI

0

1

0

1

0

1

Figure 16. Software STORE Operation

HI-Z

SO

CS

0

1

2

3

4

5

6

7

AutoStore Disable (ASDISB) instruction

SCK

SI

AutoStore is enabled by default in CY14B512P. The AutoStore

Disable instruction disables the AutoStore on CY14B512P. This

setting is not nonvolatile and needs to be followed by a STORE

sequence if this is desired to survive the power cycle.

0

1

0

HI-Z

SO

To issue this instruction, the device must be Write Enabled

(WEN = ‘1’). The instruction is performed by transmitting the

ASDISB opcode on the SI pin following the falling edge of CS.

The WEN bit is cleared on the positive edge of CS following the

To issue this instruction, the device must be Write Enabled (WEN

bit = ‘1’).The instruction is performed by transmitting the STORE

opcode on the SI pin following the falling edge of CS. The WEN

bit is cleared on the positive edge of CS following the STORE

instruction.

ASDISB instruction.

.

Figure 19. AutoStore Disable Operation

Software RECALL (RECALL) instruction

CS

When a RECALL instruction is executed, CY14B512P performs

a Software RECALL operation. To issue this instruction, the

device must be Write Enabled (WEN = ‘1’).

0

1

2

3

4

5

6

7

SCK

SI

The instruction is performed by transmitting the RECALL opcode

on the SI pin following the falling edge of CS. The WEN bit is

cleared on the positive edge of CS following the RECALL

instruction.

0

1

0

1

HI-Z

SO

Figure 17. Software RECALL Operation

CS

0

1

2

3

4

5

6

7

SCK

SI

0

1

0

HI-Z

SO

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CY14B512P

HOLD Pin Operation

The HOLD pin is used to pause the serial communication. When

the device is selected and a serial sequence is underway, HOLD

is used to pause the serial communication with the master device

without resetting the ongoing serial sequence. To pause, the

HOLD pin must be brought LOW when the SCK pin is LOW. CS

pin must remain LOW along with HOLD pin to pause serial

communication. While the device serial communication is

paused, inputs to the SI pin are ignored and the SO pin is in the

high impedance state. To resume serial communication, the

HOLD pin must be brought HIGH when the SCK pin is LOW

(SCK may toggle during HOLD).

Figure 20. HOLD Operation

CS

SCK

HOLD

SO

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CY14B512P

Backup Power

Real Time Clock Operation

The RTC in the CY14B512P is intended for permanently

powered operation. The V_RTCcapor V_RTCbatpin is connected

depending on whether a capacitor or battery is chosen for the

application. When the primary power, V_CC, fails and drops below

nvTIME Operation

The CY14B512P offers internal registers that contain clock,

alarm, watchdog, interrupt, and control functions. The RTC

registers occupy a separate address space from nvSRAM and

are accessible through read RTC (RDRTC) and write RTC

(WRTC) instructions on register addresses 0x00 to 0x0F. Internal

double buffering of the clock and the timer information registers

prevents accessing transitional internal clock data during a read

or write operation. Double buffering also circumvents disrupting

normal timing counts or the clock accuracy of the internal clock

when accessing clock data. Clock and alarm registers store data

in BCD format.

V_SWITCHthe device switches to the backup power supply.

The clock oscillator uses very little current, which maximizes the

backup time available from the backup source. Regardless of the

clock operation with the primary source removed, the data stored

in the nvSRAM is secure, having been stored in the nonvolatile

elements when power was lost.

During backup operation, the CY14B512P consumes 0.35 µA

(typical) at room temperature. The user must choose capacitor

or battery values according to the application.

Clock Operations

Backup time values based on maximum current specifications

are shown in the following table. Nominal backup times are

approximately two times longer.

The clock registers maintain time up to 9,999 years in

one-second increments. The time can be set to any calendar

time and the clock automatically keeps track of days of the week

and month, leap years, and century transitions. There are eight

registers dedicated to the clock functions, which are used to set

time with a write cycle and to read time during a read cycle.

These registers contain the time of day in BCD format. Bits

defined as ‘0’ are currently not used and are reserved for future

use by Cypress.

Table 8. RTC Backup Time

Capacitor Value

0.1 F

Backup Time

72 hours

14 days

0.47 F

1.0 F

30 days

Reading the Clock

Using a capacitor has the obvious advantage of recharging the

backup source each time the system is powered up. If a battery

is used, a 3 V lithium is recommended and the CY14B512P

sources current only from the battery when the primary power is

removed. However, the battery is not recharged at any time by

the CY14B512P. The battery capacity must be chosen for total

anticipated cumulative down time required over the life of the

system.

The double-buffered RTC register structure reduces the chance

of reading incorrect data from the clock. The user must stop

internal updates to the CY14B512P time keeping registers

before reading clock data, to prevent reading of data in transition.

Stopping the register updates does not affect clock accuracy.

The updating process is stopped by writing a ‘1’ to the read bit

‘R’ (in the flags register at 0x00), and does not restart until a ‘0’

is written to the read bit. The RTC registers are read while the

internal clock continues to run. After a ‘0’ is written to the read bit

(‘R’), all RTC registers are simultaneously updated within 20 ms.

Stopping and Starting the Oscillator

The OSCEN bit in the calibration register at 0x08 controls the

enable and disable of the oscillator. This bit is nonvolatile and is

shipped to customers in the enabled (set to 0) state. To preserve

the battery life when the system is in storage, OSCEN must be

set to ‘1’. This turns off the oscillator circuit, extending the battery

life. If the OSCEN bit goes from disabled to enabled, it takes

approximately one second (two seconds maximum) for the

oscillator to start.

Setting the Clock

Setting the write bit ‘W’ (in the flags register at 0x00) to a ‘1’ stops

updates to the time keeping registers and enables the time to be

set. The correct day, date, and time is then written into the

registers and must be in 24-hour BCD format. The time written

is referred to as the Base Time. This value is stored in nonvolatile

registers and used in the calculation of the current time.

Resetting the write bit to ‘0’ transfers the values of timekeeping

registers to the actual clock counters, after which the clock

resumes normal operation.

While system power is off, if the voltage on the backup supply

(V_RTCcapor V_RTCbat) falls below their respective minimum level,

the oscillator may fail. The CY14B512P has the ability to detect

oscillator failure when system power is restored. This is recorded

in the oscillator fail flag (OSCF) of the flags register at the

address 0x00. When the device is powered on (V_CCgoes above

V_SWITCH) the OSCEN bit is checked for enabled status. If the

OSCEN bit is enabled and the oscillator is not active within the

first 5 ms, the OSCF bit is set to ‘1’. The system must check for

this condition and then write ‘0’ to clear the flag. Note that in

addition to setting the OSCF flag bit, the time registers are reset

to the Base Time (see Setting the Clock on page 16), which is

the value last written to the timekeeping registers. The control or

calibration registers and the OSCEN bit are not affected by the

oscillator failed condition.

If the time written to the timekeeping registers is not in the correct

BCD format, each invalid nibble of the RTC registers continue

counting to 0xF before rolling over to 0x0 after which RTC

resumes normal operation.

Note After ‘W’ bit is set to ‘0’, values written into the timekeeping,

alarm, calibration, and interrupt registers are transfered to the

RTC time keeping counters in t_RTCptime. These counter values

must be saved to nonvolatile memory either by initiating a

Software/Hardware STORE or AutoStore operation. While

working in AutoStore disabled mode, perform a STORE

operation after t_RTCptime while writing into the RTC registers for

the modifications to be correctly recorded.

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CY14B512P

The value of OSCF must be reset to ‘0’ when the time registers

are written for the first time. This initializes the state of this bit

which may have become set when the system was first powered

on.

Alarm

The alarm function compares user programmed values of alarm

time and date (stored in the registers 0x01-5) with the

corresponding time of day and date values. When a match

occurs, the alarm internal flag (AF) is set and an interrupt is

generated on INT pin if alarm interrupt enable (AIE) bit is set.

To reset OSCF, set the write bit ‘W’ (in the flags register at 0x00)

to a ‘1’ to enable writes to the flags register. Write a ‘0’ to the

OSCF bit and then reset the write bit to ‘0’ to disable writes.

There are four alarm match fields: date, hours, minutes, and

seconds. Each of these fields has a match bit that is used to

determine if the field is used in the alarm match logic. Setting the

match bit to ‘0’ indicates that the corresponding field is used in

the match process. Depending on the match bits, the alarm

occurs as specifically as once a month or as frequently as once

every minute. Selecting none of the match bits (all 1s) indicates

that no match is required and therefore, alarm is disabled.

Selecting all match bits (all 0s) causes an exact time and date

match.

Calibrating the Clock

The RTC is driven by a quartz controlled crystal with a nominal

frequency of 32.768 kHz. Clock accuracy depends on the quality

of the crystal and calibration. The crystals available in market

typically have an error of +20 ppm to +35 ppm. However,

CY14B512P employs a calibration circuit that improves the

accuracy to +1 / –2 ppm at 25 °C. This implies an error of

+2.5 seconds to -5 seconds per month.

The calibration circuit adds or subtracts counts from the oscillator

divider circuit to achieve this accuracy. The number of pulses that

are suppressed (subtracted, negative calibration) or split (added,

positive calibration) depends upon the value loaded into the five

calibration bits found in calibration register at 0x08. The

calibration bits occupy the five lower order bits in the calibration

register. These bits are set to represent any value between ‘0’

and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates

positive calibration and a ‘0’ indicates negative calibration.

Adding counts speeds the clock up and subtracting counts slows

the clock down. If a binary ‘1’ is loaded into the register, it

corresponds to an adjustment of 4.068 or –2.034 ppm offset in

oscillator error, depending on the sign.

There are two ways to detect an alarm event: by reading the AF

flag or monitoring the INT pin. The AF flag in the flags register at

0x00 indicates that a date or time match has occurred. The AF

bit is set to ‘1’ when a match occurs. Reading the flags register

clears the alarm flag bit (and all others). A hardware interrupt pin

may also be used to detect an alarm event.

To set, clear or enable an alarm, set the ‘W’ bit (in the flags

register - 0x00) to ‘1’ to enable writes to alarm registers. After

writing the alarm value, clear the ‘W’ bit back to ‘0’ for the

changes to take effect.

Note CY14B512P requires the alarm match bit for seconds

(0x02 - D7) to be set to ‘0’ for proper operation of alarm flag and

Interrupt.

Calibration occurs within a 64-minute cycle. The first 62 minutes

in the cycle may, once per minute, have one second shortened

by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is

loaded into the register, only the first two minutes of the

64-minute cycle are modified. If a binary 6 is loaded, the first 12

are affected, and so on. Therefore, each calibration step has the

effect of adding 512 or subtracting 256 oscillator cycles for every

125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm

of adjustment per calibration step in the calibration register.

Watchdog Timer

The watchdog timer is a free running down counter that uses the

32-Hz clock (31.25 ms) derived from the crystal oscillator. The

oscillator must be running for the watchdog to function. It begins

counting down from the value loaded in the watchdog timer

register.

The timer consists of a loadable register and a free running

counter. On power-up, the watchdog time out value in register

0x07 is loaded into the counter load register. Counting begins on

power-up and restarts from the loadable value any time the

Watchdog Strobe (WDS) bit is set to ‘1’. The counter is compared

to the terminal value of ‘0’. If the counter reaches this value, it

causes an internal flag and an optional interrupt output. You can

prevent the time out interrupt by setting WDS bit to ‘1’ prior to the

counter reaching ‘0’. This causes the counter to reload with the

watchdog time out value and to be restarted. As long as the user

sets the WDS bit prior to the counter reaching the terminal value,

the interrupt and WDT flag never occur.

To determine the required calibration, the CAL bit in the flags

register (0x00) must be set to ‘1’. This causes the INT pin to

toggle at a nominal frequency of 512 Hz. Any deviation

measured from the 512 Hz indicates the degree and direction of

the required correction. For example, a reading of 512.01024 Hz

indicates a +20 ppm error. Hence, a decimal value of –10

(001010b) must be loaded into the calibration register to offset

this error.

Note Setting or changing the calibration register does not affect

the test output frequency.

To set or clear CAL, set the write bit ‘W’ (in the flags register at

0x00) to ‘1’ to enable writes to the flags register. Write a value to

CAL, and then reset the write bit to ‘0’ to disable writes.

New time out values are written by setting the watchdog write bit

to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out

value bits D5-D0 are enabled to modify the time out value. When

WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function

enables a user to set the WDS bit without concern that the

watchdog timer value is modified. A logical diagram of the

watchdog timer is shown in Figure 21 on page 18. Note that

setting the watchdog time out value to ‘0’ disables the watchdog

function.

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CY14B512P

The output of the watchdog timer is the flag bit WDF that is set if

the watchdog is allowed to time out. If the watchdog interrupt

enable (WIE) bit in the interrupt register is set, a hardware

interrupt on INT pin is also generated on watchdog timeout. The

flag and the hardware interrupt are both cleared when the user

the output pin driver on INT pin. These two bits are located in the

interrupt register and can be used to drive level or pulse mode

output from the INT pin. In pulse mode, the pulse width is

internally fixed at approximately 200 ms. This mode is intended

to reset a host microcontroller. In the level mode, the pin goes to

its active polarity until the flags register is read by the user. This

mode is used as an interrupt to a host microcontroller. The

control bits are summarized in the following section.

reads the flags register.

.

Figure 21. Watchdog Timer Block Diagram

Interrupts are only generated while working on normal power and

are not triggered when system is running in backup power mode.

Clock

Oscillator

1 Hz

Divider

Note CY14B512P generates valid interrupts only after the

Power-Up RECALL sequence is completed. All events on INT

pin must be ignored for t_FAduration after power-up.

32,768 KHz

32 Hz

Zero

Compare

WDF

Counter

Interrupt Register

Watchdog Interrupt Enable (WIE): When set to ‘1’, the

watchdog timer drives the INT pin and an internal flag when a

watchdog time out occurs. When WIE is set to ‘0’, the watchdog

timer only affects the WDF flag in flags register.

Load

WDS

Register

Q

D

WDW

Alarm Interrupt Enable (AIE): When set to ‘1’, the alarm match

drives the INT pin and an internal flag. When AIE is set to ‘0’, the

alarm match only affects the AF flag in flags register.

Q

Watchdog

Register

write to

Watchdog

Register

Power Fail Interrupt Enable (PFE): When set to ‘1’, the power

fail monitor drives the pin and an internal flag. When PFE is set

to ‘0’, the power fail monitor only affects the PF flag in flags

register.

Power Monitor

The CY14B512P provides a power management scheme with

power fail interrupt capability. It also controls the internal switch

to backup power for the clock and protects the memory from low

High/Low (H/L): When set to ‘1’, the INT pin is active HIGH and

the driver mode is push pull. The INT pin drives HIGH only when

V_CCis greater than V_SWITCH. When set to a ‘0’, the INT pin is

V

_CCaccess. The power monitor is based on an internal band gap

active LOW and the drive mode is open drain. The INT pin must

be pulled up to Vcc by a 10 k resistor while using the interrupt in

active LOW mode.

reference circuit that compares the V_CCvoltage to V_SWITCH

threshold.

As described in the section AutoStore Operation on page 4,

when V_SWITCHis reached as V_CCdecays from power loss, a data

STORE operation is initiated from SRAM to the nonvolatile

elements, securing the last SRAM data state. Power is also

switched from V_CCto the backup supply (battery or capacitor) to

operate the RTC oscillator.

Pulse/Level (P/L): When set to ‘1’ and an interrupt occurs, the

INT pin is driven for approximately 200 ms. When P/L is set to a

‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until

the flags register is read.

When an enabled interrupt source activates the INT pin, an

external host reads the flags register to determine the cause.

Remember that all flags are cleared when the register is read. If

the INT pin is programmed for level mode, then the condition

clears and the INT pin returns to its inactive state. If the pin is

programmed for pulse mode, then reading the flag also clears

the flag and the pin. The pulse does not complete its specified

duration if the flags register is read. If the INT pin is used as a

host reset, the flags register is not read during a reset.

When operating from the backup source, read and write

operations to nvSRAM are inhibited and the RTC functions are

not available to the user. The RTC clock continues to operate in

the background. The updated RTC time keeping registers data

are available to the user after V_CCis restored to the device (see

AutoStore or Power-Up RECALL on page 29).

Interrupts

The CY14B512P has a flags register, interrupt register, and

Interrupt logic that can signal interrupt to the microcontroller.

There are three potential sources for interrupt: watchdog timer,

power monitor, and alarm timer. Each of these can be individually

enabled to drive the INT pin by appropriate setting in the interrupt

register (0x06). In addition, each has an associated flag bit in the

flags register (0x00) that the host processor uses to determine

the cause of the interrupt. The INT pin driver has two bits that

specify its behavior when an interrupt occurs.

Flags Register

The flags register has three flag bits: WDF, AF, and PF, which

can be used to generate an interrupt. These flags are set by the

watchdog timeout, alarm match, or power fail monitor

respectively. The processor can either poll this register or enable

interrupts to be informed when a flag is set. These flags are

automatically reset when the register is read. The flags register

is automatically loaded with the value 0x00 on power-up (except

for the OSCF bit. See Stopping and Starting the Oscillator on

page 16).

An interrupt is raised only if both a flag is raised by one of the

three sources and the respective interrupt enable bit in interrupts

register is enabled (set to ‘1’). After an interrupt source is active,

two programmable bits, H/L and P/L, determine the behavior of

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Writes to the RTC register are performed using the WRTC

instruction. Writing RTC timekeeping registers and control

registers, except for the flag register needs the ‘W’ bit of the flag

register to be set to ‘1’. The internal counters are updated with

the new date and time setting when the ‘W’ bit is cleared to ‘0’.

All the RTC registers can also be written in burst mode using the

WRTC instruction.

Accessing the Real Time Clock through SPI

CY14B512P uses 16 registers for RTC. These registers can be

read out or written to by accessing all 16 registers in burst mode

or accessing each register, one at a time. The RDRTC and

WRTC instructions are used to access the RTC.

All the RTC registers can be read in burst mode by issuing the

RDRTC instruction and reading all 16 bytes without bringing the

CS pin HIGH. The ‘R’ bit must be set while reading the RTC

timekeeping registers to ensure that transitional values of time

are not read.

Figure 22. RTC Recommended Component Configuration

Recommended Values

Y1 = 32.768 KHz (12.5 pF)

C

= 10 pF

= 67 pF

1

2

X

C1

out

Y1

Note: The recommended values for C1 and C2 include

X

C2

in

board trace capacitance.

Figure 23. Interrupt Block Diagram

WDF

WIE

PF

WDF - Watchdog timer flag

WIE - Watchdog interrupt

enable

Watchdog

Timer

V

CC

P/L

PF - Power fail flag

PFE - Power fail enable

Power

Monitor

AF - Alarm flag

AIE - Alarm interrupt enable

Driver

INT

PFE

P/L - Pulse level

H/L - High / low

VINT

H/L

V

SS

AF

Clock

Alarm

AIE

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Table 9. RTC Register Map^{[2, 3]}

Register

BCD Format Data

Function/Range

D7

D6

D5

D4

D3

D2

D1

D0

0x0F

0x0E

10s years

Years

Years: 00–99

0

10s

months

Months

Months: 01–12

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0

10s day of month

0

10s hours

Day of month

Day of week

Day of month: 01–31

Day of week: 01–07

Hours: 00–23

0

Hours

Minutes

Seconds

10s minutes

10s seconds

Minutes: 00–59

Seconds: 00–59

Calibration values^[4]

OSCEN

(0)

0

Cal sign

(0)

Calibration (00000)

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

WDS (0) WDW (0)

WDT (000000)

Watchdog^[4]

Interrupts^[4]

WIE (0)

M (1)

AIE (0)

PFE (0)

0

H/L (1)

P/L (0)

0

10s alarm date

10s alarm hours

Alarm day

Alarm, Day of month: 01–31

Alarm, Hours: 00–23

Alarm, Minutes: 00–59

Alarm, Seconds: 00–59

Centuries: 00–99

Flags^[4]

Alarm hours

Alarm minutes

Alarm seconds

Centuries

10 alarm minutes

10 alarm seconds

10s centuries

WDF

AF

PF

OSCF^[5]

0

CAL (0)

W (0)

R (0)

Notes

2. ( ) designates values shipped from the factory.

3. The unused bits of RTC registers are reserved for future use and should be set to ‘0’.

4. This is a binary value, not a BCD value.

5. When user resets OSCF flag bit, the flags register will be updated after t

time.

RTCp

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Table 10. Register Map Detail

Register

Description

Time Keeping - Years

D7

D6

D5

D4

D3

D2

D1

D0

0x0F

10s years

Years

Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four

bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.

Time Keeping - Months

D7

D6

D5

D4

D3

D2

D1

D0

0x0E

0x0D

0

10s month

Months

Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper

nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12.

Time Keeping - Date

D7

D6

D5

D4

D3

D2

D1

D0

0

10s day of month

Day of month

Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0

to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap

years are automatically adjusted for.

Time Keeping - Day

D7

D6

D5

D4

D3

D2

D1

D0

0

Day of week

0x0C

Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that

counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated

with the date.

Time Keeping - Hours

D7

D6

D5

D4

D3

D2

D1

D0

0x0B

0x0A

0

10s hours

Hours

Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from

0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23.

Time Keeping - Minutes

D7

D6

D5

D4

D3

D2

D1

D0

0

10s minutes

Minutes

Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper

nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59.

Time Keeping - Seconds

D7

D6

D5

D4

D3

D2

D1

D0

0x09

0X08

0

10s seconds

Seconds

Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper

nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59.

Calibration/Control

D7

D6

D5

D4

D3

D2

D1

D0

OSCEN

0

Calibration

sign

Calibration

OSCEN Oscillator enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the oscillator

saves battery or capacitor power during storage.

Calibration Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.

sign

Calibration These five bits control the calibration of the clock.

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Table 10. Register Map Detail (continued)

Register

Description

WatchDog Timer

0x07

D7

D6

D5

D4

D3

D2

D1

D0

WDS

WDW

WDT

WDS

Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The

bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0.

WDW

Watchdog write enable. Setting this bit to ‘1’ disables any WRITE to the watchdog timeout value (D5–D0). This enables

the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows bits D5–D0 to

be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in

Watchdog Timer on page 17.

WDT

Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a

multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of ‘1’) to 2 seconds (setting

of 3 Fh). Setting the watchdog timer register to ‘0’ disables the timer. These bits can be written only if the WDW bit was

set to 0 on a previous cycle.

Interrupt Status/Control

0x06

D7

D6

D5

D4

D3

D2

D1

D0

WIE

AIE

PFE

0

H/L

P/L

0

WIE

AIE

Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT pin and

the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag.

Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm

match only affects the AF flag.

PFE

Power fail enable. When set to ‘1’, the alarm match drives the INT pin and the PF flag. When set to ‘0’, the power fail

monitor affects only the PF flag.

0

Reserved for future use.

H/L

P/L

HIGH/LOW. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0,’ the INT pin is open drain, active LOW.

Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for approximately

200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags register is read.

Alarm - Day

D7

D6

D5

D4

D3

D2

D1

Alarm date

D0

0x05

M

0

10s alarm date

Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.

M

Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit

to ignore the date value.

Alarm - Hours

D7

D6

D5

D4

D3

D2

D1

Alarm hours

D0

0x04

M

0

10s alarm hours

Contains the alarm value for the hours and the mask bit to select or deselect the hours value.

M

Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match

circuit to ignore the hours value.

Alarm - Minutes

D7

D6

D5

D4

D3

D2

D1

D0

0x03

M

10s alarm minutes

Alarm minutes

Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.

M

Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the match

circuit to ignore the minutes value.

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CY14B512P

Table 10. Register Map Detail (continued)

Register

Description

Alarm - Seconds

D7

D6

D5

D4

D3

D2

D1

D0

0x02

M

10s alarm seconds

Alarm seconds

Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.

M

Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the match

circuit to ignore the seconds value.

Time Keeping - Centuries

0x01

D7

D6

D5

10s centuries

D4

D3

D2

D1

Centuries

D0

Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble

contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.

Flags

0x00

D7

D6

D5

D4

D3

D2

D1

D0

WDF

AF

PF

OSCF

0

CAL

W

R

WDF

AF

Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being reset

by the user. It is cleared to ‘0’ when the flags register is read or on power-up.

Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with

the match bits = ‘0’. It is cleared when the flags register is read or on power-up.

PF

Power fail flag. This read only bit is set to ‘1’ when power falls below the power fail threshold V_SWITCH. It is cleared to

0 when the flags register is read or on power-up.

OSCF

Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation. This

indicates that RTC backup power failed and clock value is no longer valid. This bit survives the power cycle and is never

cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. When user resets

OSCF flag bit, the bit will be updated after t_RTCptime.

CAL

W

Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin resumes

normal operation. This bit defaults to 0 (disabled) on power-up.

Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC registers,

alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes the contents of

the RTC registers to be transferred to the time keeping counters if the time has changed . This transfer process takes

t_RTCptime to complete. This bit defaults to 0 on power-up.

R

Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen during

the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does not require

‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up.

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CY14B512P

Best Practices

nvSRAM products have been used effectively for over 27 years.

While ease-of-use is one of the product’s main system values,

experience gained working with hundreds of applications has

resulted in the following suggestions as best practices:

again rewrite the nvSRAM into the desired state as a safeguard

against events that might flip the bit inadvertently such as

program bugs and incoming inspection routines.

■ The V_CAPvalue specified in this data sheet includes a minimum

and a maximum value size. Best practice is to meet this

requirement and not exceed the maximum V_CAPvalue because

the nvSRAM internal algorithm calculates V_CAPcharge and

discharge time based on this maximum V_CAPvalue. Customers

that want to use a larger V_CAPvalue to make sure there is extra

store charge and store time should discuss their V_CAPsize

selection with Cypress to understand any impact on the V_CAP

voltage level at the end of a t_RECALLperiod.

■ The nonvolatile cells in thisnvSRAM product are delivered from

Cypress with 0x00 written in all cells. Incoming inspection

routines at customer or contract manufacturer’s sites

sometimes reprogram these values. Final NV patterns are

typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End

product’s firmware should not assume an NV array is in a set

programmed state. Routines that check memory content

values to determine first time system configuration, cold or

warm boot status, and so on should always program a unique

NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex

or more random bytes) as part of the final system

manufacturing test to ensure these system routines work

consistently.

■ When base time is updated, these updates are transferred to

the time keeping registers when ‘W’ bit is set to ‘0’. This transfer

takes t_RTCptime to complete. It is recommended to initiate

software STORE or Hardware STORE after t_RTCptime to save

the base time into nonvolatile memory.

■ Power-up boot firmware routines should rewrite the nvSRAM

into the desired state (for example, AutoStore Enabled). While

the nvSRAM is shipped in a preset state, best practice is to

Document #: 001-53872 Rev. *E

Page 24 of 36

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CY14B512P

Transient voltage (< 20 ns) on

any pin to ground potential .................. –2.0 V to V_CC+ 2.0 V

Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. These user guidelines are not tested.

Package power dissipation

capability (T_A= 25 °C) .................................................. 1.0 W

Storage temperature ............................... –65 °C to + 150 °C

Maximum accumulated storage time

Surface mount lead soldering

temperature (3 Seconds).......................................... +260 °C

DC output current (1 output at a time, 1s duration). .... 15 mA

At 150 °C ambient temperature....................... 1000 h

At 85 °C ambient temperature..................... 20 Years

Static discharge voltage.......................................... > 2001 V

(per MIL-STD-883, method 3015)

Ambient temperature with

power applied .......................................... –55 °C to + 150 °C

Latch up current..................................................... > 200 mA

Supply voltage on V_CCrelative to V_SS.........–0.5 V to + 4.1 V

Table 11. Operating Range

DC voltage applied to outputs

in high Z state......................................–0.5 V to V_CC+ 0.5 V

Range

Industrial

Ambient Temperature

V_CC

–40 °C to + 85 °C

2.7 V to 3.6 V

Input voltage........................................–0.5 V to V_CC+ 0.5 V

DC Electrical Characteristics

Over the Operating Range (V_CC= 2.7 V to 3.6 V)

Parameter

V_CC

Description

Test Conditions

Min

2.7

–

Typ^[6]

3.0

–

Max

3.6

10

Unit

V

Power supply voltage

I_CC1

Average V_cccurrent At f_SCK= 40 MHz

mA

Values obtained without output loads (I_OUT= 0 mA)

Average V_CCcurrent All inputs don’t care, V_CC= Max

during STORE Average current for duration t_STORE

Average V_CAPcurrent All inputs don’t care. Average current for duration

I_CC2

I_CC4

–

10

5

mA

during AutoStore

cycle

t_STORE

I_SB

V_CCstandby current CS > (V_CC– 0.2 V). V_IN< 0.2 V or > (V_CC– 0.2 V).

‘W’ bit set to ‘0’. Standby current level after nonvolatile

cycle is complete. Inputs are static. f = 0 MHz

–

5

mA

[7]

Input leakage current V_CC= Max, V_SS< V_IN< V_CC

(except HSB)

–1

–100

–1

–

+1

µA

I_IX

Input leakage current V_CC= Max, V_SS< V_IN< V_CC

(for HSB)

I_OZ

Off state output

leakage current

V_CC= Max, V_SS< V_OUT< V_CC

V_IH

V_IL

Input HIGH voltage

Input LOW voltage

2.0

–

V_CC+ 0.5

V

V_SS– 0.5

0.8

–

V_OH

V_OL

Output HIGH voltage I_OUT= –2 mA

Output LOW voltage I_OUT= 4 mA

2.4

–

V

–

0.4

180

V

Storage capacitor

Between V_CAPpin and V_SS, 5 V rated

61

68

µF

V_CAP

Notes

6. Typical values are at 25 °C, V = V (Typ). Not 100% tested.

CC

7. The HSB pin has I

= -2 µA for V of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This

OUT

O

H

O

H

O

L

parameter is characterized but not tested.

Document #: 001-53872 Rev. *E

Page 25 of 36

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Data Retention and Endurance

Parameter

Description

Min

Unit

Years

K

DATA_R

NV_C

Data retention

20

Nonvolatile STORE operations

1,000

Capacitance

Parameter^[8]

Description

Input capacitance

Test Conditions

T_A= 25 °C, f = 1 MHz,

_CC= V_CC(Typ)

Max

6

Unit

pF

C_IN

V

C_OUT

Output pin capacitance

8

pF

Thermal Resistance

Parameter^[8]

Description

Thermal resistance

(junction to ambient)

Test Conditions

16-SOIC

Unit

Θ_JA

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA / JESD51.

55.17

°C / W

Θ_JC

Thermal resistance

(junction to case)

2.64

°C / W

Figure 24. AC Test Loads and Waveforms

577 Ω

R1

577 Ω

3.0 V

Output

3.0 V

Output

R1

R2

789 Ω

R2

789 Ω

5 pF

30 pF

AC Test Conditions

Input pulse levels.................................................... 0 V to 3 V

Input rise and fall times (10% to 90%)......................... < 3 ns

Input and output timing reference levels........................ 1.5 V

Note

8. These parameters are guaranteed by design and are not tested.

Document #: 001-53872 Rev. *E

Page 26 of 36

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CY14B512P

RTC Characteristics

Parameters

Description

Min

1.8

–

Typ^[9]

Max

3.6

0.35

–

Units

V

V_RTCbat

RTC battery pin voltage

3.0

–

[10]

I_BAK

RTC backup current

T_A(Min)

25 °C

µA

V

–

0.35

–

T_A(Max)

T_A(Min)

25 °C

–

0.5

3.6

2

[11]

V_RTCcap

RTC capacitor pin voltage

RTC oscillator time to start

1.6

1.5

1.4

–

3.0

–

V

T_A(Max)

V

tOCS

1

sec

μs

Ω

t_RTCp

RTC processing time from end of ‘W’ bit set to ‘0’

RTC backup capacitor charge current-limiting resistor

–

350

850

R_BKCHG

350

–

AC Switching Characteristics

25 MHz

(RDRTC Instruction)^[12]

40 MHz

Cypress

Alt. Parameter

Parameter

Description

Unit

Min

–

Max

40

–

Min

–

Max

25

–

f_SCK

t_CL

f_SCK

t_WL

t_WH

t_CE

t_CES

t_CEH

t_SU

t_H

Clock frequency, SCK

Clock pulse width LOW

Clock pulse width HIGH

CS HIGH time

MHz

ns

11

20

10

5

18

20

10

5

t_CH

–

t_CS

–

t_CSS

t_CSH

t_SD

CS setup time

–

CS hold time

–

Data in setup time

Data in hold time

HOLD hold time

–

t_HD

5

–

5

–

t_HH

t_HD

t_CD

t_V

5

–

5

–

t_SH

HOLD setup time

Output valid

5

–

5

–

t_CO

–

9

–

15

–

[13]

t_HHZ

t_HZ

t_LZ

t_HO

t_DIS

HOLD to output HIGH-Z

HOLD to output LOW-Z

Output hold time

–

15

–

[13]

t_HLZ

t_OH

–

0

t_HZCS

Output disable time

–

25

–

25

Notes

9. Typical values are at 25 °C, V = V (Typ). Not 100% tested.

CC

10. Current drawn from either V

or V

when V < V

RTCcap

RTCbat CC SWITCH

11. If V

> 0.5 V or if no capacitor is connected to V

pin, the oscillator starts in tOCS time. If a backup capacitor is connected and vrtccap < 0.5 V, the capacitor

RTCcap

must be allowed to charge to 0.5 V for oscillator to start.

12. Applicable for RTC opcode cycles, address cycles, and dataout cycles.

13. These parameters are guaranteed by design and are not tested.

Document #: 001-53872 Rev. *E

Page 27 of 36

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CY14B512P

Figure 25. Synchronous Data Timing (Mode 0)

t

CS

SCK

SI

t

CSS

CH

CL

t

CSH

t

HD

SD

VALID IN

t

CO

OH

HZCS

HI-Z

SO

Figure 26. HOLD Timing

CS

SCK

t

HH

t

SH

HOLD

SO

t

HLZ

HHZ

Document #: 001-53872 Rev. *E

Page 28 of 36

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CY14B512P

AutoStore or Power-Up RECALL

CY14B512P

Parameter

Description

Unit

Min

–

Max

20

8

[14]

Power-Up RECALL duration

STORE cycle duration

ms

ns

V

t_FA

[15]

[16]

–

t_STORE

t_DELAY

Time allowed to complete SRAM write cycle

Low voltage trigger level

V_CCrise time

–

25

2.65

–

V_SWITCH

–

[17]

t_VCCRISE

150

–

µs

V

[17]

HSB output disable voltage

HSB high to nvSRAM active time

HSB high active time

1.9

5

V_HDIS

[17]

t_LZHSB

–

µs

ns

[17]

t_HHHD

–

500

Switching Waveforms

Figure 27. AutoStore or Power-Up RECALL^[18]

V_CC

V_SWITCH

V_HDIS

15

t_VCCRISE

t_STORE

Note

t_HHHD

19

Note

HSB OUT

AutoStore

t_DELAY

t_LZHSB

t_DELAY

POWER-

UP

RECALL

t_FA

Read & Write

Inhibited

(RWI)

Read & Write

POWER-UP

RECALL

BROWN

OUT

AutoStore

POWER

DOWN

AutoStore

POWER-UP

RECALL

Notes

14. t starts from the time V rises above V

SWITCH.

FA

CC

15. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

16. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time t

17. These parameters are guaranteed by design and are not tested.

.

DELAY

18. Read and write cycles are ignored during STORE, RECALL, and while V is below V

CC

SWITCH.

19. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.

Document #: 001-53872 Rev. *E

Page 29 of 36

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Software Controlled STORE/RECALL Cycles

CY14B512P

Parameter

Description

Unit

Min

–

Max

200

100

t_RECALL

RECALL duration

Soft sequence processing time

µs

[20, 21]

t_SS

–

Figure 28. Software STORE Cycle^[21]

Figure 29. Software RECALL Cycle^[21]

CS

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

SCK

SI

SCK

SI

0

1

0

1

0

t

RECALL

STORE

HI-Z

RWI

RDY

RWI

RDY

Figure 30. AutoStore Enable Cycle

Figure 31. AutoStore Disable Cycle

CS

0

1

2

3

4

5

6

7

1

0

1

2

3

4

5

6

7

SCK

SI

SCK

SI

0

1

0

1

0

1

0

1

t

SS

t

SS

HI-Z

RWI

RDY

RWI

RDY

Notes

20. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

21. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-53872 Rev. *E

Page 30 of 36

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Hardware STORE Cycle

CY14B512P

Parameter

Description

Unit

Max

Min

t_PHSB

Hardware STORE pulse width

15

–

ns

Figure 32. Hardware STORE Cycle^[22]

Write Latch set

t

PHSB

HSB (IN)

t

STORE

t

HHHD

DELAY

HSB (OUT)

RWI

t

LZHSB

Write Latch not set

t

PHSB

HSB (IN)

HSB pin is driven HIGH to V

only by Internal

CC

100 K: resistor, HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven LOW.

HSB (OUT)

RWI

t

DELAY

Note

22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

Document #: 001-53872 Rev. *E

Page 31 of 36

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Ordering Information

Ordering Code

Package Diagram

Package Type

Operating Range

CY14B512P-SFXIT

51-85022

16-pin SOIC

Industrial

CY14B512P-SFXI

All the above parts are Pb-free.

Ordering Code Definition

CY 14 B 512 P - SF X I T

Option:

T - Tape and Reel

Blank - Std.

Temperature:

I - Industrial (-40 °C to 85 °C)

Pb-free

Package:

SF - 16 SOIC

P - Serial (SPI) nvSRAM with RTC

Density:

Voltage:

B - 3.0 V

512 - 512 Kb

nvSRAM

14 -

Cypress

Document #: 001-53872 Rev. *E

Page 32 of 36

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Package Diagram

Figure 33. 16-pin (300 mil) SOIC Package, 51-85022

51-85022 *C

Document #: 001-53872 Rev. *E

Page 33 of 36

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CY14B512P

Acronyms

Document Conventions

Units of Measure

Symbol

Acronym

BCD

Description

Binary coded decimal

Unit of Measure

CMOS

CRC

Complementary metal oxide semiconductor

Cyclic redundancy check

Clock phase

°C

Hz

kbit

kHz

KΩ

μA

mA

μf

degree Celsius

Hertz

CPHA

1024 bits

CPOL

Clock polarity

kilo Hertz

kilo ohms

micro Amperes

milli Ampere

micro Farad

mega Hertz

micro seconds

milli second

nano seconds

pico Farad

pico seconds

Volts

EEPROM

Electrically erasable programmable

read-only memory

EIA

I/O

Electronic Industries Alliance

Input/output

JEDEC

nvSRAM

RoHS

RWI

Joint Electron Devices Engineering Council

nonvolatile static random access memory

Restriction of hazardous substances

Read and write inhibited

MHz

μs

ms

ns

SOIC

SONOS

SPI

Small outline integrated circuit

Silicon-oxide-nitride-oxide-silicon

Serial peripheral interface

pF

ps

V

RTC

Real time clock

Ω

ohms

W

Watts

Document #: 001-53872 Rev. *E

Page 34 of 36

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Document History Page

Document Title: CY14B512P 512-Kbit (64 K × 8) Serial (SPI) nvSRAM with Real Time Clock

Document Number: 001-53872

Orig. of

Change

Submission

Date

Rev.

ECN No.

Description of Change

**

2733272 GVCH/AESA

2758904 GVCH

07/16/09

New Data Sheet

*A

09/02/2009 Moved data sheet status from preliminary to Final

Removed commercial temperature related specs

Added thermal resistance values for 16-SOIC package

Added note to Write Sequence (WRITE) description

Changed V_RTCbatmax value from 3.3V to 3.6V

Changed R_BKCHGmin value from 450Ω to 350Ω

Updated footnote 8

*B

*C

2839453 GVCH/PYRS

01/06/10

Changed STORE cycles to QuantumTrap from 200K to 1 Million

Updated I_BAKRTC backup current specification unit from nA to μA

Updated Figure 2

Added Contents

3013834

GVCH

08/30/2010 Changed ground naming convention from GND to V_SS

Table 1: Added more clarity on HSB pin operation

Hardware STORE and HSB Pin Operation: Added more clarity on HSB pin

operation

Updated Power-Down description

Power On Reset: Added status of bits 4-6

Table 4: Added definition of bits 4-6

Updated Figure 7, Figure 25, Figure 26, and Figure 27

Updated footnote 19

Added Figure 30 and Figure 31

Updated footnote 19

Removed t_DHSBparameter

Updated Figure 32

Added Acronyms and Units of Measure.

*D

*E

3038143

3135772

GVCH

09/24/2010 Added watermark as “For Evaluation Samples only. Production will be

upported with the next revision silicon in SOIC package.”

Updated HOLD Pin Operation, Figure 20 and Figure 26 to indicate that CS

pin must remain LOW along with HOLD pin to pause serial communication.

01/12/2011 Hardware STORE and HSB Pin Operation: Added more clarity on HSB pin

operation

Updated Setting the Clock description

Updated ‘W’ bit desription in Register Map Detail table

Updated Best Practices

Added t_RTCpparameter to RTC Characteristics table

Updated t_LZHSBparameter description

Fixed typo in Figure 27

Document #: 001-53872 Rev. *E

Page 35 of 36

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Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Clocks & Buffers

Interface

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 001-53872 Rev. *E

Revised January 12, 2011

Page 36 of 36

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型号：	CY14B512P
厂家：	CYPRESS
描述：	512-Kbit (64 K × 8) Serial (SPI) nvSRAM with Real Time Clock 512千位（一个64 K × 8 ）串行（ SPI）的nvSRAM与实时时钟静态存储器时钟
文件：	总36页 (文件大小：1598K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY14B512P [CYPRESS]

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