BCM4318SKFBG [CYPRESS]
Telecom Circuit, 1-Func, CMOS, PBGA144, FBGA-144;
| 型号： | BCM4318SKFBG |
| 厂家： | 
CYPRESS |
| 描述： | Telecom Circuit, 1-Func, CMOS, PBGA144, FBGA-144 电信 电信集成电路 |
| 文件： | 总55页 (文件大小：1234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The following document contains information on Cypress products. Although the document is marked with the name “Broadcom”,
the company that originally developed the specification, Cypress will continue to offer these products to new and existing
customers.
CONTINUITY OF SPECIFICATIONS
There is no change to this document as a result of offering the device as a Cypress product. Any changes that have been made
are the result of normal document improvements and are noted in the document history page, where supported. Future revisions
will occur when appropriate, and changes will be noted in a document history page.
CONTINUITY OF ORDERING PART NUMBERS
Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in
this document.
FOR MORE INFORMATION
Please visit our website at www.cypress.com or contact your local sales office for additional information about Cypress products
and services.
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ABOUT CYPRESS
Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive,
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Cypress Semiconductor Corporation
Document Number: 002-15046 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 19, 2016
Preliminary Data Sheet
BCM4318/BCM4318E
AirForce One™ Chip 802.11g MAC/Baseband/Radio
GENERAL DESCRIPTION
FEATURES
•
Extreme Integration: IEEE 802.11a/g compliant CMOS MAC /
Baseband and 2.4-GHz Direct Conversion Radio (802.11a radio
support provided by an external BCM2060 5-GHz Direct
Conversion Radio)
BCM4318E includes Encore signal processing for industry-
leading receive sensitivity and extended range:
The BCM4318/BCM4318E provide One Chip IEEE 802.11g
MAC, Baseband, and Direct Conversion Radio functions to
provide wireless LAN connectivity supporting data rates from
1 Mbps to 54 Mbps in the 2.4-GHz band. With the addition of the
BCM2060, the solution can also support 802.11a for 1-Mbps to
54-Mbps connectivity in the 5-GHz band. In addition, the
BCM4318E includes leading-edge Encore DSP technology for
best-in-class receive sensitivity and extended range, enabling
whole home coverage. The BCM4318E also supports high-
speed performance mode (125-Mbps) that is backward-
compatible with standard 802.11b/g. Broadcom’s revolutionary
One Chip architecture implemented in bulk CMOS process
greatly reduces the external components typically required for
802.11a/g implementations, resulting in significant cost, power,
and footprint savings.
•
-
-
–74 dBm at 54Mbps
–76 dBm with external LNA
•
•
High level of integration with direct conversion radio architecture
minimizes external circuitry, leading to lowest cost, lowest power,
and smallest footprint implementation
Flexible support for a variety of system bus interfaces including:
PCI, Mini PCI, CardBus, PCMCIA/Compact Flash, and SDIO
(4-wire, 1-wire, and SPI)
•
•
Programmable data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48,
and 54 Mbps
Supports high-speed performance mode of 125-Mbps that is
backward-compatible with standard 802.11b/g; BCM4318E in
196-pin package supports Afterburner mode (125-Mbps)
24-bit IV and 40-bit/104-bit key WEP encryption support
128-bit IV and 128-bit key WEP2 encryption support
System support for 128-bit AES
IEEE 802.1x support
Programmable MAC with advanced DMA architecture and 32-bit
bus interface
Dynamic Power Management under driver control
WHQL-certified drivers for Windows® XP, Windows® Me,
Windows® 2000, Windows® 98SE, and Windows® 98 operating
systems
State-of-the-art security is provided by industry standardized
system support for WEP, WEP2, and AES encryption, coupled
with TKIP and IEEE 802.1x support. Increased performance and
a significant reduction in host-CPU utilization in both client and
access device configurations are achieved through hardware
support of encryption/decryption.
•
•
•
•
•
•
•
The BCM4318/BCM4318E employ a native 32-bit bus using a
direct memory access architecture that results in significant
performance improvements over competing solutions in both
transfer rate and CPU utilization. Various system bus interfaces
are included for maximum flexibility: Mini PCI, PCI, CardBus,
PCMCIA/Compact Flash, and SDIO/SPI.
•
All drivers are portable for embedded operating systems such as
Linux® and Windows® CE
•
•
•
•
•
Meets PCI Power Management Interface version 1.1 (ACPI)
Wi-Fi® compliant; supports SecureEZSetup™
Support for Bluetooth® Coexistence Algorithm
3.3/1.8V supply, 3/5V PCI I/O
144-ball FBGA or 196-ball FBGA (adds UART, PCI/Cardbus and
BCM2060 interfaces)
The BCM4318/BCM4318E employ adaptive equalization
algorithms resulting in significant resistance to multipath,
providing substantial improvements in real-world performance.
BCM4318/BCM4318E
Balun
WEP/AES Encryption
Diversity
Switch
LPF
LPF
Host I/F
Host I/F:
T/R
Switch
CF,
SDIO,
PCMCIA,
PCI
802.11a/g
BB
GPIO
1.8V
3.3V
MAC
2.4 GHz CMOS
Direct Conversion
Radio
Power
Amp
Buffers
Balun
BCM2060
and FE
(Optional .11a)
SPROM
20MHz
Figure 1: BCM4318/BCM4318E System Diagram
4318_4318E-DS01-405-R
16215 Alton Parkway • P.O. Box 57013 • Irvine, California 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710
11/09/04
REVISION HISTORY
Revision
Date
Change Description
4318_4318E-DS01-R
4318_4318E-DS00-R
11/09/04
10/26/04
Updated ESD value in Table 13 on page 36.
Initial release.
Broadcom Corporation
P.O. Box 57013
16215 Alton Parkway
Irvine, California 92619-7013
© 2004 by Broadcom Corporation
All rights reserved
Printed in the U.S.A.
Broadcom®, the pulse logo, AirForce One™, and SecureEZSetup™ are trademarks of Broadcom Corporation and/or
its subsidiaries in the United States and certain other countries. Bluetooth® is a trademark of the Bluetooth SIG. All other
trademarks mentioned are the property of their respective owners.
This data sheet (including, without limitation, the Broadcom component(s) identified herein) is not designed, intended,
or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control,
hazardous substances management, or other high risk application. BROADCOM PROVIDES THIS DATA SHEET "AS-
IS", WITHOUT WARRANTY OF ANY KIND. BROADCOM DISCLAIMS ALL WARRANTIES, EXPRESSED AND
IMPLIED, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT.
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
TABLE OF CONTENTS
Section 1: Functional Description......................................................................................1
Introduction .................................................................................................................................................. 1
IEEE 802.11a/g MAC Features............................................................................................................... 2
IEEE 802.11a/g MAC Description........................................................................................................... 2
IEEE 802.11a/g PHY Features ............................................................................................................... 4
IEEE 802.11a/g PHY Description ........................................................................................................... 4
Integrated Radio Transceiver...................................................................................................................... 5
Receiver Path ............................................................................................................................................... 6
Transmitter Path........................................................................................................................................... 7
Calibration .................................................................................................................................................... 7
Crystal Oscillator ......................................................................................................................................... 7
Section 2: Pin Assignments................................................................................................9
144-Pin BGA Assignments.......................................................................................................................... 9
196-Pin BGA Assignments........................................................................................................................ 11
Section 3: Signal Descriptions .........................................................................................14
144-Pin BGA Descriptions......................................................................................................................... 14
196-Pin BGA Descriptions......................................................................................................................... 20
Strapping Options...................................................................................................................................... 30
SDIO Pin Descriptions............................................................................................................................... 31
Section 4: Electrical Characteristics................................................................................34
Recommended Operating Conditions...................................................................................................... 34
Current Consumption ................................................................................................................................ 35
Local Oscillator Specifications................................................................................................................. 36
Environmental Characteristics ................................................................................................................. 36
Section 5: RF Specifications.............................................................................................37
General RF Specifications......................................................................................................................... 37
Receiver RF Specifications....................................................................................................................... 37
Transmitter RF Specifications .................................................................................................................. 38
Section 6: Timing Characteristics....................................................................................39
PCMCIA/Compact Flash Timing................................................................................................................ 39
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Page iii
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
SPROM Timing............................................................................................................................................42
JTAG Timing ...............................................................................................................................................43
Section 7: Package Specifications .................................................................................. 44
Section 8: Ordering Information ...................................................................................... 46
Broadcom Corporation
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Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
LIST OF FIGURES
Figure 1: BCM4318/BCM4318E System Diagram ...............................................................................................i
Figure 2: IEEE 802.11a/g MAC Block Diagram.................................................................................................. 3
Figure 3: IEEE 802.11a/g PHY Block Diagram .................................................................................................. 5
Figure 4: Radio Functional Block Diagram......................................................................................................... 6
Figure 5: Recommended Oscillator Configuration.............................................................................................. 8
Figure 6: BCM4318/BCM4318E 144-Pin Top View Assignments...................................................................... 9
Figure 7: BCM4318/BCM4318E 196-Pin Top View Assignments.................................................................... 11
Figure 8: Signal Connections to SDIO Card (SD 4-Bit Mode).......................................................................... 31
Figure 9: Signal Connections to SDIO Card (SD 1-Bit Mode).......................................................................... 32
Figure 10: Signal Connections to SDIO Card (SPI Mode)................................................................................ 32
Figure 11: Signal Connections to PCMCIA/Compact Flash ............................................................................. 33
Figure 12: PCMCIA/Compact Flash Read Timing Diagram ............................................................................. 39
Figure 13: PCMCIA/Compact Flash Write Timing Diagram ............................................................................. 41
Figure 14: BCM4318/BCM4318E 144-Pin FBGA............................................................................................. 44
Figure 15: BCM4318/BCM4318E 196-Pin FBGA............................................................................................. 45
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Page v
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Broadcom Corporation
Page vi
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
LIST OF TABLES
Table 1: Differences Among BCM4318/BCM4318E and 144-Pin/196-Pin Packages........................................ 1
Table 2: 20-MHz Crystal Requirements ............................................................................................................. 7
Table 3: 144-Pin Assignments............................................................................................................................ 9
Table 4: 196-Pin Assignments.......................................................................................................................... 12
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions .................................................................. 14
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions .................................................................. 20
Table 7: SPROM Mode and Size ..................................................................................................................... 30
Table 8: Bus Mode Configurations ................................................................................................................... 31
Table 9: SDIO Pin Descriptions........................................................................................................................ 31
Table 10: Recommended Operating Conditions .............................................................................................. 34
Table 11: Current Consumption ....................................................................................................................... 35
Table 12: Local Oscillator Specifications.......................................................................................................... 36
Table 13: Environmental Characteristics.......................................................................................................... 36
Table 14: General RF Specifications................................................................................................................ 37
Table 15: Receiver RF Specifications .............................................................................................................. 37
Table 16: Transmitter RF Specifications .......................................................................................................... 38
Table 17: PCMCIA/Compact Flash Read Timing Characteristics .................................................................... 40
Table 18: PCMCIA/Compact Flash Write Timing Characteristics .................................................................... 42
Table 19: SPROM Timing Characteristics........................................................................................................ 42
Table 20: JTAG Timing Characteristics............................................................................................................ 43
Table 21: BCM4318/BCM4318E Ordering Information .................................................................................... 46
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Page vii
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Broadcom Corporation
Page viii
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Section 1: Functional Description
INTRODUCTION
The BCM4318/BCM4318E are highly integrated, single-chip, IEEE Std 802.11a/g MAC, baseband and 2.4-GHz direct
conversion radios designed for client cards, modules, and WOMBO (Wireless On Motherboard) solutions. The revolutionary
Broadcom® One Chip architecture greatly reduces the external components typically required for IEEE 802.11a/g
implementations, resulting in significant savings in cost, power, and board space.
The BCM4318/BCM4318E offer flexible support for a variety of system bus interfaces including PCI, Mini PCI, CardBus,
PCMCIA, Compact Flash, and SDIO/SPI. Customer-specified parameters, such as System Vendor ID and Wireless LAN
MAC address, are stored in a small external SPROM.
In addition, the BCM4318E chip includes leading-edge Encore DSP technology for improved receive sensitivity, which
extends the range and enables whole home coverage. The BCM4318E chip also supports a UART interface for WLAN
design support.
The package options are 144 pin and 196 pin, as follows:
•
•
•
The BCM4318 chip in the 196-pin package adds PCI, CardBus, and BCM2060 IEEE 802.11a radio interfaces, but does
not support Encore DSP technology.
The BCM4318E chip in the 196-pin package adds PCI, CardBus, and BCM2060 IEEE 802.11a radio interfaces. It
includes Encore DSP technology, and it supports a UART interface.
The BCM4318E chip in the 144-pin package provides PCMCIA, Compact Flash, and SDIO/SPI bus interfaces. It
includes Encore DSP technology.
Table 1 lists differences between the BCM4318 and BCM4318E chips and between the 144-pin and 196-pin packages.
Table 1: Differences Among BCM4318/BCM4318E and 144-Pin/196-Pin Packages
Encore
and
After-
burner
IEEE
SPROM GPIO 802.11a
PHY
(Mini)
PCI
Compact SDIO/
Chip
Package
CardBus PCMCIA
Flash
SPI
BCM4318
196-pin
BCM4318KFBG
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SDIO/
SPI
Yes
Yes
8
8
Yes
Yes
–
BCM4318E 196-pin
BCM4318EKFBG
SDIO/
SPI/
UART1
Encore
and
After-
burner
BCM4318E 144-pin
BCM4318SKFBG
–
–
Yes
Yes
SDIO/
SPI
Yes
6
–
Encore
Notes:
1. The UART option is only available in the BCM4318E 196-pin package option, BCM4318EKFBG.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 1:Functional Description
Page 1
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
IEEE 802.11A/G MAC FEATURES
The IEEE 802.11a/g MAC features include:
•
•
•
•
•
•
•
•
•
•
Programmable Access Point (AP) or station (STA) functionality
Programmable Independent Basic Service Set (IBSS), or infrastructure mode
Passive scanning, 802.11h (including radio detection)
Network Allocation Vector (NAV), Interframe Space (IFS), and Timing Synchronization Function (TSF) functionality
Backoff
RTS/CTS procedure
Transmission of response frames (ACK/CTS)
Address filtering of RX frames as specified by IBSS rules
Multirate support
Programmable Target Beacon Transmission Time (TBTT), beacon transmission/cancellation, and programmable
Announcement Traffic Indication Message (ATIM) window
•
•
CF conformance: setting NAV for neighborhood Point Coordination Function (PCF) operation
Privacy through a variety of Wired Equivalent Privacy (WEP) encryption schemes and dynamically programmable WEP
keys
•
•
Power management
Statistics counters for MIB support
IEEE 802.11A/G MAC DESCRIPTION
The MAC core provides the support required for the transmission and reception of sequences of packets, together with
related timing, without any packet-by-packet driver interaction. Time-critical tasks requiring response times of only a few
milliseconds are handled in the MAC core. This achieves the required timing on the medium while keeping the host driver
easier to write and maintain. Also, incoming packets are buffered in the MAC core, which allows the MAC driver to process
them in bursts as and when it gets access to the buffers.
The MAC driver interacts with the MAC core to prepare queues of packets to transmit and to analyze and forward received
packets. The internal blocks of the MAC core are connected to a Programmable State Machine (PSM) through an internal
bus. See Figure 2.
Broadcom Corporation
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Section 1:Functional Description
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Host Interface (Host Registers)
Code
Memory
N TX FIFOs
1 RX FIFO
TX Status
FIFO
Template
Power
Management
WEP / AES Encryption
Programmable
State Machine
(PSM)
RX Engine
TX Engine
Timing and
Control
Data
Memory
PHY Interface
Figure 2: IEEE 802.11a/g MAC Block Diagram
The host interface consists of registers for controlling and monitoring the status of the MAC core and interfacing with the
TX/RX FIFOs. There are four transmit FIFOs: asynchronous, priority, Broadcast/Multicast (BC/MC) and ATIM. Each transmit
FIFO is 3-KB deep. In addition to the transmit FIFOs, there is a 1-KB template area for response frames. Whenever the host
has a frame to transmit, the host queues the frame into one of the transmit FIFOs with a TX descriptor containing TX control
information. The PSM schedules the transmission on the medium depending on the frame type, transmission rules in IEEE
802.11 protocol, and the current medium occupancy scenario. After the transmission is completed and an ACK is received,
a TX status is returned to the host confirming the same in the TX status FIFO.
The MAC contains a single 4.5-KB RX FIFO. Whenever a frame is received, the frame is sent to the host along with an RX
descriptor that contains additional information about the frame reception conditions.
The Power Management block maintains the information regarding the power management state of the core (and the
associated STAs in case of an AP) to help in dynamic decisions by the core regarding frame transmission.
The WEP block performs the required WEP operation on the TX/RX frames. The WEP block supports separate transmit and
receive keys with four shared keys and 50 link-specific keys. The link-specific keys are used to establish a secure link
between any two STAs, with the required key being shared between only those two STAs, hence excluding all the other
STAs in the same network from deciphering the communication between those two STAs. The WEP block supports the
following encryption schemes that can be selected on a per-destination basis:
•
•
None: the WEP block acts as a pass-through
WEP: 40-bit secure key and 24-bit IV as defined in IEEE Std 802.11-1999
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 1:Functional Description
Page 3
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
•
•
•
•
WEP128: 104-bit secure key and 24-bit IV
WEP2: 128-bit secure key and 128-bit IV
TKIP: IEEE 802.11i draft
AES: IEEE 802.11i draft
The transmit engine is responsible for the byte flow from the TX FIFO to the PHY interface through the WEP block and the
addition of an FCS (CRC-32) as required by IEEE 802.11. Similarly, the receive engine is responsible for byte flow from the
PHY interface to the RX FIFO through the WEP block and for detection of errors in the RX frame.
The timing block performs the TSF, NAV, and IFS functionality as described in IEEE 802.11-1999.
The Programmable State Machine (PSM) coordinates the operation of different hardware blocks required for both
transmission and reception. The PSM also maintains the statistics counters required for MIB support.
IEEE 802.11A/G PHY FEATURES
The integrated IEEE 802.11a/g physical layer device (PHY) features include:
•
•
•
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbps
Both long and optional short preamble
Resistance to multipath (>250 nanoseconds RMS delay spread) with maximal ratio combining rake receiver for data
rates of 1 and 2 Mbps and adaptive equalization for data rates of 5.5 Mbps and 11 Mbps
•
•
•
•
Programmable antenna selection
Automatic Gain Control (AGC)
Available per-packet channel quality and signal strength measurements
Dedicated interface to the BCM2060 5-GHz Direct Conversion Radio for IEEE 802.11a support
IEEE 802.11A/G PHY DESCRIPTION
The Wireless Local Area Network (WLAN) PHY integrated on this IC provides baseband processing at data rates of 1, 2,
5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 Mbps, as specified in the Direct Sequence Spread Spectrum (DSSS) and Orthogonal
Frequency Division Multiplexing (OFDM) portions of IEEE 802.11a/g. This core acts as an intermediary between the MAC
on the one hand, and the integrated 2.4-GHz Radio or external 5-GHz radio (BCM2060) integrated circuit on the other,
converting back and forth between packets and baseband waveforms.
An overview of the operations carried out by the PHY is shown in Figure 3. On transmission, physical layer framing is first
added to a packet received from the MAC. The resulting bits are then scrambled, modulated, filtered, and finally sent to the
RF via a pair of 80-MHz, 6-bit Digital-to-Analog Converters (DACs). Modulation is selected per packet as either Differential
Binary Phase Shift Keying (DBPSK), Differential Quadrature Phase Shift Keying (DQPSK), or Complementary Code Keying
(CCK). The first two types of modulation provide data rates of 1 Mbps and 2 Mbps, respectively, and require spreading the
modulated symbols with a length 11 Barker code. CCK modulation is used for data rates of 5.5 Mbps and 11 Mbps and
inherently includes the spreading.
Broadcom Corporation
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Section 1:Functional Description
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
MAC Interface
Frame and
Scramble
Descramble
and Deframe
RX FSM
TX FSM
Rake Receiver
and DPSK
Demodulation
Equalizer and
CCK
Demodulation
Modulate/Spread
PHY
Registers
Timing and Frequency
Correction
TXFilter
Sync/AGC
COFDM
DAC
ADC
Radio Interface: 2.4 GHz (Internal) or 5 GHz (external BCM2060)
Figure 3: IEEE 802.11a/g PHY Block Diagram
On reception, the reverse operations are performed. The In-phase (I) and Quadrature (Q) baseband waveforms coming from
a pair of 40-MHz, 6-bit Analog-to-Digital Converters (ADCs) are demodulated into bits and then descrambled and deframed.
To improve the likelihood of correct reception, however, the waveforms are subjected to timing and frequency offset
corrections (adapted throughout packet reception) prior to demodulation. Further, using a maximal ratio combining rake
receiver for data rates of 1 Mbps and 2 Mbps and an adaptive equalizer at the higher bit rates, the PHY is able to work in
extreme multipath channels, successfully receiving even at a data rate of 11 Mbps, with delay spreads exceeding
200 nanoseconds RMS.
Additionally, the receiver must perform synchronization at the start of packet reception, which includes Automatic Gain
Control (AGC), antenna selection, and initial frequency offset and timing estimation. A state machine coordinates all of these
activities (using information from the PHY framing) to decide how to handle the packet body.
A register interface accessible from both the MAC and the host allows programming of the PHY parameters, although
information generally needed per packet is passed as part of the packet itself. For example, this is true of preamble type and
data rate on transmission, as well as the channel metrics Signal Quality (SQ) and signal strength on reception. The internal
2.4-GHz radio and BCM2060 registers are accessed indirectly through the PHY registers.
INTEGRATED RADIO TRANSCEIVER
The BCM4318/BCM4318E include an integrated RF transceiver that has been optimized for use in 2.4-GHz Wireless LAN
systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 1:Functional Description
Page 5
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
globally available 2.4-GHz unlicensed ISM band. With an external transmit power amplifier, it develops full output power per
the IEEE 802.11b/g Specification. The transmit and receive sections include all on-chip filtering, mixing, and gain control
functions.
Rx I
LPF
LPF
RF Input
LNA
Rx Q
Sys_Clock
LO
Generation
20 MHz
PLL
XTAL
Tx I
LPF
LPF
RF Output
AMP
Tx Q
Control I/F
Control
Interface
Calibration
Figure 4: Radio Functional Block Diagram
RECEIVER PATH
The BCM4318/BCM4318E have a wide dynamic range, direct conversion receiver. The chip employs high-order on-chip
channel filtering to ensure reliable operation in the noisy 2.4-GHz ISM band. The excellent noise figure of the receiver makes
an external LNA unnecessary.
Leading-edge Encore DSP technology is included on BCM4318E for improved receive sensitivity and extended range,
enabling whole home coverage.
Broadcom Corporation
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Section 1:Functional Description
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
TRANSMITTER PATH
The BCM4318/BCM4318E include a linear transmitter capable of delivering up to +6 dBm while meeting the IEEE 802.11g
specification. The output power is adjustable in 0.6-dB steps, down to –15 dBm. Baseband data is up-converted directly to
the 2.4-GHz ISM band.
CALIBRATION
The BCM4318/BCM4318E feature on-chip calibration, eliminating process variation across components. This enables the
device to be used in high-volume applications because calibration routines are not required during manufacturing test. These
calibration routines are performed periodically in the course of normal radio operation. An example of this is automatic
calibration of the baseband filters for optimum transmit and receive performance.
CRYSTAL OSCILLATOR
The recommended configuration for the crystal oscillator including all external components is shown in Figure 5.
Table 2: 20-MHz Crystal Requirements
Parameter
Value
Frequency
Mode
20.000 MHz
AT cut, fundamental
16 pF
Load capacitance
ESR
50Ω maximum
Frequency stability
±10 ppm at 25°C
±10 ppm 0°C to +85°C
±3 ppm/year max first year, ±1 ppm thereafter
300 µW maximum
40,000 minimum
< 5 pf
Aging
Drive level
Q-factor
Shunt capacitance
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 1:Functional Description
Page 7
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
XTAL IN
36 pF
36 pF
Crystal
XTAL OUT
220Ω
Figure 5: Recommended Oscillator Configuration
Broadcom Corporation
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Section 1:Functional Description
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Section 2: Pin Assignments
144-PIN BGA ASSIGNMENTS
Figure 6 and Table 3 show the pin assignments for the 144-pin BGA device.
1 2 3 4 5 6 7 8 9 10 11 12
A
B
C
D
E
F
G
H
J
K
L
M
Figure 6: BCM4318/BCM4318E 144-Pin Top View Assignments
Table 3: 144-Pin Assignments
Pin
Name
Pin
Name
Pin
Name
Pin
Name
A1
A2
A3
A4
A5
A6
RESERVED
AVDD_DAC
TDO
B1
B2
B3
B4
B5
B6
RESERVED
AVSS_DAC
PLLGND
C1
C2
C3
C4
C5
C6
XTSSI2
D1
D2
D3
D4
D5
D6
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ANT_SELP
RESERVED
RESERVED
RESERVED
RX_PU
TCK
EXT_POR
RF_DISABLE
VDDIO
TR_SW_RX_PU
GPHY_EXT_LNA_
GAIN
TEST_SE
A7
A8
A9
SPROM_CLK
VDDIO
B7
B8
B9
SPROM_DOUT
VSS
C7
C8
C9
SPROM_DIN
SPROM_CS
SDIO_CMD
D7
D8
D9
ANT_SELN
SDIO_CLK
D12
SDIO_DATA_3
SDIO_DATA_2
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 2:Pin Assignments
Page 9
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 3: 144-Pin Assignments (Cont.)
Name Pin Name
Pin
Name
Pin
Pin
Name
A10 SDIO_DATA_0
A11 VDD
B10 D4
B11 D5
B12 D13
C10 IREQ
C11 D15
C12 A10
D10 D6
D11 VSS
D12 A11
A12 D11
E1
E2
E3
E4
E5
E6
E7
E8
E9
RGND
RGND
RGND
AVDD_ADC
TDI
F1
F2
F3
F4
F5
F6
F7
F8
F9
RGND
G1
G2
G3
G4
G5
G6
G7
G8
G9
LNAINP
H1
H2
H3
H4
H5
H6
H7
H8
H9
LNAINN
VDDLF
VDDRX
RGND
VSS
RGND
RGND
VSS
RGND
AVSS_ADC
JTAG_TRST
TR_SW_TX_PU
TX_PU
PLLDVDD
GPIO_1
D14
VSS
TMS
VDD
SDIO_DATA_1
D3
GPIO_0
GPIO_2
VDDBUS
VDDBUS
CE0
GPIO_4
A2
D7
E10 CE1
E11 OE
E12 A9
F10 A8
F11 A7
F12 WAIT
G10 A6
G11 D2
G12 A5
H10 A3
H11 A4
H12 REG
J1
RGND
K1
K2
K3
K4
K5
K6
K7
K8
K9
VDDPA
L1
PA_OUT
M1
M2
M3
M4
M5
M6
M7
M8
M9
BGREF
J2
GNDPA
RGND
RGND
RGND
RGND
RGND
RGND
A1
VDDPA
L2
VDDDR
RGND
CP_FB
VDDPLL
VDDCP
VDDXTAL
RGND
VDD
VDDTX
VDDLO
RGND
J3
GNDPA
RGND
L3
J4
L4
J5
VDDVCO
VDDPLL_REF
VDD4W
RGND
L5
XTALOUT
XTALIN
RGND
J6
L6
J7
L7
J8
L8
RGND
J9
GPIO_5
L9
GPIO_3
J10
J11
J12
A0
K10 RESET
K11 INPACK
K12 D1
L10
L11
L12
VDDIO
D10
M10 OTP_VDD
M11 XTAL_PU
M12 WE
D8
D0
D9
Broadcom Corporation
Page 10
Section 2:Pin Assignments
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
196-PIN BGA ASSIGNMENTS
Figure 7 and Table 4 show the pin assignments for the 196-pin BGA device.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Figure 7: BCM4318/BCM4318E 196-Pin Top View Assignments
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 2:Pin Assignments
Page 11
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 4: 196-Pin Assignments
Pin
Name
Pin
Name
Pin
Name
Pin
Name
A1
A2
A3
A4
A5
A6
A7
AVSS_DAC
FREF_2
PLLGND
RX_PU
B1
B2
B3
B4
B5
B6
B7
AVDD_DAC
XTEMPRSSI
PLLDVDD
TMS
C1
C2
C3
C4
C5
C6
C7
TXP_Q
D1
D2
D3
D4
D5
D6
TXN_I
TXN_Q
TXP_I
JTAG_TRST
TCK
XNRSSI
XTSSI2
PLLVDD
TDO
TDI
EXT_POR
TR_SW_TX_PU
ANT_SELN
APHY_PA_PD
TR_SW_RX_PU
ANT_SELP
TEST_SE
APHY_PA_CNTRL_ D7
0
APHY_EXT_LNA_G
AIN
A8
A9
RF_DISABLE
TX_PU
B8
B9
GPHY_EXT_LNA_
GAIN
C8
C9
APHY_SRI_E
D8
APHY_EXT_LNA_
PU
APHY_SRI_DI
APHY_SRI_DO
D9
SDIO_DATA_3/
UART_TX
A10 APHY_SYNTH_PU
B10 SPROM_DIN
C10 SDIO_DATA_1/
UART_DCD
D10 CSTSCHG
A11 APHY_SRI_C
A12 SPROM_DOUT
B11 SPROM_CS
C11 PCI_INT
D11 PCI_AD_2
D12 PCI_AD_4
B12 SDIO_DATA_0/
UART_CTS
C12 PCI_AD_5
A13 SDIO_DATA_2/
UART_DTR
B13 SDIO_CMD/
UART_RTS
C13 PCI_AD_6
C14 PCI_AD_3
D13 PCI_AD_7
D14 PCI_CBE_0
A14 PCI_AD_0
B14 PCI_AD_1
E1
E2
E3
E4
E5
E6
E7
E8
E9
XWRSSI
XTSSI5
F1
F2
F3
F4
F5
F6
F7
F8
F9
RESERVED
RESERVED
RXP_I
G1
G2
G3
G4
G5
G6
G7
G8
G9
RGND
RGND
RGND
RXN_Q
VDDBUS
VSS
H1
H2
H3
H4
H5
H6
H7
H8
H9
RGND
VDDLF
RGND
RXP_Q
VDDBUS
VSS
AVDD_ADC
AVSS_ADC
UART_RX
VDD
RXN_I
CMOUT
UART_RI
VSS
UART_DSR
VDD
VSS
VSS
VSS
VSS
VSS
SPROM_CLK
VSS
VSS
VSS
E10 SDIO_CLK/
UART_CLK
F10 PCI_AD_14
G10 PCI_AD_15
H10 PCI_AD_16
E11 VESD
F11 PCI_AD_11
F12 PCI_AD_13
F13 PCI_PAR
G11 PCI_CBE_1
G12 PCI_PERR
G13 PCI_STOP
G14 PCI_SERR
H11 PCI_CBE_2
H12 PCI_TRDY
H13 PCI_CLK
E12 PCI_AD_10
E13 PCI_AD_9
E14 PCI_AD_8
F14 PCI_AD_12
H14 PCI_DEVSEL
Broadcom Corporation
Page 12
Section 2:Pin Assignments
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 4: 196-Pin Assignments (Cont.)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
J1
LNAINP
VDDRX
RGND
K1
K2
K3
K4
K5
K6
K7
K8
K9
LNAINN
RGND
L1
RGND
M1
M2
M3
M4
M5
M6
M7
M8
M9
VDDPA
J2
L2
GNDPA
RGND
VDDPA
J3
RGND
L3
GNDPA
RGND
J4
VDDBUS
VDDBUS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
GPIO_0
GPIO_6
L4
RGND
J5
L5
RGND
VDDVCO
VDDPLL_REF
VDD4W
RGND
J6
L6
RGND
J7
VSS
L7
RGND
J8
GPIO_1
VSS
L8
RGND
J9
L9
GPIO_5
OTP_VDD
PCI_AD_28
PCI_AD_23
PCI_IDSEL
PCI_AD_22
GPIO_2
J10
J11
J12
J13
J14
VSS
K10 PCI_RST
K11 VDD
L10
L11
L12
L13
L14
M10 GPIO_7
PCI_AD_17
PCI_FRAME
PCI_AD_18
PCI_IRDY
M11 PCI_GNT
M12 PCI_AD_24
M13 PCI_AD_26
M14 PCI_CBE_3
K12 PCI_AD_20
K13 PCI_AD_21
K14 PCI_AD_19
N1
N2
N3
N4
N5
N6
N7
N8
N9
PA_OUT
VDDDR
RGND
P1
P2
P3
P4
P5
P6
P7
P8
P9
BGREF
VDDTX
VDDLO
RGND
CP_FB
VDDPLL
VDDCP
VDDXTAL
RGND
XTALOUT
XTALIN
RGND
RGND
GPIO_4
GPIO_3
N10 PCMCIA_SEL
N11 PCI_CLKRUN
N12 PCI_REQ
P10 XTAL_PU
P11 PCI_PME
P12 PCI_AD_31
P13 PCI_AD_30
P14 PCI_AD_27
N13 PCI_AD_29
N14 PCI_AD_25
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 2:Pin Assignments
Page 13
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Section 3: Signal Descriptions
The signal name, type, and description of each pin in the BCM4318/BCM4318E 144-pin FBGA package are listed in Table 5.
The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/
pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. See also
Table 8 on page 31 for resistor strapping options.
144-PIN BGA DESCRIPTIONS
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions
Signal Name
Pin
Type
Description
PCMCIA/Compact Flash
D0
J12
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
PCMCIA/Compact Flash Data Bus.
D1
K12
G11
E08
B10
B11
D10
E09
J11
D2
D3
D4
D5
D6
D7
D8
D9
L12
L11
A12
D09
B12
G07
C11
D10
D11
D12
D13
D14
D15
Broadcom Corporation
Page 14
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
A0
J10
In
PCMCIA/Compact Flash Address Bus.
A1
J09
In
A2
G09
H10
H11
G12
G10
F11
F10
E12
C12
D12
C10
In
A3
In
A4
In
A5
In
A6
In
A7
In
A8
In
A9
In
A10
A11
IREQ
In
In
Out (16 mA)
Interrupt Request. Asserted by the BCM4318/BCM4318E to
indicate to the host system that the BCM4318/BCM4318E requires
host software service. The interrupt signal at the interface is routed
by the system to one of the interrupt request signals on the
system's internal bus. The signal is negated when no interrupt is
requested.
CE0
CE1
F09
E10
In
In
Card Enable. The CE0 input enables even-numbered address
bytes, and CE1 enables odd-numbered address bytes. A
multiplexing scheme based on A0 and CE0 allows 8-bit hosts to
access all data on D[7:0], if desired. The Card Enable pins are
used to access both Common and Attribute Memory and to access
I/O.
OE
E11
F12
In
Output Enable. Used to gate Memory Read data from memory.
Hosts must negate the OE signal during write operations.
WAIT
Out (16 mA)
Extend Bus Cycle. Asserted to delay completion of the memory
access or I/O access cycle then in progress. This pin is also
sampled asynchronously at powerup to determine various bus
modes. See Table 8 on page 31 for details.
REG
H12
K11
In
Attribute Memory Select. When this signal is asserted, access is
limited to attribute memory. The REG signal is kept negated for all
common memory accesses.
INPACK
Out (16 mA)
Input Port Acknowledge. Asserted when the device is selected
and can respond to an I/O read cycle at the address on the address
bus. This signal is used by the host to control the enable of any
input data buffer between the card and the host system data bus.
This signal must be inactive until the card is configured.
WE
M12
K10
In
In
Write Enable. Used for strobing Memory Write data into memory.
RESET
Card Reset. Clears the Configuration Option register, placing the
device in an unconfigured (Memory Only interface) state. It also
signals the beginning of any additional card initialization. The
system must place the RESET signal in a High-Z state during card
powerup. The signal must remain high-impedance for at least 1 ms
after VDDBUS becomes valid.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 15
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
SDIO Bus Interface
SDIO_DATA_0
SDIO_DATA_1
SDIO_DATA_2
SDIO_DATA_3
SDIO_CLK
A10
E07
B09
A09
D08
C09
In/Out (8 mA) PU SDIO Data line 0 (see Table 9 on page 31).
In/Out (8 mA) PU SDIO Data line 1 (see Table 9 on page 31).
In/Out (8 mA) PU SDIO Data line 2 (see Table 9 on page 31).
In/Out (8 mA) PU SDIO Data line 3 (see Table 9 on page 31).
In PU
SDIO Clock (see Table 9 on page 31).
SDIO_CMD
In/Out (8 mA) PU SDIO Command Line (see Table 9 on page 31).
SPROM Bus Interface
SPROM_DIN
C07
In PD
SPROM Data In. Must be connected to the DOUT signal of the
SPROM. This pin is also used as a strapping option to determine
SPROM mode. See Table 7 on page 30 for details.
SPROM_DOUT
B07
A07
C08
In/Out (4 mA) PD SPROM Data Out. Must be connected to the DIN signal of the
SPROM (see note below). This pin is also used as a strapping
option to determine SPROM mode. See Table 7 on page 30 for
details.
SPROM_CLK
SPROM_CS
In/Out (4 mA) PD Serial Data Clock. Must be connected to the serial clock input of
the SPROM (typically called SK). This pin is also used as a
strapping option to determine SPROM mode. See
Table 7 on page 30 for details.
Out (4 mA) PU
SPROM Chip Select. Must be connected to the chip select input
of the SPROM (typically called CS).
This pin is also used as a strapping option to determine SPROM
mode. See Table 7 on page 30 for details.
JTAG Interface
TMS
E06
A04
E05
A03
F05
In PU
For normal operation, connect as described in the JTAG
specification (IEEE Std 1149.1). Otherwise, if JTAG is not used,
these pins can be left unconnected (NC), as they have internal pull-
ups. TCK is typically an 8-MHz clock
TCK
In PU
TDI
In PU
TDO
Out (8 mA) PU
PU
JTAG_TRST
GPIO Interface
GPIO_0
H07
G06
H08
M09
G08
K09
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
General Purpose Interface Pins. These pins are High-Z on
powerup and reset. Subsequently, they become inputs or outputs
through software control.
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
Crystal Oscillator
XTALOUT
XTALIN
M05
M06
20-MHz XTAL output.
20-MHz XTAL input.
Broadcom Corporation
Page 16
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
Misc. Control
BGREF
M01
Bandgap reference. Connect to GND through an external
2.87-kΩ resistor.
CP_FB
L04
B04
Feedback Filter. Refer to reference design.
EXT_POR
PU
External Power-on Reset. Allows connection of the external
power-on reset circuit. The internal POR can be used as the
default without requiring an external circuit. EXT_POR must be left
open for normal operation.
RF_DISABLE
A05
PU
PU
Radio Disable. Asserting this pin low disables the internal
2.4-GHz radio by shutting off everything (including the synthesizer)
in the radio other than the oscillator.
TEST_SE
C06
M11
Scan Enable Input. No Connect (NC).
XTAL_PU
XTAL Powerup. Pull high for normal operation.
Reserved Signals
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
A01
B01
C02
C03
C04
D01
D02
D03
D04
D05
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC).
No Connect (NC)
2.4-GHz RF Analog Interface (IEEE 802.11g)
ANT_SELN
D07
Out (12 mA)
Antenna Select Negative. Used to drive a diversity switch to
select which of the two antennas should be currently in use (for
switched diversity operation). ANT_SELN is the inverse of
ANT_SELP.
ANT_SELP
D06
Out (12 mA)
Out (12 mA)
Antenna Select Positive. Used to drive a diversity switch to select
which of the two antennas should be currently in use (for switched
diversity operation).
GPHY_EXT_LNA_ B06
GAIN
External LNA gain control.
LNAINN
LNAINP
PA_OUT
H01
G01
L01
In
LNA Differential Input.
LNA Differential Input.
In
Out
2.4-GHz Transmitter Output.
Output frequency = 2402–2495 MHz.
TR_SW_RX_PU
TR_SW_TX_PU
TX_PU
B05
F06
F07
C01
C05
Out (12 mA)
Out (12 mA)
Out (12 mA)
In
Receive Powerup Control Output for External TR Switch.
Transmit Powerup Control Output for External TR Switch.
External Power Amplifier Powerup.
XTSSI2
2.4-GHz Transmit Signal Strength Indicator.
External LNA Powerup.
RX_PU
Out (8 mA)
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 17
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
3.3V Digital
OTP_VDD
VDDBUS
VDDBUS
VDDIO
M10
F08
H09
A06
A08
L10
Connect to 3.3V digital supply.
VDDIO
VDDIO
1.8V Analog VDD Filter Group 1
AVDD_ADC
AVDD_DAC
PLLDVDD
E04
A02
G05
Connect this group of pins to a separately filtered 1.8V supply.
Connect this group of pins to a separately filtered 1.8V supply.
1.8V Analog VDD Filter Group 2
VDD4W
K07
L05
K06
L07
VDDPLL
VDDPLL_REF
VDDXTAL
1.8V Analog VDD Filter Group 3
VDDCP
VDDLF
L06
F02
M03
K05
Connect this group of pins to a separately filtered 1.8V supply.
VDDLO
VDDVCO
1.8V Analog VDD Filter Group 4
VDDDR
VDDRX
VDDTX
VDD 1.8V Digital
VDD
L02
G02
M02
Connect this group of pins to a separately filtered 1.8V supply.
A11
H06
L09
Connect to 1.8V digital supply.
VDD
VDD
1.8V Analog
VDDPA
VDDPA
K01
K02
Connect to filtered 1.8V supply.
Broadcom Corporation
Page 18
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 5: BCM4318/BCM4318E 144-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
RF Ground
GNDPA
GNDPA
PLLGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
Digital Ground
AVSS_ADC
AVSS_DAC
VSS
J02
K03
B03
E01
E02
E03
F01
F03
G03
H02
H03
J01
J03
J04
J05
J06
J07
J08
K04
K08
L03
L08
M04
M07
M08
RF GND.
F04
B02
B08
D11
G04
H04
H05
Digital GND.
VSS
VSS
VSS
VSS
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 19
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
196-PIN BGA DESCRIPTIONS
The signal name, type, and description of each pin in the BCM4318/BCM4318E 196-pin FBGA package are listed in Table 6.
The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-
down characteristics (PU = weak internal pull-up resistor, and PD = weak internal pull-down resistor), if any. See also
Table 8 on page 31 for resistor strapping options.
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions
Signal Name
PCI Bus and CardBus Interface (supports connections to PCI and CardBus systems)
Multiplexed 32-Bit Address and Data Lines.
Pin
Type
Description
PCI_AD_0
PCI_AD_1
PCI_AD_2
PCI_AD_3
PCI_AD_4
PCI_AD_5
PCI_AD_6
PCI_AD_7
PCI_AD_8
PCI_AD_9
PCI_AD_10
PCI_AD_11
PCI_AD_12
PCI_AD_13
PCI_AD_14
PCI_AD_15
PCI_AD_16
PCI_AD_17
PCI_AD_18
PCI_AD_19
PCI_AD_20
PCI_AD_21
PCI_AD_22
PCI_AD_23
PCI_AD_24
PCI_AD_25
PCI_AD_26
PCI_AD_27
PCI_AD_28
PCI_AD_29
A14
B14
D11
C14
D12
C12
C13
D13
E14
E13
E12
F11
F14
F12
F10
G10
H10
J11
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
J13
K14
K12
K13
L14
L12
M12
N14
M13
P14
L11
N13
Broadcom Corporation
Page 20
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
PCI_AD_30
PCI_AD_31
PCI_CBE_0
PCI_CBE_1
PCI_CBE_2
PCI_CBE_3
PCI_CLK
P13
P12
D14
G11
H11
M14
H13
N11
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In
Multiplexed 32-Bit Address and Data Lines.
Multiplexed Command/Byte Enables.
PCI Bus Clock.
PCI_CLKRUN
In/Out (16 mA)
As an input, this signal is driven low to indicate that PCI_CLK is
running; deasserted to indicate a request to stop PCI_CLK. As an
output, this signal is driven low to request that PCI_CLK continue
running. Supports Mini PCI.
PCI_DEVSEL
H14
In/Out (16 mA)
Asserted when a device indicates it is the destination for the
current bus cycle.
PCI_FRAME
PCI_GNT
PCI_IDSEL
PCI_INT
J12
M11
L13
C11
J14
F13
G12
P11
In/Out (16 mA)
In
Cycle Framing Signal.
Arbitration Signal Granting Access to the Bus.
Indicates that this device is the target of configuration bus cycles.
PCI INTA Interrupt Signal.
In
OD (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
OD (16 mA)
PCI_IRDY
PCI_PAR
PCI_PERR
PCI_PME
Master Ready Signal.
Even parity signal for PCI_AD[31:0] and PCI_CBE[3:0].
Parity Error.
Used to request a change in the device or system power state. The
assertion and deassertion of PCI_PME is asynchronous to
PCI_CLK. This signal has an open-drain output structure as
specified in the PCI Bus Local Bus Specification, Revision 2.2.
PCI_REQ
N12
K10
In/Out (16 mA)
In
Arbitration Signal Requesting Access to the Bus.
PCI_RST/RESET
PCI Bus (System) Reset. The pin becomes RESET for PC card
when in PCMCIA mode. The system must place the RESET signal
in a high-impedance state during card powerup. It must remain in
high-impedance state for at least 1 ms after VDDBUS becomes
valid.
PCI_SERR/WAIT
G14
In/Out (16 mA)
PCI System Error or PCMCIA /WAIT.
In PCI mode, this pin becomes the System Error signal.
In PCMCIA mode, this pin becomes the Extend Bus Cycle (wait).
It is asserted by the device to delay completion of the memory or
I/O access cycles when in progress.
This pin is also used as a strapping option to determine various bus
interface modes. See Table 8 on page 31 for details.
PCI_STOP
PCI_TRDY
G13
H12
In/Out (16 mA)
In/Out (16 mA)
Cycle Stop Signal. Asserted by the Target for Retry, Disconnect,
and Abort.
Target Ready Signal.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 21
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
PCMCIA / Compact Flash (multifunction pins shared with PCI)
D0
P14
N13
J12
In/Out (16 mA)
PCMCIA/Compact Flash Data Bus.
D1
In/Out (16 mA)
D2
In/Out (16 mA)
D3
A14
B14
C14
C12
D13
L11
P13
P12
D11
D12
C13
G13
E14
M13
N14
M12
L12
L14
K13
K12
J13
In/Out (16 mA)
D4
In/Out (16 mA)
D5
In/Out (16 mA)
D6
In/Out (16 mA)
D7
In/Out (16 mA)
D8
In/Out (16 mA)
D9
In/Out (16 mA)
D10
D11
D12
D13
D14
D15
A0
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In/Out (16 mA)
In
PCMCIA/Compact Flash Address Bus.
A1
In
A2
In
A3
In
A4
In
A5
In
A6
In
A7
In
A8
G11
F10
E13
F14
H11
F13
G12
C11
In
A9
In
A10
A11
A12
A13
A14
IREQ
In
In
In
In
In
Out (16 mA)
Interrupt Request. Asserted by the BCM4318/BCM4318E to
indicate to the host system that the device requires host software
service. The interrupt signal at the interface is routed by the system
to one of the interrupt request signals on the system's internal bus.
The signal is negated when no interrupt is requested.
PCMCIA_SEL
N10
In
Bus Mode Select. This pin is used as a strapping option to
determine various bus interface modes. See Table 8 on page 31
for details.
Broadcom Corporation
Page 22
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
CE0
CE1
D14
E12
In
In
Card Enable. The CE0 input enables even-numbered address
bytes, and CE1 enables odd-numbered address bytes. A
multiplexing scheme based on A0 and CE0 allows 8-bit hosts to
access all data on D[7:0], if desired. The Card Enable pins are
used to access both Common and Attribute Memory and to access
I/O.
OE
F11
In
In
Output Enable. Used to gate Memory Read data from memory.
Hosts must negate the OE signal during write operations.
REG
M14
Attribute Memory Select. When this signal is asserted, access is
limited to attribute memory. The REG signal is kept negated for all
common memory accesses.
INPACK
N12
Out (16 mA)
Input Port Acknowledge. Asserted when the BCM4318/
BCM4318E is selected and can respond to an I/O read cycle at the
address on the address bus. This signal is used by the host to
control the enable of any input data buffer between the card and
the host system data bus. This signal must be inactive until the
card is configured.
WE
WP
M11
N11
In
Write Enable. Used for strobing Memory Write data into memory.
Write Protect. Used to reflect the status of the Write Protect switch
of the PC card. If the Write Protect switch is present, PCMCIA_WP
is asserted by the card when the switch is enabled, and it is
negated when the switch is disabled. If the memory card has no
Write Protect switch, the card connects this line to VSS or
VDDBUS, depending on the condition of the card memory.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 23
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
SDIO/UART Bus Interfaces
SDIO_CLK/
UART_CLK
E10
B13
In PU
This pin has dual functions:
1
• In SDIO mode, it becomes the SDIO Clock (see
Table 9 on page 31).
•
In nonSDIO mode, it becomes the input from the UART Clock.
In/Out (8 mA) PU This pin has dual functions:
• In SDIO mode, it becomes the SDIO Command line (see
SDIO_CMD/
1
UART_RTS
Table 9 on page 31).
•
In nonSDIO mode, it becomes the output for the UART Request
to Send line.
SDIO_DATA_0/
B12
C10
In/Out (8 mA) PU This pin has dual functions:
• In SDIO mode, it becomes SDIO Data Line 0 (see
1
UART_CTS
Table 9 on page 31).
• In nonSDIO mode, it becomes the UART Clear to Send line.
SDIO_DATA_1/
In/Out (8 mA) PU This pin has dual functions:
1
• In SDIO mode, it becomes SDIO Data Line 1 (see
Table 9 on page 31).
UART_DCD
• In nonSDIO mode, it becomes the UART Data Carrier Detect
line.
SDIO_DATA_2/
A13
D09
In/Out (8 mA) PU This pin has dual functions:
1
• In SDIO mode, it becomes SDIO Data Line 2 (see
Table 9 on page 31).
UART_DTR
• In nonSDIO mode, it becomes the UART Data Terminal Ready
line.
This pin is also used as a strapping option to determine various bus
interface modes. See Table 8 on page 31 for details.
SDIO_DATA_3/
In/Out (8 mA)
(PU/PD)
This pin has dual functions:
1
UART_TX
• In SDIO mode, it becomes SDIO Data Line 3 (see
Table 9 on page 31).
• In nonSDIO mode, it becomes the output for the UART Serial
Transmitter line.
This pin is also used as a strapping option to select UART clock
mode. See Table 8 on page 31 for details.
1,2
E05
F06
E07
In (4 mA) PU
In (PU)
UART Serial Input
UART_RX
1,2
UART Ring Indicator
UART Data Set Ready
UART_RI
1,2
In (PU)
UART_DSR
Notes:
1. The UART option is only available on BCM4318E.
2. On BCM4318, pins E05, E07, and F06 have no internal connection.
Broadcom Corporation
Page 24
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
SPROM Bus Interface
SPROM_DIN
B10
In PD
SPROM Data In. Must be connected to the DOUT signal of the
SPROM. This pin is also used as a strapping option to determine
SPROM mode. See Table 7 on page 30 for details.
SPROM_DOUT
SPROM_CLK
SPROM_CS
A12
E09
B11
In/Out (4 mA) PD SPROM Data Out. Must be connected to the DIN signal of the
SPROM (see note below). This pin is also used as a strapping
option to determine SPROM mode. See Table 7 on page 30 for
details.
In/Out (4 mA) PD Serial Data Clock. Must be connected to the serial clock input of
the SPROM (typically called SK). This pin is also used as a
strapping option to determine SPROM mode. See
Table 7 on page 30 for details.
Out (4 mA) PU
SPROM Chip Select. Must be connected to the chip select input
of the SPROM (typically called CS).
This pin is also used as a strapping option to determine SPROM
mode. See Table 7 on page 30 for details.
JTAG Interface
TMS
B04
C04
B05
A06
C03
In (PU)
In PU
For normal operation, connect as described in the JTAG
specification (IEEE Std 1149.1). Otherwise, if JTAG is not used,
these pins can be left unconnected (NC), as they have internal pull-
ups. TCK is typically an 8-MHz clock.
TCK
TDI
In PU
TDO
Out (8 mA) PU
In PU
JTAG_TRST
GPIO Interface
GPIO_0
K08
J08
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
In/Out (8 mA)
General Purpose Interface Pins. These pins are High-Z on
powerup and reset. Subsequently, they become inputs or outputs
through software control.
GPIO_1
GPIO_2
M09
P09
N09
L09
K09
M10
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
Crystal Oscillator
XTALOUT
XTALIN
P05
P06
20-MHz XTAL Output.
20-MHz XTAL input.
Misc. Control
BGREF
P01
Bandgap Reference. Connect to GND through an external
2.87-kΩ resistor.
CP_FB
N04
D10
Feedback Filter. Refer to reference design.
CSTSCHG
Out
Optional CardBus Interrupt. Indicates a change in the status of
the card. This pin is different from pin C11.
EXT_POR
C05
In (PU)
External Power-on Reset. Allows connection of the external
power-on reset circuit. The internal POR can be used as the
default without requiring an external circuit. EXT_POR must be left
open for normal operation.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 25
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
RF_DISABLE
A08
PU
Radio Disable. Asserting this pin low disables the BCM4318/
BCM4318E's internal 2.4-GHz radio and the BCM2060 5-GHz
radio by shutting off everything (including the synthesizer) other
than the oscillator.
TEST_SE
A07
P10
PD
Scan Enable Input. No Connect (NC)
XTAL_PU
XTAL Powerup. Pull high for normal operation.
Reserved Signals
RESERVED
RESERVED
F01
F02
No Connect (NC)
No Connect (NC)
IEEE 802.11a Interface to BCM2060
APHY_EXT_LNA_
GAIN
D07
Out (12 mA)
External 5-GHz LNA gain control.
APHY_EXT_LNA_PU D08
APHY_PA_CNTRL_0 C07
Out (12 mA)
NC
External 5-GHz LNA powerup enable.
Power Amplifier Control. Power control signal to the BCM2060
radio. Leave unconnected.
APHY_PA_PD
APHY_SRI_C
APHY_SRI_DI
D06
A11
B09
Out (12 mA)
Out (4 mA)
Out (4 mA)
Power Amplifier Powerdown.
Serial Interface Clock. Connected to the BCM2060 radio.
Data Output to the SRI_DI Pin on the BCM2060 IEEE 802.11a
Radio Device. Must be connected to the SRI_DI pin on the
BCM2060 radio.
APHY_SRI_DO
C09
In
Data Input from the SRI_DO Pin on the BCM2060 IEEE
802.11b/g Radio Device. Must be connected to the SRI_DO pin
on the BCM2060 radio.
APHY_SRI_E
APHY_SYNTH_PU
CMOUT
C08
A10
F05
Out (4 mA)
Serial Interface Enable. Connected to the BCM2060 radio.
Synthesizer Powerup. Signal to the BCM2060 radio.
Out
In
Common Mode Voltage Output. Sets the common mode input
voltage of the ADC of the radio.
RXN_I
RXN_Q
RXP_I
F04
G04
F03
H04
D01
C02
D02
C01
D03
Receive Differential Input, In-Phase Negative Component
from the BCM2060 Radio.
In
Receive Differential Input, Quadrature Negative Component
from the BCM2060 Radio.
In
Receive Differential Input, In-Phase Positive Component from
the BCM2060 Radio.
RXP_Q
TXN_I
In
Receive Differential Input, Quadrature Positive Component
from the BCM2060 Radio.
Out
Out
Out
Out
In
Transmit Differential Output, In-Phase Negative Component
to the BCM2060 Radio.
TXN_Q
TXP_I
Transmit Differential Output, Quadrature Negative
Component to the BCM2060 Radio.
Transmit Differential Output, In-Phase Positive Component to
the BCM2060 Radio.
TXP_Q
XNRSSI
Transmit Differential Output, Quadrature Positive Component
to the BCM2060 Radio.
Narrowband Receive Signal Strength Indicator. Input signal
from the BCM2060 radio.
Broadcom Corporation
Page 26
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
XTEMPRSSI
B02
In
Broadcom Corporation Temperature Sense Input from the
BCM2060 Radio.
XTSSI5
E02
In
Transmit Signal Strength Indication from the BCM2060 Radio.
If used, connect to the output power detector of the connected
5-GHz power amplifier. If not used, leave unconnected.
XWRSSI
E01
A02
In
In
Wideband Receive Signal Strength Indication from the
BCM2060 Radio.
FREF_2
Input Clock. Reference clock from the BCM2060 radio.
Shared RF signals
ANT_SELN
D05
Out (12 mA)
Antenna Select Negative. Used to drive a diversity switch to
select which of the two antennas should be currently in use (for
switched diversity operation). ANT_SELN is the inverse of
ANT_SELP. This signal is shared and is used by both the 2.4-GHz
(IEEE 802.11g) and 5-GHz (IEEE 802.11a) RF front ends.
ANT_SELP
B07
Out (12 mA)
Antenna Select Positive. Used to drive a diversity switch to select
which of the two antennas should be currently in use (for switched
diversity operation). This signal is shared and is used by both the
2.4-GHz (IEEE 802.11g) and 5-GHz (IEEE 802.11a) RF front
ends.
TR_SW_RX_PU
TR_SW_TX_PU
B06
C06
Out (12 mA)
Out (12 mA)
Receive Powerup Control Output for External TR Switch. This
signal is shared and is used by both the 2.4-GHz (IEEE 802.11g)
and 5-GHz (IEEE 802.11a) RF front ends.
Transmit Powerup Control Output for External TR Switch. This
signal is shared and is used by both the 2.4-GHz (IEEE 802.11g)
and 5-GHz (IEEE 802.11a) RF front ends.
2.4-GHz RF Analog Interface (IEEE 802.11g)
GPHY_EXT_LNA_GA B08
IN
Out (12 mA)
External LNA Gain Control.
LNAINN
LNAINP
PA_OUT
K01
J01
N01
In
LNA Differential Input.
LNA Differential Input.
In
Out
2.4-GHz Transmitter Output. Output frequency = 2402–2495
MHz.
XTSSI2
D04
A09
A04
In
2.4-GHz Transmit Signal Strength Indicator.
External Power Amplifier Powerup Enable.
External LNA Powerup Enable.
TX_PU
Out (12 mA)
Out (8 mA)
RX_PU
3.3V Digital
OTP_VDD
VDDBUS
VDDBUS
VDDBUS
VDDBUS
VDDIO
L10
G05
H05
J04
J05
K04
K05
K06
K07
Connect to 3.3V digital supply.
VDDIO
VDDIO
VDDIO
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 27
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
VESD
E11
ESD Bias. For a PCI bus, this pin should be connected to one of
the VIO pins on the PCI connector (PCI pins A10, A16, A59, B19,
or B59). For Mini PCI adapters, there are no VIO pins on the Mini
PCI edge connector, so these pins should be connected to
VDDBUS.
1.8V Analog VDD Filter Group 1
AVDD_ADC
AVDD_DAC
PLLVDD
E03
B01
A05
B03
Connect this group of pins to a separately filtered 1.8V supply.
Connect this group of pins to a separately filtered 1.8V supply.
Connect this group of pins to a separately filtered 1.8V supply.
PLLDVDD
1.8V Analog VDD Filter Group 2
VDD4W
M07
N05
M06
N07
VDDPLL
VDDPLL_REF
VDDXTAL
1.8V Analog VDD Filter Group 3
VDDCP
VDDLF
N06
H02
P03
M05
VDDLO
VDDVCO
1.8V Analog VDD Filter Group 4
VDDDR
VDDRX
VDDTX
VDD 1.8V Digital
VDD
N02
J02
P02
Connect this group of pins to a separately filtered 1.8V supply.
K11
E06
E08
Connect to 1.8V digital supply.
VDD
VDD
1.8V Analog
VDDPA
VDDPA
M01
M02
Connect to filtered 1.8V supply.
Broadcom Corporation
Page 28
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
RF Ground
GNDPA
GNDPA
PLLGND
RGND
L02
M03
A03
G01
G02
G03
H01
H03
J03
RF GND.
RGND
RGND
RGND
RGND
RGND
RGND
K02
K03
L01
L03
L04
L05
L06
L07
L08
M04
M08
N03
N08
P04
P07
P08
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
Digital Ground
AVSS_ADC
AVSS_DAC
VSS
E04
A01
F07
F08
F09
Digital GND.
VSS
VSS
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 29
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 6: BCM4318/BCM4318E 196-Pin BGA Signal Descriptions (Cont.)
Signal Name
Pin
Type
Description
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G06
G07
G08
G09
H06
H07
H08
H09
J06
Digital GND.
J07
J09
J10
STRAPPING OPTIONS
The pins listed in Table 7 and Table 8 are asynchronously sampled at powerup to determine the various operating modes.
Each pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode,
connect an external PU to VDDIO or PD to GND. Sampling occurs within a few milliseconds following internal POR or
deassertion of external POR. After sampling, each pin assumes the function specified in the Signal Descriptions table,
Table 5: “BCM4318/BCM4318E 144-Pin BGA Signal Descriptions,” on page 14 or Table 6: “BCM4318/BCM4318E 196-Pin
BGA Signal Descriptions,” on page 20.
Table 7: SPROM Mode and Size
SPROM Mode—The SPROM pins are asynchronously sampled at powerup to determine SPROM mode and size. Mode is selected
using the SPROM_CS and SPROM_DIN pins as follows:.
SPROM_CS (also called CS) (PU) SPROM_DIN (PD)
Result
0
0
1
1
0
1
0
1
SPROM present, normal operation
SPROM present, locked (no writes allowed)
Reserved
Host Mode—SPROM absent
SPROM Size—SPROM size is selected using the SPROM_CLK and SPROM_DOUT pins as follows:.
SPROM_CLK (also called SK) (PD) SPROM_DOUT (PD)
Result
16 kbit
4 kbit
1
0
0
0
1
0
1 kbit
Broadcom Corporation
Page 30
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Table 8: Bus Mode Configurations
Bus Mode
PCMCIA_SEL
PCI_SERR
SDIO_DATA2 (PU)
Mini/PCI
0
0
1
1
X
X
0
1
1
0
CardBus
SDIO
X
X
PCMCIA/Compact Flash
Note: X = do not care
SDIO PIN DESCRIPTIONS
Table 9: SDIO Pin Descriptions
SD 1-Bit Mode
SD 4-Bit Mode
SPI Mode
SDIO_DATA_0
SDIO_DATA_1
Data line 0
DATA
IRQ
Data line
Interrupt
DO
Data output
Interrupt
Data line 1 or Interrupt
(optional)
IRQ
SDIO_DATA_2
Data line 2 or Read Wait
(optional)
RW
Read Wait (optional)
NC
Not used
SDIO_DATA_3
SDIO_CLK
Data line 3
Clock
N/C
Not used
Clock
CS
Card Select
Clock
CLK
CMD
SCLK
DI
SDIO_CMD
Command line
Command line
Data input
CLK
CMD
SD Host
BCM4318/BCM4318E
DAT[3:0]
Figure 8: Signal Connections to SDIO Card (SD 4-Bit Mode)
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 31
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
CLK
CMD
DATA
IRQ
SD Host
BCM4318/BCM4318E
RW
Figure 9: Signal Connections to SDIO Card (SD 1-Bit Mode)
SCLK
DI
SD Host
BCM4318/BCM4318E
DO
IRQ
CS
Figure 10: Signal Connections to SDIO Card (SPI Mode)
Broadcom Corporation
Page 32
Section 3:Signal Descriptions
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
CE0
CE1
OE
WE
RESET
REG
Compact Flash
BCM4318/
BCM4318E
or PCMCIA
Host
INPACK
WAIT
IREQ
Address Bus
Data Bus
Figure 11: Signal Connections to PCMCIA/Compact Flash
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 3:Signal Descriptions
Page 33
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Section 4: Electrical Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
RECOMMENDED OPERATING CONDITIONS
Table 10: Recommended Operating Conditions
Parameter
Minimum
Typical
Maximum
Units
Conditions/Comments
Supply Voltage
• VDDIO, VDDBUS
3.0
3.3
1.8
3.6
V
V
• VDDCORE, PLLVDD, AVDD 1.71
1.89
Logic Inputs
• V , Input High Voltage
2.0
2.4
V
V
INH
• V , Input Low Voltage
0.8
0.4
INL
Logic Outputs
• V , Output High Voltage
V
V
Current is determined by the
specified pad.
OH
• V , Output Low Voltage
Current is determined by the
specified pad.
OL
Broadcom Corporation
Page 34
Section 4:Electrical Characteristics
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
CURRENT CONSUMPTION
Table 11: Current Consumption
Typical Average Current Typical Peak Current
Parameter
Units
Consumption
Consumption
a
–
–
75
mA
mA
• 3.3V Supply—Total
a
320
• 1.8V Supply—Total
Receive
b
TBD
TBD
TBD
TBD
–
–
–
–
mA
mA
mA
mA
• Receive (54 Mbps)—1.8V Supply
b
• Receive (54 Mbps)—3.3V Supply
b
• Receive (11 Mbps)—1.8V Supply
b
• Receive (11 Mbps)—3.3V Supply
Transmit
b
TBD
TBD
TBD
TBD
–
–
–
–
mA
mA
mA
mA
• Transmit (54 Mbps)—1.8V Supply
b
• Transmit (54 Mbps)—3.3V Supply
b
• Transmit (11 Mbps)—1.8V Supply
b
• Transmit (11 Mbps)—3.3V Supply
Power Saving
• Power Save Mode, 500 msec DTIM—
TBD
TBD
–
–
mA
mA
c
1.8V Supply
• Power Save Mode, 500 msec DTIM—
c
3.3V Supply
a. For use in power supply design considerations. Specified numbers are worst case values for worst case conditions: Vcc =
1.89V and 3.6V respectively, ambient temperature = 75°C, and absolute highest TX Output power (Internal attenuators forced
to zero).
b. For use in battery life calculations. The values are typical average currents while a packet is being transmitted or received.
The values do not represent average current over a specified time where there will be periods of no packets. For example, if
the device is in power management mode and packets are only being transmitted/received 50% of the time over a period of
time, the average current over that time span would be closer to 50% of the value shown above. In other words, real world
typical power consumption will be lower than these values. These values are provided to make it easier to calculate time
averaged current based on a target application's traffic characteristics. This only applies in power management mode. If the
BCM4318/BCM4318E is not in power management mode then standby RX consumption is the same as consumption during
packet reception. Also note that these numbers assume typical TX output power under the software driver's TX power control.
c. For use in battery life calculations. These values are for current averaged over a 5 second interval.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 4:Electrical Characteristics
Page 35
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
LOCAL OSCILLATOR SPECIFICATIONS
Table 12: Local Oscillator Specifications
Parameter
Condition
Minimum
Typical
Maximum
Unit
Reference Input Frequency Range
Clock Frequency Tolerance
VCO Frequency Range
Reference Spurs
–
–
–
–
–
–
20
–
–
MHz
ppm
–
±20
2484
–34
–86.5
2412
–
MHz
dBc
–
–
–
Local Oscillator Phase Noise, single-
sided from 1–300 kHz offset
–
dBc/Hz
ENVIRONMENTAL CHARACTERISTICS
Table 13: Environmental Characteristics
Parameter
Value
Units
Conditions/Comments
Ambient Temperature (T )
0 to 75
°C
Operation
A
Storage Temperature
Relative Humidity
less than 30
less than 60
less than 85
+1 / –1.75
°C
%
–
Storage
%
Operation
ESD
kV
Human Body Model
Broadcom Corporation
Page 36
Section 4:Electrical Characteristics
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Section 5: RF Specifications
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
GENERAL RF SPECIFICATIONS
Table 14: General RF Specifications
Parameter
Condition
Minimum Typical
Maximum
Unit
Tx/Rx Switch Time
Rx/Tx Switch Time
Including Tx ramp down
Including Tx ramp up
–
–
5
5
10
5
µs
µs
RECEIVER RF SPECIFICATIONS
Table 15: Receiver RF Specifications
Parameter
Condition
Minimum Typical
Maximum
Unit
Cascaded Noise Figure
Maximum Receive Level
–
6
TBD
dB
a
@ 1, 2 Mbps
@ 5.5, 11 Mbps
@ 54 Mbps
–4
–
–
dBm
dBm
dBm
dBm
dBm
MHz
MHz
–10
–
–
–10
–
–
Input IP3
Maximum Gain
Minimum Gain
–
–16
–2
8.5
1
–
–
–
LPF 3-dB Bandwidth
8
9
PGA DC Rejection Servo Loop
Bandwidth
WB Mode
–
–
NB Mode
120 Hz
–
230 kHz
LPF DC Rejection Servo Loop
Bandwidth
WB Mode
500
–
kHz
NB Mode
120 Hz
230 kHz
Adjacent Channel Power Rejection
Alternate Channel Power Rejection
Maximum Receiver Gain
At 14-MHz offset
At 25-MHz offset
–
–
–
–
38
65
88
3
–
–
–
–
dBc
dBc
dB
Gain Control Step
dB/Step
a. When using a suitable external switch.
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 5:RF Specifications
Page 37
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
TRANSMITTER RF SPECIFICATIONS
Table 16: Transmitter RF Specifications
Condition Minimum Typical
Parameter
Maximum Unit
RF Output Frequency Range
Output Power
2400
–
2500
MHz
dBm
dB
Maximum Gain
Maximum Gain
Maximum Gain
–
–
–
–
–
+6
–
–
2
–
–
–
Gain Flatness
Output IP3
+18
+7
–15
dBm
dBm
dBm
Output P1dB
a
Minimum Gain
Output Power
Carrier Suppression
15
–
–
–
–
–
–
dBr
dBr
dBr
dBr
Tx Spectrum mask @ maximum gain fc – 22MHz < f < fc – 11MHz
fc + 11MHz < f < fc + 22MHz
–30
–30
–50
–
f < fc – 22MHz; and
f > fc + 22MHz
–
Tx Modulation Accuracy (EVM) @
maximum gain
802.11b mode
802.11g mode
–
35%
5%
–
Gain Control Step Size
I/Q Baseband Bandwidth
–
0.6
8.5
15
–
dB/step
MHz
MHz
dB
802.11b mode
802.11g mode
DC Input
7
–
–
–
b
–1
1
Amplitude Balance
b
DC Input
–1.5
–
1.5
° (degrees)
Phase Balance
Baseband Differential Input Voltage
Tx Power Ramp Up
Shaped Pulse
–
–
–
0.6
–
–
2
2
Vpp
90% of final Power
10% of final Power
µsec
µsec
Tx Power Ramp Down
–
a. IEEE 802.11(15.4.7.2) requires the minimum transmit power shall be no less than 1 mW at the antenna port.
b. At a 3 MHz offset from the carrier frequency.
Broadcom Corporation
Page 38
Section 5:RF Specifications
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
Section 6: Timing Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device
characterization.
PCMCIA/COMPACT FLASH TIMING
tc(R)
ta(A)(2)
th(A)
A[11:0]
REG
ta(CE)(2)
tv(A)
tsu(CE)
NOTE 1
NOTE 1
CE
tsu(A)
th(CE)
ta(OE)(2)
OE
tdis(CE)
tw(WT)(3)
tv(WT-OE)(3)
WAIT
ten(OE)
tdis(OE)
tv(WT)
D[15:0]
DATA Valid
1. Shaded area can be high or low.
2. Applies to card only when WAIT is negated by card.
However, the host must always provide at least this access time before sampling data.
3. Applies only when WAIT is asserted by card.
Figure 12: PCMCIA/Compact Flash Read Timing Diagram
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 6:Timing Characteristics
Page 39
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 17: PCMCIA/Compact Flash Read Timing Characteristics
Parameter
t (R)
Min
250
–
Max
–
Units
ns
c
(2)
200
ns
t (A)
a
t (A)
20
–
–
ns
ns
h
(2)
200
t (CE)
a
t (CE)
0
–
ns
ns
ns
ns
su
t (A)
0
–
v
t (A)
20
–
–
su
(2)
125
t (OE)
a
t (CE)
20
–
–
ns
ns
h
(3)
35
t (WT–OE)
v
(3)
0.01
3.0
µs
t (WT)
w
t
t
(CE)
–
30
–
ns
ns
ns
ns
dis
(OE)
10
20
–
en
t (WT)
–
v
t
(OE)
60
dis
See Figure 12 for footnotes.
Broadcom Corporation
Page 40
Section 6:Timing Characteristics
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
tc(W)
A[11:0]
REG
tsu(CE-WEH)
NOTE 1
CE
OE
NOTE 1
tsu(CE)
tsu(A-WEH)
th(CE)
NOTE 4
NOTE 3
NOTE 4
tsu(A)
trec(WE)
tw(WE)
WE
tw(WT-WE)
tw(WT)
tv(WT)
WAIT
th(OE-WE)
th(D)
tsu(D-WEH)
tsu(OE-WE)
NOTE 2
DATA INPUT ESTABLISHED
D[15:0] (DIN)
tdis(WE)
ten(OE)
tdis(OE)
ten(WE)
D[15:0] (DOUT
)
1. Shaded area can be high or low.
2. When the data I/O pin is in the output state, no signals can be applied to the data pins
(D[15:0]) by the host system.
3. Minimum write pulse width must be met whether or not WAIT is asserted by card.
4. Can be high or low for write timing, but restrictions on OE apply.
Figure 13: PCMCIA/Compact Flash Write Timing Diagram
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 6:Timing Characteristics
Page 41
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Table 18: PCMCIA/Compact Flash Write Timing Characteristics
Parameter
t (W)
Min
250
180
0
Max
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
c
t (CE-WEH)
–
su
t (CE)
–
su
t (A-WEH)
180
20
20
150
30
–
–
su
t (CE)
–
h
t (A)
–
su
t (WE)
–
w
t
(WE)
–
rec
t (WT-WE)
35
3.0
–
v
t (WT)
0.01
20
10
80
10
30
–
w
t (WT)
v
t (OE-WE)
–
su
t (D-WEH)
–
su
t (OE-WE)
–
h
t (D)
–
h
t
t
t
t
(OE)
(WE)
100
100
–
dis
dis
–
(WE)
(OE)
5
en
en
5
–
SPROM TIMING
Table 19: SPROM Timing Characteristics
Signal Name
Period
Output Max
Output Min
Setup
Hold
SPROM_CLK
1.92 µsec
–
–
–
–
–
–
SPROM_CLK falling edge to
SPROM_DOUT
–
0.5 µs
0.3 µs
SPROM_CLK falling edge to SPROM_CS
SPROM_CLK rising edge to SPROM_DIN
–
–
0.5 µs
0.3 µs
–
–
–
–
0.5 µs
–0.3 µs
Broadcom Corporation
Page 42
Section 6:Timing Characteristics
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
JTAG TIMING
Table 20: JTAG Timing Characteristics
Signal Name
Period
Output Max
Output Min
Setup
Hold
JTAG_TCK
JTAG_TDI
125 ns
–
–
–
–
–
–
–
20 ns
20 ns
–
0 ns
0 ns
–
JTAG_TMS
JTAG_TDO
JTAG_TRST
–
–
–
–
100 ns
–
0 ns
–
250 ns
–
–
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 6:Timing Characteristics
Page 43
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Section 7: Package Specifications
Figure 14: BCM4318/BCM4318E 144-Pin FBGA
Broadcom Corporation
Page 44
Section 7:Package Specifications
Document 4318_4318E-DS01-405-R
Preliminary Data Sheet
BCM4318/BCM4318E
11/09/04
ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y14.5M-1994.
Figure 15: BCM4318/BCM4318E 196-Pin FBGA
Broadcom Corporation
Document 4318_4318E-DS01-405-R
Section 7:Package Specifications
Page 45
BCM4318/BCM4318E
Preliminary Data Sheet
11/09/04
Section 8: Ordering Information
Table 21: BCM4318/BCM4318E Ordering Information
Part Number
Package
Ambient Temperature
o
o
BCM4318KFBG
BCM4318EKFBG
BCM4318SKFBG
196-pin FBGA (Lead Free)
196-pin FBGA (Lead Free)
144-pin FBGA (Lead Free)
0 C to 75 C
o
o
0 C to 75 C
o
o
0 C to 75 C
Broadcom Corporation
16215 Alton Parkway
P.O. Box 57013
Irvine, California 92619-7013
Phone: 949-450-8700
Fax: 949-450-8710
Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design.
Information furnished by Broadcom Corporation is believed to be accurate and reliable. However, Broadcom Corporation
does not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
Document 4318_4318E-DS01-405-R
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