BCM20733_技术文档

CYW20733

Single-Chip Bluetooth Transceiver

Wireless Input Devices

The Cypress CYW20733 is a Bluetooth 3.0 + EDR compliant, stand-alone baseband processor with an integrated 2.4 GHz trans-

ceiver. The device is ideal for applications in wireless input devices including game controllers, keyboards, and joysticks. Built-in

firmware adheres to the Bluetooth Human Interface Device (HID) profile and Bluetooth Device ID profile specifications. The

CYW20733 radio has been designed to provide low power, low cost, and robust communications for applications operating in the

globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification 3.0 + EDR. The single-

chip Bluetooth transceiver is a monolithic component implemented in a standard digital CMOS process and requires minimal exter-

nal components to make a fully compliant Bluetooth device. The CYW20733 is available in three package options: a 81-pin, 8 mm ×

8 mm FBGA, a 121-pin, 9 mm × 9 mm FBGA, and a 56-pin, 7 mm x 7 mm QFN.

Cypress Part Numbering Scheme

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion,

there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides

Cypress ordering part number that matches an existing IoT part number.

Table 1. Mapping Table for Part Number between Broadcom and Cypress

Broadcom Part Number

Cypress Part Number

CYW20733

BCM20733

BCM20733A3KFB1G

BCM20733A3KFB2G

BCM20733A3KML1G

CYW20733A3KFB1G

CYW20733A3KFB2G

CYW20733A3KML1G

Features

■ Integrated LDO to reduce BOM cost

■ Bluetooth specification 3.0 + EDR compatible

■ Bluetooth HID profile version 1.1 compliant

■ Bluetooth Device ID profile version 1.3 compliant

■ Supports AFH

■ On-chip support for serial peripheral interface (master and

slave modes)

■ Broadcom Serial Communications Interface (compatible

with Philips® I2C slaves)

■ Two independent half-duplex PCM/I2S interfaces

■ Real-time clock supported with 32.768 kHz oscillator

■ Excellent receiver sensitivity

■ Programmable output power control meets Class 2 or

Class 3 requirements

■ On-chip support for common keyboard and mouse inter-

faces eliminates external processor

■ On-chip PA with a maximum output power of +10dBm with-

out external component

■ Infrared (IR) modulator

■ IR learning

■ Integrated ARM7TDMI-S™-based microprocessor core

■ On-chip power on reset (POR)

■ Integrated 200 mW filterless Class-D audio amplifier

■ Triac control

■ On-chip software control power management unit

■ Three package types available:

■ Triggered Broadcom Fast Connect

■ One I/O capable of sinking 100 mA for high- current drive

applications

❐ 81-pin FBGA package (8 mm × 8 mm)

❐ 121-pin FBGA package (9 mm × 9 mm)

❐ 56-pin QFN package (7 mm x 7 mm)

■ RoHS compliant

■ Programmable key scan matrix interface, up to 8 × 20 key-

scanning matrix

■ Three-axis quadrature signal decoder

Applications

■ Game controllers

■ Point-of-sale (POS) input devices

■ Remote controls

■ Wireless pointing devices: mice, trackballs

■ Wireless keyboards

■ Joysticks

■ Home automation

■ 3D glasses

Cypress Semiconductor Corporation

Document No. 002-14859 Rev. *R

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 21, 2016

CYW20733

Figure 1. Functional Block Diagram

Muxed on GPIO

Tx

Tx RTSN

RTSN

CTSN

SCK

MISO

SDA/

MOSI

1.2V

VDDC

Rx

CTSN Rx

Speaker

VSS,

VDDO, 28 ADC

VDDC

WDT

BSC/SPI

Master

Interface

(BSC is I2C-

compat)

Inputs

Digital

Audio

Block

1.2V

POR

Class-D

Driver

3V

Test

UART

Periph

UART

Processing

Unit

(ARM7)

Speaker

Out

CT ɇ ѐ

ADC

1.2V VDDC

Domain

MIA

POR

1.62V -3.6V

System Bus

32 kHz

LPCLK

1.2V

LDO

Peripheral

Interface

Block

I/O Ring

Control

Registers

384K

ROM

80K

RAM

1.2V

LDO

CTRL

Volt. Trans

24 MHz

Power

RF Control

and Data

32 kHz

LPCLK

I/O Ring Bus

3-Axis

Bluetooth

Baseband

Core

2.4 GHz

Radio

GPIO

Control/

Status

IR

Mod.

and

Keyboard

Mouse

Signal

SPI

M/S

Matrix

Scanner

w/FIFO

PMU

PWM

24 MHz

Learning

Registers

Controller

RF I/O

T/R

Switch

Frequency

Synthesizer

WAKE

IR

I/O

8 x 20 6 quadrature inputs

Scan (3 pair) + Hi -current

Matrix Driver Controls

÷ 4

AutoCal

57 GPIO

128 kHz

LPCLK

1.2V VDDRF

Domain

128 kHz

LPO

28 ADC

Inputs

VDDO Domain

High

Sink IO

57 GPIO Pins

Ref Xtal

32 kHz Xtal (opƟonal)

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CYW20733

Contents

1.14 Infrared Modulator ..............................................18

1.15 Infrared Learning ................................................19

1.16 Shutter Control for 3D Glasses ..........................19

1.17 Triac Control .......................................................20

1.Functional Description ....................................... 4

1.1 Integrated Radio Transceiver .............................. 4

1.1.1 Transmitter Path ...................................... 4

1.1.2 Receiver Path .......................................... 4

1.1.3 Local Oscillator ........................................ 4

1.1.4 Calibration ............................................... 4

1.1.5 Internal LDO Regulator ............................ 4

1.18 Cypress Proprietary Control Signalling

and Triggered Broadcom Fast Connect .............20

1.19 Integrated Filterless Class-D Audio Amplifier .....20

1.20 High-Current I/O .................................................21

1.2 Microprocessor Unit ............................................ 5

1.2.1 EEPROM Interface .................................. 5

1.2.2 Serial Flash Interface ............................... 5

1.21 Power Management Unit ....................................22

1.21.1 RF Power Management ..........................22

1.21.2 Host Controller Power Management ......22

1.21.3 BBC Power Management .......................22

1.2.3 Internal Reset .......................................... 5

1.2.4 External Reset ......................................... 6

1.3 Bluetooth Baseband Core ................................... 6

1.3.1 Frequency Hopping Generator ................ 6

1.3.2 E0 Encryption .......................................... 6

1.3.3 Link Control Layer ................................... 6

1.3.4 Adaptive Frequency Hopping .................. 6

2.Pin Assignments............................................... 23

2.1 Ball Maps ...........................................................29

2.1.1 81-Pin FBGA Ball Map ...........................29

2.1.2 121-Pin FBGA Ball Map .........................31

2.1.3 56-Pin QFN Diagram ..............................32

1.3.5 Bluetooth Version 3.0 Features ............... 6

1.3.6 Test Mode Support .................................. 7

3.Specifications.................................................... 33

3.1 Electrical Characteristics ....................................33

3.2 RF Specifications ...............................................37

1.4 Peripheral Transport Unit (PTU) ......................... 7

1.4.1 Broadcom Serial Control Interface .......... 7

1.4.2 UART Interface ........................................ 8

1.5 PCM Interface ..................................................... 9

1.5.1 System Diagram ...................................... 9

3.3 Timing and AC Characteristics ...........................39

3.3.1 UART Timing ..........................................39

1.5.2 Slot Mapping .......................................... 10

1.5.3 Frame Synchronization .......................... 10

1.5.4 Data Formatting ..................................... 10

3.3.2 SPI Timing ..............................................40

3.3.3 BSC Interface Timing .............................41

3.3.4 PCM Interface Timing .............................43

3.3.5 I²S Timing ...............................................48

1.6 I²S Interface ...................................................... 10

1.7 Clock Frequencies ............................................ 10

1.7.1 Crystal Oscillator ................................... 10

4.Mechanical Information.................................... 53

4.0.1 Tape Reel and Packaging

1.8 GPIO Port .......................................................... 12

Specifications .........................................56

1.9 Keyboard Scanner ............................................ 12

1.9.1 Theory of Operation ............................... 13

5.Ordering Information........................................ 62

6.IoT Resources ................................................... 62

1.10 Mouse Quadrature Signal Decoder ................... 13

1.10.1 Theory of Operation ............................... 13

A.Acronyms and Abbreviations.......................... 62

Document History........................................................... 64

Sales, Solutions, and Legal Information ...................... 67

1.11 ADC Port ........................................................... 13

1.12 PWM ................................................................. 14

1.13 Serial Peripheral Interface ................................. 15

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CYW20733

1. Functional Description

1.1 Integrated Radio Transceiver

The CYW20733 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has

been designed to provide low power, low cost, robust communications for applications operating in the globally available 2.4 GHz

unlicensed ISM band. It is fully compliant with Bluetooth Radio Specification 3.0 + EDR and meets or exceeds the requirements to

provide the highest communication link quality of service.

1.1.1 Transmitter Path

The CYW20733 features a fully integrated zero IF transmitter. The baseband transmit data is GFSK modulated in the modem block

and upconverted to the 2.4 GHz ISM band. The transmit path consists of signal filtering,

I/Q upconversion, output power amplification, and RF filtering. It also incorporates the /4-DQPSK and 8-DPSK modulation schemes,

which support the 2 Mbps and 3 Mbps enhanced data rates, respectively.

Digital Modulator

The digital modulator performs the data modulation and filtering required for the GFSK, /4-DQPSK, and

8-DPSK signals. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the

transmitted signal and is much more stable than direct VCO modulation schemes.

Power Amplifier

The integrated power amplifier (PA) for the CYW20733 can transmit at a maximum power of +4 dBm for class 2 operation. The transmit

power levels are for basic rate and EDR. Due to the linear nature of the PA, combined with some integrated filtering, no external filters

are required for meeting Bluetooth and regulatory harmonic and spurious requirements.

The CYW20733 internal PAcan deliver a maximum output power of +10 dBm for basic rate and +8 dBm for EDR with a flexible supply

range of 2.5V to 3.0V.

1.1.2 Receiver Path

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit

synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel

filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation

enables the CYW20733 to be used in most applications without off-chip filtering.

Digital Demodulator and Bit Synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit

synchronization algorithm.

Receiver Signal Strength Indicator

The radio portion of the CYW20733 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller

to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the

transmitter should increase or decrease its output power.

1.1.3 Local Oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO

subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW20733 uses an internal RF and IF

loop filter.

1.1.4 Calibration

The CYW20733 radio transceiver features an automated calibration scheme that is self-contained in the radio. No user interaction is

required during normal operation or during manufacturing to provide the optimal performance. Calibration will optimize the gain and

phase performance of all the major blocks within the radio to within 2% of optimal conditions. Calibrated blocks include filters, the

matching networks between key components, and key gain blocks. The calibration process corrects for both process and temperature

variations. It occurs transparently during normal operation and the setting time of the hops and will calibrate for temperature variations

as the device cools and heats during normal operation in its environment.

1.1.5 Internal LDO Regulator

To reduce the external BOM, the CYW20733 has an integrated 1.2V LDO regulator to provide power to the digital and RF circuits and

system components. The 1.2V LDO regulator operates from a 1.62V to 3.63V input supply with a 60 mA maximum load current.

In noisy environments, a ferrite bead may be needed between the digital and RF supply pins to isolate noise coupling and suppress

noise into the RF circuits.

Note: Always place the decoupling capacitors near the pins as close together as possible.

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CYW20733

1.2 Microprocessor Unit

The CYW20733 microprocessor unit (µPU) runs software from the link control (LC) layer up to the Human Interface Device (HID). The

microprocessor is based on an ARM7™ 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The µPU

has 320 KB of ROM for program storage and boot-up, 80 KB of RAM for scratch-pad data, and patch RAM code.

The internal boot ROM allows for flexibility during power-on reset to enable the same device to be used in various configurations,

including UART, and with an external serial EEPROM or with an external flash memory. At power-up, the lower layer protocol stack

is executed from the internal ROM memory.

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes and feature additions. The device can

also support the integration of user applications.

1.2.1 EEPROM Interface

The CYW20733 provides the BSC (Broadcom Serial Control) master interface; the BSC is programmed by the CPU to generate four

different types of BSC transfers on the bus: read-only, write-only, combined read/write, and combined write/read. BSC supports both

low-speed and fast mode devices. The BSC is compatible with a Philips® I²C slave device, except that master arbitration (multiple

I²C masters contending for the bus) is not supported. Native support for Microchip® 24LC128, Microchip 24AA128, and STMicroelec-

tronics® M24128-BR is included.

The EEPROM can contain customer application configuration information, including: application code, configuration data, patches,

pairing information, BD_ADDR, baud rate, SDP service record, and file system information used for code.

1.2.2 Serial Flash Interface

The CYW20733 includes an SPI master controller that can be used to access serial flash memory. The SPI master contains an AHB

slave interface, transmit and receive FIFOs, and the SPI core PHY logic.

Devices natively supported include the following:

■ Atmel® AT25BCM512B

■ MXIC MX25V512ZUI-20G

1.2.3 Internal Reset

The CYW20733 has an integrated power-on reset circuit that resets all circuits to a known power-on state.

Figure 1. Internal Reset Timing

VDDO POR delay

~ 2 ms

VDDO

VDDO POR threshold

VDDO POR

VDDC POR threshold

VDDC

VDDC POR delay

~ 2 ms

VDDC POR

Crystal

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and firmware boot.

Crystal Enable

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CYW20733

1.2.4 External Reset

An external active-low reset signal, RESET_N, can be used to put the CYW20733 in the reset state. The RESET_N pin has an internal

pull-up resistor and, in most applications, it does not require that anything be connected to it. RESET_N should only be released after

the VDDO supply voltage level has been stabilized.

Figure 2. External Reset Timing

Pulse width

>20 µs

Crystal

RESET_N

warm‐up

delay:

~ 5 ms

Baseband Reset

Start reading EEPROM and firmware boot.

Crystal Enable

1.3 Bluetooth Baseband Core

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation.

The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it,

handles data flow control, schedules ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data

into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these

functions, it independently handles HCI event types and HCI command types.

The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/

RX data before sending over the air:

■ Receive Functions: Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic

redundancy check (CRC), data decryption, and data de-whitening.

■ Transmit Functions: Data framing, FEC generation, HEC generation, CRC generation, link key generation, data encryption, and

data whitening.

1.3.1 Frequency Hopping Generator

The frequency hopping sequence generator selects the correct hopping channel number depending on the link controller state,

Bluetooth clock, and the device address.

1.3.2 E0 Encryption

The encryption key and the encryption engine are implemented using dedicated hardware to reduce software complexity and provide

minimal intervention.

1.3.3 Link Control Layer

The Link Control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the Link Control Unit

(LCU). This layer consists of the command controller, which takes commands from the software, and other controllers that are

activated or configured by the command controller to perform the link control tasks. Each task performs in a different state in the

Bluetooth link controller. STANDBY and CONNECTION are the two major states. In addition, there are five substates: page, page

scan, inquiry, inquiry scan, and sniff.

1.3.4 Adaptive Frequency Hopping

The CYW20733 gathers link quality statistics on a channel-by-channel basis to facilitate channel assessment and channel map

selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop

map.

1.3.5 Bluetooth Version 3.0 Features

The CYW20733 is fully compliant with the Bluetooth 3.0 standard, including the following options:

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CYW20733

■ Enhanced power control

■ HCI read, encryption key size command

The CYW20733 supports all of the new Bluetooth version 2.1 features:

■ Extended inquiry response

■ Sniff subrating

■ Encryption pause and resume

■ Secure simple pairing

■ Link supervision timeout changed event

■ Erroneous data reporting

■ Non-automatically flushable packet boundary flag

■ Security Mode 4

1.3.6 Test Mode Support

The CYW20733 fully supports Bluetooth Test Mode, as described in Part 1 of the Bluetooth System Version 2.1 specification. This

includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

In addition to the standard Bluetooth test mode, the device supports enhanced testing features to simplify RF debugging and qualifi-

cation and type approval testing. These features include:

■ Fixed frequency carrier wave (unmodulated) transmission

■ Simplified type approval measurements (Japan)

■ Aid in transmitter performance analysis

■ Fixed frequency constant receiver mode

■ Receiver output directed to I/O pin

■ Direct BER measurements using standard RF test equipment

■ Facilitated spurious emissions testing for receive mode

■ Fixed frequency constant transmission

■ 8-bit fixed pattern or PRBS-9

■ Modulated signal measurements with standard RF test equipment

■ Connectionless transmitter test

■ Hopping or fixed frequency

■ Multiple packet types

■ Multiple data patterns

■ Connectionless receiver test

1.4 Peripheral Transport Unit (PTU)

1.4.1 Broadcom Serial Control Interface

The CYW20733 provides a 2-pin master BSC interface that can be used to retrieve configuration information from an external

EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse

devices. The BSC interface is compatible with I²C slave devices. The BSC does not support multimaster capability or flexible wait-

state insertion by either master or slave devices.

Listed below are the transfer clock rates supported by the BSC:

■ 100 kHz

■ 400 kHz

■ 800 kHz (Not a standard I²C-compatible speed.)

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CYW20733

■ 4 MHz maximum (Compatibility with high-speed I²C-compatible devices is not guaranteed.)

The following transfer types are supported by the BSC:

■ Read (up to 127 bytes can be read)

■ Write (up to 127 bytes can be written)

■ Read-then-Write (Up to 127 bytes can be read, and up to 127 bytes can be written.)

■ Write-then-Read (Up to 127 bytes can be written, and up to 127 bytes can be read.)

Hardware controls the transfers, requiring minimal firmware setup and supervision.

The clock pin (SCL) and data pin (SDA) are both open-drain I/O pins. Pull-up resistors external to the CYW20733 are required on

both SCL and SDA for proper operation.

1.4.2 UART Interface

The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 1.5

Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI

command. The CYW20733 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The

interface supports the Bluetooth 3.0 UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

The UART clock is 24 MHz. The baud rate of the CYW20733 UART is controlled by two values. The first is a UART clock divisor (also

called the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (also called

the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to

eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end

of each bit time.

When setting the baud rate manually, the UART clock divisor is an 8-bit value that is stored as 256 minus the chosen divisor. For

example, a divisor of 13 is stored as 256 – 13 = 243 = 0xF3.

The baud rate adjustment is also an 8-bit value, of which the four MSBs are the number of additional clock cycles to insert in the first

half of each bit time, and the four LSBs are the number of clock cycles to insert in the second half of each bit time. If either of these

two values is over eight, it is rounded to eight.

To compute the baud rate, the calculation is expressed as:

24 MHz ÷ ((16 × UART clock divisor) + total inserted 24-MHz clock cycles)

Table 2 contains example values to generate common baud rates.

Table 2. Common Baud Rate Examples

Baud Rate Adjustment

High Nibble Low Nibble

DesiredBaudRate UART Clock Divi-

(bps) sor

Actual Baud Rate

(bps)

Error

(%)

1500000

0xFF

0xFD

0xFA

0xF3

0xE6

0xD9

0xCC

0xB2

0x98

0x64

0x00

0x05

0x02

0x04

0x00

0x01

0x00

0x01

0x00

0x02

0x00

0x05

0x02

0x04

0x00

0x01

0x00

0x02

1500000

923077

461538

230769

115385

57692

38400

28846

19200

14423

9600

0.00

0.16

0.00

0.16

0.00

0.16

0.00

921600

460800

230400

115200

57600

38400

28800

19200

14400

9600

Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during

normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud

rate registers.

The CYW20733 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%.

Peripheral UART Interface

The CYW20733 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through

the optional I/O ports, which can be configured individually and separately for each functional pin as shown in Table 3.

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CYW20733

Table 3. CYW20733 Peripheral UART

Pin Name

pUART_TX

pUART_RX

pUART_CTS_N

pUART_RTS_N

Configured pin name

P0

P2

P3

P7

P1

P6

P5

P4

P24

P31

P32

P25

P33

P34

P35

–

P30

–

1.5 PCM Interface

The CYW20733 PCM interface can connect to linear PCM codec devices in master or slave mode. In master mode, the device

generates the PCM_BCLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM

interface as inputs to the device.

The channels can be configured to either transmit or receive, but they must be assigned to different time slots. The two half-duplex

channels cannot be combined to form a single full-duplex channel.

1.5.1 System Diagram

Figure 3 shows options for connecting the device to a PCM codec device as a master or a slave.

Figure 3. PCM Interface with Linear PCM Codec

PCM_IN

PCM_OUT

PCM Codec

(Master)

CYW20733

(Slave)

PCM_BCLK

PCM_SYNC

PCM Interface Slave Mode

PCM_IN

PCM_OUT

PCM_BCLK

PCM_SYNC

PCM Codec

(Slave)

CYW20733

(Master)

PCM Interface Master Mode

PCM_IN

PCM_OUT

PCM_BCLK

PCM_SYNC

PCM Codec

(Hybrid)

CYW20733

(Hybrid)

PCM Interface Hybrid Mode

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CYW20733

1.5.2 Slot Mapping

Table 4. PCM Interface Time-Slotting Scheme

Audio Sample Rate

Time-Slotting Scheme

8 kHz

The number of slots depends on the selected interface rate, as follows:

Interface rate

1281

Slot

2562

5124

10248

204816

16 kHz

The number of slots depends on the selected interface rate, as follows:

Interface rate

2561

Slot

5122

10244

20488

The PCM data output driver tri-states its output on unused slots to allow other devices to share the same PCM interface signals. The

data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.

1.5.3 Frame Synchronization

The device supports both short and long frame synchronization types in both master and slave configurations. In short frame synchro-

nization mode, the frame synchronization signal is an active-high pulse at the 8 kHz audio frame rate (which is a single bit period in

width) and synchronized to the rising edge of the bit clock. The PCM slave expects PCM_SYNC to be high on the falling edge of the

bit clock and the first bit of the first slot to start at the next rising edge of the clock. In the long frame synchronization mode, the frame

synchronization signal is an active-high pulse at the 8 kHz audio frame rate. However, the duration is 3-bit periods, and the pulse

starts coincident with the first bit of the first slot.

1.5.4 Data Formatting

The device can be configured to generate and accept several different data formats. The device uses 13 of the 16 bits in each PCM

frame. The location and order of these 13 bits is configurable to support various data formats on the PCM interface. The remaining

three bits are ignored on the input and may be filled with zeros, ones, a sign bit, or a programmed value on the output. The default

format is 13-bit two’s complement data, left justified, and clocked most significant bit first.

2

1.6 I S Interface

The I²S interface supports up to two half-duplex channels. The channels can be configured to either transmit or receive, but they must

be assigned to different time slots (left or right). The two half-duplex channels cannot be combined to form a single full-duplex channel.

The I²S interface is capable of operating in either slave or master mode. The device supports a 16-bit data width with 8-kHz and 16-

kHz frame rates.

1.7 Clock Frequencies

The CYW20733 is set with a crystal frequency of 24 MHz.

1.7.1 Crystal Oscillator

The crystal oscillator requires a crystal with an accuracy of ±20 ppm as defined by the Bluetooth specification. Two external load

capacitors in the 5 pF to 30 pF range are required to work with the crystal oscillator. The selection of the load capacitors is crystal

dependent. Table 5 shows the recommended crystal specification.

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CYW20733

Figure 4. Recommended Oscillator Configuration—12 pF Load Crystal

Table 5. Reference Crystal Electrical Specifications

Parameter Conditions

Min

Typ

Max

Unit

Input signal amplitude

–

400

–

2000

mVp-p

Nominal frequency

Oscillation mode

–

24.000

–

MHz

–

Fundamental

Frequency tolerance

Tolerance stability over temp

Equivalent series resistance

Load capacitance

@25°C

–

±10

–

ppm

Ω

@0°C to +70°C

–

±10

–

50

–

12

–

pF

Operating temperature range

Storage temperature range

Drive level

0

+70

+125

200

±10

2

°C

–40

–

°C

–

W

ppm/year

pF

Aging

–

Shunt capacitance

–

HID Peripheral Block

The peripheral blocks of the CYW20733 all run from a single 128-kHz low-power RC oscillator. The oscillator can be turned on at the

request of any of the peripherals. If a peripheral is not enabled, it shall not assert its clock request line.

The keyboard scanner is a special case in that it may drop its clock request line even when enabled and then reassert the clock

request line if a key-press is detected.

Real-Time Clock and 32 kHz Crystal Oscillator

The CYW20733 has a 48-bit counter that can be configured to be clocked directly from a 32.768 kHz or 32.000 kHz crystal oscillator.

The real-time clock counter value is accessible via firmware.

Figure 5 shows the 32 kHz crystal (XTAL) oscillator with external components, and Table 6 lists the oscillator’s characteristics. It is a

standard Pierce oscillator using a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis was

added to eliminate any chatter when the input is around the threshold of the comparator and is ~100 mV. This circuit can be operated

with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at a similar frequency. The default component values are:

R1 = 10 M, C1 = C2 = ~10 pF. The values of C1 and C2 are used to fine-tune the oscillator.

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CYW20733

Figure 5. 32-kHz Oscillator Block Diagram

C2

32.768 kHz

R1

XTAL

C1

Table 6. XTAL Oscillator Characteristics

Parameter Symbol

Conditions

Minimum

Typical

Maximum

Unit

Output frequency

F_oscout

–

32.768

–

kHz

Frequency tolerance

–

Crystal

dependent

100

–

ppm

Start-up time

T_startup

P_drv

–

500

–

ms

XTAL drive level

For crystal

selection

0.5

W

XTAL series resistance

XTAL shunt capacitance

R_series

C_shunt

For crystal

selection

–

70

k

For crystal

selection

–

1.3

pF

1.8 GPIO Port

The CYW20733 has 40 general-purpose I/Os (GPIOs) in the 81-pin package and 58 GPIOs in the 121-pin package. All GPIOs support

programmable pull-ups and are capable of driving up to 8 mA at 3.3V or 4 mA at 1.8V, except P26, P27, P28, and P29, which are

capable of driving up to 16 mA at 3.3V or 8 mA at 1.8V. GPIO P57 is capable of sinking 100 mA for VDDIO = 3.0V and 60 mA for

VDDIO = 1.62V.

Port 0–Port 1, Port 8–Port 18, Port 20–Port 23, and Port 28–Port 38

All of these pins can be programmed as ADC inputs.

Port 26–Port 29

P[26:29] consist of four pins. All pins are capable of sinking up to 16 mA for LEDs. These pins also have the PWM function, which

can be used for LED dimming.

1.9 Keyboard Scanner

The keyboard scanner is designed to autonomously sample keys and store them into buffer registers without the need for the host

microcontroller to intervene. The scanner has the following features:

■ Ability to turn off its clock if no keys are pressed.

■ Sequential scanning of up to 160 keys in an 8 × 20 matrix.

■ Programmable number of columns from 1 to 20.

■ Programmable number of rows from 1 to 8.

■ 16-byte key-code buffer (can be augmented by firmware).

■ 128 kHz clock—allows scanning of full 160-key matrix in about 1.2 ms.

■ N-key rollover with selective 2-key lockout if ghost is detected.

■ Keys are buffered until host microcontroller has a chance to read it, or until overflow occurs.

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■ Hardware debouncing and noise/glitch filtering.

■ Low-power consumption. Single-digit µA-level sleep current.

1.9.1 Theory of Operation

The key scan block is controlled by a state machine with the following states:

Idle

The state machine begins in the idle state. In this state, all column outputs are driven high. If any key is pressed, a transition occurs

on one of the row inputs. This transition causes the 128 kHz clock to be enabled (if it is not already enabled by another peripheral)

and the state machine to enter the scan state. Also in this state, an 8-bit row-hit register and an 8-bit key-index counter is reset to 0.

Scan

In the scan state, a row counter counts from 0 up to a programmable number of rows minus 1. After the last row is reached, the row

counter is reset and the column counter is incremented. This cycle repeats until the row and column counters are both at their

respective terminal count values. At that point, the state machine moves into the Scan-End state.

As the keys are being scanned, the key-index counter is incremented. This counter is the value compared to the modifier key codes

stored, or in the key-code buffer if the key is not a modifier key. It can be used by the microprocessor as an index into a lookup table

of usage codes.

Also, as the nth row is scanned, the row-hit register is ORed with the current 8-bit row input values if the current column contains two

or more row hits. During the scan of any column, if a key is detected at the current row, and the row-hit register indicates that a hit

was detected in that same row on a previous column, then a ghost condition may have occurred, and a bit in the status register is set

to indicate this.

Scan End

This state determines whether any keys were detected while in the scan state. If yes, the state machine returns to the scan state. If

no, the state machine returns to the idle state, and the 128 kHz clock request signal is made inactive.

The microcontroller can poll the key status register.

1.10 Mouse Quadrature Signal Decoder

The mouse signal decoder is designed to autonomously sample two quadrature signals commonly generated by an optomechanical

mouse. The decoder has the following features:

■ Three pairs of inputs for X, Y, and Z (typical scroll wheel) axis signals. Each axis has two options:

❐ For the X axis, choose P2 or P32 as X0 and P3 or P33 as X1.

❐ For the Y axis, choose P4 or P34 as Y0 and P5 or P35 as Y1.

❐ For the Z axis, choose P6 or P36 as Z0 and P7 or P37 as Z1.

■ Control of up to four external high-current GPIOs to power external optoelectronics:

❐ Turn-on and turn-off time can be staggered for each HC-GPIO to avoid simultaneous switching of high currents and having multiple

high-current devices on at the same time.

❐ Sample time can be staggered for each axis.

❐ Sense of the control signal can be active high or active low.

❐ Control signal can be tristated for off condition or driven high or low, as appropriate.

1.10.1 Theory of Operation

The mouse decoder block has four 10-bit PWMs for controlling external quadrature devices and sampling the quadrature inputs at its

core.

The GPIO signals may be used to control such items as LEDs, external ICs that may emulate quadrature signals, photodiodes, and

photodetectors.

1.11 ADC Port

The CYW20733 contains a 16-bit ADC.

Additionally:

■ There are 28 analog input channels. All channels are multiplexed on various GPIOs.

■ There is a built-in reference with bandgap-based reference modes.

■ The maximum conversion rate is 187 kHz.

■ There is a rail-to-rail input swing.

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CYW20733

The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes

the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input

multiplexers that select the ADC input signal (V_inp) and the ADC reference signals (V_ref).

Table 7. Sampling Rate and Effective Number of Bits

Effective Number of Bits (ENOB)

Mode

Sampling Rate (kHz)

Latency^a(μs)

Minimum

Typical

0

1

2

3

4

10.4

10.2

9.7

13.0

12.6

12.0

11.5

10.0

5.859

171

85

21

11

5

11.7

46.875

93.75

187

9.3

7.9

a. Settling time of the ADC and filter after switching channels.

1.12 PWM

The CYW20733 has four internal PWMs. The PWM module consists of the following:

■ PWM1–4

■ Each of the four PWM channels, PWM1–4, contains the following registers:

❐ 10-bit initial value register (read/write)

❐ 10-bit toggle register (read/write)

❐ 10-bit PWM counter value register (read)

■ PWM configuration register shared among PWM1–4 (read/write). This 12-bit register is used:

❐ To configure each PWM channel

❐ To select the clock of each PWM channel

❐ To change the phase of each PWM channel

Figure 6 on page 15 shows the structure of one PWM.

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CYW20733

Figure 6. PWM Block Diagram

pwm_cfg_adr register

pwm#_init_val_adr register

10

pwm#_togg_val_adr register

10

pwm#_cntr_adr

10

cntr value is ARM readable

pwm_out

Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)

PWM cntr w/ pwm#_init_val = x (solid line)

10'H3FF

pwm_togg_val_adr

10'Hx

10'H000

pwm_out

1.13 Serial Peripheral Interface

The CYW20733 has two independent SPI interfaces. One is a master-only interface (SPI_1) and the other (SPI_2) can be either a

master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user

applications, the CYW20733 has optional I/O ports that can be configured individually and separately for each functional pin, as shown

in Table 8. The CYW20733 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20733 can also act as an

SPI slave device that supports a 1.8V or 3.3V SPI master.

Note: SPI voltage depends on VDDO/VDDM; therefore, it defines the type of devices that can be supported.

Table 8. CYW20733 First SPI Set (Master Mode)

Pin Name

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS^a

Configured Pin Name

SCL

SDA

P24

P26

P32^b

P39

–

P33^b

–

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

b. Default for serial flash.

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Table 9. CYW20733 Second SPI Set (Master Mode)

Configuration SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS^a

1

p3

p0

p1

–

2

p3

p0

p5

3

p3

p4

p1

4

p3

p4

p5

5

p3

p27

p38

p0

p1

6

p3

p5

7

p3

p1

8

p3

p5

9

p7

p1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

p7

p0

p5

p7

p4

p1

p7

p4

p5

p7

p27

p38

p0

p1

p7

p5

p7

p1

p7

p5

p24

P24

p36

P36

p25

P25

p25

p4

p27

P38

p0

p4

p27

P38

a. Any GPIO can be used as SPI_CS when SPI is in master mode.

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Table 10. CYW20733 Second SPI Set (Slave Mode)

Configuration SPI_CLK

SPI_MOSI

SPI_MISO

SPI_CS

1

p3

p0

p1

p6

2

p3

p0

p1

p2

3

p3

p0

p5

p6

4

p3

p0

p5

p2

5

p3

p0

p25

p1

p6

6

p3

p0

p2

7

p3

p4

p6

8

p3

p4

p1

p2

9

p3

p4

p5

p6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

p3

p4

p5

p2

p3

p4

p25

p1

p6

p3

p4

p2

p7

p0

p2

p7

p0

p1

p6

p7

p0

p5

p6

p7

p0

p5

p2

p7

p0

p25

p1

p2

p7

p0

p6

p7

p4

p6

p7

p4

p1

p2

p7

p4

p5

p6

p7

p4

p5

p2

p7

p4

p25

p1

p2

p7

p4

p6

p24

P24

p24

P24

p24

P24

p24

P24

p24

p27

P27

p27

P27

p33

P33

p33

P33

p38

p26

p32

p39

p26

p32

p39

P26

p32

P39

p26

p32

p39

p26

p32

p39

P26

p32

P39

p26

p32

p39

p1

p5

P25

p25

P25

p1

p5

P25

p25

P25

p1

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CYW20733

Table 10. CYW20733 Second SPI Set (Slave Mode) (Cont.)

Configuration SPI_CLK SPI_MOSI

SPI_MISO

SPI_CS

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

p24

P24

p24

P24

p36

P36

p36

P36

p36

P36

p36

P36

p36

P36

p36

P36

p38

P38

p38

P38

p27

P27

p27

P27

p33

P33

p33

P33

p38

P38

p38

P38

p5

p26

p32

p39

P26

p32

P39

p26

p32

p39

p26

p32

p39

P26

p32

P39

p26

p32

p39

p26

p32

p39

P26

p32

P39

p26

p32

p39

p26

p32

p39

P26

p32

P39

p5

P25

p25

P25

p1

p5

P25

p25

P25

p1

p5

P25

p25

P25

p1

p5

P25

p25

P25

1.14 Infrared Modulator

The CYW20733 includes hardware support for infrared TX. The hardware can transmit both modulated and unmodulated waveforms.

For modulated waveforms, hardware inserts the desired carrier frequency into all IR transmissions. IR TX can be sourced from

firmware-supplied descriptors, a programmable bit, or the peripheral UART transmitter.

If descriptors are used, they include IR on/off state and the duration between 1–32767 µsec. The CYW20733 IR TX firmware driver

inserts this information in a hardware FIFO and makes sure that all descriptors are played out without an underrun glitch. See Figure 7.

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CYW20733

Figure 7. Infrared TX

VCC

R1

Infrared‐LD

D1

U1

CYW20733

R2

IR TX

Q1

1.15 Infrared Learning

The CYW20733 includes hardware support for infrared learning. The hardware can detect both modulated and unmodulated signals.

For modulated signals, the CYW20733 can detect carrier frequencies between

10–500 kHz and the duration that the signal is present or absent. The CYW20733 firmware driver supports further analysis and

compression of a learned signal. A learned signal can then be played back through the CYW20733 IR TX subsystem. See Figure 8.

Figure 8. Infrared RX

VCC

U3

CYW20733

D2

Photodiode

IR RX

1.16 Shutter Control for 3D Glasses

The CYW20733, combined with the CYW20702, provides full system support for 3D glasses on televisions. The CYW20702 gets

frame synchronization signals from the TV, converts them into proprietary timing control messages, then passes the messages to the

CYW20733. The CYW20733 uses these messages to synchronize the shutter control for the 3D glasses with the television frames.

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The CYW20733 can provide up to four synchronized control signals for left and right eye shutter control. These four lines can output

pulses with microsecond resolution for on and off timing. The total cycle time can be set for any period up to 65535 msec. The pulses

are synchronized to each other for left and right eye shutters.

The CYW20733 seamlessly adjusts the timing of the control signals based on control messages from the CYW20702, ensuring that

the 3D glasses remain synchronized to the TV display frame.

3D hardware control on the CYW20733 works independently of the rest of the system. The CYW20733 negotiates sniff with the

CYW20702 and, except for sniff resynchronization periods, most of the CYW20733 circuitry remains in a low power state while the

3D glasses subsystem continues to provide shutter timing and control pulses. This significantly reduces total system power

consumption.

1.17 Triac Control

The CYW20733 includes hardware support for zero-crossing detection and trigger control for up to four triacs. The CYW20733 detects

zero-crossing on the AC zero detection line and uses that to provide a pulse that is offset from the zero crossing. This allows the

CYW20733 to be used in dimmer applications, as well as any other applications that require a control signal that is offset from an

input event.

The zero-crossing hardware includes an option to suppress glitches. See Figure .

Figure 9. Triac Control (TBD)

1.18 Cypress Proprietary Control Signalling and Triggered Broadcom Fast Connect

Cypress Proprietary Control Signaling (BPCS) and Triggered Broadcom Fast Connect (TBFC) are Cypress-proprietary baseband

(ACL) suspension and low-latency reconnection mechanisms that reestablish the baseband connection with the peer controller that

also supports BPCS/TBFC.

The CYW20733 uses BPCS primitives to allow a Human Interface Device (HID) to suspend all RF traffic after a configurable idle

period with no reportable activity. To conserve power, it can then enter one of its low power states while still logically remaining

connected at the L2CAP and HID layers with the peer device. When an event requires the HID to deliver a report to the peer device,

the CYW20733 uses the TBFC and BPCS mechanisms to reestablish the baseband connection and immediately resume L2CAP

traffic, greatly reducing latency between the event and delivery of the report to the peer device.

To achieve power savings and low latencies that cannot be achieved using long sniff intervals, certain applications may make use of

the CYW20733 Broadcom Fast Connect (BFC) mechanism, which will eliminate the need to maintain an RF link, while still being able

to establish ACL and L2CAP connections much faster than regular methods.

1.19 Integrated Filterless Class-D Audio Amplifier

The CYW20733 has an integrated speaker driver that includes both the digital path and an internal audio amplifier. The digital audio

path includes a FIFO, LPF, rate adapter, and PWM modulator. The output of the PWM modulator drives an on-chip class-D high

efficiency audio amplifier as shown in the figure below.

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CYW20733

Figure 10. Class-D Block Diagram

667 kHz or 1.33 MHz

PWM Modulator

150 kHz

From FIFO

To Class-D

audio amplifier

16

22

16

Hi-Fi Rate

Adapter

ΔΣ-

16 LPF

M

MOD.

8 kHz

128 kHz

256 kHz

352.8 kHz

705.6 kHz

768 kHz

16 kHz

M = 160 or 320

22.05 kHz

44.1 kHz

48 kHz

AP Interface

3

The on-chip Class-D audio amplifier is designed to drive up to 200 mW into an 8 load and has a range of 20 Hz to 20 kHz, covering

the entire audio spectrum. The amplifier is designed to deliver maximum dynamic range and power efficiency while minimizing

quiescent current. The amplifier has two nonoverlapping switch drivers and a pair of MOSFET power switches for bridge-tie load. The

digital Class-D modulator converts the audio input to a PWM signal that drives the switch driver. The modulator bitstream is retimed

by a low-jitter 24/48 MHz clock at the input of the nonoverlapping switch drivers, used to prevent large crowbar currents during

switching. A large W/L aspect ratio of the power transistor is used to minimize the on-resistance of the devices for improved efficiency.

The integrated audio amplifier requires a 3.0V regulated power supply. The required LDO characteristic is shown in Table 11.

Table 11. LDO Requirement for the Integrated Audio Amplifier

Parameter

Condition

Minimum

Typical

Maximum

Unit

Output voltage

–

2.9

–

3.1

V

Output load current

–

200

40

–

mA rms

mV

Load regulation

Vin = 2.9V and load current = 200 mA –

Power supply rejection ration (PSRR)

Output impedance

–

60

dB

–

20

1.5

m

Output spot noise

At 1 kHz

Vrms/

sqrt (Hz)

Output noise

–

50

Vrms

1.20 High-Current I/O

The CYW20733 has one high-current I/O pin (GPIO P57) capable of sinking up to 100 mA with a maximum output voltage of 0.4V

(VDDIO = 3.0V). For VDDIO = 1.62V, GPIO P57 is limited to sinking up to 60 mA. This pin can be used for LEDs, motors, or other

high current devices. This pin can also be used as a GPIO if high current sink capability is not required. An example usage for driving

a motor/vibrator is shown in Figure 11.

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CYW20733

Figure 11. Motor/Vibrator Circuit

D1

VCC

MA2S111

U1

CYW20733

MG1

1

2

P57

2

Motor

C1

10 uF

1.21 Power Management Unit

The Power Management Unit (PMU) provides power management features that can be invoked by software through power

management registers or packet handling in the baseband core.

1.21.1 RF Power Management

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz trans-

ceiver, which then processes the power-down functions accordingly.

1.21.2 Host Controller Power Management

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the

disabling of the on-chip regulator when in Deep-sleep mode.

1.21.3 BBC Power Management

There are several low-power operations for the BBC:

■ Physical layer packet handling turns RF on and off dynamically within packet TX and RX.

■ Bluetooth-specified low-power connection sniff mode. While in these low-power connection modes, the CYW20733 runs on the

Low-Power Oscillator (LPO) and wakes up after a predefined time period.

The CYW20733 automatically adjusts its power dissipation based on user activity. The following power modes are supported:

■ Active mode

■ Idle mode

■ Suspend mode

■ Power-down mode

■ HIDOFF mode

The CYW20733 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered

when user activity resumes.

HIDOFF mode is one of the power modes in which the core is powered down and only supervisory circuits running directly from the

battery retain power.

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2. Pin Assignments

Table 12. Pin Descriptions

Pin Number

Power Do-

main

Pin Name

I/O

Description

81-pin

FBGA

121-pin

FBGA

56-pin

QFN

Radio I/O

D1

RF Power Supplies

E1

9

RFP

I/O

VDDTF

RF antenna port

B1

C1

6

VDDIF

I

VDDIF

IFPLL power supply

RF front-end supply

VCO, LOGEN supply

RFPLL and crystal oscillator supply

PA supply

E1

F1

G1

H1

D1

11

12

13

7

VDDLNA

VDDRF

VDDPX

VDDTF

VDDLNA

VDDRF

VDDPX

VDDTF

F1

G1

C1

Power Supplies

A3, J7

A2, L7

B4, A8, E11

L8

5

VDDC

I

VDDC

Baseband core supply

I/O pad and core supply

I/O pad supply

A7

54

28

–

VDDO

J6

VDDM

VDD1P2

VDDSP

VDDM

VDD1P2

VDDSP

–

L3

Speaker differential clock conversion power supply

Speaker analog power supply

–

K10, L10

–

Ground

C2, D2, E2, F2, F8, H7, G7, F7, Center VSS

G2, E3, F3, H3, H6, G6, H5, G5, paddle

J3, E4, E5, E6, F5, H4, G4, J3,

I

VSS

Ground

E7

H3, G3, K2, J2,

H2, G2, F2, E2,

D2

–

K3

–

VSS1P2

VSSSP

I

–

Speaker differential clock conversion ground

Speaker analog ground

J9, J10, J11

Clock Generator and Crystal Interface

J1

K1

16

XTALI

I

VDDRF

Crystal oscillator input. See “Crystal Oscillator”

on page 10 for options.

J2

–

L1

15

–

XTALO

TP1

O

I

VDDPX

Crystal oscillator output.

C2

XTAL divide by 2.

Connect to GND if main XTAL = 24 MHz.

H1

B4

J1

14

–

RES

O

I

VDDPX

External calibration resistor, 15 k at 1%

A3

XTALI32K

Low-power oscillator (LPO) input.

Alternate function:

•

P39 (FBGA-81 only)

D5

B3

–

XTALO32K

O

VDDPX

LPO output.

Alternate function:

•

P38 (FBGA-81 only)

Core

B2

C3

B2

L2

2

RESET_N

TMC

I/O PU VDDO

Active-low system reset with open-drain output

and internal pull-up resistor.

G3

H2

1

I

VDDO

VDDM

Device test mode control.

Connect to GND for all applications.

17

TMA

ARM JTAG debug mode control.

Connect to GND for all applications.

Speaker

–

L11

K11

–

AMPLP

AMPLN

O

VDDSP

Speaker driver positive output

Speaker driver negative output

Document No. 002-14859 Rev. *R

Page 23 of 67

CYW20733

Table 12. Pin Descriptions (Cont.)

Pin Number

Power Do-

main

Pin Name

I/O

Description

81-pin

FBGA

121-pin

FBGA

56-pin

QFN

PCM2/I²S

G5

G4

F4

F5

J8

J7

K7

K8

24

23

22

25

PCM_SYNC

PCM_CLK

PCM_IN

I/O, PD VDDM

Frame synchronization for PCM interface.

Alternate function:

•

I²S word select

Clock for PCM interface.

Alternate function:

•

I²S clock

I, PU

VDDM

Data input for PCM interface.

Alternate function:

•

I²S data input

PCM_OUT

O, PD VDDM

Data output for PCM interface.

Alternate function:

•

I²S data output

UART

J4

K6

L6

L5

K5

20

21

19

18

UART_RXD

UART_TXD

I

VDDM

UART serial input – Serial data input for the HCI

UART interface.

J5

O, PU VDDM

UART serial output – Serial data output for the HCI

UART interface.

H4

H5

UART_RTS_N O, PU VDDM

UART_CTS_N I, PU VDDM

Request to send (RTS) for HCI UART interface.

Leave unconnected if not used.

Cleartosend(CTS)for HCIUARTinterface. Leave

unconnected if not used.

BSC

H6

L9

K9

26

27

SDA

SCL

I/O, PU VDDM

Data signal for an external I²C device.

Alternate function:

•

SPI_1: MOSI (master only)

H7

Clock signal for an external I²C device.

Alternate function:

•

SPI_1: SPI_CLK (master only)

LDO Regulator Power Supplies

A2

A1

B1

3

4

LDOIN

I

LDOIN

Battery input supply for the LDO

LDO output

LDOOUT

O

LDOOUT

Document No. 002-14859 Rev. *R

Page 24 of 67

CYW20733

Table 13. GPIO Pin Descriptions^a

Pin Number

Default Di-

rection

POR

State

Power

Domain

Pin Name

Alternate Function Description

81-pin 121-pin 56-pin

FBGA FBGA QFN

H8

H9

29

P0

Input

Floating

VDDO

•

GPIO: P0

Keyboard scan input (row): KSI0

A/D converter input 29

Peripheral UART: puart_tx

SPI_2: MOSI (master and slave)

IR_RX

60Hz_main

Note: Not available during TMC = 1.

J8

G9

31

P1

Input

Floating

VDDO

•

GPIO: P1

Keyboard scan input (row): KSI1

A/D converter input 28

Peripheral UART: puart_rts

SPI_2: MISO (master and slave)

IR_TX

J9

H10

H11

G10

30

32

34

P2

P3

P4

Input

Floating

VDDO

•

GPIO: P2

Keyboard scan input (row): KSI2

Quadrature: QDX0

Peripheral UART: puart_rx

SPI_2: SPI_CS (slave only)

H9

G8

•

GPIO: P3

Keyboard scan input (row): KSI3

Quadrature: QDX1

Peripheral UART: puart_cts

SPI_2: SPI_CLK (master and slave)

•

GPIO: P4

Keyboard scan input (row): KSI4

Quadrature: QDY0

Peripheral UART: puart_rx

SPI_2: MOSI (master and slave)

IR_TX

G9

F8

F10

F11

33

35

P5

P6

Input

Floating

VDDO

•

GPIO: P5

Keyboard scan input (row): KSI5

Quadrature: QDY1

Peripheral UART: puart_tx

SPI_2: MISO (master and slave)

•

GPIO: P6

Keyboard scan input (row): KSI6

Quadrature: QDZ0

Peripheral UART: puart_rts

SPI_2: SPI_CS (slave only)

60Hz_main

F9

E8

E10

D11

36

37

P7

P8

Input

Floating

VDDO

•

GPIO: P7

Keyboard scan input (row): KSI7

Quadrature: QDZ1

Peripheral UART: puart_cts

SPI_2: SPI_CLK (master and slave)

•

GPIO: P8

Keyboard scan output (column): KSO0

A/D converter input 27

External T/R switch control: ~tx_pd

Document No. 002-14859 Rev. *R

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CYW20733

Table 13. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

POR

State

Power

Domain

Pin Name

Alternate Function Description

81-pin 121-pin 56-pin

FBGA

QFN

E9

D10

38

P9

Input

Floating

VDDO

•

GPIO: P9

Keyboard scan output (column): KSO1

A/D converter input 26

External T/R switch control: tx_pd

D8

E9

39

P10

Input

Floating

VDDO

•

GPIO: P10

Keyboard scan output (column): KSO2

A/D converter input 25

External PA ramp control: ~PA_Ramp

D9

C9

C8

C11

C10

B11

41

40

43

P11

P12

P13

Input

Floating

VDDO

•

GPIO: P11

Keyboard scan output (column): KSO3

A/D converter input 24

•

GPIO: P12

Keyboard scan output (column): KSO4

A/D converter input 23

•

GPIO: P13

Keyboard scan output (column): KSO5

A/D converter input 22

External PA ramp control: ~PA_Ramp

Triac control 3

B9

A9

B10

A11

44

42

P14

P15

Input

Floating

VDDO

•

GPIO: P14

Keyboard scan output (column): KSO6

A/D converter input 21

External T/R switch control: ~tx_pd

Triac control 4

•

GPIO: P15

Keyboard scan output (column): KSO7

A/D converter input 20

IR_RX

60Hz_main

B7

B8

C7

G7

F7

D7

A9

A10

B9

C9

D9

E8

–

P16

P17

P18

P19

P20

P21

Input

Floating

VDDO

•

GPIO: P16

Keyboard scan output (column): KSO8

A/D converter input 19

•

GPIO: P17

Keyboard scan output (column): KSO9

A/D converter input 18

•

GPIO: P18

Keyboard scan output (column): KSO10

A/D converter input 17

•

GPIO: P19

Keyboard scan output (column): KSO11

•

GPIO: P20

Keyboard scan output (column): KSO12

A/D converter input 15

•

GPIO: P21

Keyboard scan output (column): KSO13

A/D converter input 14

Triac control 3

Document No. 002-14859 Rev. *R

Page 26 of 67

CYW20733

Table 13. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

POR

State

Power

Domain

Pin Name

Alternate Function Description

81-pin 121-pin 56-pin

FBGA FBGA QFN

A8

G8

–

P22

Input

Floating

VDDO

•

GPIO: P22

Keyboard scan output (column): KSO14

A/D converter input 13

Triac control 4

D6

G6

C6

F9

–

P23

P24

Input

Floating

VDDO

•

GPIO: P23

Keyboard scan output (column): KSO15

A/D converter input 12

45

•

GPIO: P24

Keyboard scan output (column): KSO16

SPI_2: SPI_CLK (master and slave)

SPI_1: MISO (master only)

Peripheral UART: puart_tx

F6

A4

D8

A5

46

56

P25

Input

Floating

VDDO

•

GPIO: P25

Keyboard scan output (column): KSO17

SPI_2: MISO (master and slave)

Peripheral UART: puart_rx

P26

PWM0

•

GPIO: P26

Keyboard scan output (column): KSO18

SPI_2: SPI_CS (slave only)

SPI_1: MISO (master only)

Optical control output: QOC0

Triac control 1

Current: 16 mA sink

B3

C3

B5

A4

55

P27

Input

Floating

VDDO

•

GPIO: P27

PWM1

Keyboard scan output (column): KSO19

SPI_2: MOSI (master and slave)

Optical control output: QOC1

Triac control 2

Current: 16 mA sink

–

P28

PWM2

•

GPIO: P28

Optical control output: QOC2

A/D converter input 11

LED1

Current: 16 mA sink

D3

C4

–

P29

PWM3

Input

Floating

VDDO

•

GPIO: P29

Optical control output: QOC3

A/D converter input 10

LED2

Current: 16 mA sink

C6

B6

C8

B8

47

–

P30

P31

Input

Floating

VDDO

•

GPIO: P30

A/D converter input 9

Pairing button pin in default FW

Peripheral UART: puart_rts

•

GPIO: P31

A/D converter input 8

EEPROM WP pin in default FW

Peripheral UART: puart_tx

Document No. 002-14859 Rev. *R

Page 27 of 67

CYW20733

Table 13. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

POR

State

Power

Domain

Pin Name

Alternate Function Description

81-pin 121-pin 56-pin

FBGA FBGA QFN

A6

B7

48

P32

Input

Floating

VDDO

•

GPIO: P32

A/D converter input 7

Quadrature: QDX0

SPI_2: SPI_CS (slave only)

SPI_1: MISO (master only)

Auxiliary clock output: ACLK0

Peripheral UART: puart_tx

C4

C5

B6

C7

53

P33

P34

Input

Floating

VDDO

•

GPIO: P33

A/D converter input 6

Quadrature: QDX1

SPI_2: MOSI (slave only)

Auxiliary clock output: ACLK1

Peripheral UART: puart_rx

–

•

GPIO: P34

A/D converter input 5

Quadrature: QDY0

Peripheral UART: puart_rx

External T/R switch control: tx_pd

B5

A5

D7

A7

49

50

P35

P36

Input

Floating

VDDO

•

GPIO: P35

A/D converter input 4

Quadrature: QDY1

Peripheral UART: puart_cts

•

GPIO: P36

A/D converter input 3

Quadrature: QDZ0

SPI_2: SPI_CLK (master and slave)

Auxiliary Clock Output: ACLK0

Battery detect pin in default FW

External T/R switch control: ~tx_pd

D4

A6

–

P37

Input

Floating

VDDO

•

GPIO: P37

A/D converter input 2

Quadrature: QDZ1

SPI_2: MISO (slave only)

Auxiliary clock output: ACLK1

D5

B4

C5

D4

51

52

P38

P39

Input

Floating

VDDO

•

GPIO: P38

A/D converter input 1

SPI_2: MOSI (master and slave)

IR_TX

XTALO32K (FBGA-81 only)

•

GPIO: P39

SPI_2: SPI_CS (slave only)

SPI_1: MISO (master only)

Infrared control: IR_RX

External PA ramp control: PA_Ramp

60Hz_main

XTALI32K (FBGA-81 only)

–

H8

–

P40

Input

Floating

VDDO

•

GPIO: P40

pcm2_clk

Document No. 002-14859 Rev. *R

Page 28 of 67

CYW20733

Table 13. GPIO Pin Descriptions^a(Cont.)

Pin Number

Default Di-

rection

POR

State

Power

Domain

Pin Name

Alternate Function Description

81-pin 121-pin 56-pin

FBGA FBGA QFN

–

K4

–

P41

P42

P43

Input

Floating

VDDO

•

GPIO: P41

pcm2_sync

–

F6

J5

Input

•

GPIO: P42

pcm2_di

•

GPIO: P43

pcm2_do

–

J4

–

P44

P45

P46

P47

P48

P49

P50

P51

P52

P53

P54

P55

P56

P57

Input

Floating

VDDO

•

GPIO: P44

GPIO: P45

GPIO: P46

GPIO: P47

GPIO: P48

GPIO: P49

GPIO: P50

GPIO: P51

GPIO: P52

GPIO: P53

GPIO: P54

GPIO: P55

GPIO: P56

J6

L4

E7

E6

D6

E5

D5

F4

F3

E4

E3

D3

G11

•

GPIO: P57

PWM3

a. During power-on reset, all inputs are disabled.

2.1 Ball Maps

This section presents the CYW20733 ball maps.

2.1.1 81-Pin FBGA Ball Map

Figure 12 shows the 81-pin FBGA package ball map.

Document No. 002-14859 Rev. *R

Page 29 of 67

CYW20733

Figure 12. 81-Pin FBGA Ball Map

1

2

3

4

5

6

7

8

9

P26

PWM0

LDOOUT

LDOIN

VDDC

P36

P32

VDDO

P22

P15

A

B

C

D

E

F

A

P27

PWM1

P39/

XTALI32K

VDDIF

VDDTF

RFP

RESET_N

VSS

P35

P34

P31

P30

P23

VSS

P25

P24

SDA

P16

P18

P21

VSS

P20

P19

SCL

P17

P13

P10

P8

P14

B

P28

PWM2

P33

P37

P12

C

P29

PWM3

P38/

XTALO32K

VSS

P11

D

VDDLNA

VDDRF

VDDPX

RES

VSS

P9

E

PCM_

OUT

VSS

PCM_IN

P6

P7

F

PCM_

CLK

PCM_

SYNC

VSS

TMC

VSS

P4

P5

G

H

J

G

UART_

RTS_N

UART_

CTS_N

TMA

P0

P3

H

UART_

RXD

UART_

TXD

XTALI

XTALO

VSS

VDDM

VDDC

P1

P2

J

1

2

3

4

5

6

7

8

9

Document No. 002-14859 Rev. *R

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CYW20733

2.1.2 121-Pin FBGA Ball Map

Figure 13 shows the 121-pin FBGA package ball map.

Figure 13. 121-Pin FBGA Ball Map

1

2

3

4

5

6

7

8

9

10

11

P28

PWM2

P26

PWM0

LDOIN

VDDC

XTALI32K

P37

P36

VDDO

P16

P17

P15

A

B

C

D

E

F

A

P27

PWM1

LDOOUT

VDDIF

VDDTF

RFP

TMC

TP1

VSS

XTALO32K

RESET_N

P56

VDDO

P33

P23

P49

P48

P42

VSS

P45

P32

P34

P31

P30

P25

P21

VSS

P22

P40

P18

P19

P20

P10

P24

P1

P14

P12

P9

P13

B

P29

PWM3

P38

P51

P50

VSS

P43

P11

C

P39

P54

P52

VSS

P44

P41

P35

P8

D

P55

P47

P7

VDDO

E

VDDLNA

VDDRF

VDDPX

RES

P53

VSS

P5

P6

F

VSS

P4

P57

G

H

J

G

VSS

P0

P2

P3

H

PCM_

SYNC

VSS

PCM_CLK

PCM_IN

VSSSP

SCL

VSSSP

VDDSP

VSSSP

J

UART_

CTS_N

UART_

RXD

XTALI

VSS1P2

PCM_OUT

AMPLN

K

L

K

UART_

RTS_N

UART_

TXD

XTALO

TMA

VDD1P2

P46

VDDC

VDDM

SDA

VDDSP

AMPLP

L

1

2

3

4

5

6

7

8

9

10

11

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CYW20733

2.1.3 56-Pin QFN Diagram

Figure 14 shows the 56-pin QFN package.

Figure 14. 56-Pin QFN Diagram

TMC

RESET_N

LDOIN

LDOOUT

VDDC

VDDIF

VDDTF

NC

P15

P11

P12

P10

P9

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

29

3

4

5

P8

6

P7

7

P6

8

RFP

P4

9

NC

P5

10

11

12

13

14

VDDLNA

VDDRF

VDDPX

RES

P3

P1

P2

P0

Document No. 002-14859 Rev. *R

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CYW20733

3. Specifications

3.1 Electrical Characteristics

Table 14 shows the maximum electrical rating for voltages referenced to the VDD pin.

Table 14. Maximum Electrical Rating

Rating

Symbol

Value

Unit

V

DC supply voltage for RF domain

–

1.32

1.4

3.8

1.4

3.3

DC supply voltage for Core domain

DC supply voltage for VDDM domain (UART/I²C)

DC supply voltage for VDDO domain

DC supply voltage for LDOIN

V

DC supply voltage for VDDLNA

DC supply voltage for VDDTF

V

Voltage on input or output pin

VSS – 0.3 to VDD + 0.3

0 to +70

V

Operating ambient temperature range

Storage temperature range

Topr

Tstg

°C

–40 to +125

Table 15 shows the power supply characteristics for the range T_J= 0 to 125°C.

Table 15. Power Supply

Parameter

Minimum^a

Typical

Maximum^a

Unit

DC supply voltage for RF

DC supply voltage for Core

1.14

1.2

1.26

3.63

1.26

3.3

V

1.14

1.62

1.14

1.2

–

DC supply voltage for VDDM (UART/I²C)

DC supply voltage for VDDO

–

DC supply voltage for LDOIN

DC supply voltage for VDDLNA

DC supply voltage for VDDTF

–

1.2^b

a. Overall performance degrades beyond minimum and maximum supply voltages.

b. 1.2V for Class 2 output with internal VREG.

Table 16 shows the digital level characteristics for the LDO (VSS = 0V).

Table 16. LDO Regulator Electrical Specifications

Parameter

Conditions

Min

Typ

Max

Unit

Input voltage range

–

1.62

–

3.63

V

Default output voltage

Output voltage

–

1.2

–

V

Range

0.88

–

1.32

80

V

Step size

40

–

mV

Accuracy at any step

–

–5

–

+5

%

Load current

–

60

mA

Line regulation

Load regulation

Vin from 1.62 to 3.63V, I_load= 30 mA

–0.5

–

0.5

0.15

%V_O/V

%V_O/mA

I

_loadfrom 1 µA to 30 mA, Vin = 3.3V,

0.1

^{Bonding R = 0.3}

Quiescent current

No load @Vin = 3.3V

*Current limit enabled

–

6^a

–

12^a

200

µA

nA

Power-down current

Vin = 3.3V, worst@70°C

a. Includes the bandgap quiescent current.

Document No. 002-14859 Rev. *R

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CYW20733

Table 17. ADC Specifications

Parameter

ADC Characteristics

Number of Input channels

Channel switching rate

Input signal range

Symbol

Conditions

Min

Typ

Max

Unit

–

0

28

–

f_ch

V_inp

–

187

3.63

–

kHz

V

–

Reference settling time

Input resistance

7.5

–

s

R_inp

Single-ended, input range of 0–1.2V

–

680

1.84

3

–

k

M

pF

Single-ended, input range of 0–2.4V

–

Single-ended, input range of 0–3.6V

–

Input capacitance

Conversion rate

Resolution

C_inp

f_C

–

5

–

5.859

–

187

–

kHz

bits

R

–

16

Effective number of bits

–

In guaranteed performance range

See Table 7

on page 14

–

Absolutevoltagemeasurement

error

Integral nonlinearity¹

Differential nonlinearity¹

Notes:

Using on-chip ADC firmware driver

–

±2

%

INL

In guaranteed performance range

–1

–

1

LSB¹

DNL

1. LSBs are expressed at the 10-bit level.

Table 18. Integrated Audio Amplifier Electrical Specifications

Parameter Conditions

Min

Typ

Max

Unit

Analog supply voltage

–

2.9

3.0

3.1

1.32

–

V

Digital supply voltage

Quiescent current

Power down current

Output power

1.08

–

1.2

2

V

Zero digital input

–

mA

A

mW

%

–

0.5

240

70

68

40

–

R_L= 8Ω

200

–

Maximum efficiency

Dynamic range (DR)

At 200 mW output power

At –60 dBFs input

At 200 mW output power

–

65

–

dB

Signal-to-noise plus distortion ratio

(SNDR)

–

Table 19. Digital Level^a

Characteristics

Symbol

Min

Typ

Max

Unit

Input low voltage

VIL

–

0.4

–

V

Input high voltage

VIH

VIL

0.75 × VDDO

–

V

Input low voltage (VDDO = 1.62V)

Input high voltage (VDDO = 1.62V)

Output low voltage^b

–

0.4

–

V

VIH

VOL

VOH

CIN

1.2

–

V

–

0.4

–

V

Output high voltage^b

VDDO – 0.4

–

V

Input capacitance (VDDMEM domain)

0.12

–

pF

a. This table is also applicable to VDDMEM domain.

b. At the specified drive current for the pad.

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CYW20733

Table 20. Current Consumption, Class 1^a

Operational Mode

Conditions

Typ

Unit

mA

Receive (1 Mbps)

Transmit (1 Mbps)

Peak current level during reception of a basic-rate packet.

28.2

Peak current level during the transmission of a basic-rate packet: GFSK

output power = 10 dBm.

63.1

mA

Receive (EDR)

Transmit (EDR)

Peak current level during the reception of a 2 or 3 Mbps rate packet.

28.6

mA

Peak current level during the transmission of a 2 or 3 Mbps rate packet: EDR 63.7

output power = 8 dBm.

Average Current

DM1/DH1 (RX)

Average current during basic rate maximum throughput connection, which 24.3

includes only this packet type.

mA

DM5/DH5 (RX)

3DH1 (RX)

Average current during basic rate maximum throughput connection, which 26.3

includes only this packet type.

Average current during extended data rate maximum throughput connection 24.9

which includes only this packet type.

3DH5 (RX)

Averagecurrentduringextended dataratemaximumthroughputconnection, 26.4

which includes only this packet type.

DM1/DH1 (TX)

DM5/DH5 (TX)

3DH1 (TX)

Average current during basic rate maximum throughput connection, which 29.6

includes only this packet type.

Average current during basic rate maximum throughput connection, which 47.2

includes only this packet type.

Averagecurrentduringextended dataratemaximumthroughputconnection, 29.7

which includes only this packet type.

3DH5 (TX)

Averagecurrentduringextended dataratemaximumthroughputconnection, 44.8

which includes only this packet type.

Paging

–

23.7

290

mA

Sniff slave (495 ms)

Based on one attempt and no timeout parameter. Quality connection that

rarely requires more than minimum packet exchange. Sniff master follows

the optimal sniff protocol of the CYW20702 master.

A

Sniff slave (22.5 ms)

Sniff slave (11.25 ms)

–

2.57

4.93

mA

a. Current consumption measurements are taken at LDOIN. LDOIN = VDDIO = 2.6V, VDDPA = 3.0V.

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Table 21. Current Consumption, Class 2 (0 dBm)^a

Operational Mode

Conditions

Typ

Unit

mA

Receive (1 Mbps)

Transmit (1 Mbps)

Peak current level during the reception of a basic-rate packet.

29.0

Peak current level during the transmission of a basic-rate packet: GFSK

output power = 0 dBm.

39.3

mA

Receive (EDR)

Transmit (EDR)

Peak current level during the reception of a 2 or 3 Mbps rate packet.

30.5

mA

Peak current level during the transmission of a 2 or 3 Mbps rate packet: EDR 39.3

output power = 0 dBm.

Average Current

DM1/DH1 (RX)

Average current during basic rate maximum throughput connection, which 22.1

includes only this packet type.

mA

DM5/DH5 (RX)

3DH1 (RX)

Average current during basic rate maximum throughput connection, which 25.8

includes only this packet type.

Averagecurrentduring extendeddataratemaximumthroughputconnection, 22.8

which includes only this packet type.

3DH5 (RX)

Averagecurrentduring extendeddataratemaximumthroughputconnection, 24.7

which includes only this packet type.

DM1/DH1 (TX)

DM5/DH5 (TX)

3DH1 (TX)

Average current during basic rate maximum throughput connection, which 22.0

includes only this packet type.

Average current during basic rate maximum throughput connection, which 30.9

includes only this packet type.

Averagecurrentduring extendeddataratemaximumthroughputconnection, 22.1

which includes only this packet type.

3DH5 (TX)

Averagecurrentduring extendeddataratemaximumthroughputconnection, 31.6

which includes only this packet type.

Paging

–

22.9

240

mA

Sniff slave (495 ms)

Based on one attempt and no timeout parameter. Quality connection that

rarely requires more than minimum packet exchange. Sniff master follows

optimal sniff protocol of CYW20702 master.

A

Sniff slave (22.5 ms)

Sniff slave (11.25 ms)

–

2.27

4.46

mA

a. Current consumption measurements are taken at LDOIN. LDOIN = VDDIO = 2.6V, VDDPA = 1.2V.

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Table 22. Current Consumption

Operational Mode

Sleep

Conditions

Typ

Unit

A

Internal LPO is in use.

–

46.5

HIDOFF

1.1

A

Inquiry scan (1.28 sec.)

Page Scan (R1)

Periodic scan rate is R1 (1.28 seconds).

540

490

940

A

Inquiry Scan + Page Scan (R1)

Both inquiry and page scans are interlaced together at a

periodic scan rate of 1.28 seconds.

A

3.2 RF Specifications

Table 23. Receiver RF Specifications^a,b

Parameter

Conditions

Minimum Typical ^cMaximum

Unit

General

Frequency range

RX sensitivity ^d

–

2402

–

2480

–85

–81

–20

MHz

GFSK, 0.1% BER, 1 Mbps

/4-DQPSK, 0.01% BER, 2 Mbps

8-DPSK, 0.01% BER, 3 Mbps

GFSK, 1 Mbps

–

–89

–91

–86

–

dBm

Maximum input

/4-DQPSK, 8-DPSK, 2/3 Mbps

–

Interference Performance

C/I cochannel

GFSK, 0.1% BER

–

11

dB

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I > 3 MHz adjacent channel

C/I image channel

GFSK, 0.1% BER

0

GFSK, 0.1% BER

–30.0

–40.0

–9.0

–20.0

13

GFSK, 0.1% BER

C/I 1 MHz adjacent to image channel

C/I cochannel

GFSK, 0.1% BER

/4-DQPSK, 0.1% BER

8-DPSK, 0.1% BER

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I > 3 MHz adjacent channel

C/I image channel

0

–30.0

–40.0

–7.0

–20.0

21

C/I 1 MHz adjacent to image channel

C/I cochannel

C/I 1 MHz adjacent channel

C/I 2 MHz adjacent channel

C/I > 3 MHz adjacent channel

C/I image channel

5

–25.0

–33.0

0

C/I 1 MHz adjacent to image channel

–13.0

Out-of-Band Blocking Performance (CW) ^e

30–2000 MHz

0.1% BER

–

–10.0

–27

–

dBm

2000–2399 MHz

2498–3000 MHz

–27

3000 MHz–12.75 GHz

–10.0

Intermodulation Performance ^f

BT, ∆f = 5 MHz

–

–39.0

–

dBm

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Table 23. Receiver RF Specifications^a,b(Cont.)

Parameter

Conditions

Minimum Typical ^cMaximum

Unit

Spurious Emissions ^g

30 MHz to 1 GHz

–

–57

–47

dBm

1 GHz to 12.75 GHz

a. All specifications are single ended. Unused inputs are left open.

b. All specifications, except typical, are for commercial temperatures.

c. Typical operating conditions are 1.22V operating voltage and 25°C ambient temperature.

d. The receiver sensitivity is measured at a BER of 0.1% on the device interface.

e. Meets this specification using front-end band-pass filter.

f. f0 = –64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n × 1 MHz, where

n is 3, 4, or 5. For the typical case, n = 5.

g. Includes baseband radiated emissions.

Table 24. Transmitter RF Specifications ^a,b

Parameter

Conditions

Minimum

Typical

Maximum

Unit

General

Frequency range

–

2402

–

2480

MHz

Class1: GFSK Tx power^cd

Class1: EDR Tx power^de

Class 2: GFSK Tx power^d

Power control step

6.5

4.5

–0.5

2

10

8

–

6

dBm

dB

3

4

Modulation Accuracy

/4-DQPSK frequency stability

/4-DQPSK RMS DEVM

/4-QPSK peak DEVM

/4-DQPSK 99% DEVM

8-DPSK frequency stability

8-DPSK RMS DEVM

8-DPSK peak DEVM

–

–10

–

10

20

35

30

10

13

25

20

kHz

%

–

%

–

%

–10

–

kHz

%

–

%

8-DPSK 99% DEVM

–

%

In-Band Spurious Emissions

+500 kHz

–

–20

–26

–20

–40

dBc

dBm

1.0 MHz < |M – N| < 1.5 MHz

1.5 MHz < |M – N| < 2.5 MHz

|M – N| > 2.5 MHz

Out-of-Band Spurious Emissions

30 MHz to 1 GHz

–

–36.0 ^f

–30.0 ^{f, g}

–47.0

dBm

1 GHz to 12.75 GHz

1.8 GHz to 1.9 GHz

5.15 GHz to 5.3 GHz

–47.0

a. All specifications are for commercial temperatures.

b. All specifications are single-ended. Unused inputs are left open.

c. +10 dBm output for GFSK measured with VDDTF = 2.9 V.

d. Power output is measured at the device without a front-end band-pass filter.

e. +8 dBm output for EDR measured with VDDTF = 2.9 V.

f. Maximum value is the value required for Bluetooth qualification.

g. Meets this specification using a front-end band-pass filter.

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3.3 Timing and AC Characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

3.3.1 UART Timing

Table 25. UART Timing Specifications

Reference

Characteristics

Min

Max

Unit

1

2

3

Delay time, UART_CTS_N low to UART_TXD valid

–

24

10

2

Baud out

cycles

Setup time, UART_CTS_N high before midpoint of

stop bit

ns

Delay time, midpoint of stop bit to UART_RTS_N

high

Baud out

cycles

Figure 15. UART Timing

UART_CTS_N

UART_TXD

1

2

Midpoint of

STOP bit

UART_RXD

3

UART_RTS_N

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3.3.2 SPI Timing

Figure 16. SPI Timing Diagram

5

6

CS

SCLK

Mode 1

SCLK

Mode 3

2

1

MSB

LSB

MOSI

MISO

4

3

Invalid bit

MSB

Table 26. SPI1 Timing Values—SCLK = 12 MHz and VDDM = 1.8V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max

Unit

1

Output setup time, from MOSI

Tds_mo

–

23

–

ns

data valid to sample edge of SCLK

2

3

4

Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo

Tds_mi

Tdh_mi

60

ns

Input setup time, from MISO data valid to

sample edge of SCLK

TBD

Input hold time, from sample

edge of SCLK to MISO data update

5^c

6^c

Time from CS assert to first SCLK edge

Time from first SCLK edge to CS deassert

Tsu_cs

Thd_cs

½ SCLK period – 1

½ SCLK period

–

ns

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as 400

Hz by configuring the firmware.

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.

c. CS timing is firmware controlled.

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Table 27. SPI1 Timing Values—SCLK = 12 MHz and VDDM = 3.3V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max Unit

1

Output setup time, from MOSI data valid to

sample edge of SCLK

Tds_mo

–

34

–

ns

2

3

4

Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo

Tds_mi

Tdh_mi

49

Input setup time, from MISO

data valid to sample edge of SCLK

TBD

Input hold time, from sample

edge of SCLK to MISO data update

5^c

6^c

Time from CS assert to first SCLK edge

Time from first SCLK edge to CS deassert

Tsu_cs

Thd_cs

½ SCLK period – 1

½ SCLK period

–

ns

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The speed can be adjusted to as low as

400 Hz by configuring the firmware.

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.

c. CS timing is firmware controlled.

Table 28. SPI2 Timing Values—SCLK = 6 MHz and VDDM = 3.3V^a

Reference

Characteristics

Symbol

Min

Typical^b

Max Unit

1

Output setup time, from MOSI

Tds_mo

–

67

–

ns

data valid to sample edge of SCLK

2

3

4

Output hold time, from sample

edge of SCLK to MOSI data update

Tdh_mo

Tds_mi

Tdh_mi

99

ns

Input setup time, from MISO

data valid to sample edge of SCLK

TBD

Input hold time, from sample

edge of SCLK to MISO data update

5^c

6^c

Time from CS assert to first SCLK edge

Time from first SCLK edge to CS deassert

Tsu_cs

Thd_cs

½ SCLK period – 1

½ SCLK period

–

ns

a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The speed can be adjusted to as low as 400

Hz by configuring the firmware.

b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.

c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.

3.3.3 BSC Interface Timing

The specifications in Table 29 and Table 30 on page 43 reference Figure 17 on page 43.

Table 29. BSC Interface Timing Specifications (up to 1 MHz)

Reference

Characteristics

Min

Max

Unit

1

Clock frequency

100

400

800

1000

–

kHz

2

3

4

5

6

7

START condition setup time

START condition hold time

Clock low time

650

280

650

280

0

ns

–

Clock high time

Data input hold time^a

–

Data input setup time

100

–

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Table 29. BSC Interface Timing Specifications (up to 1 MHz)

Reference Characteristics

Min

Max

Unit

ns

8

STOP condition setup time

Output valid from clock

Bus free time^b

280

–

9

–

400

–

ns

10

650

ns

a. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP

conditions.

b. Time that the CBUS must be free before a new transaction can start.

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Table 30. BSC Interface Timing Specification (1 MHz through 4 MHz)

Reference Characteristics

Min

Max

Unit

1

Clock frequency^a

1.000

4.000

MHz

2

3

4

START condition setup time

START condition hold time

Clock low time^b

233

66

–

ns

½ SCL period

5

Clock high time^b

–

ns

6

7

Data input hold time^c

Data input setup time^d

0

–

ns

33.4

8

STOP condition setup time

Output valid from clock

Bus free time^e

233

–

ns

9

150

–

10

650

2

a. Maximum speed is achieved without clock stretching. Strict timing parameter adherence for modes beyond I C fast mode may require that the total

capacitance of the SDA and SCL traces be very similar so that signal transition times are very similar.

b. Programmable by firmware. Use 50% of period for overclocking frequencies greater than 2.400 MHz. Can be asymmetric (65/35 duty) for modest

overclocking—up to 2.400 MHz.

c. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP

conditions.

d. Depends on the degree of overclocking. Application-specific programmability of the hardware block can affect this parameter.

e. Time that CBUS must be free before a new transaction can start.

Figure 17. BSC Interface Timing Diagram

1

5

SCL

2

8

6

4

3

7

SDA

IN

10

9

SDA

OUT

3.3.4 PCM Interface Timing

The following is a list of the PCM interface timing diagrams.

■ PCM Electrical Timing Slave— Short Frame Sync

■ PCM Electrical Timing Master—Short Frame Sync

■ PCM Electrical Timing Burst (Slave Rx Only)—Short Frame Sync

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■ PCM Electrical Timing Slave—Long Frame Sync

■ PCM Electrical Timing Master—Long Frame Sync

■ PCM Electrical Timing Burst (Slave Rx Only)—Long Frame Sync

Note: The TX and RX timings are combined on the same diagram. The CYW20733 can only either transmit or receive in a given slot.

PCM Electrical Timing Slave— Short Frame Sync

Figure 18. PCM Electrical Timing Slave—Short Frame Sync Diagram

1

2

3

PCM_BCLK

4

5

PCM_SYNC

PCM_OUT

9

Bit 15 (Previous Frame)

High impedance

8

Bit 0

6

7

Bit 0

PCM_IN

Table 31. PCM Electrical Timing Slave—Short Frame Sync Characteristics

Reference Characteristics Minimum

Typical

Maximum

Unit

1

PCM bit clock frequency

–

12

–

MHz

2

3

4

5

6

7

8

9

PCM bit clock low time

PCM bit clock high time

PCM_SYNC setup time

PCM_SYNC hold time

PCM_OUT delay

41

8

ns

–

8

–

0

25

–

PCM_IN setup

8

PCM_IN hold

8

–

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

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PCM Electrical Timing Master—Short Frame Sync

Figure 19. PCM Electrical Timing Master—Short Frame Sync Diagram

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

High impedance

7

Bit 15 (Previous Frame)

Bit 0

5

6

PCM_IN

Table 32. Values of PCM Electrical Timing Master—Short Frame Sync Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

MHz

ns

1

PCM bit clock frequency

–

12

–

2

3

4

5

6

7

8

PCM bit clock low time

PCM bit clock high time

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

41

0

–

ns

25

–

ns

0

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

PCM Electrical Timing Burst (Slave Rx Only)—Short Frame Sync

Figure 20. PCM Electrical Timing Burst (Slave Rx-Only)—Short Frame Sync Diagram

1

2

3

PCM_BCLK

PCM_SYNC

4

5

6

7

Bit 15 (previous frame)

Bit 0

PCM_IN

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Table 33. Values of PCM Electrical Timing Burst (Slave Rx-Only)—Short Frame Sync Characteristics

Reference Characteristics Minimum Typical Maximum

Unit

MHz

ns

1

PCM bit clock frequency

–

24

–

2

3

4

5

6

7

PCM bit clock low time

PCM bit clock high time

PCM_SYNC setup time

PCM_SYNC hold time

PCM_IN setup

20.8

8

–

ns

–

ns

8

–

ns

8

–

ns

PCM_IN hold

8

–

ns

PCM Electrical Timing Slave—Long Frame Sync

Figure 21. PCM Electrical Timing Slave—Long Frame Sync Diagram

1

2

3

PCM_BCLK

PCM_SYNC

4

5

9

Bit 0

High impedance

PCM_OUT

Bit 1

6

8

7

Bit 1

PCM_IN

Table 34. Values of PCM Electrical Timing Slave—Long Frame Sync Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

1

PCM bit clock frequency

–

12

–

MHz

ns

2

3

4

5

6

7

8

9

PCM bit clock low time

PCM bit clock high time

PCM_SYNC setup time

PCM_SYNC hold time

PCM_OUT delay

41

8

–

ns

–

ns

8

–

ns

0

25

–

ns

PCM_IN setup

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

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PCM Electrical Timing Master—Long Frame Sync

Figure 22. PCM Electrical Timing Master—Long Frame Sync Diagram

1

2

3

PCM_BCLK

4

PCM_SYNC

PCM_OUT

8

High impedance

Bit 0

Bit 1

5

7

6

PCM_IN

Table 35. Values of PCM Electrical Timing Master—Long Frame Sync Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

1

PCM bit clock frequency

–

12

–

MHz

ns

2

3

4

5

6

7

8

PCM bit clock low time

PCM bit clock high time

PCM_SYNC delay

PCM_OUT delay

PCM_IN setup

41

0

–

ns

25

–

ns

0

ns

8

ns

PCM_IN hold

8

–

ns

Delay from rising edge of PCM_BCLK during last bit

period to PCM_OUT becoming high impedance

0

25

ns

PCM Electrical Timing Burst (Slave Rx Only)—Long Frame Sync

Figure 23. PCM Electrical Timing Burst (Slave Rx-Only)—Long Frame Sync Diagram

1

2

3

PCM_BCLK

PCM_SYNC

4

5

7

6

Bit 0

Bit 1

PCM_IN

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Table 36. Values of PCM Electrical Timing Burst (Slave Rx Only)—Long Frame Sync Characteristics

Reference Characteristics Minimum Typical Maximum

Unit

MHz

ns

1

PCM bit clock frequency

–

24

–

2

3

4

5

6

7

PCM bit clock low time

PCM bit clock high time

PCM_SYNC setup time

PCM_SYNC hold time

PCM_IN setup

20.8

8

–

ns

–

ns

8

–

ns

8

–

ns

PCM_IN hold

8

–

ns

3.3.5 I²S Timing

The following is a list of the I²S timing diagrams.

■ I²S Electrical Timing Slave—Short Frame WS

■ I²S Electrical Timing Master—Short Frame WS

■ I²S Electrical Timing Burst (Slave Rx Only)—Short Frame WS

■ I²S Electrical Timing Slave—Long Frame WS

■ I²S Electrical Timing Master—Long Frame WS

■ I²S Electrical Timing Burst (Slave Rx Only)—Long Frame WS

Note: The TX and RX timings are combined on the same diagram. The CYW20733 can only either transmit or receive in a given slot.

I²S Electrical Timing Slave—Short Frame WS

Figure 24. I²S Electrical Timing Slave —Short Frame WS Diagram

1

2

3

I2S_BCLK

4

I2S_WS

Bit 15 (previous frame)

I2S_OUT

Bit 0

5

7

6

Bit 0

I2S_IN

Table 37. Values of I²S Electrical Timing Slave—Short Frame WS Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

1

I²S bit clock frequency

–

12

–

MHz

ns

2

3

4

5

I²S bit clock low time

I²S bit clock high time

I2S_WS setup time

I2S_OUT delay

41

8

–

ns

–

ns

0

25

ns

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Table 37. Values of I²S Electrical Timing Slave—Short Frame WS Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

ns

6

I2S_IN setup

I2S_IN hold

8

–

7

ns

I²S Electrical Timing Master—Short Frame WS

Figure 25. I²S Electrical Timing Master— Short Frame WS Diagram

1

2

3

I2S_BCLK

4

I2S_WS

I2S_OUT

Bit 15 (previous frame)

Bit 0

5

7

6

I2S_IN

Table 38. Values of I²S Electrical Timing Master—Short Frame WS Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

MHz

ns

1

I²S bit clock frequency

–

12

–

2

3

4

5

6

7

I²S bit clock low time

I²S bit clock high time

I2S_WS delay

41

0

–

ns

25

–

ns

I2S_OUT delay

I2S_IN setup

0

ns

8

ns

I2S_IN hold

8

–

ns

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I²S Electrical Timing Burst (Slave Rx Only)—Short Frame WS

Figure 26. I²S Electrical Timing Burst (Slave Rx Only) —Short Frame WS Diagram

1

2

3

I2S_BCLK

I2S_WS

4

6

5

Bit 15 (previous frame)

Bit 0

I2S_IN

Table 39. Values of I²S Electrical Timing Burst (Slave Rx-Only)—Short Frame WS Characteristics

Reference Characteristics Minimum Typical Maximum

Unit

1

I²S bit clock frequency

–

24

–

MHz

2

3

4

5

6

I2S bit clock low time

I²S bit clock high time

I2S_WS setup time

I2S_IN setup

20.8

8

ns

–

8

–

I2S_IN hold

8

–

I²S Electrical Timing Slave—Long Frame WS

Figure 27. I²S Electrical Timing Slave— Long Frame WS Diagram

1

2

3

I2S_BCLK

4

I2S_WS

I2S_OUT

Bit 0

Bit 1

5

7

6

I2S_IN

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Table 40. Values of I²S Electrical Timing Slave—Long Frame WS Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

MHz

ns

1

I²S bit clock frequency

–

12

–

2

3

4

5

6

7

I²S bit clock low time

I²S bit clock high time

I2S_WS setup time

I2S_OUT delay

41

8

–

ns

–

ns

0

25

–

ns

I2S_IN setup

8

ns

I2S_IN hold

8

–

ns

I²S Electrical Timing Master—Long Frame WS

Figure 28. I²S Electrical Timing Master—Long Frame WS Diagram

1

2

3

I2S_BCLK

4

I2S_WS

I2S_OUT

Bit 0

Bit 1

5

7

6

I2S_IN

Table 41. Values of I²S Electrical Timing Master—Long Frame WS Characteristics

Reference Characteristics Minimum Typical

Maximum

Unit

MHz

ns

1

I²S bit clock frequency

–

12

–

2

3

4

5

6

7

I²S bit clock low time

I²S bit clock high time

I2S_WS delay

41

0

–

ns

25

–

ns

I2S_OUT delay

I2S_IN setup

0

ns

8

ns

I2S_IN hold

8

–

ns

Document No. 002-14859 Rev. *R

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CYW20733

I²S Electrical Timing Burst (Slave Rx Only)—Long Frame WS

Figure 29. I²S Electrical Timing Burst (Slave Rx Only) — Long Frame WS Diagram

1

2

3

I2S_BCLK

I2S_WS

4

6

5

Bit 0

Bit 1

I2S_IN

Table 42. Values of I²S Electrical Timing Burst (Slave Rx Only)—Long Frame WS Characteristics

Reference Characteristics Minimum Typical Maximum

Unit

MHz

ns

1

I²S bit clock frequency

–

24

–

2

3

4

5

6

I²S bit clock low time

I²S bit clock high time

I2S_WS setup time

I2S_IN setup

20.8

8

–

ns

–

ns

8

–

ns

I2S_IN hold

8

–

ns

Document No. 002-14859 Rev. *R

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CYW20733

4. Mechanical Information

Figure 30. 81-Pin FBGA

Document No. 002-14859 Rev. *R

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CYW20733

Figure 31. 121-Pin FBGA

Document No. 002-14859 Rev. *R

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CYW20733

Figure 32. 56-Pin QFN

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CYW20733

4.0.1 Tape Reel and Packaging Specifications

Table 43. CYW20733 8 × 8 × 1.0 mm FBGA 81-Pin Tape Reel Specifications

Quantity per reel

Reel diameter

Hub diameter

Tape width

2500 pieces

13 inches

7 inches

16 mm

Tape pitch

12 mm

Table 44. CYW20733 9 x 9 x 1.0 mm FBGA 121-Pin Tape Reel Specifications

Quantity per reel

Reel diameter

Hub diameter

Tape width

1500 pieces

13 inches

4 inches

16 mm

Tape pitch

12 mm

Table 45. CYW20733 7 x 7 x 1.0 mm QFN 56-Pin Tape Reel Specifications

Quantity per reel

Reel diameter

Hub diameter

Tape width

2500 pieces

13 inches

7 inches

16 mm

Tape pitch

12 mm

Document No. 002-14859 Rev. *R

Page 56 of 67

CYW20733

Figure 33. CYW20733 Reel/Labeling/Packaging Specification

Reel Specifications:

ꢀ

(6'ꢀ:DUQLQJꢀ

0RLVWXUHꢀ6HQVLWLYLW\ꢀ6WLFNHUꢀ

ꢀ

(Per MSL Labeling

ꢀ

Specification – P-PDE-1051)

ꢀ

ꢀ&\SUHVVꢀ%DUFRGHꢀ/DEHOꢀ

(Per Standard Barcode Label

Specification – P-PDE-1101)

ꢀ

Device Orientation/Mix Lot Number:

ꢀ

(DFKꢀ5HHOꢀPD\ꢀFRQWDLQꢀXSꢀWRꢀWKUHHꢀLQGLYLGXDOꢀORWꢀQXPEHUVꢀZLWKLQꢀꢁꢂꢀZRUNꢀZHHNVꢃꢀ

7KHVHꢀLQGLYLGXDOꢀORWVꢀPXVWꢀEHꢀODEHOHGꢀRQꢀWKHꢀER[ꢄꢀPRLVWXUHꢀEDUULHUꢀEDJꢀDQGꢀUHHOꢃꢀ

ꢀ

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ3LQꢀꢁꢅꢀ7RSꢀ/HIWꢀ&RUQHUꢀ7RSꢀRIꢀSDFNDJHꢀWRZDUGꢀ6SURFNHWꢀ+ROHVꢀ

ꢀ

ꢀꢀ

ꢀ&

Document No. 002-14859 Rev. *R

Page 57 of 67

CYW20733

5. Ordering Information

Table 46. Ordering Information

Part Number

CYW20733A3KFB1G

CYW20733A3KFB2G

CYW20733A3KML1G

Package

Commercial 81-pin FBGA

Commercial 121-pin FBGA

Commercial 56-pin QFN

Ambient Operating Temperature

0°C to 70°C

6. IoT Resources

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your

design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of

information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software

updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://

community.cypress.com/).

A. Acronyms and Abbreviations

The following list of acronyms and abbreviations may appear in this document.

For a more complete list of acronyms and other terms used in Cypress documents, go to:

http://www.cypress.com/glossary

Acronym

Description

ADC

AFH

AHB

APB

APU

analog-to-digital converter

adaptive frequency hopping

advanced high-performance bus

advanced peripheral bus

audio processing unit

ARM7TDMI-S™

BSC

BTC

COEX

DFU

DMA

EBI

Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable

Broadcom Serial Control

Bluetooth® controller

coexistence

device firmware update

direct memory access

external bus interface

Host Control Interface

high voltage

HCI

HV

IDC

initial digital calibration

intermediate frequency

interrupt request

IF

IRQ

JTAG

LCU

LDO

LHL

Joint Test Action Group

link control unit

low drop-out

lean high land

LPO

LV

low power oscillator

LogicVision™

MIA

multiple interface agent

pulse code modulation

phase locked loop

PCM

PLL

PMU

power management unit

Document No. 002-14859 Rev. *R

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CYW20733

Acronym

Description

POR

power-on reset

PWM

QD

pulse width modulation

quadrature decoder

random access memory

radio frequency

RAM

RF

ROM

RX/TX

SPI

read-only memory

receive, transmit

serial peripheral interface

software

SW

UART

UPI

universal asynchronous receiver/transmitter

µ-processor interface

universal serial bus

watchdog

USB

WD

Document No. 002-14859 Rev. *R

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CYW20733

Document History

Document Title: CYW20733 Single-Chip Bluetooth Transceiver Wireless Input Devices

Document Number: 002-14859

Orig. of Submission

Revision

ECN

Description of Change

Change

Date

20733-DS00-R

Initial release

**

–

07/23/2010

Updated:

Table 10: “Pin Descriptions,” on page 35 and Table 11: “GPIO Pin Descriptions,” on

page 38.

Figure 13: “81-Pin FBGA Ball Map,” on page 44.

Table 16: “Integrated Audio Amplifier Electrical Specifications,” on page 48.

Table 25: “PCM Electrical Timing Slave—Short Frame Sync Characteristics,” on

page 57.

*A

–

07/20/2010

Table 26: “Values of PCM Electrical Timing Master—Short Frame Sync Character-

istics,” on page 58.

“PCM Interface Timing” on page 57.

“I2S Timing” on page 63.

20733-DS02-R

Updated:

“Microprocessor Unit” on page 13: ROM memory capacity.

“Link Control Layer” on page 15: Bluetooth Link Controller tasks.

“UART Interface” on page 17: normal baud rate mode.

“GPIO Port” on page 23.

“Theory of Operation” on page 25: mouse decoder PWMs.

“ADC Port” on page 26: analog input channels.

Table 7: “CYW20733 First SPI Set (Master Mode),” on page 28.

Table 11: “Pin Descriptions,” on page 35 and Table 12: “GPIO Pin Descriptions,” on

page 37.

*B

–

08/30/2010

Figure 13: “81-Pin FBGA Ball Map,” on page 44.

Added:

“Peripheral UART Interface” on page 19.

20733-DS03-R

Updated:

“General Description” and “Features” on page 1

TBD for second package changed to 121-pin, 9 mm x 9 mm FBGA, throughout the

document.

Table 11: “Pin Descriptions,” on page 39 (added 121-pin info)

Table 12: “GPIO Pin Descriptions,” on page 41 (added 121-pin info)

Figure 14: “121-Pin FBGA Ball Map,” on page 49 (added)

Figure 30: “81-Pin FBGA,” on page 73

*C

–

10/25/2010

Figure 31: “121-Pin FBGA,” on page 74 (121-pin outline drawing, added)

Table 38: “CYW20733 8 × 8 × 1.0 mm FBGA TBD Tape Reel Specifications,” on

page 75

Table 39: “CYW20733M 9 x 9 x 1.0 mm FBGA TBD Tape Reel Specifications,” on

page 75

Figure 33: “CYW20733 9×9 FBGA Package Tray (1 of 2),” on page 77

Figure 35: “CYW20733 8×8 FBGA Package Tray (1 of 2),” on page 79

Table 40: “Ordering Information,” on page 81

20733-DS04-R

Updated:

Figure 1: “Functional Block Diagram,” on page 2

“UART Interface” on page 19

Table 1: “Common Baud Rate Examples,” on page 20

Table 5: “XTAL Oscillator Characteristics,” on page 25

“Port 0–Port 1, Port 8 – Port 18, Port 20 – Port 23, and Port 28 – Port 38” on page 26

Table 6: “Sampling Rate and Effective Number of Bits,” on page 29

Table 12: “GPIO Pin Descriptions,” on page 40

Table 16: “ADC Specifications,” on page 50

*D

–

04/04/2011

Table 19: “Current Consumption, Class 1,” on page 52

Table 20: “Current Consumption, Class 2 (0 dBm),” on page 53 (added)

Table 21: “Receiver RF Specifications” on page 54

Table 22: “Transmitter RF Specifications,” on page 55

Section 5: “Ordering Information,” on page 81

Document No. 002-14859 Rev. *R

Page 64 of 67

CYW20733

Document Title: CYW20733 Single-Chip Bluetooth Transceiver Wireless Input Devices

Document Number: 002-14859

20733-DS05-R

Updated:

Figure 1: “Functional Block Diagram,” on page 2

“GPIO Port” on page 25

“High Current I/O” on page 34

Table 10: “Pin Descriptions,” on page 36

Figure 13: “121-Pin FBGA Ball Map,” on page 46

*E

–

06/29/2011

Table 15: “ADC Specifications,” on page 48

Table 17: “Current Consumption, Class 1,” on page 49

Table 18: “Current Consumption, Class 2 (0 dBm),” on page 51

Added:

Table 19: “Current Consumption,” on page 52Removed:

“Integrated Filterless Class-D Audio Amplifier,” on page 35

Table 16: “Integrated Audio Amplifier Electrical Specifications,” on p. 49.

20733-DS06-R

Updated:

Table 7: “CYW20733 First SPI Set (Master Mode),” on page 32

Table 10: “Pin Descriptions,” on page 38

Table 11: “GPIO Pin Descriptions,” on page 41

Table 15: “ADC Specifications,” on page 52

Table 17: “Current Consumption, Class 1,” on page 53

Table 18: “Current Consumption, Class 2 (0 dBm),” on page 55

Notes in Table 20 on page 57 and Table 21 on page 59

Table 23: “Values of SPI1 Timing Characteristics,” on page 61

Table 39: “CYW20733 8 × 8 × 1.0 mm FBGA 81-Pin Tape Reel Specifications,” on

page 80

*F

–

03/01/2012

Table 40: “CYW20733 9 x 9 x 1.0 mm FBGA 121-Pin Tape Reel Specifications,” on

page 80

Added:

Information related to the 56-pin QFN package on page 1

“56-Pin QFN Diagram” on page 50

Table 24: “Values of SPI2 Timing Characteristics,” on page 62

Figure 32: “56-Pin QFN,” on page 79

Table 41: “CYW20733 7 x 7 x 1.0 mm QFN 56-Pin Tape Reel Specifications,” on

page 80

Figure 33: “CYW20733 Reel/Labeling/Packaging Specification,” on page 81

20733-DS07-R

Updated:

*G

*H

–

03/19/2012

05/18/2012

Notes in Table 23: “Values of SPI1 Timing Characteristics,” on page 65 and

Table 24: “Values of SPI2 Timing Characteristics,” on page 66

20733-DS08-R

Updated:

Table 8: “CYW20733 Second SPI Set (Master Mode),” on page 33.

Table 9: “CYW20733 Second SPI Set (Slave Mode),” on page 34.

20733-DS09-R

Updated:

Bluetooth HID profile version 1.0 to 1.1 on the cover page.

“Calibration” on page 15.

“Triac Control” on page 38.

“Cypress Proprietary Control Signalling and Triggered Broadcom Fast Connect” on

page 38.

*I

–

06/08/2012

Table 15: “ADC Specifications,” on page 56 by fixing the Conditions for the

Reference settling time and Input resistance parameters.

Table 20: “Receiver RF Specifications” on page 59 by updating Df to uf in the inter-

modulation performance row.

“SPI Timing” on page 63.

20733-DS10-R

*J

–

08/30/2012

10/01/2012

Updated:

Table 43: “Ordering Information,” on page 89.

20733-DS11-R

Updated:

Cover page features to include Class-D audio amplifier.

Figure 1: “Functional Block Diagram,” on page 2 by adding Class-D audio driver.

Table 11: “Pin Descriptions,” on page 43.

Figure 14: “56-Pin QFN Diagram,” on page 55.

Added:

*K

“Integrated Filterless Class-D Audio Amplifier” on page 40.

Table 17: “Integrated Audio Amplifier Electrical Specifications,” on page 58

Document No. 002-14859 Rev. *R

Page 65 of 67

CYW20733

Document Title: CYW20733 Single-Chip Bluetooth Transceiver Wireless Input Devices

Document Number: 002-14859

20733-DS12-R

Updated:

*L

–

11/26/2012

Table 17: “Integrated Audio Amplifier Electrical Specifications,” on page 58.

Table 21: “Current Consumption,” on page 61.

20733-DS13-R

*M

*N

*O

*P

–

01/21/2013

05/31/2013

08/12/2013

09/25/2013

Updated:

Table 12: “GPIO Pin Descriptions,” on page 46.

20733-DS14-R

Updated:

Table 45: “Ordering Information,” on page 91.

20733-DS15-R

Updated:

Table 21: “Current Consumption,” on page 62.

20733-DS16-R

Updated:

Table 4: “Reference Crystal Electrical Specifications,” on page 26.

20733-DS17-R

*Q

*R

–

07/10/2015

10/21/2016

Updated document status.

Updated to Cypress Template

Added Cypress part numbering scheme

5487130

UTSV

Document No. 002-14859 Rev. *R

Page 66 of 67

CYW20733

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

ARM^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Training | Components

Internet of Things

Lighting & Power Control

Memory

Technical Support

cypress.com/powerpsoc

cypress.com/memory

cypress.com/psoc

cypress.com/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/touch

cypress.com/usb

cypress.com/wireless

67

including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent

permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any

product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is

the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products

are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or

systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the

device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device or system whose failure to perform can be reasonably

expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,

damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other

liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document No. 002-14859 Rev. *R

Revised October 21, 2016

Page 67 of 67


型号：	BCM20733
厂家：	CYPRESS
描述：	Single-Chip Bluetooth Transceiver Wireless Input Devices 无线
文件：	总67页 (文件大小：7237K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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