7C142-30 [CYPRESS]
2Kx8 Dual-Port Static RAM; 2Kx8双口静态RAM
| 型号： | 7C142-30 |
| 厂家： | 
CYPRESS |
| 描述： | 2Kx8 Dual-Port Static RAM |
| 文件： | 总18页 (文件大小：341K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C132/CY7C136
fax id: 5201
CY7C132/CY7C136
CY7C142/CY7C146
2Kx8 Dual-Port Static RAM
Features
Functional Description
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER du-
al-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
• Low operating power: I = 90 mA (max.)
CC
• Fully asynchronous operation
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits using slave CY7C142/CY7C146
• BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
• Availablein 48-pin DIP (CY7C132/142), 52-pin PLCCand
52-pin TQFP (CY7C136/146)
• Pin-compatible and functionally equivalent to
IDT7132/IDT7142
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. On the PLCC version, INT
is an interrupt flag indicating that data has been placed in a
unique location (7FF for the left port and 7FE for the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
Pin Configuration
R/W
L
R/W
R
DIP
Top View
CE
L
CE
R
OE
L
OE
R
V
CC
48
1
CE
L
R/W
BUSY
47
CE
R
R/W
R
BUSY
L
2
46
3
L
45
A
10L
R
4
A
44
5
I/O
I/O
OE
10R
I/O
I/O
7L
L
7R
0R
I/O
CONTROL
I/O
CONTROL
A
0L
OE
43
R
6
42
7
A
0R
A
A
A
0L
[1]
1L
A
A
41
2L
1R
8
[1]
BUSY
BUSY
R
L
40
9
2R
3L
A
A
A
39
10
3R
4L
A
A
A
10L
10R
0R
MEMORY
ARRAY
A
A
ADDRESS
DECODER
5L
38
37
ADDRESS
DECODER
11
12
4R
A
6L
A
7L
A
8L
5R
7C132
A
0L
A
6R
13 7C142
36
35
34
A
A
14
15
16
17
18
7R
A
9L
8R
I/O
I/O
A
9R
0L
1L
33
32
I/O
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
7R
I/O
I/O
I/O
I/O
I/O
I/O
I/O
31
30
29
28
27
26
25
2L
3L
6R
5R
4R
3R
2R
19
20
21
22
23
24
CE
L
I/O
I/O
CE
R
4L
5L
OE
L
OE
R
I/O
I/O
6L
7L
R/W
L
R/W
R
I/O
I/O
1R
0R
GND
[2]
[2]
INT
L
INT
R
C132-2
C132-1
Notes:
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 1989 – Revised March 27, 1997
CY7C132/CY7C136
CY7C142/CY7C146
Pin Configurations (continued)
PLCC
Top View
PQFP
Top View
7
6
5
4
3
2
1
52 51 50 49 48 47
46
A
A
OE
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
8
R
A
A
A
A
A
A
9
45
44
43
42
41
40
39
38
37
36
35
34
0R
1R
2R
3R
A
52 51 50 49 48 47 46 45 44 43 42 41 40
10
11
12
13
14
15
16
17
18
19
20
A
A
A
A
A
A
A
OE
R
1L
2L
3L
4L
5L
6L
1
39
38
37
36
35
34
33
32
31
30
29
28
27
A
0R
A
1R
A
2
A
3
4R
5R
7C136
7C146
A
2R
A
3R
A
4R
A
5R
A
4
A
5
A
6R
A
7R
A
8R
A
9R
A
6
7C136
7C146
A
A
I/O
I/O
I/O
I/O
7L
7
A
A
A
A
8L
6R
8
A
I/O
I/O
9L
0L
1L
7R
9
NC
I/O
8R
9R
10
11
12
13
7R
2122 23 24 25 26 27 28 29 30 31 32 33
I/O
I/O
NC
I/O
2L
3L
C132-3
7R
1415 16 17 18 19 20 21 22 23 24 25 26
C132-4
Selection Guide
[3]
7C132-25
7C132-30
7C136-30
7C142-30
7C146-30
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
7C136-25
7C142-25
7C146-25
[3,4]
7C136-15
7C146-15
Maximum Access Time (ns)
15
25
30
35
45
90
55
90
Maximum Operating
Current (mA)
Com’l/Ind
Military
190
170
170
120
Maximum Operating
Current (mA)
170
120
120
Maximum Standby
Current (mA)
Com’l/Ind
Military
75
65
65
45
65
35
45
35
45
Notes:
3. 15 and 25-ns version available in PQFP and PLCC packages only.
4. Shaded area contains preliminary information.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential
(Pin 48 to Pin 24).................................................−0.5V to +7.0V
Range
Commercial
Industrial
Temperature
V
CC
0°C to +70°C
5V ± 10%
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
−40°C to +85°C
−55°C to +125°C
DC Input Voltage .................................................−3.5V to +7.0V
[5]
Military
Output Current into Outputs (LOW) .............................20 mA
Note:
5.
TA is the “instant on” case temperature.
]
2
CY7C132/CY7C136
CY7C142/CY7C146
Electrical Characteristics Over the Operating Range[6]
[3]
7C132-30
7C132-35 7C132-45,55
7C136-25,30 7C136-35 7C136-45,55
[3,4]
7C136-15
7C146-15
7C142-30
7C142-35 7C142-45,55
7C146-25,30 7C146-35 7C146-45,55
Parameter Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
V
Output HIGH Voltage V = Min., I = -4.0 mA
2.4
2.4
2.4
2.4
V
V
OH
OL
CC
OH
Output LOW Voltage I = 4.0 mA
0.4
0.5
0.4
0.5
0.4
0.5
0.4
0.5
OL
[7]
I
= 16.0 mA
OL
V
V
Input HIGH Voltage
Input LOW Voltage
2.2
2.2
2.2
2.2
V
V
IH
IL
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
0.8
+5
+5
I
I
Input Load Current GND < V < V
CC
-5
-5
−5
−5
−5
−5
−5
−5
µA
µA
IX
I
Output Leakage
Current
GND < V < V
,
OZ
OS
CC
O
CC
Output Disabled
I
I
Output Short
Circuit Current
V
= Max.,
= GND
-350
190
−350
−350
−350 mA
CC
[8]
V
OUT
V
Operating
CE = V ,
Com’l
Mil
170
120
170
90
mA
mA
mA
CC
IL
Supply Current
Outputs Open,
120
[9]
f = f
MAX
I
I
Standby Current
Both Ports,
TTL Inputs
CE and CE > V , Com’l
75
65
45
65
35
45
SB1
SB2
L
R
IH
[9]
f = f
MAX
Mil
Standby Current
One Port,
TTL Inputs
CE or CE > V , Com’l
Active Port Outputs
135
115
90
75
90
L
R
IH
Mil
115
Open,
f = f
[9]
MAX
I
I
Standby Current
Both Ports,
CMOS Inputs
Both Ports CE and Com’l
15
15
15
15
15
15
mA
mA
SB3
SB4
L
CE > V – 0.2V,
R
CC
Mil
V
> V – 0.2V or
IN
CC
V
< 0.2V, f = 0
IN
Standby Current
One Port,
CMOS Inputs
One Port CE or
Com’l
Mil
125
105
85
70
85
L
CE > V – 0.2V,
R
CC
105
V
> V – 0.2V or
IN
CC
V
< 0.2V,
IN
Active Port Outputs
Open,
[9]
f = f
MAX
]
Capacitance[10]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max.
15
Unit
C
C
pF
pF
IN
A
V
= 5.0V
CC
10
OUT
Notes:
6. See the last page of this specification for Group A subgroup testing information.
7. BUSY and INT pins only.
8. Duration of the short circuit should not exceed 30 seconds.
9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V.
10. This parameter is guaranteed but not tested.
3
CY7C132/CY7C136
CY7C142/CY7C146
AC Test Loads and Waveforms
5V
R1893Ω
R1893Ω
5V
5V
OUTPUT
OUTPUT
281Ω
BUSY
OR
INT
R2
347Ω
R2
347Ω
30 pF
5 pF
INCLUDING
JIGAND
INCLUDING
JIGAND
30pF
C132-6
C132-5
SCOPE
SCOPE
(a)
(b)
BUSYOutput Load
(CY7C132/CY7C136
ONLY)
Equivalent to:
THVÉNIN EQUIVALENT
ALL INPUT PULSES
3.0V
90%
10%
90%
250Ω
10%
OUTPUT
1.4V
GND
< 5 ns
< 5 ns
]
[6, 11]
Switching Characteristics Over the Operating Range
[3]
7C132-25
7C132-30
7C136-30
7C142-30
7C146-30
7C136-25
7C142-25
7C146-25
[3,4]
7C136-15
7C146-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
Address to Data Valid
15
0
25
0
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
[12]
15
25
30
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
[12]
CE LOW to Data Valid
15
10
25
15
30
20
[12]
OE LOW to Data Valid
[10, 13]
OE LOW to Low Z
3
3
0
3
5
0
3
5
0
[10, 13, 14]
OE HIGH to High Z
10
10
15
15
15
25
15
15
25
[10, 13]
CE LOW to Low Z
[10, 13, 14]
CE HIGH to High Z
[10]
CE LOW to Power-Up
[10]
CE HIGH to Power-Down
PD
[15]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
15
12
12
2
25
20
20
2
30
25
25
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
HA
0
0
0
SA
12
10
0
15
15
0
25
15
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[10]
R/W LOW to High Z
10
15
15
HZWE
LZWE
[10]
R/W HIGH to Low Z
0
0
0
4
CY7C132/CY7C136
CY7C142/CY7C146
[6, 11]
Switching Characteristics Over the Operating Range
(continued)
[3]
7C132-25
7C132-30
7C136-30
7C142-30
7C146-30
7C136-25
7C142-25
7C146-25
[3,4]
7C136-15
7C146-15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY/INTERRUPT TIMING
t
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
15
15
15
15
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
[16]
[16]
BUSY HIGH from CE HIGH
Port Set Up for Priority
5
0
5
0
5
0
[17]
R/W LOW after BUSY LOW
WB
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
13
20
30
WH
15
25
30
BDD
DDD
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
t
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
WDD
[19]
INTERRUPT TIMING
t
t
t
t
t
t
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
15
15
15
15
15
15
25
25
25
25
25
25
25
25
25
25
25
25
ns
ns
ns
ns
ns
ns
WINS
EINS
INS
[16]
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset Time
OINR
EINR
INR
[16]
[16]
Address to INTERRUPT Reset Time
[6, 11]
Switching Characteristics Over the Operating Range
7C132-35
7C132-45
7C132-55
7C136-35
7C142-35
7C146-35
7C136-45
7C142-45
7C146-45
7C136-55
7C142-55
7C146-55
Description
Unit
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
Address to Data Valid
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
[12]
35
45
55
AA
Data Hold from Address Change
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
[12]
CE LOW to Data Valid
35
20
45
25
55
25
[12]
OE LOW to Data Valid
[10, 13]
OE LOW to Low Z
3
5
0
3
5
0
3
5
0
[10, 13, 14]
OE HIGH to High Z
20
20
35
20
20
35
25
25
35
[10, 13]
CE LOW to Low Z
[10, 13, 14]
CE HIGH to High Z
[10]
CE LOW to Power-Up
[10]
CE HIGH to Power-Down
PD
5
CY7C132/CY7C136
CY7C142/CY7C146
[6, 11]
Switching Characteristics Over the Operating Range
(continued)
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C142-55
7C146-55
[15]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
35
45
55
40
40
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
30
30
2
35
35
2
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
R/W Pulse Width
HA
0
0
0
SA
25
15
0
30
20
0
30
20
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[10]
R/W LOW to High Z
20
20
25
HZWE
LZWE
[10]
R/W HIGH to Low Z
0
0
0
BUSY/INTERRUPT TIMING
t
t
t
t
t
t
t
t
t
BUSY LOW from Address Match
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
[16]
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
[16]
BUSY HIGH from CE HIGH
Port Set Up for Priority
5
0
5
0
5
0
[17]
R/W LOW after BUSY LOW
WB
R/W HIGH after BUSY HIGH
BUSY HIGH to Valid Data
30
35
35
WH
35
45
45
BDD
DDD
Write Data Valid to Read Data Valid
Note
18
Note
18
Note
18
t
Write Pulse to Data Delay
Note
18
Note
18
Note
18
ns
WDD
[19]
INTERRUPT TIMING
t
t
t
t
t
t
R/W to INTERRUPT Set Time
25
25
25
25
25
25
35
35
35
35
35
35
45
45
45
45
45
45
ns
ns
ns
ns
ns
ns
WINS
EINS
INS
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
[16]
OE to INTERRUPT Reset Time
CE to INTERRUPT Reset Time
OINR
EINR
INR
[16]
[16]
Address to INTERRUPT Reset Time
Notes:
11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
OL/IOH, and 30-pF load capacitance.
I
12. AC test conditions use VOH = 1.6V and VOL = 1.4V.
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
14.
tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.
17. CY7C142/CY7C146 only.
18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:
BUSY on Port B goes HIGH.
Port B’s address toggled.
CE for Port B is toggled.
R/W for Port B is toggled during valid read.
19. 52-pin PLCC and PQFP versions only.
6
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms
[20, 21]
Read Cycle No. 1 (Either Port-Address Access)
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C132-7
[20, 22]
Read Cycle No. 2 (Either Port-CE/OE)
CE
OE
t
HZCE
t
ACE
t
HZOE
t
DOE
t
LZOE
t
LZCE
DATA VALID
DATA OUT
t
PU
t
PD
I
CC
I
SB
C132-8
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
n
t
RC
ADDRESS
ADDRESS MATCH
R
t
PWE
R/W
R
D
INR
VALID
t
PS
ADDRESS MATCH
ADDRESS
L
t
BHA
BUSY
L
t
t
BDD
BLA
DOUT
VALID
L
t
DDD
t
WDD
C132-9
Notes:
20. R/W is HIGH for read cycle.
21. Device is continuously selected, CE = VIL and OE = VIL.
22. Address valid prior to or coincident with CE transition LOW.
7
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
[15, 23]
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATA
IN
DATA VALID
OE
t
HZOE
HIGH IMPEDANCE
D
OUT
C132-10
[15, 24]
Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)
t
WC
ADDRESS
CE
t
t
HA
SCE
t
AW
t
SA
t
PWE
R/W
t
t
HD
SD
DATA
IN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
D
OUT
C132-11
Notes:
23. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required tSD
.
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
8
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
R
t
t
BHC
BLC
BUSY
C132-12
CE Valid First:
R
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
t
t
BHC
BLC
BUSY
L
C132-13
Busy Timing Diagram No. 2 (Address Arbitration)
Left AddressValidFirst:
t
or t
WC
RC
ADDRESS
ADDRESS MATCH
ADDRESS MISMATCH
L
t
PS
ADDRESS
BUSY
R
R
t
t
BHA
BLA
C132-14
RightAddress ValidFirst:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
BUSY
L
L
t
t
BHA
BLA
C132-15
9
CY7C132/CY7C136
CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
CE
t
PWE
R/W
t
t
WH
WB
BUSY
C132-16
Interrupt Timing Diagrams[19]
Left Side Sets INT :
R
t
WC
ADDRESS
L
WRITE 7FF
t
t
HA
INS
CE
L
t
EINS
R/W
L
t
SA
t
WINS
INT
R
C132-17
Right Side Clears INT :
R
t
RC
ADDRESS
R
READ 7FF
t
t
INR
HA
CE
R
t
EINR
R/W
R
OE
R
t
OINR
INT
R
C132-18
10
CY7C132/CY7C136
CY7C142/CY7C146
Interrupt Timing Diagrams[19] (continued)
Right Side Sets INT :
L
t
WC
ADDRESS
R
WRITE 7FE
t
t
HA
INS
CE
R
t
EINS
R/W
R
t
SA
t
WINS
INT
L
C132-19
Right Side Clears INT :
L
t
RC
ADDRESS
L
READ 7FE
t
t
INR
HA
CE
L
t
EINR
R/W
L
OE
L
t
OINR
C132-20
INT
L
11
CY7C132/CY7C136
CY7C142/CY7C146
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
120
100
80
1.4
1.2
1.0
I
CC
1.2
I
CC
1.0
0.8
0.8
0.6
0.4
60
V
CC
=5.0V
V
V
=5.0V
=5.0V
CC
0.6
0.4
T =25°C
A
IN
40
0.2
0.6
20
0
I
I
SB3
0.2
0.0
SB3
-55
25
125
0
1.0
2.0
3.0
4.0
4.0
4.5
5.0
5.5
6.0
AMBIENTTEMPERATURE(°C)
OUTPUTVOLTAGE(V)
SUPPLYVOLTAGE(V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
140
120
1.6
1.4
1.4
1.3
1.2
1.1
100
80
1.2
1.0
60
T =25°C
A
V
CC
=5.0V
1.0
40
0.8
V
=5.0V
CC
20
0
0.9
0.8
T =25°C
A
0.6
-55
0.0
1.0
2.0
3.0
4.0
25
125
4.0
4.5
5.0
5.5
6.0
AMBIENTTEMPERATURE(°C)
OUTPUTVOLTAGE(V)
SUPPLYVOLTAGE(V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
NORMALIZED I
vs. CYCLE TIME
CC
1.25
30.0
25.0
3.0
2.5
V
CC
=5.0V
T =25°C
A
V
IN
=0.5V
1.0
2.0
20.0
15.0
10.0
1.5
1.0
0.75
V
=4.5V
CC
0.5
0.0
5.0
0
T =25°C
A
0.50
10
20
30
40
0
1.0
2.0
3.0
4.0 5.0
0
200 400 600 800 1000
CAPACITANCE(pF)
CYCLE FREQUENCY (MHz)
SUPPLYVOLTAGE(V)
12
CY7C132/CY7C136
CY7C142/CY7C146
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
48-Lead (600-Mil) Molded DIP
30
CY7C132-30PC
CY7C132-30PI
CY7C132-35PC
CY7C132-35PI
CY7C132-35DMB
CY7C132-45PC
CY7C132-45PI
CY7C132-45DMB
CY7C132-55PC
CY7C132-55PI
CY7C132-55DMB
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
Commercial
Industrial
Commercial
Industrial
Military
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
35
45
55
Commercial
Industrial
Military
Commercial
Industrial
Military
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C136-15JC
CY7C136-15NC
CY7C136-25JC
CY7C136-25NC
CY7C136-30JC
CY7C136-30NC
CY7C136-30JI
Package Type
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
15
25
30
J69
N52
J69
N52
J69
N52
J69
J69
N52
J69
L69
J69
N52
J69
L69
J69
N52
J69
L69
Commercial
Commercial
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
35
45
55
CY7C136-35JC
CY7C136-35NC
CY7C136-35JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
CY7C136-35LMB
CY7C136-45JC
CY7C136-45NC
CY7C136-45JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
CY7C136-45LMB
CY7C136-55JC
CY7C136-55NC
CY7C136-55JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
Industrial
Military
CY7C136-55LMB
Shaded area contains preliminary information.
13
CY7C132/CY7C136
CY7C142/CY7C146
Ordering Information (continued)
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C142-30PC
Package Type
48-Lead (600-Mil) Molded DIP
30
P25
P25
P25
P25
D26
P25
P25
D26
P25
P25
D26
Commercial
Industrial
Commercial
Industrial
Military
CY7C142-30PI
CY7C142-35PC
CY7C142-35PI
CY7C142-35DMB
CY7C142-45PC
CY7C142-45PI
CY7C142-45DMB
CY7C142-55PC
CY7C142-55PI
CY7C142-55DMB
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Molded DIP
48-Lead (600-Mil) Sidebraze DIP
35
45
55
Commercial
Industrial
Military
Commercial
Industrial
Military
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
CY7C136-15JC
CY7C136-15NC
CY7C146-25JC
CY7C146-25NC
CY7C146-30JC
CY7C146-30NC
CY7C146-30JI
Package Type
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
15
25
30
J69
N52
J69
N52
J69
N52
J69
J69
N52
J69
L69
J69
N52
J69
L69
J69
N52
J69
L69
Commercial
Commercial
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
52-Lead Plastic Leaded Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
35
45
55
CY7C146-35JC
CY7C146-35NC
CY7C146-35JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
CY7C146-35LMB
CY7C146-45JC
CY7C146-45NC
CY7C146-45JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
52-Lead Plastic Leaded Chip Carrier
52-Pin Plastic Quad Flatpack
Industrial
Military
CY7C146-45LMB
CY7C146-55JC
CY7C146-55NC
CY7C146-55JI
Commercial
52-Lead Plastic Leaded Chip Carrier
52-Square Leadless Chip Carrier
Industrial
Military
CY7C146-55LMB
Shaded area contains preliminary information.
14
CY7C132/CY7C136
CY7C142/CY7C146
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
Parameter
Subgroups
V
OH
READ CYCLE
V
OL
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
RC
V
IH
t
AA
V Max.
IL
t
t
ACE
I
IX
I
I
DOE
OZ
CC
WRITE CYCLE
I
I
I
I
SB1
SB2
SB3
SB4
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WC
t
SCE
t
AW
t
HA
SA
t
t
PWE
t
SD
t
HD
BUSY/INTERRUPT TIMING
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WINS
t
EINS
t
INS
OINR
t
t
EINR
t
INR
BUSY TIMING
[25]
t
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
WB
t
WH
t
BDD
Note:
25. CY7C142/CY7C146 only.
Document #: 38-00061-K
15
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
52-Lead Plastic Leaded Chip Carrier J69
16
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams (continued)
52-Square Leadless Chip Carrier L69
52-Lead Plastic Quad Flatpack N52
17
CY7C132/CY7C136
CY7C142/CY7C146
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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