5962-9314402MUX_技术文档

41

CY7C341

192-Macrocell MAX^®EPLD

Features

Programmable Interconnect Array

• 192 macrocells in 12 logic array blocks (LABs)

• Eight dedicated inputs, 64 bidirectional I/O pins

• 0.8-micron double-metal CMOS EPROM technology

• Programmable interconnect array

The Programmable Interconnect Array (PIA) solves inter-

connect limitations by routing only the signals needed by each

logic array block. The inputs to the PIA are the outputs of every

macrocell within the device and the I/O pin feedback of every

pin on the device.

• 384 expander product terms

Unlike masked or programmable gate arrays, which induce

variable delay dependent on routing, the PIA has a fixed delay.

This eliminates undesired skews among logic signals, which

may cause glitches in internal or external logic. The fixed

delay, regardless of programmable interconnect array config-

uration, simplifies design by assuring that internal signal

skews or races are avoided. The result is ease of design imple-

mentation, often in a single pass, without the multiple internal

logic placement and routing iterations required for a program-

mable gate array to achieve design timing objectives.

• Available in 84-pin HLCC, PLCC, and PGA packages

Functional Description

The CY7C341 is an Erasable Programmable Logic Device

(EPLD) in which CMOS EPROM cells are used to configure

logic functions within the device. The MAX^®architecture is

100% user-configurable, allowing the devices to accom-

modate a variety of independent logic functions.

The 192 macrocells in the CY7C341 are divided into 12 LABs,

16 per LAB. There are 384 expander product terms, 32 per

LAB, to be used and shared by the macrocells within each

LAB. Each LAB is interconnected with a programmable inter-

connect array, allowing all signals to be routed throughout the

chip.

Timing Delays

Timing delays within the CY7C341 may be easily determined

using Warp™, Warp Professional™, or Warp Enterprise™

software. The CY7C341 has fixed internal delays, allowing the

user to determine the worst case timing delays for any design.

The speed and density of the CY7C341 allows them to be

used in a wide range of applications, from replacement of large

amounts of 7400-series TTL logic, to complex controllers and

multifunction chips. With greater than 37 times the function-

ality of 20-pin PLDs, the CY7C341 allows the replacement of

over 75 TTL devices. By replacing large amounts of logic, the

CY7C341 reduces board space and part count, and increases

system reliability.

Design Recommendations

For proper operation, input and output pins must be

constrained to the range GND < (V_INor V_OUT) < V_CC. Unused

inputs must always be tied to an appropriate logic level (either

V_CCor GND). Each set of V_CCand GND pins must be

connected together directly at the device. Power supply

decoupling capacitors of at least 0.2 µF must be connected

between V_CCand GND. For the most effective decoupling,

each V_CCpin should be separately decoupled to GND, directly

at the device. Decoupling capacitors should have good

frequency response, such as monolithic ceramic types.

Each LAB contains 16 macrocells. In LABs A, F, G, and L, eight

macrocells are connected to I/O pins and eight are buried,

while for LABs B, C, D, E, H, I, J, and K, four macrocells are

connected to I/O pins and 12 are buried. Moreover, in addition

to the I/O and buried macrocells, there are 32 single product

term logic expanders in each LAB. Their use greatly enhances

the capability of the macrocells without increasing the number

of product terms in each macrocell.

Design Security

The CY7C341 contains a programmable design security

feature that controls the access to the data programmed into

the device. If this programmable feature is used, a proprietary

design implemented in the device cannot be copied or

retrieved. This enables a high level of design control to be

obtained since programmed data within EPROM cells is

invisible. The bit that controls this function, along with all other

program data, may be reset simply by erasing the device. The

CY7C341 is fully functionally tested and guaranteed through

complete testing of each programmable EPROM bit and all internal

logic elements thus ensuring 100% programming yield.

Logic Array Blocks

There are 12 logic array blocks in the CY7C341. Each LAB

consists of a macrocell array containing 16 macrocells, an

expander product term array containing 32 expanders, and an

I/O block. The LAB is fed by the programmable interconnect

array and the dedicated input bus. All macrocell feedbacks go

to the macrocell array, the expander array, and the program-

mable interconnect array. Expanders feed themselves and the

macrocell array. All I/O feedbacks go to the programmable

interconnect array so that they may be accessed by macro-

cells in other LABs as well as the macrocells in the LAB in

which they are situated.

The erasable nature of these devices allows test programs to

be used and erased during early stages of the production flow.

The devices also contain on-board logic test circuitry to allow

verification of function and AC specification once encapsu-

lated in non-windowed packages.

Externally, the CY7C341 provides eight dedicated inputs, one

of which may be used as a system clock. There are 64 I/O pins

that may be individually configured for input, output, or bidirec-

tional data flow.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-03034 Rev. *A

Revised December 11, 2001

CY7C341

Selection Guide

7C341-25

25

7C341-30

30

7C341-35

35

Unit

ns

Maximum Access Time

Maximum Operating Current

Commercial

Industrial

Military

380

mA

480

Maximum Standby Current

Commercial

Industrial

Military

360

mA

435

Logic Block Diagram

1 (A6)

INPUT/CLK

INPUT

(C6) 84

(C7) 83

(L7) 44

(J7) 43

2 (A5)

INPUT

41 (K6)

42 (J6)

INPUT

SYSTEMCLOCK

LAB A

LAB G

MACROCELL97

4

5

6

7

8

9

(C5)

(A4)

(B4)

(A3)

(A2)

(B3)

MACROCELL1

46 (L6)

MACROCELL2

MACROCELL3

MACROCELL4

MACROCELL5

MACROCELL6

MACROCELL7

MACROCELL8

MACROCELL98

MACROCELL99

MACROCELL100

MACROCELL101

MACROCELL102

MACROCELL103

MACROCELL104

47 (L8)

48 (K8)

49 (L9)

50 (L10)

51 (K9)

52 (L11)

53 (K10)

10 (A1)

11 (B2)

MACROCELL 9–16

MACROCELL 105–112

LAB B

LAB H

12 (C2)

13 (B1)

14 (C1)

15 (D2)

MACROCELL17

MACROCELL18

MACROCELL19

MACROCELL20

MACROCELL113

MACROCELL114

MACROCELL115

MACROCELL116

54 (J10)

55 (K11)

56 (J11)

57 (H10)

MACROCELL 21–32

MACROCELL 117–128

LAB C

LAB I

16 (D1)

17 (E3)

20 (F2)

21 (F3)

MACROCELL33

MACROCELL34

MACROCELL35

MACROCELL36

MACROCELL129

MACROCELL130

MACROCELL131

MACROCELL132

58 (H11)

59 (F10)

62 (G9)

63 (F9)

P

I

A

MACROCELL 37–48

MACROCELL 133–144

LAB D

LAB J

22 (G3)

23 (G1)

25 (F1)

26 (H1)

MACROCELL49

MACROCELL50

MACROCELL51

MACROCELL52

MACROCELL145

MACROCELL146

MACROCELL147

MACROCELL148

64 (F11)

65 (E11)

67 (E9)

68 (D11)

MACROCELL 53–64

MACROCELL 149–160

LAB E

LAB K

27 (H2)

28 (J1)

29 (K1)

30 (J2)

MACROCELL65

MACROCELL66

MACROCELL67

MACROCELL68

MACROCELL161

MACROCELL162

MACROCELL163

MACROCELL164

69 (D10)

70 (C11)

71 (B11)

72 (C10)

MACROCELL 69–80

MACROCELL 165–176

LAB F

LAB L

MACROCELL81

MACROCELL82

MACROCELL83

MACROCELL84

MACROCELL85

MACROCELL86

MACROCELL87

MACROCELL88

MACROCELL177

MACROCELL178

MACROCELL179

MACROCELL180

MACROCELL181

MACROCELL182

MACROCELL183

MACROCELL184

31 (L1)

32 (K2)

33 (K3)

34 (L2)

35 (L3)

36 (K4)

37 (L4)

38 (J5)

73 (A11)

74 (B10)

75 (B9)

76 (A10)

77 (A9)

78 (B8)

79 (A8)

80 (B6)

MACROCELL 185–192

MACROCELL 89–96

() – PERTAIN TO 84-PIN PGA PACKAGE

3, 24, 45, 66 (B5, G2, K7, E10)

18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)

V

CC

GND

C341-1

Document #: 38-03034 Rev. *A

Page 2 of 15

CY7C341

Pin Configurations

PGA

Bottom View

PLCC/HLCC

Top View

L

I/O

GND

I/O INPUT I/O

I/O

GND INPUT

V

CC

I/O

K

J

11 10

2 1

9

8

7

6

5

4

3

84 83 82 81 80 79 78 77 76 75

74

I/O

12

13

14

15

16

17

I/O

INPUT INPUT

I/O

73

I/O

72

71

70

69

68

67

I/O

H

I/O

V

I/O

GND

V

CC

I/O

GND

I/O

GND

I/O

G

F

18

19

20

21

22

23

24

GND

I/O

66

65

64

63

62

61

60

59

58

CC

7C341

I/O

GND

7C341

I/O

GND GND

V

CC

I/O

E

V

CC

I/O

25

26

27

28

29

I/O

D

C

I/O

57

56

55

54

I/O

INPUT INPUT

I/O

30

31

32

I/O

V

I/O

GND

I/O

11

B

A

CC

INPUT

5

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

INPUT/

CLK

I/O

1

I/O

2

I/O

3

I/O

4

GND

7

I/O

8

I/O

9

I/O

10

C341-2

6

C341-3

EXPANDER

DELAY

t

EXP

REGISTER

LOGIC ARRAY

OUTPUT

DELAY

t

CONTROLDELAY

INPUT/

OUTPUT

CLR

INPUT

t

INPUT

DELAY

LAC

t

PRE

t

OD

XZ

ZX

t

IN

t

LOGIC ARRAY

DELAY

t

RD

t

RSU

t

COMB

LATCH

t

RH

t

LAD

SYSTEM CLOCK DELAY t

ICS

CLOCK

DELAY

PIA

DELAY

t

IC

PIA

LOGIC ARRAY

DELAY

t

FD

I/O DELAY

t

IO

C341-4

Figure 1. CY7C341 Internal Timing Model

Document #: 38-03034 Rev. *A

Page 3 of 15

CY7C341

DC Output Current, per Pin........................ −25 mA to +25 mA

DC Input Voltage^[1]................................................−3.0V to +7.0V

DC Program Voltage .................................................... 13.0V

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .......................................−65°C to +150°C

Static Discharge Voltage..................................................>1100V

(per MIL-STD-883, method 3015)

Ambient Temperature with

Power Applied.................................................... 0°C to +70°C

Operating Range

Maximum Junction Temperature

(Under Bias)................................................................. 150°C

Range

Commercial

Industrial

Military

Ambient Temperature

0°C to +70°C

V_CC

Supply Voltage to Ground Potential .................−2.0V to +7.0V

Maximum Power Dissipation...................................2500 mW

DC V_CCor GND Current......................................................500 mA

5V ± 5%

5V ± 10%

–40°C to +85°C

–55°C to +125°C (Case)

Electrical Characteristics Over the Operating Range^[2]

Parameter

V_OH

Description

Test Conditions

V_CC= Min., I_OH= –4.0 mA

Min.

Max.

Unit

Output HIGH Voltage

2.4

V

V_OL

V_IH

V_IL

I_IX

Output LOW Voltage

Input HIGH Level

Input LOW Level

Input Current

V_CC= Min., I_OL= 8 mA

0.45

V

2.2

−0.3

−10

−40

−30

V_CC+ 0.3

0.8

V

GND ≤ V_IN≤ V_CC

+10

µA

mA

I_OZ

I_OS

Output Leakage Current V_O= V_CCor GND

+40

Output Short

V_CC= Max., V_OUT= GND^{[3, 4]}

−90

Circuit Current

I_CC1

Power Supply Current

(Standby)

V_I= V_CCor GND (No Load)

Commercial

360

435

380

480

100

mA

ns

Military/Industrial

Commercial

I_CC2

Power Supply Current^[5]V_I= V_CCor GND (No Load)

f = 1.0 MHz^{[3, 5]}

Military/Industrial

t_R(Recom-

mended)

Input Rise Time

Input Fall Time

t_F(Recom-

mended)

100

ns

Capacitance^[6]

Parameter

Description

Input Capacitance

Output Capacitance

Test Conditions

T_A= 25°C, f = 1 MHz, V_CC= 5.0V

Max.

Unit

pF

C_IN

10

20

C_OUT

pF

Notes:

1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.

2. Typical values are for T_A= 25°C and V_CC= 5V.

3. Guaranteed but not 100% tested.

4. No more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V_OUT= 0.5V has been chosen to avoid

test problems caused by tester ground degradation.

5. This parameter is measured with device programmed as a 16-bit counter in each LAB and is tested periodically by sampling production material.

6. Part (a) in AC Test Load and Waveforms is used for all parameters except t_ERand t_XZ, which is used for part (b) in AC Test Load and Waveforms. All external timing

parameters are measured referenced to external pins of the device.

Document #: 38-03034 Rev. *A

Page 4 of 15

CY7C341

AC Test Loads and Waveforms

R1 464Ω

5V

OUTPUT

ALL INPUT PULSES

90%

10%

OUTPUT

3.0V

GND

90%

10%

R2

250Ω

R2

250Ω

50 pF

5 pF

< 6 ns

INCLUDING

JIG AND

SCOPE

t

R

t

F

C341-5

C341-6

(a)

(b)

Equivalent to:

THÉVENIN EQUIVALENT (commercial/military)

163Ω

OUTPUT

1.75V

External Synchronous Switching Characteristics Over the Operating Range^[6]

7C341-25

7C341-30

7C341-35

Parameter

t_PD1

Description

Min.

Max

25

40

37

52

25

14

30

Min.

Max

Min.

Max

Unit

Dedicated Input to Combinatorial

Output Delay^[7]

Com’l

Mil

30

45

44

59

30

16

35

55

75

35

20

42

ns

t_PD2

t_PD3

t_PD4

t_EA

I/O Input to Combinatorial

Output Delay^[8]

Com’l

Mil

Dedicated Input to Combinatorial

Com’l

Mil

Output Delay with Expander Delay^[9]

I/O Input to Combinatorial Output

Delay with Expander Delay^{[3, 10]}

Com’l

Mil

Input to Output Enable Delay^{[3, 7]}

Com’l

Mil

t_ER

Input to Output Disable Delay^[6]

Com’l

Mil

t_CO1

Synchronous Clock Input to

Output Delay

Com’l

Mil

t_CO2

Synchronous Clock to Local

Feedback to Combinatorial

Output^{[3, 11]}

Com’l

Mil

t_S1

Dedicated Input or Feedback Set-up Com’l

15

20

25

ns

Time to Synchronous Clock

Mil

Output^{[6, 12]}

t_S2

I/O Input Set-up Time to

Com’l

30

39

45

Synchronous Clock Input^[8]

Mil

Notes:

7. This specification is a measure of the delay from input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes that

no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous

clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic.

If an input signal is applied to an I/O pin an additional delay equal to t_PIAshould be added to the comparable delay for a dedicated input. If expanders are used, add the

maximum expander delay t_EXPto the overall delay for the comparable delay without expanders.

8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used

to form the logic function.

9. This specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes

expander terms are used to form the logic functions and includes the worst-case expander logic delay for one pass through the expander logic.

10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used

to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by

sampling production material.

11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array

and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB.

This parameter is tested periodically by sampling production material.

12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are t_S2for

synchronous operation and t_AS2for asynchronous operation.

Document #: 38-03034 Rev. *A

Page 5 of 15

CY7C341

External Synchronous Switching Characteristics Over the Operating Range^[6](continued)

7C341-25 7C341-30

Min. Max

7C341-35

Min. Max

Parameter

Description

Min.

0

Max

Unit

t_H

Input Hold Time from

Com’l

Mil

0

ns

Synchronous Clock Input^[6]

0

t_WH

t_WL

t_RW

t_RO

t_RR

t_PW

t_PR

Synchronous Clock Input

High Time

Com’l

Mil

8

10

30

12.5

35

ns

8

Synchronous Clock Input

Low Time

Com’l

Mil

8

Asynchronous Clear Width^{[3, 6]}

Com’l

Mil

25

ns

35

Asynchronous Clear to

Com’l

Mil

25

30

35

ns

Registered Output Delay^[5]

Asynchronous Clear Recovery^{[3, 7]}

Asynchronous Preset Width^{[3, 6]}

Com’l

Mil

25

30

35

ns

Com’l

Mil

ns

Asynchronous Preset Recovery

Time^{[3, 6]}

Com’l

Mil

ns

t_PO

Asynchronous Preset to

Com’l

Mil

25

3

30

3

35

5

ns

Registered Output Delay^[6]

t_CF

Synchronous Clock to Local

Feedback Input^{[3, 13]}

Com’l

Mil

ns

3

5

t_P

External Synchronous Clock Period Com’l

16

20

25

ns

[3]

(1/f_MAX3

)

Mil

16

f_MAX1

External Feedback Maximum

Frequency (1/(t_CO1+t_S1))^{[3, 14]}

Com’l

Mil

34.5

55.5

27.7

43

22.2

33

MHz

f_MAX2

Internal Local Feedback Maximum

Com’l

Mil

Frequency, lesser of (1/(t_S1+ t_CF))

43

33

[3, 15]

or (1/t_CO1

)

f_MAX3

DataPathMaximumFrequency,least Com’l

62.5

50

40.0

MHz

of 1/(t_WL+ t_WH), 1/(t_S1+ t_H),

Mil

[3, 16]

or (1/t_CO1

)

f_MAX4

Maximum Register Toggle Frequency Com’l

62.5

3

50

3

40.0

3

MHz

ns

(1/(t_WL+ t_WH))^{[3, 17]}

Mil

t_OH

Output Data Stable Time from Syn- Com’l

chronous Clock Input^{[3, 18]}

Mil

3

Notes:

13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array

input. This delay plus the register set-up time, t_S1, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within

the same LAB. This parameter is tested periodically by sampling production material.

14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can

operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the same

LAB.

15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states

must also control external points, this frequency can still be observed as long as this frequency is less than 1/t_CO1

.

16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data

input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, t_S2is the appropriate t_Sfor calculation.

17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycle by a clock

signal applied to the dedicated clock input pin.

18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.

Document #: 38-03034 Rev. *A

Page 6 of 15

CY7C341

External Synchronous Switching Characteristics Over the Operating Range^[6](continued)

7C341-25 7C341-30

7C341-35

Parameter

t_ACO1

Description

Min.

Max

Min.

Max

30

Min.

Max

Unit

Dedicated Asynchronous Clock Input Com’l

25

40

35

55

ns

to Output Delay^[6]

Mil

30

t_ACO2

Asynchronous Clock Input to Local

Feedback to Combinatorial Output^[19]

Com’l

46

ns

Mil

46

t_AS1

Dedicated Input or Feedback Set-up Com’l

5

6

8

Time to Asynchronous Clock Input^[6]

Mil

8

t_AS2

I/O Input Set-Up Time to

Com’l

Mil

20

6

27

8

30

10

16

14

ns

Asynchronous Clock Input^[6]

t_AH

Input Hold Time from

Com’l

Mil

ns

Asynchronous Clock Input^[6]

6

8

t_AWH

t_AWL

t_ACF

t_AP

Asynchronous Clock Input

HIGH Time^[6]

Com’l

Mil

11

9

14

11

ns

Asynchronous Clock Input

LOW Time^{[6, 20]}

Com’l

Mil

ns

9

Asynchronous Clock to

Local Feedback Input^[21]

Com’l

Mil

15

18

22

ns

External Asynchronous

Com’l

Mil

20

25

27

30

23

ns

Clock Period (1/f_MAX4

)

f_MAXA1

External Feedback Maximum Fre-

Com’l

Mil

33.3

MHz

quency in Asynchronous Mode

[22]

1/(t_ACO1+ t_AS1

)

f_MAXA2

f_MAXA3

f_MAXA4

Maximum Internal

Com’l

Mil

50

40

50

15

40

33.3

28.5

33.3

15

MHz

ns

Asynchronous Frequency^[23]

Data Path Maximum Frequency in

Asynchronous Mode^[24]

Com’l

Mil

33.3

40

Maximum Asynchronous Register

Toggle Frequency 1/(t_AWH+ t_AWL

Com’l

Mil

[25]

)

40

t_AOH

Output Data Stable Time from Asyn- Com’l

15

chronous Clock Input^[26]

Mil

15

Notes:

19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB

logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.

The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production

material.

20. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge triggering, the t_AWHand t_AWLparameters must be swapped. If

a given input is used to clock multiple registers with both positive and negative polarity, t_AWHshould be used for both t_AWHand t_AWL

.

21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay

plus the asynchronous register set-up time, t_AS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for

feedback within the same LAB, and assumes there is no expander logic in the clock path and the clock input signal is applied to a dedicated input pin. This parameter is tested

periodically by sampling production material.

22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can

operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the

clock signal path or data path.

23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.

This parameter is determined by the lesser of (1/t_ACF+ t_AS1)) or (1/(t_AWH+t_AWL)). If register output states must also control external points, this frequency can still be

observed as long as this frequency is less than 1/t_ACO1

.

24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined

by the least of 1/(t_AWH+ t_AWL), 1/(t_AS1+ t_AH) or 1/t_ACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.

25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode

by a clock signal applied to an external dedicated input pin.

26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied

to an external dedicated input pin.

Document #: 38-03034 Rev. *A

Page 7 of 15

CY7C341

Internal Switching Characteristics Over the Operating Range^[2]

7C341-25

Min. Max

7C341-30

Min. Max

7C341-35

Min. Max

Parameter

t_IN

Description

Dedicated Input Pad and

Buffer Delay

Unit

Com’l

Mil

5

7

9

ns

9

t_IO

I/O Input Pad and Buffer Delay

Com’l

Mil

6

9

ns

6

9

t_EXP

t_LAD

t_LAC

t_OD

Expander Array Delay

Com’l

Mil

12

10

5

14

12

5

20

16

13

6

Logic Array Data Delay

Com’l

Mil

Logic Array Control Delay

Output Buffer and Pad Delay

Output Buffer Enable Delay^[27]

Output Buffer Disable Delay

Com’l

Mil

Com’l

Mil

5

6

t_ZX

Com’l

Mil

10

11

13

t_XZ

Com’l

Mil

t_RSU

Register Set-Up Time Relative to Com’l

Clock Signal at Register

6

8

10

Mil

t_RH

Register Hold Time Relative to

Clock Signal at Register

Com’l

Mil

t_LATCH

Flow-Through Latch Delay

Register Delay

Com’l

Mil

3

1

3

4

2

4

2

4

t_RD

Com’l

Mil

t_COMB

Transparent Mode Delay^[28]

Clock High Time

Com’l

Mil

t_CH

Com’l

Mil

8

10

12.5

t_CL

Clock Low Time

Com’l

Mil

t_IC

Asynchronous Clock Logic Delay Com’l

14

2

16

2

18

3

Mil

t_ICS

Synchronous Clock Delay

Feedback Delay

Com’l

Mil

2

3

t_FD

Com’l

Mil

1

2

1

2

t_PRE

Asynchronous Register Preset

Time

Com’l

Mil

5

6

7

5

6

7

Document #: 38-03034 Rev. *A

Page 8 of 15

CY7C341

Internal Switching Characteristics Over the Operating Range^[2](continued)

7C341-25

7C341-30

Min. Max

7C341-35

Min. Max

Parameter

t_CLR

Description

Min.

Max

5

Unit

Asynchronous Register Clear

Time

Com’l

6

7

ns

Mil

5

t_PCW

Asynchronous Preset and Clear Com’l

5

6

7

ns

Pulse Width

Mil

t_PCR

Asynchronous Preset and Clear Com’l

Recovery Time

Mil

t_PIA

Programmable Interconnect

Array Delay

Com’l

14

16

20

Mil

Notes:

27. Sample tested only for an output change of 500 mV.

28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combi-

natorial operation.

Switching Waveforms

External Combinatorial

DEDICATED INPUT/

I/O INPUT

t

/t

PD1 PD2

COMBINATORIAL

OUTPUT

t_ER

COMBINATORIAL

REGISTERED OUTPUT

HIGH-IMPEDANCE

3-STATE

t_EA

HIGH IMPEDANCE

3-STATE

VALID OUTPUT

C341-7

External Synchronous

DEDICATED INPUT/

[7]

I/O INPUT

t

H

t

WL

WH

t

S1

SYNCHRONOUS

CLOCK

t

/t

t /t

RR PR

CO1

RW PW

t

OH

ASYNCHRONOUS

CLEAR/PRESET

[7]

t

/t

RO PO

REGISTERED

OUTPUTS

t

CO2

COMBINATORIAL OUTPUT FROM

[10]

REGISTERED FEEDBACK

C341-8

Document #: 38-03034 Rev. *A

Page 9 of 15

CY7C341

Switching Waveforms (continued)

External Asynchronous

DEDICATEDINPUT/

[7]

I/OINPUT

t

AWL

AH

AWH

t

AS1

ASYNCHRONOUS

CLOCK INPUT

t

/t

t /t

RR PR

ACO1

RW PW

t

AOH

ASYNCHRONOUS

CLEAR/PRESET

[7]

t

/t

RO PO

ASYNCHRONOUS REGISTERED

OUTPUTS

t

ACO2

COMBINATORIAL OUTPUT

FROM ASYNCH. REGISTERED

FEEDBACK

C341-9

Internal Combinatorial

t

IN

INPUT PIN

t

PIA

t

IO

I/O PIN

t

EXP

EXPANDER

ARRAY DELAY

t

, t

LAC LAD

LOGIC ARRAY

INPUT

LOGIC ARRAY

OUTPUT

C341-10

Document #: 38-03034 Rev. *A

Page 10 of 15

CY7C341

Switching Waveforms (continued)

Internal Asynchronous

t

AWL

AWH

t t

IOR

t

F

CLOCK PIN

t

IN

CLOCK INTO

LOGIC ARRAY

t

IC

CLOCK FROM

LOGIC ARRAY

t

RH

RSU

DATA FROM

LOGIC ARRAY

t

,t

t

FD

t

,t

t

FD

RD LATCH

CLR PRE

REGISTER OUTPUT

TO LOCAL LAB

LOGIC ARRAY

t

PIA

REGISTER OUTPUT

TO ANOTHER LAB

C341-11

Internal Synchronous

t

CL

CH

SYSTEM CLOCK PIN

t

IH

t

ICS

SYSTEM CLOCK

AT REGISTER

t

RH

RSU

DATA FROM

LOGIC ARRAY

C341-12

Internal Synchronous

CLOCK FROM

LOGIC ARRAY

t

OD

t

RD

DATA FROM

LOGIC ARRAY

t

XZ

t

XZ

t

ZX

HIGH IMPEDANCE

STATE

OUTPUT PIN

C341-13

Document #: 38-03034 Rev. *A

Page 11 of 15

CY7C341

Ordering Information

Speed

(ns)

Package

Name

Operating

Range

Ordering Code

Package Type

25

CY7C341-25HC/HI

CY7C341-25JC/JI

CY7C341-25RC/RI

CY7C341-30HC/HI

CY7C341-30JC/JI

CY7C341-30RC/RI

CY7C341-30HMB

CY7C341-30RMB

CY7C341-35HC/HI

CY7C341-35JC/JI

CY7C341-35RC/RI

CY7C341-35HMB

CY7C341-35RMB

H84

J83

84-Lead Windowed Leaded Chip Carrier

84-Lead Plastic Leaded Chip Carrier