5962-9311201MXX_技术文档

CY7B991

CY7B992

Programmable Skew Clock Buffer

functions. These multiple-output clock drivers provide the sys-

tem integrator with functions necessary to optimize the timing

of high-performance computer systems. Eight individual driv-

ers, arranged as four pairs of user-controllable outputs, can

each drive terminated transmission lines with impedances as

low as 50Ω while delivering minimal and specified output skews

and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Features

• All output pair skew <100 ps typical (250 max.)

• 3.75- to 80-MHz output operation

• User-selectable output functions

— Selectable skew to 18 ns

— Inverted and non-inverted

Each output can be hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs able to skew up

to ±6 time units from their nominal “zero” skew position. The com-

pletely integrated PLL allows external load and transmission line

delay effects to be canceled. When this “zero delay” capability of the

PSCB is combined with the selectable output skew functions, the

user can create output-to-output delays of up to ±12 time units.

1

— Operation at

and

input frequency

4

⁄

2

— Operation at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input to output delay

• 50% duty-cycle outputs

Outputs drive 50 terminated lines

•

Ω

• Low operating current

• 32-pin PLCC/LCC package

• Jitter < 200 ps peak-to-peak (< 25 ps RMS)

• Compatible with a Pentium™-based processor

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low-frequency clock that can be multi-

plied by two or four at the clock destination. This facility mini-

mizes clock distribution difficulty while allowing maximum sys-

tem clock speed and flexibility.

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buff-

ers (PSCB) offer user-selectable control over system clock

Logic Block Diagram

Pin Configuration

TEST

PLCC/LCC

PHASE

FREQ

DET

FB

VCO AND

TIME UNIT

GENERATOR

FILTER

REF

4

3

2

1

32 31 30

29

FS

2F0

GND

1F1

1F0

5

6

3F1

4F0

28

27

4Q0

4Q1

4F0

4F1

7

8

9

SELECT

INPUTS

(THREE

LEVEL)

V

26

25

24

23

CCQ

CY7B991

CY7B992

V

CCN

SKEW

SELECT

MATRIX

V

CCN

3Q0

3Q1

3F0

3F1

4Q1

10

1Q0

1Q1

GND

4Q0

GND

11

12

22

21

2Q0

2Q1

2F0

2F1

13

14 15 16 17 18 19 20

1Q0

1Q1

1F0

1F1

7B991–2

7B991–1

Pentium is a trademark of Intel Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

November 1991 - Revised July 7, 1997

CY7B991

CY7B992

Pin Definitions

Signal

Name

I/O

Description

REF

I

Reference frequency input. This input supplies the frequency and timing against which allfunctional

variation is measured.

FB

I

PLL feedback input (typically connected to one of the eight outputs).

Three-level frequency range select. See Table 1.

Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.

Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.

Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.

Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.

Three-level select. See test mode section under the block diagram descriptions.

Output pair 1. See Table 2.

FS

I

1F0, 1F1

2F0, 2F1

3F0, 3F1

4F0, 4F1

TEST

I

1Q0, 1Q1

2Q0, 2Q1

3Q0, 3Q1

4Q0, 4Q1

O

Output pair 2. See Table 2.

O

Output pair 3. See Table 2.

O

Output pair 4. See Table 2.

V

PWR

Power supply for output drivers.

CCN

CCQ

Power supply for internal circuitry.

GND

Ground.

(xF0, xF1) inputs. Table 2 below shows the nine possible out-

Block Diagram Description

put functions for each section as determined by the function

select inputs. All times are measured with respect to the REF

input assuming that the output connected to the FB input has

Phase Frequency Detector and Filter

These two blocks accept inputs from the reference frequency

(REF) input and the feedback (FB) input and generate correc-

tion information to control the frequency of the Voltage-Con-

trolled Oscillator (VCO). These blocks, along with the VCO,

form a Phase-Locked Loop (PLL) that tracks the incoming

REF signal.

0t selected.

U

[1]

Table 2. Programmable Skew Configurations

Function Selects

Output Functions

1F1,2F1, 1F0,2F0, 1Q0,1Q1,

3F1, 4F1 3F0, 4F0 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1

VCO and Time Unit Generator

LOW

MID

LOW

MID

–4t

–3t

–2t

–1t

Divide by 2 Divide by 2

U

The VCO accepts analog control inputs from the PLL filter

block and generates a frequency that is used by the time unit

generator to create discrete time units that are selected in the

skew select matrix. The operational range of the VCO is de-

–6t

–4t

–2t

–6t

–4t

–2t

U

HIGH

LOW

MID

termined by the FS control pin. The time unit (t ) is determined

U

by the operating frequency of the device and the level of the

FS pin as shown in Table 1.

MID

0t

U

MID

HIGH

LOW

MID

+1t

+2t

+3t

+4t

+2t

+4t

+6t

+2t

+4t

+6t

U

[1]

Table 1. Frequency Range Select and t Calculation

HIGH

U

f

(MHz)

NOM

1

t_U= -----------------------

_NOM× N

Approximate

HIGH

Divide by 4 Inverted

f

Frequency(MHz)At

[2, 3]

Notes:

FS

Min. Max.

where N =

Which t = 1.0 ns

U

1. For all three-state inputs, HIGH indicates a connection to V_CC, LOW

indicates a connection to GND, and MID indicates an open connection.

Internal termination circuitry holds an unconnected input to V_CC/2.

2. The level to be set on FS is determined by the “normal” operating fre-

quency (f_NOM) of the V_COand Time Unit Generator (see Logic Block

Diagram). Nominal frequency (f_NOM) always appears at 1Q0 and the

other outputs when they are operated in their undivided modes (see

Table 2). The frequency appearing at the REF and FB inputs will be f_NOM

when the output connected to FB is undivided. The frequency of the REF

and FB inputs will be f_NOM/2 or f_NOM/4 when the part is configured for a

frequency multiplication by using a divided output as the FB input.

3. When the FS pin is selected HIGH, the REF input must not transition

upon power-up until V_CChas reached 4.3V.

LOW

MID

15

25

40

30

50

80

44

26

16

22.7

38.5

62.5

HIGH

Skew Select Matrix

The skew select matrix is comprised of four independent sec-

tions. Each section has two low-skew, high-fanout drivers

(xQ0, xQ1), and two corresponding three-level function select

2

CY7B991

CY7B992

FBInput

REFInput

1Fx

2Fx

3Fx

4Fx

(N/A)

LM

– 6t

– 4t

– 3t

U

LL

LH

LM

(N/A)

LH

ML

– 2t

– 1t

U

(N/A)

MM

MH

HL

MM

(N/A)

MH

0t

U

+1t

+2t

+3t

HM

(N/A)

HH

HL

HM

+4t

+6t

U

(N/A)

LL/HH

HH

DIVIDED

INVERT

7B991–3

[4]

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

Ambient Temperature with

Test Mode

Power Applied ............................................ –55°C to +125°C

Supply Voltage to Ground Potential ...............–0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

Output Current into Outputs (LOW)............................. 64 mA

The TEST input is a three-level input. In normal system oper-

ation, this pin is connected to ground, allowing the

CY7B991/CY7B992 to operate as explained briefly above (for

testing purposes, any of the three-level inputs can have a re-

movable jumper to ground, or be tied LOW through a 100Ω

resistor. This will allow an external tester to change the state

of these pins.)

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current..................................................... >200 mA

If the TEST input is forced to its MID or HIGH state, the device

will operate with its internal phase locked loop disconnected,

and input levels supplied to REF will directly control all outputs.

Relative output to output functions are the same as in normal

mode.

Operating Range

Ambient

Range

Commercial

Industrial

Temperature

V

CC

In contrast with normal operation (TEST tied LOW). All outputs

will function based only on the connection of their own function

select inputs (xF0 and xF1) and the waveform characteristics

of the REF input.

0°C to +70°C

5V ± 10%

–40°C to +85°C

–55°C to +125°C

[5]

Military

Maximum Ratings

Notes:

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 =

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

MID).

5. Indicates case temperature.

Storage Temperature .................................–65°C to +150°C

3

CY7B991

CY7B992

[6]

Electrical Characteristics Over the Operating Range

CY7B991

CY7B992

Min. Max.

Parameter

Description

Test Conditions

Min.

Max.

Unit

V

Output HIGH Voltage

V

= Min., I

= –16 mA

=–40 mA

2.4

V

OH

CC

OH

V

–0.75

CC

V

Output LOW Voltage

= Min., I = 46 mA

0.45

V

OL

= Min., I = 46 mA

0.45

OL

V

Input HIGH Voltage

(REF and FB inputs only)

2.0

V

1.35

–

V

CC

V

IH

CC

Input LOW Voltage

(REF and FB inputs only)

–0.5

0.8

–0.5

1.35

IL

Three-Level Input HIGH

Voltage (Test, FS, xFn)

Min. ≤ V ≤ Max.

V

– 0.85

V

– 0.85

V

CC

V

IHH

IMM

ILL

CC

[7]

Three-Level Input MID

Voltage (Test, FS, xFn)

Min. ≤ V ≤ Max.

V

/2 –

V

/2 +

V

/2 –

V /2 +

CC

500 mV

V

CC

500 mV

CC

[7]

500 mV

Three-Level Input LOW

Voltage (Test, FS, xFn)

Min. ≤ V ≤ Max.

0.0

0.85

0.0

0.85

V

CC

[7]

I

InputHIGH LeakageCurrent

(REF and FB inputs only)

V

= Max., V = Max.

10

µA

mA

IH

CC

IN

Input LOW Leakage Current

(REF and FB inputs only)

= Max., V = 0.4V

–500

–50

–500

–50

IL

IN

Input HIGH Current

(Test, FS, xFn)

= V

CC

200

50

200

50

IHH

IMM

ILL

IN

Input MID Current

(Test, FS, xFn)

= V /2

IN

CC

Input LOW Current

(Test, FS, xFn)

= GND

–200

–250

–200

N/A

IN

Output Short Circuit

= Max., V

OUT

OS

CCQ

CC

[8]

Current

= GND (25°C only)

Operating Current Used by

Internal Circuitry

V

= V

=

Com’l

85

90

85

90

CCN

CCQ

Max., All Input

Selects Open

Mil/Ind

I

Output Buffer Current per

Output Pair

V

= V = Max.,

CCQ

= 0 mA

14

19

mA

CCN

[9]

I

OUT

Input Selects Open, f

MAX

PD

Power Dissipation per

Output Pair

V

= V

= 0 mA

= Max.,

78

104^[11]

mW

CCN

CCQ

[10]

I

OUT

Input Selects Open, f

MAX

Notes:

6. See the last page of this specification for Group A subgroup testing information.

7. These inputs are normally wired to V_CC, GND, or left unconnected (actual threshold voltages vary as a percentage of V_CC). Internal termination resistors hold

unconnected inputs at V_CC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t_LOCKtime

before all datasheet limits are achieved.

8. CY7B991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs

should not be shorted to GND. Doing so may cause permanent damage.

9. Total output current per output pair can be approximated by the following expression that includes device current plus load current:

CY7B991: I_CCN= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1

CY7B992: I_CCN= [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1

Where

F = frequency in MHz

C = capacitive load in pF

Z = line impedance in ohms

N = number of loaded outputs; 0, 1, or 2

FC = F < C

10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to

the load circuit:

CY7B991: PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1

CY7B992: PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1

See note 9 for variable definition.

11. CMOS output buffer current and power dissipation specified at 50-MHz reference frequency.

4

CY7B991

CY7B992

Capacitance^[12]

Parameter

Description

Test Conditions

Max.

Unit

C

Input Capacitance

T = 25°C, f = 1 MHz, V = 5.0V

10

pF

IN

A

CC

Note:

12. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.

AC Test Loads and Waveforms

5V

3.0V

2.0V

=1.5V

0.8V

2.0V

=1.5V

0.8V

R1=130

R2=91

R1

R2

V

th

V

th

C = 50 pF (C =30 pF for –2 and –5 devices)

L

0.0V

C

(Includes fixture and probe capacitance)

L

1ns

≤

1ns

≤

7B991–4

7B991–5

TTL ACTest Load (CY7B991)

TTL Input Test Waveform (CY7B991)

V

CC

V

CC

R1=100

R2=100

80%

= V /2

20%

R1

=30 pF for –2 and –5 devices)

C = 50 pF (C

L

V

th

= V /2

V

CC

th

CC

(Includes fixture and probe capacitance)

20%

0.0V

C

L

R2

3ns

≤

7B991–6

7B991–7

CMOS AC Test Load (CY7B992)

CMOS Input Test Waveform (CY7B992)

5

CY7B991

CY7B992

[2, 13]

Switching Characteristics Over the Operating Range

[14]

CY7B991–2

CY7B992–2

Parameter

Description

FS = LOW

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

[1, 2]

f

Operating Clock

15

25

30

50

80

15

30

50

MHz

NOM

Frequency in MHz

FS = MID

25

40

[1, 2 , 3]

[15]

FS = HIGH

40

80

t

REF Pulse Width HIGH

REF Pulse Width LOW

Programmable Skew Unit

5.0

ns

RPWH

RPWL

U

5.0

See Table 1

Zero Output Matched-Pair Skew

0.05

0.20

0.05

0.20

ns

SKEWPR

[16, 17]

(XQ0, XQ1)

[16, 18,19]

t

Zero Output Skew (All Outputs)

0.1

0.25

0.5

0.1

0.25

0.5

ns

SKEW0

Output Skew (Rise-Rise, Fall-Fall, Same

0.25

SKEW1

[16, 20]

Class Outputs)

t

Output Skew (Rise-Fall, Nominal-Inverted,

Divided-Divided)

0.3

0.25

0.5

0.9

0.3

0.25

0.5

0.7

ns

SKEW2

SKEW3

SKEW4

[16, 20]

Output Skew (Rise-Rise, Fall-Fall, Different

[16, 20]

Class Outputs)

Output Skew (Rise-Fall, Nominal-Divided,

[16, 20]

Divided-Inverted)

[14, 21]

t

Device-to-Device Skew

0.75

+0.25

+0.65

2.0

0.75

+0.25

+0.5

3.0

ns

ms

ps

DEV

Propagation Delay, REF Rise to FB Rise

–0.25

–0.65

0.0

–0.25

–0.5

0.0

PD

[22]

Output Duty Cycle Variation

ODCV

PWH

PWL

ORISE

OFALL

LOCK

JR

[23, 24]

Output HIGH Time Deviation from 50%

[23, 24]

Output LOW Time Deviation from 50%

1.5

3.0

[23, 25]

Output Rise Time

0.15

1.0

1.2

0.5

2.0

2.5

[23, 25]

Output Fall Time

1.2

2.5

[26]

PLL Lock Time

0.5

[14]

Cycle-to-Cycle Output

Jitter

RMS

25

[14]

Peak-to-Peak

200

Note:

13. Test measurement levels for the CY7B991 are TTL levels (1.5V to 1.5V). Test measurement levels for the CY7B992 are CMOS levels (V_CC/2 to V_CC/2). Test

conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.

14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.

15. Except as noted, all CY7B992–2 and –5 timing parameters are specified to 80-MHz with a 30-pF load.

16. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t_Udelay has been selected when all are

loaded with 50 pF and terminated with 50Ω to 2.06V (CY7B991) or V_CC/2 (CY7B992).

17. t_SKEWPRis defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t_U.

18. t_SKEW0is defined as the skew between outputs when they are selected for 0t_U. Other outputs are divided or inverted but not shifted.

19. C_L=0 pF. For C_L=30 pF, t_SKEW0=0.35 ns.

20. There are three classes of outputs: Nominal (multiple of t_Udelay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2

or Divide-by-4 mode).

21. t_DEVis the output-to-output skew between any two devices operating under the same conditions (V_CCambient temperature, air flow, etc.)

22. t_ODCVis the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t_SKEW2and t_SKEW4specifications.

23. Specified with outputs loaded with 30 pF for the CY7B99X–2 and –5 devices and 50 pF for the CY7B99X–7 devices. Devices are terminated through 50Ω to

2.06V (CY7B991) or V_CC/2 (CY7B992).

24. t_PWHis measured at 2.0V for the CY7B991 and 0.8 V_CCfor the CY7B992. t_PWLis measured at 0.8V for the CY7B991 and 0.2 V_CCfor the CY7B992.

25. t_ORISEand t_OFALLmeasured between 0.8V and 2.0V for the CY7B991 or 0.8V_CCand 0.2V_CCfor the CY7B992.

26. t_LOCKis the time that is required before synchronization is achieved. This specification is valid only after V_CCis stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until t_PDis within specified limits.

6

CY7B991

CY7B992

[2, 13]

Switching Characteristics Over the Operating Range

(continued)

CY7B991–5

CY7B992–5

Typ.

Parameter

Description

FS = LOW

Min.

15

Typ.

Max.

30

Min.

15

Max.

30

Unit

[1, 2]

f

Operating Clock

MHz

NOM

Frequency in MHz

FS = MID

25

50

25

50

[1, 2 , 3]

[15]

FS = HIGH

40

80

40

80

t

REF Pulse Width HIGH

REF Pulse Width LOW

Programmable Skew Unit

5.0

ns

RPWH

RPWL

U

See Table 1

Zero Output Matched-Pair Skew

0.1

0.25

0.1

0.25

ns

SKEWPR

[16, 17]

(XQ0, XQ1)

[16, 18]

t

Zero Output Skew (All Outputs)

0.25

0.6

0.5

0.7

0.25

0.6

0.5

0.7

ns

SKEW0

Output Skew (Rise-Rise, Fall-Fall, Same

SKEW1

[16, 20]

Class Outputs)

t

Output Skew (Rise-Fall, Nominal-Inverted,

Divided-Divided)

0.5

1.0

0.7

1.0

0.6

0.5

0.6

1.5

0.7

1.7

ns

SKEW2

SKEW3

SKEW4

[16, 20]

Output Skew (Rise-Rise, Fall-Fall, Different

[16, 20]

Class Outputs)

Output Skew (Rise-Fall, Nominal-Divided,

[16, 20]

Divided-Inverted)

[14, 21]

t

Device-to-Device Skew

1.25

+0.5

+1.0

2.5

3

1.25

+0.5

+1.2

4.0

ns

ms

ps

DEV

Propagation Delay, REF Rise to FB Rise

–0.5

–1.0

0.0

–0.5

–1.2

0.0

PD

[22]

Output Duty Cycle Variation

ODCV

PWH

PWL

ORISE

OFALL

LOCK

JR

[23, 24]

Output HIGH Time Deviation from 50%

[23, 24]

Output LOW Time Deviation from 50%

4.0

[23, 25]

Output Rise Time

0.15

1.0

1.5

0.5

25

0.5

2.0

3.5

[23, 25]

Output Fall Time

3.5

[26]

PLL Lock Time

0.5

[14]

Cycle-to-Cycle Output

Jitter

RMS

25

[14]

Peak-to-Peak

200

7

CY7B991

CY7B992

[2, 13]

Switching Characteristics Over the Operating Range

(continued)

CY7B991–7

CY7B992–7

Typ.

Parameter

Description

Operating Clock FS = LOW

Min.

Typ.

Max.

30

Min.

15

Max.

Unit

[1, 2]

f

15

25

30

50

MHz

NOM

Frequency in MHz

[1, 2]

FS = MID

50

25

[15]

FS = HIGH

40

80

40

80

t

REF Pulse Width HIGH

REF Pulse Width LOW

Programmable Skew Unit

5.0

ns

RPWH

RPWL

U

See Table 1

Zero Output Matched-Pair Skew

0.1

0.25

0.1

0.25

ns

SKEWPR

[16, 17]

(XQ0, XQ1)

[16, 18]

t

Zero Output Skew (All Outputs)

0.3

0.6

0.75

1.0

0.3

0.6

0.75

1.0

ns

SKEW0

Output Skew (Rise-Rise, Fall-Fall, Same

SKEW1

[16, 20]

Class Outputs)

t

Output Skew (Rise-Fall, Nominal-Inverted,

Divided-Divided)

1.0

0.7

1.2

1.5

1.2

1.7

1.0

0.7

1.2

1.5

1.2

1.7

ns

SKEW2

SKEW3

SKEW4

[16, 20]

Output Skew (Rise-Rise, Fall-Fall, Different

[16, 20]

Class Outputs)

Output Skew (Rise-Fall, Nominal-Divided,

[16, 20]

Divided-Inverted)

[14, 21]

t

Device-to-Device Skew

1.65

+0.7

+1.2

3

1.65

+0.7

+1.5

5.5

ns

ms

ps

DEV

Propagation Delay, REF Rise to FB Rise

–0.7

–1.2

0.0

–0.7

–1.5

0.0

PD

[22]

Output Duty Cycle Variation

ODCV

PWH

PWL

ORISE

OFALL

LOCK

JR

[23, 24]

Output HIGH Time Deviation from 50%

[23, 24]

Output LOW Time Deviation from 50%

3.5

2.5

0.5

25

5.5

[23, 25]

Output Rise Time

0.15

1.5

0.5

3.0

5.0

[23, 25]

Output Fall Time

5.0

[26]

PLL Lock Time

0.5

[14]

Cycle-to-Cycle Output

Jitter

RMS

25

[14]

Peak-to-Peak

200

8

CY7B991

CY7B992

AC Timing Diagrams

t

RPWL

REF

t

RPWH

REF

t

ODCV

PD

t

ODCV

FB

Q

t

JR

t

SKEWPR,

SKEW0,1

SKEWPR,

SKEW0,1

OTHERQ

t

SKEW2

t

SKEW2

INVERTED Q

t

SKEW3,4

t

SKEW3,4

t

SKEW3,4

REF DIVIDED BY 2

REF DIVIDED BY 4

t

SKEW1,3, 4

SKEW2,4

7B991–8

9

CY7B991

CY7B992

Operational Mode Descriptions

REF

LOAD

Z

0

L1

L2

FB

SYSTEM

CLOCK

REF

FS

LOAD

4Q0

4Q1

4F0

4F1

0

3Q0

3Q1

3F0

3F1

L3

L4

2F0

2F1

2Q0

2Q1

Z

0

1F0

1F1

1Q0

1Q1

LOAD

TEST

Z

0

LENGTH L1 = L2 = L3 = L4

7B991–9

Figure 2. Zero-Skew and/or Zero-Delay Clock Driver

Figure 2 shows the PSCB configured as a zero-skew clock

buffer. In this mode the 7B991/992 can be used as the basis

for a low-skew clock distribution tree. When all of the function

select inputs (xF0, xF1) are left open, the outputs are aligned

and may each drive a terminated transmission line to an inde-

pendent load. The FB input can be tied to any output in this

configuration and the operating frequency range is selected

with the FS pin. The low-skew specification, coupled with the

ability to drive terminated transmission lines (with impedances

as low as 50 ohms), allows efficient printed circuit board de-

sign.

REF

LOAD

Z

0

L1

L2

FB

REF

FS

SYS–

TEM

CLOCK

LOAD

4Q0

4Q1

4F0

4F1

Z

0

3Q0

3Q1

3F0

3F1

L3

L4

2F0

2F1

2Q0

2Q1

Z

0

1F0

1F1

1Q0

1Q1

LOAD

TEST

Z

0

LENGTH L1 = L2

L3 < L2 by 6 inches

L4 > L2 by 6 inches

7B991–10

Figure 3. Programmable-Skew Clock Driver

Figure 3 shows a configuration to equalize skew between met-

al traces of different lengths. In addition to low skew between

outputs, the PSCB can be programmed to stagger the timing

of its outputs. The four groups of output pairs can each be

programmed to different output timing. Skew timing can be

adjusted over a wide range in small increments with the appro-

priate strapping of the function select pins. In this configuration

the 4Q0 output is fed back to FB and configured for zero skew.

The other three pairs of outputs are programmed to yield dif-

ferent skews relative to the feedback. By advancing the clock

signal on the longer traces or retarding the clock signal on

shorter traces, all loads can receive the clock pulse at the

same time.

In this illustration the FB input is connected to an output with

0-ns skew (xF1, xF0 = MID) selected. The internal PLL syn-

chronizes the FB and REF inputs and aligns their rising edges

to insure that all outputs have precise phase alignment.

Clock skews can be advanced by ±6 time units (t ) when using

U

an output selected for zero skew as the feedback. A wider range of

delays is possible if the output connected to FB is also skewed.

Since “Zero Skew”, +t , and –t are defined relative to output

U

groups, and since the PLL aligns the rising edges of REF and FB,

it is possible to create wider output skews by proper selection of the

xFn inputs. For example a +10 t between REF and 3Qx can be

U

achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND,

10

CY7B991

CY7B992

3F0 = MID, and 3F1 = High. (Since FB aligns at –4 t and 3Qx

form at these outputs. Note that the 20- and 40-MHz clocks fall

U

skews to +6 t , a total of +10 t skew is realized.) Many other con-

figurations can be realized by skewing both the output used as the

FB input and skewing the other outputs.

simultaneously and are out of phase on their rising edge. This

U

1

will allow the designer to use the rising edges of the

⁄

fre-

2

1

quency and

⁄

frequency outputs without concern for ris-

4

ing-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at

80 MHz and are skewed by programming their select inputs

accordingly. Note that the FS pin is wired for 80-MHz operation

because that is the frequency of the fastest output.

REF

FB

REF

FS

4Q0

4Q1

4F0

4F1

FB

REF

20 MHz

FS

3Q0

3Q1

3F0

3F1

10 MHz

4Q0

4F0

4Q1

4F1

2Q0

2Q1

2F0

2F1

5 MHz

3Q0

3Q1

3F0

3F1

1Q0

1Q1

1F0

1F1

20 MHz

2Q0

2Q1

2F0

2F1

TEST

1F0

1F1

1Q0

1Q1

7B991–11

Figure 4. Inverted Output Connections

TEST

7B991–13

Figure 4 shows an example of the invert function of the PSCB.

In this example the 4Q0 output used as the FB input is pro-

grammed for invert (4F0 = 4F1 = HIGH) while the other three

pairs of outputs are programmed for zero skew. When 4F0 and

4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase

outputs. The PLL aligns the rising edge of the FB input with the

rising edge of the REF. This causes the 1Q, 2Q, and 3Q out-

puts to become the “inverted” outputs with respect to the REF

input. By selecting which output is connect to FB, it is possible

to have 2 inverted and 6 non-inverted outputs or 6 inverted and

2 non-inverted outputs. The correct configuration would be de-

termined by the need for more (or fewer) inverted outputs. 1Q,

2Q, and 3Q outputs can also be skewed to compensate for

varying trace delays independent of inversion on 4Q.

Figure 6. Frequency Divider Connections

Figure 6 demonstrates the PSCB in a clock divider application.

2Q0 is fed back to the FB input and programmed for zero

skew. 3Qx is programmed to divide by four. 4Qx is pro-

grammed to divide by two. Note that the falling edges of the

4Qx and 3Qx outputs are aligned. This allows use of the rising

1

edges of the ⁄ frequency and ⁄ frequency without concern

2

4

for skew mismatch. The 1Qx outputs are programmed to zero

skew and are aligned with the 2Qx outputs. In this example,

the FS input is grounded to configure the device in the 15- to

30-MHz range since the highest frequency output is running at

20 MHz.

Figure 7 shows some of the functions that are selectable on

the 3Qx and 4Qx outputs. These include inverted outputs and

outputs that offer divide-by-2 and divide-by-4 timing. An invert-

ed output allows the system designer to clock different sub-

systems on opposite edges, without suffering from the pulse

asymmetry typical of non-ideal loading. This function allows

the two subsystems to each be clocked 180 degrees out of

phase, but still to be aligned within the skew spec.

REF

FB

20 MHz

REF

FS

40 MHz

4Q0

4Q1

4F0

4F1

The divided outputs offer a zero-delay divider for portions of

the system that need the clock to be divided by either two or

four, and still remain within a narrow skew of the “1X” clock.

Without this feature, an external divider would need to be add-

ed, and the propagation delay of the divider would add to the

skew between the different clock signals.

20 MHz

80 MHz

3Q0

3Q1

3F0

3F1

2F0

2F1

2Q0

2Q1

1Q0

1Q1

1F0

1F1

These divided outputs, coupled with the Phase Locked Loop,

allow the PSCB to multiply the clock rate at the REF input by

either two or four. This mode will enable the designer to dis-

tribute a low-frequency clock between various portions of the

system, and then locally multiply the clock rate to a more suit-

able frequency, while still maintaining the low-skew character-

istics of the clock driver. The PSCB can perform all of the func-

tions described above at the same time. It can multiply by two

and four or divide by two (and four) at the same time that it is

shifting its outputs over a wide range or maintaining zero skew

between selected outputs.

TEST

7B991–12

Figure 5. Frequency Multiplier with Skew Connections

Figure 5 illustrates the PSCB configured as a clock multiplier.

The 3Q0 output is programmed to divide by four and is fed

back to FB. This causes the PLL to increase its frequency until

the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx

and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are

programmed to divide by two, which results in a 40-MHz wave-

11

CY7B991

CY7B992

REF

LOAD

Z

0

80-MHz

INVERTED

FB

REF

FS

20–MHz

DISTRIBUTION

CLOCK

LOAD

4Q0

4Q1

4F0

4F1

20-MHz

Z

0

3Q0

3Q1

2Q0

2Q1

3F0

3F1

2F0

2F1

80-MHz

ZERO SKEW

Z

0

1Q0

1Q1

1F0

LOAD

80-MHz

SKEWED –3.125 ns (–4t_U)

1F1

TEST

Z

0

7B991–14

Figure 7. Multi-Function Clock Driver

LOAD

REF

Z

0

L1

FB

SYSTEM

CLOCK

REF

FS

4F0

4F1

L2

Z

0

4Q0

4Q1

3Q0

3Q1

3F0

3F1

LOAD

L3

2F0

2F1

2Q0

2Q1

Z

0

1F0

1F1

1Q0

1Q1

L4

FB

REF

TEST

FS

LOAD

4Q0

4Q1

4F0

4F1

3F0

3F1

2F0

2F1

Z

0

3Q0

3Q1

2Q0

2Q1

LOAD

1F0

1Q0

1Q1

1F1

TEST

7B991–15

Figure 8. Board-to-Board Clock Distribution

Figure 8 shows the CY7B991/992 connected in series to con-

struct a zero-skew clock distribution tree between boards. De-

lays of the downstream clock buffers can be programmed to

compensate for the wire length (i.e., select negative skew

equal to the wire delay) necessary to connect them to the mas-

ter clock source, approximating a zero-delay clock tree. Cas-

caded clock buffers will accumulate low-frequency jitter be-

cause of the non-ideal filtering characteristics of the PLL filter.

It is recommended that not more than two clock buffers be

connected in series.

12

CY7B991

CY7B992

Ordering Information

Accuracy

Package

Name

Operating

Range

(ps)

250

500

Ordering Code

Package Type

CY7B991–2JC

CY7B991–5JC

CY7B991–5JI

CY7B991–7JC

CY7B991–7JI

CY7B991–7LMB

CY7B992–2JC

CY7B992–5JC

CY7B992–5JI

CY7B992–7JC

CY7B992–7JI

CY7B992–7LMB

J65

L55

J65

L55

32-Lead Plastic Leaded Chip Carrier

Commercial

Industrial

750

Commercial

Industrial

32-Pin Rectangular Leadless Chip Carrier Military

250

500

32-Lead Plastic Leaded Chip Carrier

Commercial

Industrial

750

Commercial

Industrial

32-Pin Rectangular Leadless Chip Carrier Military

MILITARY SPECIFICATIONS

Group A Subgroup Testing

DC Characteristics

Parameter

Subgroups

1, 2, 3

V

OH

V

OL

V

IH

V

IL

V

IHH

V

IMM

V

ILL

IH

I

IL

I

IHH

I

IMM

I

ILL

I

CCQ

I

CCN

Document #: 38–00513–A

13

CY7B991

CY7B992

Package Diagrams

32-Lead Plastic Leaded Chip Carrier

32-Pin Rectangular Leadless Chip Carrier

MIL-STD-1835 C-12

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	5962-9311201MXX
厂家：	CYPRESS
描述：	PLL Based Clock Driver, 7B Series, 2 True Output(s), 0 Inverted Output(s), CMOS, CQCC32, CERAMIC, LCC-32 驱动逻辑集成电路
文件：	总14页 (文件大小：326K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

5962-9311201MXX [CYPRESS]

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