635E6I3010M0000 [CTS]
LVPECL Output Clock Oscillator, 10MHz Nom,;
| 型号： | 635E6I3010M0000 |
| 厂家： | 
CTS |
| 描述： | LVPECL Output Clock Oscillator, 10MHz Nom, 机械 振荡器 |
| 文件： | 总3页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Model 635
Low Jitter
FEATURES
• Standard 7.0mm x 5.0mm, 6-Pad Surface Mount Package
• Low Phase Jitter, 0.7ps RMS Maximum
• LVPECL or LVDS Output
• Fundamental and 3rd Overtone Crystal Designs
• Frequency Range 10 – 320 MHz
• Frequency Stability ±50 ppm Standard
• Operating Voltages +2.5Vdc or +3.3Vdc
• Operating Temperature to -40°C to +85°C
• Output Enable Standard
• Tape & Reel Packaging Standard, EIA-418
• RoHS/Green Compliant [6/6]
APPLICATIONS
Model 635 is ideal for applications such as broadband access, SerDes, Ethernet/Gigabit Ethernet, SONET/SDH
and optical networking.
ORDERING INFORMATION
635
M
OUTPUT TYPE
FREQUENCY IN MHz
P = LVPECL - Pin 1 Enable [std]
L = LVDS - Pin 1 Enable [std]
E = LVPECL - Pin 2 Enable [opt]
V = LVDS - Pin 2 Enable [opt]
2
M - indicates MHz and decimal point.
SUPPLY VOLTAGE
2 = 2.5 Vdc
FREQUENCY STABILITY
3 = 3.3 Vdc
6 = ± 20 ppm 1
5 = ± 25 ppm
3 = ± 50 ppm
2 = ± 100 ppm
OPERATING TEMPERATURE RANGE
A = -10°C to +60°C
C = -20°C to +70°C
2
I = -40°C to +85°C
1] Consult factory for availability of 6I Stability/Temperature combination.
2] Frequency is recorded with 3 significant digits before the ‘M’ and 4 significant digits after the ‘M’ (including zeros).
See Table I for part number frequency codes that exceed 4 significant digits.
[Ex. XXXMXXXX (008M0000), XXXMXXXX (049M1520), XXXMXXXX (122M8800)]
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
PACKAGING INFORMATION [reference]
Device quantity is 1k pcs. maximum per 180mm reel.
Table I
NOMINAL FREQUENCY
[MHz]
CTS PART NUMBER
FREQUENCY CODE
025M0006
025.000625
101.575694
125.009375
148.351648
153.600770
156.253906
178.018970
101M5756
125M0093
148M351A
153M6007
156M2539
178M0189
Document No. 008-0284-0
Page 1- 3
Rev. E
www.ctscorp.com
Model 635
7.0mm x 5.0mm Low Jitter
LVPECL or LVDS Clock
ELECTRICAL CHARACTERISTICS
PARAMETER
Maximum Supply Voltage
Storage Temperature
Frequency Range
LVPECL
SYMBOL
VCC
CONDITIONS
MIN
-0.5
-40
TYP
-
MAX
5.0
UNIT
V
-
TSTG
-
-
+100
°C
fO
Δf/fO
TA
-
MHz
± ppm
°C
10.00
-
-
-
-
320
LVDS
80.00
320
Frequency Stability
All Inclusive, see Note 1.
1st year aging
-
-
20, 25, 50, 100
3
Operating Temperature
Commercial
-
-20
-40
+70
+85
2.63
3.47
25
Industrial
Supply Voltage
2.38
3.14
2.5
3.3
VCC
± 5 %
V
Supply Current
LVPECL
ICC
Maximum Load
mA
ms
ps
-
-
-
-
-
-
-
-
88
65
5
LVDS
TS
Application of VCC
Start Up Time
2
Phase Jitter
tjrms
pjrms
Bandwidth 12 kHz - 20 MHz
0.3
2.6
25
0.7
-
Period Jitter RMS
Period Jitter Pk-Pk
Enable Function
Enable Input Voltage
Disable Input Voltage
Disable Time
-
-
-
Standby
VIH
VIL
0.7*VCC
V
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0' , Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
-
-
-
-
-
0.3*VCC
200
-
-
-
TPLZ
TPLZ
ns
Enable Time
2
ms
LVPECL WAVEFORM
Output Load
RL
Terminated to VCC - 2.0V
@ VCC - 1.3V
-
50
-
-
Ohms
%
Output Duty Cycle
Output Voltage Levels
Logic '1' Level
SYM
45
55
VOH
VOL
VCC - 1.025
VCC - 1.810
VCC - 1.085
VCC - 1.830
-
VCC - 0.880
VCC - 1.620
VCC - 0.880
VCC - 1.555
0.7
PECL Load, -20°C to +70°C
PECL Load, -20°C to +70°C
PECL Load, -40°C to +85°C
PECL Load, -40°C to +85°C
@ 20% - 80% Levels
-
-
V
Logic '0' Level
VOH
Logic '1' Level
-
V
VOL
Logic '0' Level
-
TR, TF
Rise and Fall Time
LVDS WAVEFORM
Output Load
0.3
ns
RL
Between Outputs
@ 1.25V
-
100
-
-
Ohms
%
Output Duty Cycle
Differential Output Voltage
Offset Voltage
SYM
VOD
VOS
45
55
RL = 100 Ohms
LVDS Load
247
1.125
350
1.25
454
1.375
mV
V
Output Voltage Levels
Logic '1' Level
VOH
VOL
V
LVDS Load
-
0.90
-
1.43
1.10
0.4
1.60
-
Logic '0' Level
LVDS Load
TR, TF
Rise and Fall Time
Notes:
@ 20% - 80% Levels
0.7
ns
1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
LVPECL/LVDS OUTPUT WAVEFORM
ENABLE TRUTH TABLE
PIN 1 or Pin 2
Logic ‘1’
PIN 4 & 5
Output
Output
High Z
Open
Logic ‘0’
Document No. 008-0284-0
Page 2 - 3
Rev. E
Model 635
7.0mm x 5.0mm Low Jitter
LVPECL or LVDS Clock
TEST CIRCUIT, LVDS LOAD
TEST CIRCUIT, LVPECL LOAD
MECHANICAL SPECIFICATIONS
MARKING INFORMATION
PACKAGE DRAWING
1. ** - Manufacturing Site Code.
2. YYWW – Date code, YY – year, WW – week.
3. O – Output Type. P or E = LVPECL, L or V = LVDS.
4. ST – Frequency stability/temperature code.
[Refer to Ordering Information.]
CTS**YYWW
635OSTV
● XXXMXXXXXX
5. V – Voltage code. 3 = 3.3V, 2 = 2.5V
6. XXXMXXXXXX – Frequency is marked with only
leading significant digits before the ‘M’ and
4 – 6 digits after the ‘M’ (including zeros).
Ex. XXMXXXX
[19M4400]
XXXMXXXXX [153M60077]
XXXMXXXXXX [148M351648]
NOTES
1. Complete CTS part number, frequency value and
date code information must appear on reel and
carton labels.
2. Termination pads [e4]. Barrier-plating is nickel [Ni]
with gold [Au] flash plate.
3. Reflow conditions per JEDEC J-STD-020; 260°C
maximum, 20 seconds.
SUGGESTED SOLDER PAD GEOMETRY
CBYPASS should be ≥ 0.01 uF.
4. MSL = 1.
D.U.T. PIN ASSIGNMENTS
PIN
SYMBOL
EOH or N.C.
N.C. or EOH
DESCRIPTION
1
Enable [std] or No Connect
No Connect or Enable [opt]
2
3
4
5
6
GND
Circuit & Package Ground
RF Output
Output
Output
VCC
Complimentary RF Output
Supply Voltage
Document No. 008-0284-0
Page 3 - 3
Rev. E
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