633E2502C3T [CTS]
LVPECL Output Clock Oscillator;
| 型号： | 633E2502C3T |
| 厂家： | 
CTS |
| 描述： | LVPECL Output Clock Oscillator |
| 文件： | 总9页 (文件大小：799K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Model 633
Very Low Jitter LVPECL or LVDS Clock
Features
. Ceramic Surface Mount Package
. Very Low Phase Jitter Performance, 500fs Maximum
. Fundamental or 3rd Overtone Crystal Design
. Frequency Range 10 – 220MHz *
. +2.5V or +3.3V Operation
Part Dimensions:
3.2 × 2.5 × 1.0mm • 25.00mg
. Output Enable Standard
. Tape and Reel Packaging, EIA-418
Standard Frequencies
- 25.00MHz
- 50.00MHz
- 74.1758MHz
- 74.25MHz
- 100.00MHz
- 125.00MHz
- 148.3516MHz - 187.50MHz
- 150.00MHz
- 155.52MHz
- 156.25MHz
- 161.1328MHz
Applications
- 200.00MHz
- 212.50MHz
. SerDes
. PON
. Storage Area Networking
. Broadband Access
. SONET/SDH/DWDM
. Ethernet/GbE/SyncE
. Fiber Channel
. Test and Measurement
* See Page 9 for additional developed frequencies.
Check with factory for availability of frequencies not listed.
Description
CTS Model 633 is a low cost, high performance clock oscillator supporting differential LVPECL or LVDS outputs.
Employing the latest IC technology, M633 has excellent stability and very low jitter/phase noise performance.
Ordering Information
Model
Output
Type
P
Frequency
Stability
3
Temperature
Supply
Voltage
3
Frequency Code
[MHz]
Packaging
T
Range
I
633
XXX or XXXX
Output
Stability
Voltage
+2.5Vdc
+3.3Vdc
Code
P
L
E
V
Code
Code
2
3
±20ppm 2
±25ppm
±50ppm
±100ppm
LVPECL - Pin 1 Enable
LVDS - Pin 1 Enable
LVPECL - Pin 2 Enable
LVDS - Pin 2 Enable
6
5
3
2
Frequency
Product Frequency Code 1
Temp. Range
-10°C to +60°C
-20°C to +70°C
-40°C to +85°C
Packing
1k pcs./reel
Code
Code
Code
T
A
C
I
Notes:
1] Refer to document 016-1454-0, Frequency Code Tables. 3-digits for frequencies <100MHz, 4-digits for frequencies 100MHz or greater.
Consult factory for availability of 6I Stability/Temperature combination.
2]
Not all performance combinations and frequencies may be available.
Contact your local CTS Representative or CTS Customer Service for availability.
This product is specified for use only in standard commercial applications. Supplier disclaims all express and implied warranties and liability in connection with any use of this
product in any non-commercial applications or in any application that may expose the product to conditions that are outside of the tolerances provided in its specification.
DOC# 008-0578-0 Rev. D
Page 1 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
-
MIN
-0.5
TYP
-
MAX
5.0
UNIT
V
Maximum Supply Voltage
VCC
2.375
3.135
2.5
3.3
2.625
3.465
Supply Voltage
VCC
±5%
V
Supply Current
LVPECL
ICC
Maximum Load
-
55
45
88
66
mA
LVDS
-
-20
-40
-40
+70
+85
+125
Operating Temperature
Storage Temperature
TA
-
-
+25
-
°C
°C
TSTG
Frequency Stability
PARAMETER
Frequency Range
LVPECL
SYMBOL
fO
CONDITIONS
-
MIN
TYP
MAX
UNIT
MHz
10 - 220
10 - 220
LVDS
Frequency Stability
Δf/fO
-
20, 25, 50 or 100
-
±ppm
ppm
[Note 1]
Aging
Δf/f25
First Year @ +25°C, nominal VCC
-3
3
1.] Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.
Output Parameters
PARAMETER
Output Type
Output Load
SYMBOL
-
CONDITIONS
MIN
-
TYP
MAX
UNIT
-
LVPECL
-
RL
Terminated to VCC - 2.0V
50
-
Ohms
VOH
V
CC - 1.025
-
VCC - 0.880
PECL Load, -20°C to +70°C
PECL Load, -40°C to +85°C
V
V
VOL
VCC - 1.810
VCC - 1.085
-
-
VCC - 1.620
Output Voltage Levels
VOH
VCC - 0.880
VOL
V
CC - 1.830
-
VCC - 1.555
Output Duty Cycle
Rise and Fall Time
SYM
TR, TF
@ VCC - 1.3V
45
-
-
55
%
@ 20%/80% Levels, RL = 50 Ohms
0.3
0.7
ns
LVDS
100
1.43
1.10
-
Output Type
Output Load
-
-
-
RL
Between Outputs
-
-
-
1.60
-
Ohms
VOH
VOL
Output Voltage Levels
LVDS Load
V
0.90
45
Output Duty Cycle
Differential Output Voltage
Offset Voltage
SYM
VOD
VOS
TR, TF
@ 1.25V
RL = 100 Ohms
55
%
mV
V
247
1.125
-
330
1.25
0.4
454
1.375
0.7
LVDS Load
Rise and Fall Time
@ 20%/80% Levels, RL = 100 Ohms
ns
DOC# 008-0578-0 Rev. D
Page 2 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Output Parameters
PARAMETER
SYMBOL
CONDITIONS
MIN
-
TYP
2
MAX
5
UNIT
ms
Start Up Time
TS
Application of VCC
Enable Function [Standby]
Enable Input Voltage
Disable Input Voltage
Disable Time
VIH
VIL
Pin 1 or 2 Logic '1', Output Enabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '0', Output Disabled
Pin 1 or 2 Logic '1', Output Enabled
Bandwidth 12 kHz - 20 MHz
-
0.7VCC
-
-
-
V
V
-
-
-
-
-
-
0.3VCC
TPLZ
-
200
ns
ms
fs
Enable Time
TPLZ
-
2
Phase Jitter, RMS
Period Jitter, RMS
Period Jitter, pk-pk
tjrms
pjrms
pjpk-pk
300
2.6
25
500
-
-
ps
ps
-
Enable Truth Table
Pin 1 or Pin 2
Logic ‘1’
Open
Pin 4 & Pin 5
Output
Output
Logic ‘0’
High Imp.
Test Circuit
LVPECL
LVDS
Output Waveform
LVPECL or LVDS
DOC# 008-0578-0 Rev. D
Page 3 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
25MHz, LVPECL, VCC = 3.3V, TA = +25°C
100MHz, LVPECL, VCC = 3.3V, TA = +25°C
DOC# 008-0578-0 Rev. D
Page 4 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Performance Data
Phase Noise [typical]
312.50MHz, LVPECL, VCC = 3.3V, TA = +25°C
155.52MHz, LVDS, VCC = 3.3V, TA = +25°C
DOC# 008-0578-0 Rev. D
Page 5 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Electrical Specifications
Phase Noise Tabulated
Typical, VCC = 3.3V, TA = +25°C
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
LVPECL @ 25.00MHz
Phase Noise
LVPECL @ 100.00MHz
Phase Noise
Single Side Band
Single Side Band
@ 10Hz
-82.16
-113.77
-139.77
-156.60
-161.45
-161.31
-159.28
@ 10Hz
-65.65
-100.19
-131.02
-145.49
-150.36
-151.37
-152.11
@ 100Hz
@ 1kHz
@ 100Hz
@ 1kHz
-
dBc/Hz
-
dBc/Hz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 5MHz
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz - 20MHz 192.78
fs
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz - 20MHz 132.20
fs
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
PARAMETER
SYMBOL
CONDITIONS
TYP
UNIT
LVPECL @ 312.20MHz
Phase Noise
LVDS @ 155.52MHz
Phase Noise
Single Side Band
Single Side Band
@ 10Hz
-65.93
-95.92
@ 10Hz
-69.89
-103.42
-130.99
-142.69
-144.46
-144.49
-145.13
@ 100Hz
@ 1kHz
@ 100Hz
@ 1kHz
-128.25
-130.51
-142.82
-142.84
-143.80
-
dBc/Hz
-
dBc/Hz
@ 10kHz
@ 100kHz
@ 1MHz
@ 10MHz
@ 10kHz
@ 100kHz
@ 1MHz
@ 20MHz
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz - 20MHz 208.52
fs
Phase Jitter, RMS
tjrms
Integration Bandwidth 12kHz - 20MHz 383.70
fs
DOC# 008-0578-0 Rev. D
Page 6 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Mechanical Specifications
Package Drawing
Marking Information
Option 1 [3 lines, 7 characters maximum per line]
1. ** - Manufacturing Site Code.
2. D – Date Code. See Table I for codes.
3. O – Output Type; P or E = LVPECL, L or V = LVDS.
4. ST – Frequency Stability/Temperature Code.
[Refer to Ordering Information]
5. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.
6. xxxx – Frequency Code.
CTS**D
633OSTV
● xxxx
3-digits, frequencies below 100MHz
4-digits, frequencies 100MHz or greater
[See document 016-1454-0, Frequency Code Tables.]
CTS**D
633OSTV
● xxxx
Recommended Pad Layout
Option 2 [2 lines, 7 characters maximum per line]
1. O – Output Type; P or E = LVPECL, L or V = LVDS.
2. ST – Frequency Stability/Temperature Code.
[Refer to Ordering Information]
3. V – Voltage Code; 3 = 3.3V, 2 = 2.5V.
4. xxxx – Frequency Code.
3-digits, frequencies below 100MHz
4-digits, frequencies 100MHz or greater
[See document 016-1454-0, Frequency Code Tables.]
5. D – Date Code. See Table I for codes.
[Note: Manufacturing site code must appear on reel
and carton labels.]
633OSTV
● xxxxD
Pin Assignments
Notes
Pin
Symbol
EOH or N.C.
N.C. or EOH
GND
Function
1. JEDEC termination code (e4). Barrier-plating is
nickel [Ni] with gold [Au] flash plate.
2. Reflow conditions per JEDEC J-STD-020; +260°C
maximum, 20 seconds.
1
Enable [std] or No Connect
No Connect or Enable [opt]
Circuit & Package Ground
RF Output
2
3
3. MSL = 1.
4
Output
5
Output
Complimentary RF Output
Supply Voltage
6
VCC
Table I - Date Code
MONTH
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
NOV
DEC
YEAR
2001 2005 2009 2013 2017
2002 2006 2010 2014 2018
2003 2007 2011 2015 2019
2004 2008 2012 2016 2020
A
N
a
B
P
b
p
C
Q
c
D
R
d
r
E
S
e
s
F
T
f
G
U
g
H
V
h
v
J
W
j
K
X
k
x
L
Y
l
M
Z
m
z
n
q
t
u
w
y
DOC# 008-0578-0 Rev. D
Page 7 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Packaging - Tape and Reel
Tape Drawing
Reel Drawing
Notes
1. Device quantity is 1k pieces minimum or 3k pieces maximum per 180mm reel.
2. Complete CTS part number, frequency value and date code information must appear on reel and carton labels.
DOC# 008-0578-0 Rev. D
Page 8 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
Model 633
Very Low Jitter LVPECL or LVDS Clock
Addendum
Additional Developed Frequencies – MHz
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
CODE
CODE
10.000000
19.440000
27.000000
40.000000
44.736000
80.000000
120.000000
133.000000
148.351600
148.500000
100
153.600000
156.253906
167.372800
173.370800
175.000000
178.500000
180.000000
184.320000
1536
156A
167A
1733
1750
1785
1800
1843
194
270
400
447
800
1200
1330
148A
1485
Frequency Codes for Cover Page Table – MHz
FREQUENCY
CODE
FREQUENCY
FREQUENCY
CODE
FREQUENCY
CODE
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
212.500000
CODE
25.000000
50.000000
74.175800
74.250000
250
500
74A
742
100.000000
125.000000
150.000000
155.520000
1000
156.250000
161.132800
187.500000
200.000000
1562
1611
1875
2000
2125
1250
1500
1555
DOC# 008-0578-0 Rev. D
Page 9 of 9
©2017 CTS® Corporation. Information/product(s) subject to change. No warranty that product(s) will meet the stated specifications for customer specific applications or test
equipment. Visit www.ctscorp.com for list of applicable patent(s), more information, or to request a quote.
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