MX828 [CMLMICRO]
CTCSS/DCS/SelCall Processor; CTCSS / DCS /选呼处理器
| 型号： | MX828 |
| 厂家： | 
CML MICROCIRCUITS |
| 描述： | CTCSS/DCS/SelCall Processor |
| 文件： | 总34页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA BULLETIN
CTCSS/DCS/SelCall
Processor
MX828
PRELIMINARY INFORMATION
Features
Applications
• Fast CTCSS Detection
• Radio Systems Requiring Sub-Audible
Signaling
• Full Duplex CTCSS and SelCall
• Full 23/24 Bit DCS Codec
• SelCall Codec
Trunking Control
Selective Calling
Group Calling
• Non Predictive Tone Detection
• Low Power 3.3V/5.0V Operation
• Variable Gain Audio Filter
• Increased Efficiency
Scanning Systems
Trunking Systems
• Programmable:
Tone Decoder
Tone Encoder
Modulator Drivers
Comparator for RSSI
• Pin compatible with reduced function MX818
• Full control via 4-Wire Serial Interface
CTCSS
RADIO
FAST CTCSS
SELCALL
DCS
Tx MOD1
MODULATOR
Tx MOD2
RF
RSSI
DISCRIMINATOR
CARRIER DETECT
TIMER
ANALOG Rx
LEVEL CONTROL
AUDIO FILTER
AUDIO
MSK
AUDIO
SIGNALS
MX828
DTMF
KEYBOARD
DISPLAY
LEVEL & VOLUME
CONTROLS
HOST µC
SERIAL C-BUS:
DATA & CONTROL
(OPTIONAL) MX829
The MX828 is a low power SelCall, CTCSS, and DCS signal processor designed for use in the latest generation of LMR
(Land Mobile Radio) equipment where sub-audible signaling is required for functions such as Trunking Control, Selective
Calling, and Group Calling applications. The MX828 is full duplex and offers many advanced features to assist in the
design of new Sub-Audible and in-band based systems. These include: a programmable tone decoder which may be set
to respond to between 1 and 15 CTCSS or SelCall tones with minimum software intervention, a Fast/Predictive CTCSS
detector that can respond to a single programmed tone in less than 60ms or provide an output if CTCSS tone is present at
the detector input, two high resolution tone encoders that accurately generate CTCSS or SelCall tones, and a full 23/24 bit
DCS encoder and decoder. The MX828 also provides a general purpose timer, a comparator with a programmable
threshold, and a summing amplifier with two adjustable gain blocks to facilitate design integration and reduce part count.
The MX828 may be used with a 3.0 to 5.5 volt supply and is available in the following packages: 24-pin SSOP
(MX828DS), 24-pin SOIC (MX828DW), and 24-pin PDIP (MX828P).
© 1997 MX
•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
2
MX828 PRELIMINARY INFORMATION
CONTENTS
Section
Page
1. Block Diagram.................................................................................................................................. 3
2. Signal List......................................................................................................................................... 4
3. External Components...................................................................................................................... 5
4. General Description......................................................................................................................... 6
4.1 Software Description................................................................................................................................. 7
4.2 8-bit Write Only Registers ........................................................................................................................ 8
4.3 16-bit Write Only Registers ...................................................................................................................... 9
4.4 Write Only Register Description............................................................................................................... 10
4.5 8-bit Read Only Registers....................................................................................................................... 16
4.6 Read Only Register Description............................................................................................................... 16
5. Application Notes............................................................................................................................ 20
5.1 General .................................................................................................................................................... 20
5.2 Transmitters ............................................................................................................................................. 20
5.3 Receiver (CTCSS/SelCall Decoder) ........................................................................................................ 21
5.4 Receiver (CTCSS Fast/Predictive Detector)............................................................................................ 21
5.5 Receiver (DCS Decoder) ......................................................................................................................... 21
5.6 General Purpose Timer (GPT)................................................................................................................. 21
5.7 Full Duplex Modes ................................................................................................................................... 21
6. Performance Specification............................................................................................................. 26
6.1 Electrical Performance............................................................................................................................. 26
6.2 Timing Diagrams...................................................................................................................................... 31
6.3 Packaging ................................................................................................................................................ 32
MX•COM, Inc. reserves the right to change specifications at any time and without notice.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
3
MX828 PRELIMINARY INFORMATION
1. Block Diagram
R7
R6
C3
R2
SUM
OUT
MOD 1
IN
SUM
IN
TX TONE
TX SUB
AUDIO
OUT
RX
AUDIO
OUT
TX AUDIO
OUT
MOD 1
CTCSS TX TONE
GENERATOR
SUMMING
AMP
SELCALL TX TONE
TRIM
TRIM
GENERATOR
-
MOD 1
ENABLE
DCS CODE
GENERATOR
+
23 / 24 bits
V
BIAS
CTCSS / DCS / SELCALL TX
MOD 2
V
SS
V
C4
BIAS
GENERAL PURPOSE
TIMER
MOD 2
ENABLE
C6
V
DD
COMMAND DATA
REPLY DATA
CS
VDD
C - BUS
INTERFACE
AND
CONTROL
LOGIC
AUDIO BPF
R5
6dB
ATTENUATOR
AUDIO RX
RX AMP OUT
IRQ
SERIAL CLOCK
R3
C5
CTCSS / DCS / SELCALL RX
ADC
CTCSS/SELCALL
TONE
DECODER
RX AMP IN
-
SUB AUDIO
L P F
ADC
R4
+
Input from
Demodulator
RX AMP
CTCSS
FAST TONE
DETECTOR
V
DCS
EQUALIZER
FILTER
BIAS
DCS
DECODER
ADC
C7
XTAL/CLOCK
XTAL
COMPARATOR
+
CLOCK
OSCILLATOR
AND
C1
C2
X1
CTCSS
PREDICTIVE
TONE DETECTOR
R1
CBUS
3-bit
DAC
-
TX TONE
A/D CAP1
DIVIDERS
COMPIN
A/D CAP2
COMPOUT
C9
C8
Figure 1: Block Diagram
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
4
MX828 PRELIMINARY INFORMATION
2. Signal List
Pin No.
Name
Type
Description
1
output The inverted output of the on-chip oscillator.
XTAL
2
3
XTAL/CLOCK
SERIAL CLOCK
input
input
The input to the on-chip oscillator, for external Xtal circuit or clock.
The “C-BUS” serial clock input. This clock, produced by the µC, is used for
timing transfer of commands and data to and from the device. (Figure 4).
4
5
COMMAND DATA
REPLY DATA
input
The “C-BUS” serial data input from the µC. Data is loaded into this device
in 8-bit bytes, MSB (B7) first, and LSB (B0) last, synchronized to the
SERIAL CLOCK. (Figure 4).
output The “C-BUS” serial data output to the µC. The transmission of REPLY
DATA bytes is synchronized to the SERIAL CLOCK under the control of the
CS input. This 3-state output is held at high impedance when not sending
data to the µC. (Figure 4).
6
7
input
The “C-BUS” data loading control function: this input is provided by the µC.
Data transfer sequences are initiated, completed or aborted by the CS
signal (Figure 4).
CS
output This output indicates an interrupt condition to the µC by going to a logic "0".
This is a "wire-ORable" output, enabling the connection of up to 8
peripherals to 1 interrupt port on the µC. This pin has a low impedance
pulldown to logic "0" when active and a high-impedance when inactive. An
external pullup resistor is required.
IRQ
The conditions that cause interrupts are indicated in the IRQ FLAG register
and are effective if not masked out by a corresponding bit in the IRQ MASK
register.
8
9
COMPOUT
COMPIN
output The output of the comparator.
input
The input to the comparator.
10
A/D CAP 1
output An internal reference voltage for the CTCSS A/D. Bypassed to VSS with an
external capacitor.
11
A/D CAP 2
output An internal reference voltage for the DCS A/D. Bypassed to VSS with an
external capacitor.
12
13
VSS
Power Negative supply (ground).
output A bias line for the internal circuitry, held at VDD/2. This pin must be
bypassed by a capacitor mounted close to the device pins.
VBIAS
14
15
16
17
18
19
20
21
22
23
24
RX AMP IN
RX AMP OUT
RX AUDIO OUT
TX AUDIO OUT
SUM IN
input
The inverting input to the Rx input amplifier.
output Output of the Rx input amplifier
output Output of the Rx audio filter section.
output Output of the SelCall tone generator.
input
output Output of the audio summing amplifier.
input Input to MOD1 audio gain control.
Input to the audio summing amplifier.
SUM OUT
MOD1 IN
TX SUB AUDIO OUT
MOD1
output Output of the CTCSS or DCS Tx tone generator.
output Output of MOD1 audio gain control.
output Output of MOD2 audio gain control.
MOD2
VDD
Power Positive supply. Levels and voltages are dependent upon this supply. This
pin should be bypassed to VSS by a capacitor.
Table 1: Signal List
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
5
MX828 PRELIMINARY INFORMATION
3. External Components
XTAL
R1
X1
C1
C2
XTAL/CLOCK
VDD
C6
VSS
VDD
VDD
XTAL
1
2
3
4
5
6
24
23
22
21
20
19
18
17
16
15
14
13
MOD2
MOD1
XTAL/CLOCK
SERIAL CLOCK
COMMAND DATA
REPLY DATA
CS
TX SUB AUDIO OUT
MOD1 IN
R6
C3
R2
R5
"C-BUS"
INTERFACE
SUM OUT
SUM IN
MX828
IRQ
7
8
TX AUDIO OUT
COMPOUT
R7
COMPIN
A/D CAP1
A/D CAP2
VSS
RX AUDIO OUT
RX AMP OUT
RX AMP IN
VBIAS
9
R3
C5
10
11
12
C8
C4
R4
C9
Input from
Demodulator
C7
Figure 2: Recommended External Components
R1
R2
R3
1M:
100k:
100k:
±5%
C3
C4
C5
C6
C7
C8
C9
100pF
0.1µF
100pF
0.1µF
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±10%
±10%
±10%
±10%
±10%
±10%
±20%
±20%
R4
R5
R6
R7
C1
C2
Note 2
22k:
Note 2
Note 3
Note 1
Note 1
0.1µF
1.0µF to 3.3µF
22pF
22pF
X1
4.032MHz
±100ppm
Table 2: External Components
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
6
MX828 PRELIMINARY INFORMATION
External Components Notes:
1. R2, R6, R7 and C3 form the gain components for the Summing Amplifier. R6 and R7 should be chosen as
required from the system specification, using the following formula:
R2
R2
Tx Sub Audio Gain = −
Tx Audio Gain = −
R6
R7
2. R3, R4, C5 and C7 form the gain components for the Rx Input Amplifier. R4 should be chosen as required by the
signal level, using the following formula:
R3
Gain = −
R4
C7 x R4 should be chosen so as not to compromise the low frequency performance of this product.
3. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of
VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design
assistance, consult your crystal manufacturer.
4. General Description
The MX828 is a signaling encoder/decoder for use in land mobile radio equipment, see Figure 1. The transmitter section
of the MX828 has independently controllable tone generators for sub-audio (CTCSS) and inband (SelCall) signaling. Also
featured is a DCS code generator, which may be used in place of the CTCSS tone generator.
The receiver section of the MX828 has a fast/predictive CTCSS tone detector which operates in parallel with a DCS
decoder and a CTCSS/SelCall tone decoder. The latter is switchable to perform either CTCSS or SelCall tone decoding of
a user-programmable set of up to 15 tones. In the CTCSS mode it performs a more accurate (but slower) analysis of the
tones detected by the fast/predictive CTCSS tone detector, which is a single detector that is switchable to provide either a
fast response to any CTCSS tone (FAST DETECT mode) or a fast response to a single user-programmed CTCSS tone
(PREDICTIVE mode).
Both the DCS transmit and receive bit rates are fixed at 134.4bps.
Other functions on the MX828 are a comparator with programmable threshold level, a general purpose timer and a
summing amplifier with two adjustable gain blocks, which may be used for two point modulation, for example. All MX828
functions are controlled by an external µC over the “C-BUS” interface, a serial interface designed to reduce interference
levels in radio equipment.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
7
MX828 PRELIMINARY INFORMATION
4.1 Software Description
4.1.1 Command Summary
The following table contains a brief description of all valid Commands. Details follow below.
DATA BYTE(S)
REGISTER NAME
SECTION HEX ADDRESS
COMMAND
READ /
WRITE
BYTE 1
BYTE 2
General Reset
4.4.1
4.4.2
$01
$80
W
W
none
none
none
Sub-Audio Control
Refer to Bit
Description
SelCall
Sub-Audio Status
4.5
$81
R
Refer to Bit
Description
none
none
4.6.1
4.4.3
Sub-Audio Set-Up
$82
$83
W
W
Refer to Bit
Description
CTCSS
TX/ Fast RX
Frequency
Specify Tx or Fast Rx
Frequency per command $80
& $83 Bit descriptions
4.4.10
4.4.11
RX Tone Program
$84
W
1 of 15 possible Registers
Select & Decode Frequencies
DCS Code
4.4.4
4.4.5
4.4.6
4.4.7
$85
$86
$87
$88
W
W
W
W
Byte 3 of 3
Byte 2 of 3
Byte 1 of 3
none
none
none
none
DCS Code
DCS Code
General Control
Refer to Bit
Description
Audio Control
4.4.12
4.4.8
$8A
$8B
$8D
W
W
W
Mod 1
Attenuation
Mod 2
Attenuation
General Purpose
Timer
Refer to Bit
Description
none
SelCall TX
4.4.13
4.4.2
4.4.3
4.4.9
Specify TX SelCall
Frequencies
IRQ Mask
IRQ Flag
$8E
$8F
W
R
Refer to Bit
Description
none
none
4.5
Refer to Bit
Description
4.6.2
Table 3: Command Summary
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
8
MX828 PRELIMINARY INFORMATION
4.1.2 Address/Commands
Instructions and data are transferred, via “C-BUS”, in accordance with the timing information given in Figure 4.
Instruction and data transactions to and from the MX828 consist of an Address/Command (A/C) byte followed by either:
(i)
a further instruction or data (1 or 2 bytes) or
a status or Rx data reply (1 byte)
(ii)
4.2 8-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
$01
$80
$82
GENERAL
RESET
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
SUBAUDIO
TX
TONE
FAST
SELCALL
TX
DCS
RX
SIGNALLING
CONTROL
DECODER DETECT
ENABLE ENABLE
ENABLE
0
0
ENABLE
0
ENABLE
TONE DECODER BANDWIDTH
FAST CTCSS
MODE
SIGNALLING
SET-UP
MSB
LSB
TONE
SUBAUDIO
TX MODE
DCS
DETECT/
PREDICTIVE
DECODER
MODE
BIT 3
BIT 2
BIT 1
BIT 0
23/24
DCS BYTE 3
OPTIONAL
MSB
$85
DCS
BYTE 3
BIT 23
BIT 15
BIT 7
BIT 22
BIT 14
BIT 6
BIT 21
BIT 13
BIT 20
BIT 19
BIT 18
BIT 10
BIT 17
BIT 9
BIT 1
BIT 16
BIT 8
DCS BYTE 2
$86
$87
$88
$8B
DCS
BYTE 2
BIT 12
BIT 11
BIT 3
DCS BYTE 1
DCS
LSB
BYTE 1
BIT 5
BPF
6dB
BIT 4
MSB
DAC
BIT 2
BIT 2
LSB
BIT 0
GENERAL
CONTROL
GENERAL
PURPOSE
TIMER
BPF
BPF
DAC
DAC
BIT 0
GP TIMER
ENABLE
GP TIMER
RE-CYCLE
ENABLE
UN-MUTE
PAD
BIT 1
GENERAL PURPOSE TIMER
MSB
LSB
BIT 0
DCS
IRQ
BIT 7
BIT 6
GP TIMER
IRQ
BIT 5
COMP
BIT 4
COMP
BIT 3
TONE
IRQ
BIT 2
CTCSS
FAST IRQ
MASK
BIT 1
0
$8E
$9C
IRQ
0
0 to 1
1 to 0
MASK
MASK
IRQ MASK
IRQ MASK
MASK
MASK
Reserved for later use
Table 4: 8-bit Write Only Registers
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
9
MX828 PRELIMINARY INFORMATION
4.3 16-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
CTCSS TX/FAST RX FREQUENCY
CTCSS TX/
FAST RX
FREQUENCY (1)
CTCSS TX/
FAST RX
FREQUENCY (2)
RX TONE
PROGRAM
(1)
$83
$84
$8A
$8D
CTCSS (TX)
NOTONE
0
0
MSB
BIT 12
BIT 11
BIT 10
BIT 9
BIT 1
BIT 8
CTCSS TX/FAST RX FREQUENCY
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 0
TONE ADDRESS
TONE FREQUENCY
MSB
LSB
MSB
BIT 3
BIT 2
BIT 1
BIT 5
BIT 0
BIT 11
BIT 10
BIT 9
BIT 1
BIT 1
BIT 1
BIT 8
TONE FREQUENCY
RX TONE
PROGRAM
(2)
LSB
BIT 7
0
BIT 6
0
BIT 4
BIT 3
BIT 3
BIT 3
BIT 2
BIT 0
MOD 1
AUDIO
CONTROL
(1)
MOD 1
MSB
LSB
ENABLE
BIT 4
BIT 2
BIT 0
MOD 2
AUDIO
CONTROL
(2)
0
0
0
MOD 2
MSB
LSB
ENABLE
BIT 4
BIT 2
BIT 0
SELCALL TX TONE
SELCALL TX
(1)
SELCALL
NOTONE
0
MSB
BIT 12
BIT 11
BIT 10
BIT 2
BIT 9
BIT 8
SELCALL TX TONE
SELCALL TX
(2)
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 1
BIT 0
Table 5: 16-bit Write Only Registers
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
10
MX828 PRELIMINARY INFORMATION
4.4 Write Only Register Description
4.4.1 GENERAL RESET (Hex address $01)
The reset command has no data attached to it. It sets the device registers into the specific (all powersaved) states as
listed below:
REGISTER NAME
HEX
ADDRESS
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
D0)
SIGNALING CONTROL
$80
$81
$82
$83
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELCALL & SUB-AUDIO STATUS
SIGNALING SET-UP
CTCSS TX / FAST RX FREQUENCY (1)
CTCSS TX / FAST RX FREQUENCY (2)
RX TONE PROGRAM
RX TONE PROGRAM
DCS BYTE 3
(1)
(2)
$84
$85
$86
$87
$88
$8A
DCS BYTE 2
DCS BYTE 1
GENERAL CONTROL
AUDIO CONTROL
AUDIO CONTROL
GENERAL PURPOSE TIMER
SELCALL TX
(1)
(2)
$8B
$8D
(1)
(2)
SELCALL TX
IRQ MASK
$8E
$8F
IRQ FLAG
X = undefined
Table 6: GENERAL RESET (Hex address $01)
4.4.2 SIGNALING CONTROL Register (Hex address $80)
This register is used to control the functions of the device as described below:
Bit 7 should be set to “1” to enable the CTCSS/DCS subaudio transmitter. The
subaudio Tx type will depend on the state of the SUBAUDIO TX MODE (Bit 1
SIGNALING SET-UP Register $82).
SUBAUDIO TX
ENABLE
(Bit 7)
Bit 6 should be set to “1” to enable the CTCSS/SelCall tone decoder or the DCS
decoder. Note: See Bit 0 for DCS decoder operation.
TONE DECODER
ENABLE
(Bit 6)
Bits 7 and 6 should not both be set to “1” when Bit 0 is set to “1” because the DCS
function is half-duplex only.
When this bit is "1", the FAST CTCSS DETECT or FAST CTCSS PREDICTIVE mode
is enabled, depending upon the setting of FAST CTCSS MODE (Bit 3 SIGNALING
SET-UP Register, $82). When this bit is "0", both FAST CTCSS DETECT and FAST
CTCSS PREDICTIVE tone detectors are disabled.
CTCSS FAST DETECT
ENABLE
(Bit 5)
When this bit is "1" the SelCall transmitter is enabled. When this bit is "0" the SelCall
transmitter is disabled and powersaved.
SELCALL TX
ENABLE
(Bit 2)
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
11
MX828 PRELIMINARY INFORMATION
When this bit is "1", the DCS decoder is enabled. When this bit is "0" the DCS
decoder is disabled.
DCS RX ENABLE
(Bit 0)
The DCS decoder and the subaudio (CTCSS or DCS) transmitter should not be
enabled at the same time.
Reserved for future use. These bits should be set to "0".
(Bits 4, 3, and 1)
Table 7: SIGNALING CONTROL Register (Hex address $80)
4.4.3 SIGNALING SET-UP Register (Hex address $82)
This register is used to define the signaling parameters, as described below:
These four bits set the bandwidth of the CTCSS/SelCall tone decoder according to the
table below:
TONE DECODER
BANDWIDTH
(Bits 7, 6, 5 and 4)
When CTCSS FAST DETECT ENABLE (Bit 5 SIGNALING CONTROL Register, $80)
is "1", this bit selects the FAST CTCSS DETECT or the FAST CTCSS PREDICTIVE
mode, according to the table below:
FAST CTCSS MODE
(Bit 3)
If the CTCSS FAST DETECT ENABLE bit is "0" then both modes are deselected.
When this bit is "1" the CTCSS/SelCall tone decoder is set to detect inband (SelCall)
tones. When this bit is "0" the tone decoder is set to detect subaudio (CTCSS) tones.
TONE DECODER
MODE
(Bit 2)
When this bit is "1" the subaudio transmitter will be set to transmit DCS signals, if
enabled. When this bit is "0" the subaudio transmitter will be set to transmit CTCSS
signals, if enabled.
SUBAUDIO TX MODE
(Bit 1)
When this bit is "1" the DCS transmitter and decoder are configured for a 23-bit code.
When this bit is "0" they are configured for a 24-bit code.
DCS 23/24
(Bit 0)
Table 8: SIGNALING SET-UP Register (Hex address $82)
BANDWIDTH
Bit 7 Bit 6 Bit 5 Bit 4
Will Decode
±1.1%
Will Not Decode
±2.4%
Recommended for CTCSS
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Recommended for CCIR
±1.3%
±2.7%
±1.6%
±2.9%
±1.8%
±3.2%
±2.0%
±3.5%
±2.2%
±3.7%
Recommended for ZVEI
±2.5%
±4.0%
±2.7%
±4.2%
Table 9: TONE DECODER BANDWIDTH
DETECT/PREDICTIVE
Function
DETECT mode
Bit 3
0
1
PREDICTIVE mode
Table 10: FAST CTCSS MODE
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
12
MX828 PRELIMINARY INFORMATION
4.4.4 DCS BYTE 3 Register (Hex address $85)
4.4.5 DCS BYTE 2 Register (Hex address $86)
4.4.6 DCS BYTE 1 Register (Hex address $87)
These three bytes set the code that is transmitted or received in the DCS mode. The LSB bit "0" of the DCS BYTE 1 is
transmitted first and the last bit is the MSB bit 23 of DCS BYTE 3 in the 24-bit mode or bit 22 in the 23-bit mode. See
Table 22 or refer to the latest version of ANSI/TIA/EIA - 603 specification and programming documentation for DCS
standard 23-bit codes.
4.4.7 GENERAL CONTROL Register (Hex address $88)
This register is used to control the functions of the device as described below:
When this bit is "1" the audio band-pass filter is enabled. When this bit is "0" the audio
band-pass filter is disabled (powersaved).
BPF ENABLE
(Bit 7)
When this bit is "1" the audio band-pass filter output is switched to the RX AUDIO OUT
pin. When this bit is "0" the output of the filter is disconnected from RX AUDIO OUT,
which is then in a high impedance state.
BPF UN-MUTE
(Bit 6)
This control, along with BPF ENABLE, allows the filter to power up and settle internally
before switching the output on, to avoid clicks when coming out of powersave.
When this bit is "1" a 6dB attenuator is inserted into the output of the audio band-pass
filter. When this bit is "0" the output of the audio band-pass filter is not attenuated.
BPF 6dB PAD
(Bit 5)
These three bits set the level of the digital to analogue converter that feeds the negative
input of the comparator. The DAC can be set to one of eight levels equally spaced
between VSS and VBIAS, not including VSS, but including VBIAS, i.e. with a 5V supply, the
lowest level would be 312.5mV set by "000" in bits 2, 3 and 4 and the highest level would
be 2.5V set by "111" in bits 2, 3 and 4.
DAC
(Bits 4, 3 and 2)
When this bit goes to a "1" the general purpose timer is restarted and its internal register is
re-loaded from the value specified in the GENERAL PURPOSE TIMER Register (Hex
address $8B). It will then count down from the count held in its internal register. When
this bit is "0" the count down is disabled and the last pre-programmed value is retained in
the timer's internal register.
TIMER ENABLE
(Bit 1)
When this bit is "1" the general purpose timer will re-load its internal register from the
value specified in the GENERAL PURPOSE TIMER Register (Hex Address $8B) when the
count in the internal register reaches zero (i.e. the timeout has expired). It then restarts the
count down, so that the timer continuously cycles.
TIMER RE-CYCLE
(Bit 0)
When this bit is "0" the general purpose timer will stop when the count in the internal
register reaches zero (i.e. the timeout has expired). The timer can only be restarted by
reloading a value into the GENERAL PURPOSE TIMER Register (Hex address $8B).
If this bit is switched from "1" to "0" while the timer is enabled then the timer will complete
the present count before stopping.
Table 11: GENERAL CONTROL Register (Hex address $88)
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
13
MX828 PRELIMINARY INFORMATION
4.4.8 GENERAL PURPOSE TIMER (GPT) Register (Hex address $8B)
This register is used to preset the value of a countdown timer. Once a binary value has been loaded into this register, it
will be automatically transferred to an internal register within the timer. This internal register is then decremented at each
count interval (1ms) until it reaches zero. On reaching zero, the GPT IRQ FLAG in the IRQ FLAG Register (Hex address
$8F) is set to "1". An interrupt is generated on the IRQ pin if the GPT IRQ MASK in the IRQ MASK Register (Hex address
$8E) is "1" otherwise the GPT IRQ FLAG remains set to "1" and no interrupt is generated.
When the internal register has reached a count of zero, the action of the timer depends on the setting of the TIMER RE-
CYCLE bit in the GENERAL CONTROL Register (Hex address $88). If the TIMER RE-CYCLE bit is "1" then the timer will
re-load the countdown value from the GENERAL PURPOSE TIMER Register and restart the countdown from this value.
If the TIME RE-CYCLE bit is "0" then the timer will stop and no further action or timer interrupts will take place until the
GENERAL PURPOSE TIMER Register is re-loaded. Loading the GENERAL PURPOSE TIMER with "0" will cause the
timer circuitry to be disabled (i.e. powersaved).
4.4.9 IRQ MASK Register (Hex address $8E)
This register is used to control the interrupts (IRQs) as described below:
Reserved for future use. These should be set to "0".
(Bits 7 and 1)
When this bit is set to "1" it enables an interrupt that occurs when GPT IRQ FLAG (Bit 6, IRQ
FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is masked.
GPT IRQ MASK
(Bit 6)
When this bit is set to "1" it enables an interrupt that occurs when the comparator output
goes from "0" to "1". When this bit is set to "0" the interrupt is masked.
COMP 0 to 1
IRQ MASK
(Bit 5)
When this bit is set to "1" it enables an interrupt that occurs when the comparator output
goes from "1" to "0". When this bit is set to "0" the interrupt is masked.
COMP 0 to 1
IRQ MASK
(Bit 4)
When this bit is set to "1" it enables an interrupt that occurs when the TONE IRQ FLAG (Bit
3, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the interrupt is
masked.
TONE IRQ MASK
(Bit 3)
When this bit is set to "1" it enables an interrupt that occurs when the CTCSS FAST IRQ
FLAG (Bit 2, IRQ FLAG Register, $8F) changes from "0" to "1". When this bit is "0" the
interrupt is masked.
CTCSS FAST IRQ MASK
(Bit 2)
When this bit is set to "1" it enables an interrupt that occurs when the DCS DECODE/NO
DECODE FLAG (Bit 7, SELCALL & SUB-AUDIO STATUS Register $81) changes state.
When this bit is set to "0" the interrupt is masked.
DCS IRQ MASK
(Bit 0)
Table 12: IRQ MASK Register (Hex address $8E)
4.4.10 CTCSS TX/FAST RX FREQUENCY Register (Hex address $83)
This is a 16-bit register. Byte (1) is sent first. When the CTCSS fast detector is enabled, the bits 0 to 12 define the
receive frequency which the fast predictive detector is looking for according to the formula below:
fXTAL (Hz)
A =
16 xfTONE (Hz)
where A is the binary number programmed into the 13 bits.
When the CTCSS transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted CTCSS tones according
to the formula above.
When the fast detector and the transmitter are both enabled, bits 0-12 define the receive frequency which the fast
predictive detector is looking for and the frequency of the transmitted tone according to the formula above. (i.e. Tx Tone =
predictive tone).
When Bit 7 in byte (1) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A"
programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the Tx
into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SUBAUDIO Tx and the CTCSS
FAST DETECT.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
14
MX828 PRELIMINARY INFORMATION
4.4.11 RX TONE PROGRAM Register (Hex address $84)
This is a 16-bit register. Byte (1) is sent first. The two bytes are used to program the center frequencies of up to 15 tones
in either the audio or sub-audio band that will be decoded by the receiver.
Each tone is identified by its address in bits 7, 6, 5 and 4 of byte (1). The remaining 12 bits contain the data representing
the tone frequency according to the formula below. If a tone is not required the 12 bits should be set to zero.
Byte 1
Byte 2
Bit Bit Bit Bit
Bit
3
Bit
2
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
5
4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
<------------------------ N -----------------------> <----------------------- R ------------------------>
N is the binary representation of the
following decimal number (n):
R is the nearest 6-bit binary
representation of (r), where:
SUBAUDIO (CTCSS)
SUBAUDIO (CTCSS)
n = INT (948982 x fTONE / fXTAL
)
r = ((237245/fXTAL) - (n/(4 x fTONE))) x 8400
INBAND (SELCALL)
n = INT (83036 x fTONE / fXTAL
INBAND (SELCALL)
)
r = ((20759/fXTAL) - (n/(4 x fTONE))) x 96000
Table 13: RX TONE PROGRAM Register (Hex address $84)
Example: To program 100Hz when using the recommended 4.032MHz Xtal in SUBAUDIO (CTCSS) mode.
n = INT (948982 x 100 / 4.032 x 10^6)
=
INT (23.536) = 23
N = 010111 (binary)
r
=
=
((237245 / 4.032 x 106) - (23 / (4 x 100))) x 8400
11.26
R = 11 (rounding up if exactly halfway)
001011 (binary)
=
Thus the 12-bit code is 010111001011
The Hex address represented by bits 7, 6, 5 and 4 in byte (1) is used as the code to indicate which tone has been
decoded. This code appears in bits 3, 2, 1 and 0 of the SELCALL and SUB-AUDIO STATUS Register (Hex address $81).
The 15 programmed tones use Hex addresses $0 - $E.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
15
MX828 PRELIMINARY INFORMATION
4.4.12 AUDIO CONTROL Register (Hex address $8A)
This is a 16-bit register. Byte (1) is sent first. Bits 0 - 5 of the first byte in this register are used to set the attenuation of
the Modulator 1 amplifier and bits 0 - 5 of the second byte in this register are used to set the attenuation of the Modulator
2 amplifier, according to Table 14.
BYTE 1
Mod. 1 Attenuation
BYTE 2
0 Mod. 2 Attenuation
5
0
4
3
2
1
0
5
0
4
3
2
1
X
X
X
X
X
X
X
X
X
X
Disabled (VBIAS
>40dB
12.0dB
11.6dB
11.2dB
10.8dB
10.4dB
10.0dB
9.6dB
9.2dB
8.8dB
8.4dB
8.0dB
7.6dB
7.2dB
6.8dB
6.4dB
6.0dB
5.6dB
5.2dB
4.8dB
4.4dB
4.0dB
3.6dB
3.2dB
2.8dB
2.4dB
2.0dB
1.6dB
1.2dB
0.8dB
0.4dB
0dB
)
Disabled (VBIAS
>40dB
6.0dB
5.8dB
5.6dB
5.4dB
5.2dB
5.0dB
4.8dB
4.6dB
4.4dB
4.2dB
4.0dB
3.8dB
3.6dB
3.4dB
3.2dB
3.0dB
2.8dB
2.6dB
2.4dB
2.2dB
2.0dB
1.8dB
1.6dB
1.4dB
1.2dB
1.0dB
0.8dB
0.6dB
0.4dB
0.2dB
0dB
)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X = don't care
When this bit is "1" the MOD1 attenuator is enabled.
When this bit is "0" the MOD1 attenuator is disabled (i.e. powersaved).
MOD1 ENABLE
(Bit 5, first byte)
When this bit is "1" the MOD2 attenuator and the SUMMING AMP are enabled.
When this bit is "0" they are both disabled (i.e. powersaved).
MOD2 ENABLE
(Bit 5, second
byte)
Reserved for future use. These should be set to "0".
(Bits 7 and 6, first
and second bytes)
Table 14: AUDIO CONTROL Register (Hex address $8A)
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
16
MX828 PRELIMINARY INFORMATION
4.4.13 SELCALL TX Register (Hex address $8D)
This is a 16-bit register. Byte (1) is sent first.
When the SELCALL transmitter is enabled, bits 0 to 12 control the frequency of the transmitted SELCALL tones according
to the formula below:
fXTAL (Hz)
A =
4 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A"
programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming bits 0 through 12 to "0" places
the Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SELCALL Tx.
4.5 8-bit Read Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
RX TONE
SELCALL &
SUB-AUDIO
STATUS
DCS
CTCSS
FAST
$81
$8F
DECODE/
NO DECODE
0
TONE
DECODE
COMP
MSB
BIT 3
TONE
IRQ
LSB
BIT 0
DCS
IRQ
TONE
BIT 2
CTCSS FAST
IRQ
BIT 1
0
GP TIMER
IRQ
COMP
0 to 1
IRQ FLAG
0
1 to 0
FLAG
IRQ FLAG
IRQ FLAG
FLAG
FLAG
FLAG
Table 15: 8-bit Read Only Registers
4.6 Read Only Register Description
4.6.1 SELCALL and SUB-AUDIO STATUS Register (Hex address $81)
This register is used to indicate the status of the device as described below:
When the DCS decoder is enabled this bit is continuously updated with the result. A "1"
indicates a successful decode (with 3 or less errors). A "0" indicates a failure to decode.
DCS DECODE/
NO DECODE
(Bit 7)
When Bit 5 in the SIGNALING CONTROL Register and Bit 3 in the SIGNALING SET-UP
Register are set to enable FAST CTCSS DETECT mode, this bit will be set to "1" if a periodic
tone is detected. If no periodic tone is detected this bit will be "0".
CTCSS FAST TONE
(Bit 6)
When bits 5 and 3 are set to enable FAST CTCSS PREDICTIVE mode, this bit will be set to "1"
if a periodic tone that matches the frequency programmed in the CTCSS TX/FAST RX
FREQUENCY Register is detected. If no match is found this bit will be "0".
When Bit 5 in the SIGNALING CONTROL Register is set to "0" this bit will be "0".
Reserved for future use. This will be set to "0" but should be ignored by the user's software.
(Bit 5)
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
17
MX828 PRELIMINARY INFORMATION
This bit indicates the status of the tone decoder. A "1" indicates a tone has been detected
(TONE DECODE) and a "0" indicates the loss of the tone (NOTONE).
TONE DECODE
(Bit 4)
TONE DECODE means that a tone has been decoded and its characteristics are defined by the
bandwidth (See SIGNALING SET-UP Register bits 7, 6, 5 and 4) and the RX TONE number
(See SELCALL and SUB-AUDIO STATUS Register bits 3, 2, 1 and 0).
When Bit 6 in the SIGNALING CONTROL Register is set to "0" the TONE DECODE bit 4 will be
set to "0".
Identification of a valid tone which is not in the pre-programmed list of up to 15 tones will cause
the decoder to move to the TONE DECODE state with the RX TONE address of "1111" in bits 3,
2, 1 and 0; indicating a valid, but unrecognized, tone. Loss of tone, will cause the NOTONE
timer to be started. If loss of tone continues for the duration of the timeout period, then the
decoder will move to NOTONE state and the identification of pre-programmed tones will start
again.
These four bits hold a Hex number from $0 to $F. Numbers $0 to $E represent the address of
the tone decoded according to the tones programmed in the RX TONE PROGRAM Register,
$84. The Hex number $F indicates the presence of any tone that is not described by
DECODER BANDWIDTH (Bits 7, 6, 5 and 4, SIGNALING SET-UP Register, $82) and
FREQUENCY (Bits 11 - 0, RX TONE PROGRAM Register, $84).
RX TONE
(Bits 3, 2, 1 and 0)
Table 16: SELCALL and SUB-AUDIO STATUS Register (Hex address $81)
4.6.2 IRQ FLAG Register (Hex address $8F)
This register is used to indicate when the device requires attention as below:
Reserved for future use. These will be set to "0" but should be ignored by user's software.
(Bits 7 and 1)
When the general purpose timer has reached zero in its internal register, this bit will be set to "1"
to indicate the timeout has expired. This bit is cleared to "0" by a read of the IRQ FLAG Register
(Hex address $8F).
GPT IRQ FLAG
(Bit 6)
When the comparator output goes from "0" to "1" (i.e. when the input voltage is above the DAC
output voltage) this bit will be set to "1" and an interrupt generated (if bit 5 of the IRQ MASK
Register $8E is set to "1"). This bit is set to "0" when the IRQ FLAG Register $8F is read.
COMP 0 to 1
IRQ FLAG
(Bit 5)
When the comparator output goes from "1" to "0" this bit will be set to "1" and an interrupt
generated (if bit 4 of the IRQ MASK Register $8E is set to "1"). This bit is set to "0" when the IRQ
FLAG Register $8F is read.
COMP 1 to 0
IRQ FLAG
(Bit 4)
When RX TONE DECODE (Bit 4, SELCALL and SUB-AUDIO STATUS Register, $81) changes
state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex
address $8F).
TONE IRQ FLAG
(Bit 3)
When CTCSS FAST TONE (Bit 6, SELCALL and SUB-AUDIO STATUS Register, $81) changes
state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex
address $8F).
CTCSS FAST IRQ
FLAG
(Bit 2)
When DCS DECODE/NO DECODE (Bit 7 SELCALL and SUB-AUDIO STATUS Register, $81)
changes state this bit will be set to "1". This bit is cleared to "0" by a read of the IRQ FLAG
Register (Hex address $8F).
DCS IRQ FLAG
(Bit 0)
Table 17: IRQ FLAG Register (Hex address $8F)
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
18
MX828 PRELIMINARY INFORMATION
The flow chart shows the following modes of operation for the example below:
1. Decode
)
2. Decode and Fast Detect
3. Decode & Fast Predictive
4. Transmit, e.g. Tx = 100Hz
) e.g. Address 3 = 100Hz, bandwidth = ±2.7%, interrupt enabled
)
Note: $8X is the Hex address/command.
Power Up
Clear registers $01
Tx
Rx or Tx?
Rx
Program 100Hz
into address 3
$84 (1) = 00110101
$84 (2) = 11001011
Program Tx Tone
Generator to 100Hz
$83 (1) = 00001001
$83 (2) = 11011000
Decoder or
Decoder & Fast
Predictive
?
Decoder & Fast Predictive
Enable Tx
$80 = 10000000
Program bandwidth
to 2.7% &
_
+
Fast Predictive
$82 = 11111000
Decoder
Program bandwidth
_
+
to 2.7%
$82 = 11110000
Program Fast Rx
Frequency to 100Hz
$83(1) = 00001001
$83(2) = 11011000
Decoder or
Decoder & Fast
Detector
Decoder & Fast Detect
?
Decoder
Enable IRQ masks
(optional)
Enable IRQ mask
(optional)
$8E = 00001100
$8E = 00001000
Enable Decoder &
Fast Detect/Predictive
$80 = 01100000
Enable Decoder
$80 = 01000000
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
19
MX828 PRELIMINARY INFORMATION
The flow chart shows the decoder, fast detect/fast predictive and transmitter enabled with the following example.
1. Tx tone generator = 100Hz
2. Decoder programmed with 100Hz in address 3
3. Bandwidth setting = ±2.7%
4. Interrupt enabled
Note: $8X is the Hex address/command.
Power Up
Clear registers $01
Program Tx/Fast Rx
Frequency to 100Hz
$83 (1) = 00001001
$83 (2) = 11011000
Program 100Hz into
address 3
$84 (1) = 00110101
$84 (2) = 11001011
Fast
Detect
or
Fast
Fast Predictive
Predictive
?
Fast Detect
Program bandwidth
to ± 2.7% &
Fast Predictive
$82 = 11111000
Program bandwidth
to ± 2.7%
$82 = 11110000
Enable IRQ mask
(optinal)
$8E = 00001100
Enable decoder, Tx &
Fast Detect/Predictive
$80 = 11100000
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
20
MX828 PRELIMINARY INFORMATION
5. Application
5.1 General
The MX828 is intended for use in radio systems where signaling is required for functions such as trunking, control,
selective calling or group calling.
The CTCSS fast/predictive detector is useful for the detection of occupied channels indicating either the presence of any
sub-audio tone, or range of tones, depending if it is set in fast detect or predictive mode. This will increase the efficiency
of scanning and trunking systems, reducing the average time allocated to assessing each channel.
The facility to decode any of up to 15 programmed tones allows the use of tones for various signaling functions such as
masking a free channel or identifying sub groups within a user's groups.
Adjustable decoder bandwidths permit certainty and signal to noise performance to be traded when congestion or range
limits the system performance.
5.2 Transmitters
5.2.1 CTCSS
The CTCSS transmitter is enabled with Bit 7 in the SIGNALING CONTROL Register ($80) and bit 1 in the SIGNALING
SET UP Register ($82).
The Tx frequency is set using Bit 0 to Bit 12 in the CTCSS TX/FAST RX FREQUENCY Register ($83) using the formula
below:
fXTAL (Hz)
A =
16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A"
programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the Tx
into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SUBAUDIO Tx and the CTCSS
FAST DETECT (Bits 7 and 5 in the SIGNALING CONTROL Register $80).
5.2.2 The SelCall transmitter
The SelCall transmitter is enabled with Bit 2 in the SIGNALING CONTROL Register ($80).
The Tx frequency is set using Bit 0 to Bit 12 in the SELCALL TX Register ($8D) using the formula below:
fXTAL (Hz)
A =
4 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the number "A"
programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0 to 12 to "0" puts the
SelCall Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling the SELCALL TX
ENABLE (Bit 2 in the SIGNALING CONTROL Register $80).
5.2.3 DCS Transmitter
The DCS transmitter is enabled with Bit 7 in the SIGNALING CONTROL Register ($80) and bit 1 in the SIGNALING SET
UP Register ($82).
The Tx data is set in the DCS BYTE 3, DCS BYTE 2 and DCS BYTE 1 Registers ($85, $86 and $87).
Note: The DCS transmitter produces an inverted output. When the signal is fed through the summing amp, in an inverted
configuration, the correct polarity of the DCS signal will be restored (The MOD1 and MOD2 amplifier blocks do not invert).
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
21
MX828 PRELIMINARY INFORMATION
5.3 Receiver (CTCSS/SelCall Decoder)
The CTCSS/SelCall decoder should first be set up according to the desired characteristics. This entails setting the TONE
DECODER MODE Bit 2 of the SIGNALING SET UP Register ($82), and setting the TONE decoder bandwidth in the
SIGNALING SET-UP Register ($82), also programming the center frequencies of the desired tones in the RX TONE
PROGRAM Register ($84). (It can hold up to 15 different tones). Any tone can be in any location. When the device is
decoding, the tones are scanned in the sequence of their location, i.e. $0 first and $E last. Once a tone is detected the
remaining tones are not checked. Therefore if two tones are close enough in frequency for their bandwidths to overlap
then the one in the lowest location will be detected.
The TONE IRQ MASK in the IRQ MASK Register ($8E) should also be set as required.
The TONE DECODER ENABLE in the SIGNALING CONTROL Register ($80) should then be set to "1". While in the
CTCSS/SelCall decoder mode the fast/predictive detector may be enabled (see below). (Bit 5 in the SIGNALING
CONTROL Register $80).
When the CTCSS/SelCall decoder detects a change in its present state an IRQ will be generated and Bit 3 of the IRQ
FLAG Register ($8F) will indicate this.
The change that occurred can be read from Bit 4 of the SELCALL and SUB-AUDIO STATUS Register ($81) and if a tone
is indicated by this bit then the number of that tone can be read from Bits 3, 2, 1 and 0 of the same register.
5.4 Receiver (CTCSS Fast/Predictive Detector)
This is used for detecting, in the fastest possible time, that sub-audio tones are present on the Rx channel. Response time
is optimized for speed at the expense of frequency resolution.
It is enabled using Bit 5 of the SIGNALING CONTROL Register ($80). It has an IRQ which may be unmasked with Bit 2
of the IRQ MASK Register ($8E). The FAST CTCSS MODE DETECT/PREDICTIVE Bit 3 in the SIGNALING SET-UP
Register ($82) allows for one of two alternatives in the FAST mode. In DETECT mode it will detect any periodic tone in
the sub-audio band and when in PREDICTIVE mode it will detect specific tones determined by the frequency set in the
CTCSS TX/FAST RX FREQUENCY Register ($83) and the fixed PREDICTIVE mode bandwidth. Successful detection is
indicated by the CTCSS FAST IRQ FLAG Bit 2 in the IRQ FLAG Register ($8F), and the CTCSS FAST TONE Bit 6 in the
SELCALL and SUB-AUDIO STATUS Register ($81).
5.5 Receiver (DCS Decoder)
The incoming signal is matched with the DCS code programmed into the DCS BYTE 1/2/3 Registers. When the DCS
decoder is enabled, the DCS DECODE/NO DECODE FLAG in Bit 7 of the SELCALL and SUB-AUDIO STATUS Register
($81) will be set if the decode is successful (3 or fewer errors). A ''0" flag indicates a failure to decode. This flag is
updated for every bit of the incoming signal.
In order to detect the DCS turn-off code (134Hz) the CTCSS tone decoder should also be enabled and programmed with
this value. Once detected, this will cause a CTCSS tone decoder interrupt, the receiver audio output should then be
muted.
5.6 General Purpose Timer (GPT)
This may be used in conjunction with the CTCSS/SelCall decoder to form part of the decode algorithm or as a timer for
any other purpose. It has an 8-bit value in the GENERAL PURPOSE TIMER Register ($8B) set in units of 1msec, an IRQ
FLAG in Bit 6 of the IRQ FLAG Register ($8F) and an IRQ MASK in Bit 6 of the IRQ MASK Register ($8E).
5.7 Full Duplex Modes
Although the device is specified as half duplex, the only functions that must operate as such are:
DCS Tx
or
or
or
DCS Rx
DCS Tx
CTCSS Tx
CTCSS decode
SELCALL decode
All other functions are totally independent and therefore a full duplex CTCSS or full duplex SELCALL along with many
other combinations are possible.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
22
MX828 PRELIMINARY INFORMATION
5.7.1 Tx / Fast Rx Tone Table : CTCSS
The following table lists the commonly used CTCSS tones and the corresponding values for programming the transmitter
frequency / fast predictive frequency register (Hex address $83).
Freq.
(Hz)
Byte 1 Byte 2
Freq.
(Hz)
Byte 1 Byte 2
Freq.
(Hz)
Byte 1 Byte 2
(hex)
E
(hex)
B1
34
(hex)
8
(hex)
93
(hex)
5
(hex)
49
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
E
8
49
5
2F
1B
2
D
D
C
C
B
B1
3B
C9
5A
EF
87
8
1
5
7
BC
78
5
7
4
EF
D6
C4
AC
83
7
36
4
6
F7
BC
80
4
B
6
4
B
1F
C2
62
6
4
A
6
48
4
5D
4C
37
A
6
29
4
A
1B
D8
83
6
12
4
9
5
DD
AA
79
4
12
9
5
3
EF
E0
9
2F
E0
5
3
8
5
5D
Table 18: Tx/Fast Rx Tone Table CTCSS
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
23
MX828 PRELIMINARY INFORMATION
5.7.2 Rx Tone Program Tables : CTCSS
The following table lists the commonly used CTCSS tones together with the values for programming the “RX TONE
PROGRAM” register (Hex address $84).
Note: The values for byte 1 and 2 below apply to tone address 0 only. These values will vary depending on the location
they are programmed into.
Freq.
(Hz)
Byte 1 Byte 2
Freq.
(Hz)
Byte 1 Byte 2
Freq.
(Hz)
Byte 1 Byte 2
(hex)
3
(hex)
D8
9
(hex)
6
(hex)
C0
D1
10
50
C0
2
(hex)
A
(hex)
C9
8
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
4
6
B
4
1B
4E
83
94
CB
2
7
B
44
83
8A
C9
6
4
7
B
4
7
B
4
8
B
4
8
44
86
C9
C
C
C
C
D
D
D
E
5
8
46
C3
41
48
89
8
5
14
4C
87
94
CB
7
8
5
9
5
9
48
82
C6
B
5
9
5
9
6
A
A
A
E
88
C7
6
45
82
84
C2
E
6
Table 19: Rx Tone Program Tables : CTCSS
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
24
MX828 PRELIMINARY INFORMATION
5.7.3 Tx Tone Program Table : SelCall
The following two tables list commonly used SelCall tonesets together with the values for programming the ‘SELCALL TX’
register ($8D).
EEA
CCIR
ZVEI 1
ZVEI 2
Freq.
(Hz)
Byte 1
(hex)
Byte 2
(hex)
Freq.
(Hz)
Byte 1
(hex)
Byte 2
(hex)
Freq.
(Hz)
Byte 1
(hex)
Byte 2
hex)
Freq.
(Hz)
Byte 1
(hex)
Byte 2
(hex)
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
01
03
03
03
02
02
02
02
02
02
03
04
01
03
01
FD
81
4A
17
E6
B9
8F
67
41
1E
BB
3C
C1
F9
DE
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
01
03
03
03
02
02
02
02
02
02
01
04
01
03
01
FD
81
4A
17
E6
B9
8F
67
41
1E
A4
3C
C1
F9
DE
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
01
03
03
03
02
02
02
02
01
01
01
04
04
04
01
A4
B7
65
1A
D0
93
5C
27
F8
CA
68
DC
0F
73
84
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
885
01
03
03
03
02
02
02
02
01
01
04
04
04
05
04
A4
B7
65
1A
D0
93
5C
27
F8
CA
73
810
DC
0F
CA
0F
2247
991
2247
991
970
740
885
680
2110
2110
2600
970
Table 20: Tx Tone Program Table : SelCall
5.7.4 Rx Tone Program Table : SelCall
The following two tables list commonly used SelCall tonesets together with the values for programming the ‘RX TONE
PROGRAM’ register ($84) in each Tone Address location as shown.
EEA
CCIR
ZVEI 1
ZVEI 2
Tone
Address
Freq.
(Hz)
Byte 1
(hex)
Byte 2
(hex)
Freq.
(Hz)
Byte 1
(hex)
Byte 2
(hex)
Freq.
(Hz)
Byte 1
(hex)
Byte 2
(hex)
Freq
(Hz)
Byte 1
(hex)
Byte 2
(hex)
0
1
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
1055
930
A
A
C3
D
1981
1124
1197
1275
1358
1446
1540
1640
1747
1860
2400
930
A
A
C3
D
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
2800
810
C
44
53
D2
83
E
2400
1060
1160
1270
1400
1530
1670
1830
2000
2200
885
C
44
53
D2
83
E
15
26
36
46
57
67
78
88
99
A5
B4
CB
D5
EA
15
26
36
46
57
67
78
88
99
AC
B4
CB
D5
EA
15
25
36
47
57
68
79
8A
9B
AE
B4
C4
D4
ED
15
25
36
47
57
68
79
8A
9B
A4
B4
C3
D3
E4
2
3
85
D1
4D
CB
4B
CD
84
51
C4
83
A
85
D1
4D
CB
4B
CD
84
44
C4
83
A
4
5
C8
86
49
42
43
46
14
D8
86
45
C8
86
49
42
43
86
14
C8
80
D8
6
7
8
9
10
11
12
13
14
810
2247
991
2247
991
970
740
885
680
2110
C5
2110
C5
2600
970
Table 21: Rx Tone Program Table : SelCall
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
25
MX828 PRELIMINARY INFORMATION
5.7.5 DCS Code Table
The following table gives a list of DCS codes together with the corresponding values (in Hex) which should be
programmed into the DCS BYTE registers for a 23-bit DCS sequence.
DCS
Code
DCS
Byte 3
($85)
DCS
Byte 2
($86)
DCS
Byte 1
($87)
DCS
Code
DCS
Byte 3
($85)
DCS
Byte 2
($86)
DCS
Byte 1
($87)
023
025
026
031
032
043
047
051
054
065
071
072
073
074
114
115
116
125
131
132
134
143
152
155
156
162
165
172
174
205
223
226
243
244
245
251
261
263
265
271
306
311
76
6B
65
51
5F
5B
0F
7C
6F
5D
67
69
2E
74
35
72
7C
07
3D
33
2E
37
1E
44
4A
6B
31
05
18
6E
68
7B
45
1F
58
62
17
5E
43
79
0C
38
38
78
D8
F8
58
68
D8
A8
48
18
98
38
68
78
E8
B8
18
B8
38
98
D8
A8
C8
D8
78
C8
D8
F8
B8
98
E8
08
B8
A8
F8
78
78
88
C8
48
F8
D8
13
15
16
19
1A
23
27
29
2C
35
39
3A
3B
3C
4C
4D
4E
55
59
5A
5C
63
6A
6D
6E
72
75
7A
7C
85
93
96
A3
A4
A5
A9
B1
B3
B5
B9
C6
C9
315
331
343
346
351
364
365
371
411
412
413
423
431
432
445
464
465
466
503
506
516
532
546
565
606
612
624
627
631
632
654
662
664
703
712
723
731
732
734
743
754
6C
23
29
3A
0E
68
2F
15
77
79
3E
4B
6C
62
7B
27
60
6E
3C
2F
41
0E
19
0C
5D
67
0F
01
72
7C
4C
24
39
22
0B
39
1E
10
0D
14
20
68
E8
78
98
B8
58
08
88
69
C9
99
99
59
F9
89
E9
B9
19
69
89
B9
39
E9
79
99
19
59
F9
89
29
39
79
39
B9
D9
89
49
E9
A9
D9
F9
CD
D9
E3
E6
E9
F4
F5
F9
09
0A
0B
13
19
1A
25
34
35
36
43
46
4E
5A
66
75
86
8A
94
97
99
9A
AC
B2
B4
C3
CA
D3
D9
DA
DC
E3
EC
Table 22: DCS Code Table
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
26
MX828 PRELIMINARY INFORMATION
6. Performance Specification
6.1 Electrical Performance
6.1.1 Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
General
Min.
-0.3
-0.3
Max.
7.0
Units
Supply (VDD - VSS)
V
V
Voltage on any pin to VSS
Current
VDD + 0.3
VDD
-30
-30
-20
30
30
20
mA
mA
mA
VSS
Any other pin
DW / P Package
Total Allowable Power Dissipation at TAMB = 25°C
Derating above 25°C
Storage Temperature
Operating Temperature
DS Package
800
13
mW
mW/°C
°C
-55
-40
125
85
°C
Total Allowable Power Dissipation at TAMB = 25°C
Derating above 25°C
Storage Temperature
Operating Temperature
550
9
mW
mW/°C
°C
-55
-40
125
85
°C
6.1.2 Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Min.
3.0
Max.
5.5
Units
V
Supply (VDD - VSS)
Operating Temperature
-40
85
°C
Xtal Frequency
4.0315968
4.0324032
MHz
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
27
MX828 PRELIMINARY INFORMATION
6.1.3 Operating Characteristics
For the following conditions unless otherwise specified:
Xtal Frequency = 4.032MHz
Audio Level 0dB ref. = 308 mVRMS at 1kHz
VDD = 3.3V to 5.0V, TAMB= 25°C, TOP = -40°C to 85°C
Composite Signal = 308 mVRMS at 1kHz + 75mVRMS Noise + 31 mVRMS Sub-Audio Signal
Noise Bandwidth = 5kHz Band Limited Gaussian
Notes
Min.
Typ.
Max.
Units
DC Parameters
VDD = 3.3V
IDD
All Powersaved
2
2
0.5
1.7
1.0
2.5
mA
mA
FAST DETECT Enabled
Rx Operating
DCS, FAST DETECT and CTCSS or SelCall
Tx Operating
2
3.0
4.5
mA
DCS or SelCall or SUB AUDIO
DCS and SelCall
2
2
1.5
2.5
3.0
4.0
mA
mA
VDD = 5.0V
IDD
All Powersaved
1, 2
1, 2
1.0
3.0
1.5
4.5
mA
mA
FAST DETECT Enabled
Rx Operating
DCS, FAST DETECT and CTCSS or SelCall
Tx Operating
1, 2
5.5
7.5
mA
DCS or SelCall or SUB AUDIO
DCS and SelCall
1, 2
1, 2
4.5
5.0
6.0
6.5
mA
mA
"C-BUS" Interface
Input Logic "1"
70%
-1.0
VDD
VDD
µA
Input Logic "0"
30%
1.0
Input Leakage Current
Input Capacitance
Output Logic "1"
Output Logic "0"
"Off" State Leakage Current
AC Parameters
TONE Decoder
Sensitivity
Logic "1" or "0"
7.5
pF
IOH = 120µA
IOL = 360µA
VOUT = VDD
90%
VDD
VDD
µA
10%
10
6
5
Pure Tone
-26.0
dB
CTCSS
Response Time
De-response Time
Frequency Range
SelCall
Composite Signal
Composite Signal
140
145
ms
ms
Hz
60
253
Response Time
De-response Time
Good Signal
Good Signal
14
22
ms
ms
Hz
625
3000
Frequency Range
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
28
MX828 PRELIMINARY INFORMATION
DCS Decoder
Bit-Rate Sync Time
Sensitivity
2
edges
mVP-P
1
5
58
60
60
116
253
253
CTCSS Detector - Fast Detect
Sensitivity
Pure CTCSS Tone
Composite Signal
-26.0
56.0
dB
ms
Hz
Response Time
Frequency Range
CTCSS Detector - Fast Predictive
Sensitivity
Pure CTCSS Tone
Composite Signal
5
7
-26.0
37.0
dB
ms
Hz
Hz
Response Time
Frequency Range
Decode Bandwidth
CTCSS Encoder
40
Frequency Range
60.0
-1.0
253
0.3
Hz
%
Tone Frequency Resolution
Tone Amplitude Tolerance
1
9
0
+1.0
dB
%
Total Harmonic Distortion
2.0
SELCALL Encoder
Frequency Range
208
-1.0
3000
0.2
Hz
%
Tone Frequency Resolution
Tone Amplitude Tolerance
1
9
+1.0
dB
%
Total Harmonic Distortion
2.0
134.4
871
DCS Encoder
Bit Rate
bps
dB
Amplitude Tolerance
1
1
-1.0
300
+1.0
Amplitude
mVP-P
Audio Band-Pass Filter
Passband
8
8
8
8
3000
+0.5
Hz
dB
Passband Gain (at 1.0kHz)
Passband Ripple
0
wrt gain at 1.0kHz
-2
dB
Stopband Attenuation
Residual Hum and Noise
Alias Frequency
33.0
dB
-50.0
63
dBp
kHz
Output Impedance
TX AUDIO OUT, TX SUB AUDIO OUT and
RX AUDIO OUT
Enabled
10
2.0
k:
k:
Disabled
500
Rx Amp and Summing Amp
Open Loop Gain
input = 1mV at 100Hz
70.0
5.0
dB
MHz
MΩ
kΩ
Unity Gain Bandwidth
Input Impedance
Output Impedance
at 100Hz
10
Open Loop
6.0
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
29
MX828 PRELIMINARY INFORMATION
Transmitter Modulator Drives:
Mod.1 Attenuator
Attenuation
at 0dB
-0.2
-1.0
0
0.2
1.0
dB
dB
Ω
Cumulative Attenuation Error
Output Impedance
Input Impedance
Mod.2 Attenuator
Attenuation
wrt attenuation at 0dB
3
3
4
600
at 100Hz
15.0
kΩ
at 0dB
-0.2
-0.6
0
0.2
0.6
dB
dB
Ω
Cumulative Attenuation Error
Output Impedance
General Purpose Timer
Timing Period Range
Count Interval
wrt attenuation at 0dB
600
1
255
ms
ms
1
Xtal/Clock Input
Pulse Width
('High' or 'Low'
(at 100Hz)
40.0
10.0
20.0
ns
MΩ
dB
Input Impedance
Gain
input = 1mVRMS at 100Hz
D/A
Range
1
1
1
312.5
-30
2500
30
mV
mV
mV
MΩ
kΩ
Step Size
312.5
Step Accuracy
Input Impedance
Output Impedance
COMPIN
10
1
COMPOUT
Table 23: Operating Characteristics
Operating Characteristics Notes:
1. At VDD = 5.0V only. Signal levels or currents are proportional to VDD.
2. Not including any current drawn from the device by external circuitry.
3. Small signal impedance, at VDD = 5.0V and TAMB = 25°C.
4. Timing for an external input to the XTAL/CLOCK pin.
5. With input gain components set as recommended in Figure 2.
6. IRQ pin.
7. From one tone to another tone.
8. See filter response (Figure 3).
9. Measured at MOD 1 or MOD 2 output.
10. SUBAUDIO, SELCALL and DCS.
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
30
MX828 PRELIMINARY INFORMATION
10
0
-10
-20
-30
-40
-50
-60
10
100
1000
Frequency (Hz)
10000
100000
Figure 3: Audio Band-Pass Filter Frequency Response
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
31
MX828 PRELIMINARY INFORMATION
6.2 Timing Diagrams
For the following conditions unless otherwise specified:
Xtal Frequency = 4.032MHz, VDD = 3.3V to 5.0V, TAMB = -40°C to +85°C.
Parameter
"CS-Enable to Clock-High"
Last "Clock-High to CS-High"
"CS-High to Reply Output 3-state"
"CS-High" Time between transactions
"Inter-Byte" Time
Min.
Typ.
Max.
Units
µs
tCSE
tCSH
tHIZ
2.0
4.0
µs
2.0
µs
tCSOFF
tNXT
tCK
2.0
4.0
2.0
µs
µs
"Clock-Cycle" time
µs
Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first,
LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µC serial interface formats "C-BUS" compatible ICs are able to work with either polarity
SERIAL CLOCK pulses.
tCSOFF
CS
tNXT
tNXT
tCSE
tNXT
SERIAL CLOCK
tCK
COMMAND DATA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
7
6
6
5
4
3
2
1
1
0
0
MSB
LSB
FIRST DATA BYTE
LAST DATA BYTE
ADDRESS/COMMAND
BYTE
tHIZ
REPLY DATA
7
6
5
4
3
2
1
0
5
4
3
2
MSB
LSB
Logic level is not important
FIRST REPLY DATA BYTE
LAST REPLY DATA BYTE
Figure 4: "C-BUS" Timing
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
32
MX828 PRELIMINARY INFORMATION
6.3 Packaging
Package Tolerances
A
DIM.
MIN.
TYP.
MAX.
Z
A
B
C
E
H
J
K
L
P
0.613 (15.57)
0.299 (7.59)
0.105 (2.67)
0.419 (10.64)
0.020 (0.51)
0.020 (0.51)
0.046 (1.17)
0.597 (15.16)
0.286 (7.26)
0.093 (2.36)
0.390 (9.90)
0.003 (0.08)
0.013 (0.33)
0.036 (0.91)
B
E
Alternative Pin
Location
W
X
Marking
L
0.050 (1.27)
0.016 (0.41)
T
PIN 1
Y
0.050 (1.27)
45°
0.0125 (0.32)
0.009 (0.23)
T
W
X
10°
7°
0°
5°
K
C
Y
Z
5°
H
J
P
NOTE : All dimensions in inches (mm.)
Angles are in degrees
Figure 5: 24-pin SOIC Mechanical Outline: Order as part no. MX828DW
Package Tolerances
A
Z
TYP.
DIM.
MIN.
MAX.
A
B
C
E
H
J
0.318 (8.07)
0.205 (5.20)
0.066 (1.67)
0.301 (7.65)
0.002 (0.05)
0.010 (0.25)
0.022 (0.55)
0.328 (8.33)
0.213 (5.39)
0.079 (2.00)
0.312 (7.90)
0.008 (0.21)
0.015 (0.38)
0.037 (0.95)
E
B
L
T
PIN 1
H
L
P
T
X
Y
Z
0.026 (0.65)
X
0.005 (0.13)
0.009 (0.22)
Y
0°
7°
4°
8°
9°
10°
C
NOTE : All dimensions in inches (mm.)
Angles are in degrees
P
J
Figure 6: 24-pin SSOP Mechanical Outline: Order as part no. MX828DS
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CTCSS/DCS/SelCall Processor
33
MX828 PRELIMINARY INFORMATION
A
Package Tolerances
DIM.
MIN.
TYP.
MAX.
A
B
C
E
1.200 (30.48)
0.500 (12.70)
0.151 (3.84)
0.600 (15.24)
1.270 (32.26)
0.555 (14.04)
0.220 (5.59)
0.670 (17.02)
0.625 (15.88)
0.045 (1.14)
0.023 (0.58)
0.065 (1.65)
0.074 (1.88)
0.160 (4.05)
E
B
E1
Y
E1 0.590 (14.99)
H
J
J1
K
L
P
T
T
0.015 (0.38)
0.015 (0.38)
0.040 (1.02)
0.066 (1.67)
0.121 (3.07)
PIN1
K
C
0.100 (2.54)
H
L
0.008 (0.20)
0.015 (0.38)
Y
7°
NOTE : All dimensions in inches (mm.)
Angles are in degrees
P
J1
J
Figure 7: Figure 5: 24-pin PDIP Mechanical Outline: Order as part no. MX828P
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 336 744-5050 Fax: 336 744-5054
Doc. # 20480161.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor
companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc
(USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst
maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA)
Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML
Microcircuits.
These companies are all 100% owned operating companies of the CML Microsystems Plc
Group and these changes are purely changes of name and do not change any underlying legal
entities and hence will have no effect on any agreements or contacts currently in force.
CML Microcircuits Product Prefix Codes
Until the latter part of 1996, the differentiator between products manufactured and sold from
MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX
respectively. These products use the same silicon etc. and today still carry the same prefixes.
In the latter part of 1996, both companies adopted the common prefix: CMX.
This notification is relevant product information to which it is attached.
CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking
On CML Microcircuits (USA) products, the ‘MX-COM’ textual logo is being replaced by a ‘CML’
textual logo.
Company contact information is as below:
CML Microcircuits
(UK)Ltd
CML Microcircuits
(USA) Inc.
CML Microcircuits
(Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon,
Essex, CM9 6WG, England
Tel: +44 (0)1621 875500
Fax: +44 (0)1621 875600
uk.sales@cmlmicro.com
www.cmlmicro.com
4800 Bethania Station Road,
Winston-Salem, NC 27105, USA
Tel: +1 336 744 5050,
0800 638 5577
Fax: +1 336 744 5054
us.sales@cmlmicro.com
www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/
06 Mactech Industrial Building,
Singapore 349307
Tel: +65 7450426
Fax: +65 7452917
sg.sales@cmlmicro.com
www.cmlmicro.com
D/CML (D)/2 May 2002
相关型号：
©2020 ICPDF网 联系我们和版权申明