M8880 [CLARE]
DTMF Transceiver;
CLARE 
M-8880 DTMF Transceiver
· Advanced CMOS technology for low power consump-
tion and increased noise immunity
· Complete DTMF transmitter/receiver in a single chip
· Standard 6500/6800 series microprocessor port
· Central office quality and performance
· Adjustable guard time
· Automatic tone burst mode
· Call progress mode
· Single +5 Volt power supply
· 20-pin DIP and SOIC packages
· 2 MHz microprocessor port operation
· Inexpensive 3.58 MHz crystal
Figure 1 Pin Diagram
· No continuous f 2 clock required, only strobe
· Applications include: paging systems, repeater sys-
tems/mobile radio, interconnect dialers, PBX systems,
computer systems, fax machines, pay telephones,
credit card verification
Functional Description
M-8880 functions consist of a high-performance DTMF receiver
withaninternalgainsettingamplifierandaDTMFgeneratorthat
contains a tone burst counter for generating precise tone bursts
and pauses. The call progress mode, when selected, allows the
detection of call progress tones. A standard 6500/6800 series
microprocessor interface allows access to an internal status
register, two control registers, and two data registers.
The M-8880 is a complete DTMF Transmitter/Receiver that fea-
tures adjustable guard time, automatic tone burst mode, call
progress mode, and a fully compatible 6500/6800 microproces-
sor interface. The receiver portion is based on the industry stan-
dard M-8870 DTMF Receiver, while the transmitter uses a
switched-capacitor digital-to-analog converter for
low-distortion, highlyaccurateDTMFsignaling. Toneburstscan
be transmitted with precise timing by making use of the auto-
matic tone burst mode. To analyze call progress tones, a call
progress filter can be selected by an external microprocessor.
Input Configuration
The input arrangement consists of a differential input opera-
tional amplifier and bias sources (VREF) for biasing the amplifier
inputs at VDD/2. Provisions are made for the connection of a
feedback resistor to the op-amp output (GS) for gain adjust-
Figure 2 Block Diagram
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M-8880
Figure 3 Single-Ended Input Configuration
Figure 4 Differential Input Configuration
ment. In a single-ended configuration, the input pins should be
connected as shown in Figure 3. Figure 4 shows the necessary
connections for a differential input configuration.
A decoder employs digital counting techniques to determine the
frequencies of the incoming tones, and to verify that they corre-
spond to standard DTMF frequencies. A complex averaging al-
gorithm protects against tone simulation by extraneous signals
(such as voice), while tolerating small deviations in frequency.
The algorithm provides an optimum combination of immunity to
talkoff with tolerance to interfering frequencies (third tones) and
noise. When the detector recognizes the presence of two valid
tones (referred to as “signal condition”), the early steering (ESt)
output goes to an active state. Any subsequent loss of signal
condition will cause ESt to assume an inactive state.
Receiver Section
The low and high group tones are separated by applying the
DTMF signal to the inputs of two sixth-order switched capacitor
bandpass filters with bandwidths that correspond to the low and
high group frequencies listed in Table 2. The low group filter in-
corporates notches at 350 and 440 Hz, providing excellent dial
tone rejection. Each filter output is followed by a single-order
switchedcapacitorfilterthatsmoothsthesignalspriortolimiting.
Limiting is performed by high-gain comparators with hysteresis
to prevent detection of unwanted low-level signals. The com-
parator outputs provide full-rail logic swings at the incoming
DTMF signal frequencies.
Steering Circuit: Before a decoded tone pair is registered, the
receiver checks for a valid signal duration (referred to as “char-
acter recognition condition”). This check is performed by an ex-
ternal RC time constant driven by ESt. A logic high on ESt
Table 1 Pin Functions
Name
Description
IN+
IN-
GS
Noninverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection of feedback resistor.
V
Reference voltage output. Nominally V /2 is used to bias inputs at mid-rail.
REF
DD
V
Negative power supply input.
SS
OSC1
DTMF clock/oscillator input.
OSC2
TONE
R/W
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit.
Dual tone multifrequency (DTMF) output.
Read/write input. Controls the direction of data transfer to and from the microprocessor and the receiver/transmitter. TTL
compatible.
CS
RS0
Chip select. TTL input (CS = 0 to select the chip).
Register select input. See Table 6. TTL compatible.
System clock input. May be continuous or strobed only during read or write. TTL compatible.
φ2
IRQ/CP
Interrupt request to microprocessor (open-drain output). Also, when call progress (CP) mode has been selected and inter-
rupt enabled, the IRQ/CP pin will output a rectangular wave signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 11
D0 - D3
ESt
Microprocessor data bus. TTL compatible.
Early steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any
momentary loss of signal condition will cause ESt to return to a logic low.
St/GT
Steering input/guard time output (bidirectional). A voltage greater than V
detected at St causes the device to register the
TSt
detected tone pair and update the output latch. A voltage less than V
frees the device to accept a new tone pair. The
TSt
GT output acts to reset the external steering time-constant; its state is a funciton of ESt and the voltage on St.
V
DD
Positive power supply input.
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M-8880
causes VC (see Figure 5) to rise as the capacitor discharges.
The steering circuit works in reverse to validate the interdigit
pause between signals. Thus, as well as rejecting signals too
short to be considered valid, the receiver will tolerate signal in-
terruptions (dropout) too short to be considered a valid pause.
This capability, together with the ability to select the steering
time constants externally, allows the designer to tailor perfor-
mance to meet a wide variety of system requirements.
Provided that the signal condition is maintained (ESt remains
high) for the validation period (tGTP), VC reaches the threshold
(VTSt) of the steering logic to register the tone pair, latching its
corresponding4-bitcode(seeTable2)intothereceivedatareg-
ister.
Table 2 Tone Encoding/Decoding
Guard Time Adjustment: The simple steering circuit shown in
Figure 5 is adequate for most applications. Component values
are chosen according to the formula:
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
Digit
1
D3
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
tREC = tDP + tGTP
TID = tDA + tGTA
2
The value of tDP is a device parameter and tREC is the minimum
signal duration to be recognized by the receiver. A value for C1
of 0.1 µF is recommended for most applications, leaving R1 to
be selected by the designer. Different steering arrangements
may be used to select independently the guard times for tone
present (tGTP) and tone absent (tGTA). This may be necessary to
meet system specifications that place both accept and reject
limits on both tone duration and interdigit pause. Guard time ad-
justment also allows the designer to tailor system parameters
such as talkoff and noise immunity. Increasing tREC improves
talkoff performance since it reduces the probability that tones
simulated by speech will maintain signal condition long enough
to be registered. Alternatively, a relatively short tREC with a long
tDO would be appropriate for extremely noisy environments
where fast acquisition time and immunity to tone dropouts are
required. Designinformationforguardtimeadjustmentisshown
in Figure 6.
3
4
5
6
7
8
9
0
*
#
A
B
C
D
0 = logic low, 1 = logic high
At this point the StGT output is activated and drives VC to VDD
.
StGT continues to drive high as long as ESt remains high.
Finally, after a short delay to allow the output latch to settle, the
delayed steering output flag goes high, signaling that a received
tone pair has been registered. It is possible to monitor the status
ofthedelayedsteeringflagbycheckingtheappropriatebitinthe
status register. If interrupt mode has been selected, the IRQ/CP
pin will pull low when the delayed steering flag is active.
Figure 6 Guard Time Adjustment
Call Progress Filter
Figure 5 Basic Steering Circuit
A call progress (CP) mode can be selected, allowing the detec-
tionofvarioustonesthatidentifytheprogressofatelephonecall
onthenetwork. ThecallprogresstoneinputandDTMFinputare
common; however, call progress tones can only be detected
when the CP mode has been selected. DTMF signals cannot be
The contents of the output latch are updated on an active de-
layed steering transition. This data is presented to the 4-bit
bidirectional data bus when the receive data register is read.
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M-8880
detected if the CP mode has been selected (see Table 3). Fig-
accuracy. When there is no tone output signal, the TONE pin
assumes a DC level of 2.5 volts (typically). A bandwidth limiting
filter is incorporated to attenuate distortion products above 4
KHz.
ure 7 indicates the useful detect bandwidth of the call progress
filter. Frequencies presented to the input (IN+ and IN-) that are
within the “accept” bandwidth limits of the filter are hard-limited
by a high-gain comparator with the IRQ /CP pin serving as the
output. The square wave output obtained from the schmitt trig-
ger can be analyzed by a microprocessor or counter arrange-
ment to determine the nature of the call progress tone being
detected. Frequencies in the “reject” area will not be detected,
and consequently there will be no activity on IRQ /CP as a result
of these frequencies.
Burst Mode: Certain telephony applications require that gener-
ated DTMF signals be of a specific duration, determined either
by the application or by any of the existing exchange transmitter
specifications. Standard DTMF signal timing can be accom-
plished by making use of the burst mode. The transmitter is ca-
pable of issuing symmetric bursts/pauses of predetermined
duration. This burst/pause duration is 51 ms ± 1 ms, a standard
interval for autodialer and central office applications. After the
burst/pausehasbeenissued, theappropriatebitissetinthesta-
tusregister, indicatingthatthetransmitterisreadyformoredata.
The timing described is available when the DTMF mode has
been selected. However, when call progress (CP) mode is se-
lected, a secondary burst/pause time is available that extends
this interval to 102 ms ± 2 ms. The extended interval is useful
when precise tone bursts of longer than 51 ms duration and 51
mspausearedesired. NotethatwhenCPmodeandburstmode
have been selected, DTMF tones may be transmitted only and
not received. In applications requiring a nonstandard
burst/pause time, use a software timing loop or external timer.
This provides the timing pulses when the burst mode is disabled
by enabling and disabling the transmitter.
Figure 7 Call Progress Response
DTMF Generator
The M-8880 is initialized on powerup sequence with DTMF
mode and burst mode selected.
Single-Tone Generation: A single-tone mode is available
whereby individual tones from the low group or high group can
be generated. This mode can be used for DTMF test equipment
applications, acknowledgment tone generation, and distortion
measurements. Refer to Table 4 for details.
TheDTMFtransmitterusedintheM-8880iscapableofgenerat-
ing all 16 standard DTMF tone pairs with low distortion and high
accuracy. All frequencies are derived from an external 3.58
MHz crystal. The sinusoidal waveforms for the individual tones
are digitally synthesized using row and column programmable
dividers and switched capacitor digital-to-analog converters.
The row and column tones are mixed and filtered, providing a
DTMF signal with low total harmonic distortion and high accu-
racy. To specify a DTMF signal, data conforming to the encod-
ing format shown in Table 2 must be written to the transmit data
register. Note that this is the same as the receiver output code.
The individual tones that are generated (fLOW and fHIGH) are re-
ferred to as low-group and high-group tones. Typically, the
high-group to low-group amplitude ratio (twist) is 2 dB to com-
pensate for high-group attenuation on long loops.
Distortion Calculations: The M-8880 is capable of producing
precise tone bursts with minimal error in frequency (see Table
3). The internal summing amplifier is followed by a first-order
low-pass switched capacitor filter to minimize harmonic compo-
nents and intermodulation products. The total harmonic distor-
tion for a single tone can be calculated using Equation 1, (see
Figure 9) which is the ratio of the total power of all the extrane-
ous frequencies to the power of the fundamental frequency ex-
pressed as a percentage. The Fourier components of the tone
output correspond to V2f... Vnf as measured on the output
waveform. The total harmonic distortion for a dual tone can be
calculated using Equation 2 (see Figure 9).
Operation:Duringwriteoperationstothetransmitdataregister,
4-bit data on the bus is latched and converted to a 2 of 8 code for
use by the programmable divider circuitry to specify a time seg-
ment length that will ultimately determine the tone frequency.
The number of time segments is fixed at 32, but the frequency is
varied by varying the segment length. When the divider reaches
the appropriate count as determined by the input code, a reset
pulse is issued and the counter starts again. The divider output
clocks another counter that addresses the sinewave lookup
ROM. The lookup table contains codes used by the switched
capacitor D/A converter to obtain discrete and highly accurate
DC voltage levels. Two identical circuits are used to produce
row and column tones, which are then mixed using a low-noise
summing amplifier. The oscillator described needs no “startup”
time as in other DTMF generators, since the crystal oscillator is
running continuously, thus providing a high degree of tone burst
Table 3 Actual Frequencies vs. Standard
Requirements
% Error
Active
Cell
Output Frequency (Hz)
Specified
Actual
L1
L2
L3
L4
H1
H2
H3
H4
697
699.1
+ 0.30
- 0.49
- 0.54
+ 0.74
+ 0.57
- 0.32
- 0.35
+ 0.73
770
766.2
852
847.4
941
948.0
1209
1336
1447
1633
1215.9
1331.7
1471.9
1645.0
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M-8880
Table 4 Control Register A Description
Bit
Name
Function
Description
b0
TOUT
Tone output
A logic 1 enables the tone output. This function can be implemented in either the burst mode or
nonburst mode.
b1
CP/DTMF
Mode control In DTMF mode (logic 0), the device is capable of generating and receiving DTMF signals. When
the call progress (CP) mode is selected (logic 1), a 6th-order bandpass filter is enabled to allow
call progress tones to be detected. Call progress tones within the specified bandwidth will be pre-
sented at the IRQ/CP pin in rectangular wave format if the IRQ bit has been enabled (b2 =1). Also,
when the CP mode and burst mode have both been selected, the transmitter will issue DTMF sig-
nals with a burst and pause of 102 ms (typ) duration. This signal duration is twice that obtained
from the DTMF transmitter, if DTMF mode had been selected. Note that DTMF signals cannot be
decoded when the CP mode has been selected.
b2
b3
IRQ
Interrupt enable A logic 1 enables the interrupt mode. When this mode is active and the DTMF mode has been se-
lected (b1 = 0), the IRQ/CP pin will pull to a logic 0 condition when either (1) a valid DTMF signal
has been received and has been present for the guard time or (2) the transmitter is ready for more
data (burst mode only).
RSET
Register select A logic 1 selects control register B on the next write cycle to the control register address. Subse-
quent write cycles to the control register are directed back to control register A.
Table 5 Control Register B Description
Bit
Name
Function
Description
b0
BURST
Burst mode
A logic 0 enables the burst mode. When this mode is selected, data corresponding to the desired
DTMF tone pair can be written to the transmit data register, resulting in a tone burst of a specific
duration (see Table 12). Subsequently, a pause of the same duration is induced. Immediately fol-
lowing the pause, the status register is updated indicating that the transmit data register is ready
for further instructions, and an interrupt will be generated if the interrupt mode has been enabled.
Additionally, if call progress (CP) mode has been enabled, the burst and pause duration is increed
by a factor of two. When the burst mode is not selected (logic 1), tone bursts of any desired dura-
tion may be generated.
b1
b2
b3
TEST
S/D
Test mode
By enabling the test mode (logic 1), the IRQ/CP pin will present the delayed steering (inverted)
signal from the DTMF receiver. Refer to Figure 11 (b3 waveform) for details concerning the output
waveform. DTMF mode must be selected (CRA b1 = 0) before test mode can be implemented.
Single/dual tone A logic 0 will allow DTMF signals to be produced. If single-tone generation is enabled (logic 1), ei-
generation
ther now or column tones (low or high group) can be generated depending on the state of b3 in
control register B.
C/R
Column/row
tones
When used in conjunction with b2 (above), the transmitter can be made to generate single-row or
single-column frequencies. A logic0 will select row frequencies and a logic 1 will select column fre-
quencies.
VL and VH correspond to the low-group and high-group ampli-
tude, respectively, andV2IMD isthesumofalltheintermodulation
components. The internal switched capacitor filter following the
D/A converter keeps distortion products down to a very low
level.
DTMF Clock Circuit
Theinternalclockcircuitiscompletedwiththeadditionofastan-
dard 3.579545 MHz television color burst crystal. A number of
M-8880 devices can be connected as shown in Figure 8 using
only one crystal.
Microprocessor Interface
Figure 8 Common Crystal Connection
The M-8880 uses a microprocessor interface that allows pre-
cise control of transmitter and receiver functions. Five internal
registers are associated with the microprocessor interface,
which can be subdivided into three categories: data transfer,
transceiver control, and transceiver status. Two registers are
associated with data transfer operations. The receive data,
read-only, contains the output code of the last valid DTMF tone
pair to be decoded. The data entered in the transmit data regis-
terdetermineswhichtonepairistobegenerated(seeTable2).
Data can only be written to the transmit data register. Trans-
ceiver control is accomplished with two control registers (CRA
and CRB), occupying the same address space. A write opera-
tion to CRB can be executed by setting the appropriate bit in
CRA. The following write operation to the same address will
then be directed to CRB, and subsequent write cycles will then
be redirected to CRA. Internal reset circuitry clears the control
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M-8880
registersonpowerup;however, asaprecautionarymeasurethe
initialization software should include a routine to clear the regis-
ters. Refer to Tables 3 and 4 for details on the control registers.
The IRQ/CP pin can be programmed to provide an interrupt re-
quest signal on validation of DTMF signals, or when the trans-
mitter is ready for more data (burst mode only). The IRQ/CP pin
is configured as an open-drain output device and as such re-
quires a pullup resistor (see Figure 10).
Ordering Information
M-888001P
M-8880-01SM
M-8880-01T
20-pin plastic DIP
20-pin plastic SOIC
20-pin plastic SOIC,Tape and Reel
Figure 9 Equations
Table 7 CRA Bit Postions
Table 6 Internal Register Functions
b3
b2
b1
b0
RSEL
IRQ
CP/DTMF
TOUT
RS0
R/W
Function
0
0
1
1
0
1
0
1
Write to transmitter
Read from receiver
Write to control register
Read from status register
Table 8 CRB Bit Positions
b3
b2
b1
b0
C/R
S/D
TEST
BURST
Figure 10 Application Circuit (Single-Ended Input)
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M-8880
Table 9 Status Register Description
Status Flag Set
BIT
Name
Status Flag Cleared
b0 IRQ
Interrupt has occurred. Bi tone (b1) and/or bit 2 (b2) Interrupt is inactive. Cleared after status register is
is set.
read.
b1 Transmit data register
Pause duration has terminated and transmitter is
Cleared after status register is read or when not in
burst mode.
empty (burst mode only) ready for new data.
b2 Receive data register
full
Valid data is in the receive data register.
Cleared after status register is read.
b3 Delayed steering
Set on valid detection of the absence of a DTMF sig- Cleared on detection of a valid DTMF signal.
nal.
Table 10 Absolute Maximum Ratings
Parameter
Symbol
Value
Power supply voltage (V - V
)
V
DD
+ 6.0 V max
DD
SS
Voltage on any pin
Current on any pin
Operating temperature
Storage temperature
V
V
-0.3 V to V + 0.3 V
dc
SS
DD
I
10 mA max
-40°C to +85°C
-65°C to +150°C
DD
T
T
A
S
Note: Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied.
Table 11 DC Characteristics
Parameter
Symbol
Min
4.75
—
Typ*
5.0
10
Max
5.25
15
Units
V
Operating supply voltage
Operating supply current
Power consumption
Inputs
V
DD
DD
I
mA
mW
P
—
50
78.75
O
High-level input voltage, OSC1
Low-level input voltage, OSC1
Input impedance (@ 1 kHz), IN+, IN-
Steering threshold voltage
V
3.5
—
—
—
—
1.5
—
V
V
IHO
V
ILO
R
—
10
2.3
MΩ
V
IN
V
2.2
2.5
TSt
Outputs
High-level output voltage (no load), OSC2
Low-level output voltage (no load), OSC2
V
V
- 0.1V
DD
—
—
—
0.1
10.0
2.7
1.0
V
V
OHO
V
—
—
OLO
Output leakage current (V = 2.4V), IRQ
I
1.0
—
µA
V
OH
OZ
V
V
output voltage (no load)
output resistance
V
2.4
—
REF
REF
REF
R
kΩ
OR
Data Bus
Low-level input voltage
High-level input voltage
V
—
2.0
—
—
—
—
—
—
0.8
—
V
V
V
V
IL
V
IH
Low-level output voltage (I = 1.6 mA)
V
V
0.4
—
OL
OL
2.4
—
High-level output voltage (I = 400 µA)
OH
OH
Input leakage current (V = 0.4 to 2.4 V)
I
IZ
10.0
µA
IN
All voltages referenced to V unless otherwise noted. V = 5.0 V ± 5%; f = 3.579545 MHz; Τ = -40°C to +85°C, unless otherwise
SS
DD
C
A
noted. *Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
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M-8880
Table 12 AC Characteristics
PARAMETER
Receive signal conditions
SYMBOL
MIN
TYP*
MAX
UNITS
Valid input signal levels
-29
27.5
—
—
+1
869
dBm
(each tone of composite signal; Notes 1, 2, 3, 5, 6, 9)
mV
RMS
Positive twist accept (Notes 2, 3, 6, 9)
Negative twist accept (Notes 2, 3, 6, 9)
Frequency deviation accept (Notes 2, 3, 5, 9)
Frequency deviation reject (Notes 2, 3, 5)
Third tone tolerance (Notes 2, 3, 4, 5, 9, 10)
Noise tolerance (Notes 2, 3, 4, 5, 7, 9, 10)
Dial tone tolerance (Notes 2, 3, 4, 5, 8, 9, 11)
Call progress
—
6
dB
—
6
dB
Nom.
Nom.
dB
± 1.5% ± 2 Hz
—
—
—
—
—
—
—
± 3.5%
—
-16
-12
+22
—
dB
—
dB
Lower frequency (@ -25 dBm) accept
Upper frequency (@ -25 dBm) accept
Lower frequency (@ -25 dBm) reject
Upper frequency (@ -25 dBm) reject
Receive timing
f
—
—
—
—
320
510
290
540
—
—
—
—
Hz
Hz
Hz
Hz
LA
f
HA
f
LR
f
HR
Tone present detect time
t
t
5
11
4
14
8.5
40
—
ms
ms
ms
ms
ms
ms
µs
DP
DA
Tone absent detect time
0.5
—
20
—
20
—
—
Tone duration accept (ref. Figure 12)
Tone duration reject (ref. Figure 12)
Interdigit pause accept (ref. Figure 12)
Interdigit pause reject (ref. Figure 12)
Delay St to b3
t
t
—
—
—
—
13
8
REC
REC
t
40
—
ID
t
DO
t
—
PStb3
Delay St to RX —RX
t
—
µs
O
3
PStRX
Transmit timing
Tone burst duration (DTMF mode)
Tone pause duration (DTMF mode)
Tone burst duration (extended, call progress mode)
Tone pause duration (extended, call progress mode)
Tone output
t
50
50
—
—
—
—
52
52
ms
ms
ms
ms
BST
t
PS
t
100
100
104
104
BSTE
t
PSE
V
-6.1
-8.1
0
—
—
-2.1
-4.1
3
dBm
dBm
dB
High group output level (R = 10 kΩ)
HOUT
L
V
Low group output level (R = 10 kW)
LOUT
L
dB
2
Pre-emphasis (R = 10 kW)
P
L
THD
—
-25
± 0.7
—
—
dB
Output distortion (R = 10 kΩ, 3.4 kHz bandwidth)
L
Frequency deviation (f = 3.5795 MHz)
Output load resistance
Microprocessor interface
φ 2 cycle period
f
D
—
± 1.5
50
%
R
10
kΩ
LT
t
0.5
200
180
—
—
—
—
—
—
—
—
—
µs
ns
ns
ns
ns
ns
CYC
t
φ2 high pulse width
CH
t
φ2 low pulse width
CL
t , t
R
25
—
—
φ2 rise and fall time
F
Address, R/W hold time
Address, R/W setup time (prior to φ2)
t
, t
10
AH RWH
t
, t
23
AS RWS
40-406-00012, Rev. G
www.clare.com
Page 8
M-8880
Table 12 AC Characteristics (continued)
Parameter
Microprocessor interface (continued)
Data hold time (read)
Symbol
Min
Typ*
Max
Units
t
t
22
—
45
10
—
—
—
—
—
—
5
—
150
—
ns
ns
ns
ns
pF
pF
DHR
DDR
DSW
DHW
f2 to valid data delay (read) (200 pF load)
Data setup time (write)
t
Data hold time (write)
t
—
Input capacitance, D0—D3
Output capacitance, IRQ/CP
DTMF clock
C
IN
—
C/
OUT
5
—
Crystal clock frequency
f
3.5759
—
3.5795
—
3.5831
110
110
60
MHz
ns
C
Clock input rise time (external clock)
Clock input fall time (external clock)
Clock input duty cycle (external clock)
Capacitive load, OSC2
t
t
LHCL
HLCL
—
—
ns
DC
40
50
%
CL
C
LO
—
—
30
pF
All voltages referenced to unless otherwise noted. V = 5.0 V ± 5%; V = 0 V; f = 3.579545 MHz; T = -40°C to +85°C
DD
SS
C
A
*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
Notes:
1. dBm = decibels above or below a reference power of 1 mW into a 600 W load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms. Tone pause = 40 ms.
4. Nominal DTMF frequencies are used.
5. Both tones in the composite signal have an equal amplitude.
6. The tone pair is deviated by ± 1.5% ± 2 Hz.
7. Bandwidth limited (3 kHz) Gaussian noise.
8. The precise dial tone frequencies are 350 and 440 Hz (± 2%).
9. For an error rate of less than 1 in 10,000.
10. Referenced to the lowest amplitude tone in the DTMF signal.
11. Referenced to the minimum valid accept level.
Table 13 Electrical Characteristics - Gain Setting Amplifier
Parameter
Symbol
Min
—
—
—
—
—
—
—
—
—
—
—
Typ*
100
10
Max
—
—
—
—
—
—
—
—
—
—
—
Units
I
IN
nA
Input leakage current (V £ V £ V )
DD
SS
IN
Input resistance
R
IN
MΩ
mV
dB
Input offset voltage
V
25
OS
Power supply rejection (1 KHz)
PSRR
CMRR
60
60
dB
Common mode rejection (-3.0 V £ V £ 3.0 V
IN
)
DC open-loop voltage gain
Unity gain bandwidth
A
65
dB
VOL
BW
1.5
4.5
100
50
MHz
V
O
V
PP
Output voltage swing (R ³ 100 KΩ to V
)
L
SS
Maximum capacitive load, GS
Maximum resistive load, GS
Common mode range (no load)
C
R
pF
L
KΩ
L
V
3.0
V
PP
CM
All voltages referenced to unless otherwise noted. V = 5.0 V; V = 0 V; T = 25°C
DD
SS
A
*Typical values are for use as design aids only, and are not guaranteed or subject to production testing.
40-406-00012, Rev. G
www.clare.com
Page 9
M-8880
Figure 11 Timing Diagrams
Figure 12 Test Loads
40-406-00012, Rev. G
www.clare.com
Page 10
M-8880
Explanation of Events
(A) Tone bursts detected, tone duration invalid, RX Data Register not updated.
(B) Tone #n detected, tone duration valid, tone decoded and latched in RX Data Register.
(C) End of tone #n detected, tone absent duration valid, RX Data Register remain latched until next valid tone.
(D) Tone #n + 1 detected, tone duration valid, tone decoded and latched in RX Data Register.
(E) Acceptable dropout of tone #n + 1, tone absent duration invalid, RX Data Register remain latched.
(F) End of tone #n + 1 detected, tone absent duration valid, RX Data Register remain latched until next valid tone.
Explanation of Symbols
VIN
DTMF composite input signal.
ESt
Early steering output. Indicates detection of valid tone frequencies.
Steering input/guard time output. Drives external RC timing circuit.
4-bit decoded data in receive data register.
Delayed steering output. Indicates that valid frequencies have been present/absent for the
required guard time, thus constituting a valid DTMF signal.
St/GT
RX0-RX3
b3
b2
Output enable (input). A low level shifts Q1 - Q4 to its high impedance state.
IRQ/CP
Interrupt is active indicating that new data is in the RX data register. The interrupt is cleared
after the status register is ready.
tREC
tREC
tID
tDO
tDP
tDA
TGTP
tGTA
Maximum DTMF signal duration not detected as valid.
Minimum DTMF signal duration required for valid recognition.
Minimum time between valid DTMF signals.
Maximum allowable dropout during valid DTMF signal.
Time to detect the presence of valid DTMF signals.
Time to detect the absence of valid DTMF signals.
Guard time, tone present.
Guard time, tone absent.
Figure 13 Timing Diagrams
40-406-00012, Rev. G
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Page 11
M-8880
Tolerances
Inches
Metric (mm)
Min
Max
.210
Min
Max
5.33
A
A1
b
b2
C
D
E
E1
e
.015
.014
.045
.008
.980
.300
.240
.38
.36
1.14
.20
24.89
7.62
6.10
.022
.070
.014
1.060
.325
.280
.56
1.78
.36
26.92
8.26
7.11
.100 BSC
2.54 BSC
ec
L
15°
.150
0°
2.92
15°
3.81
0°
.115
Tolerances
Inches
Metric (mm)
Min
.093
.004
.013
.496
.291
Max
.104
.012
.020
.512
.299
Min
2.35
.10
.33
12.60
7.39
Max
2.65
.30
.51
13.00
7.59
A
A1
b
D
E
e
.050 BSC
1.27 BSC
H
L
.394
.016
.419
.050
10.00
.40
10.65
1.27
Figure 14 Package Dimensions
40-406-00012, Rev. G
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Page 12
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cuitry entirely embodied in this Clare product. No circuit patent licenses nor
indemnity are expressed or implied.Clare reserves the right to change the
specification and circuitry, without notice at any time. The products de-
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Specification: 40-406-00012, Rev. G
© Copyright 2000, CP Clare Corporation d/b/a Clare
All rights reserved. Printed in USA.
07/28/00
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