CPC7583BD [CLARE]
Line Card Access Switch; 线卡接入交换机
| 型号： | CPC7583BD |
| 厂家： | 
CLARE |
| 描述： | Line Card Access Switch |
| 文件： | 总16页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CPC7583
Line Card Access Switch
Features
Description
• Small 28 pin surface mount SOIC package
The CPC7583 is a monolithic solid state switch in a 28 pin
surface mount SOIC package. It provides the necessary
functions to replace three 2-Form-C electromechanical re-
lays on analog line cards found in Central Office, Access
and PBX equipment. The device contains solid state
switches for tip and ring line break, ring injection/ring re-
turn, line test access, test in access and ringing generator
testing. The CPC7583 requires only a +5V supply and of-
fers “break-before-make” or “make-before-break” switch
operation using simple logic level input control. The
CPC7583 has 4 versions. The CPC7583BA and the
CPC7583BC contain the integrated protection SCR while
the CPC7583BC and the CPC7583BD contain an extra
logic state which is detailed in later sections.
• Monolithic IC reliability
• Low matched RDSON
• Eliminates the need for zero cross switching
• Flexible switch timing to transition from ringing mode to
idle/talk mode
• Clean, bounce free switching
• Tertiary protection consisting of integrated current
limiting, thermal shutdown and SLIC protection
• 5V operation with power consumption <10mW
• Intelligent battery monitor
• Latched logic level inputs, no drive circuitry
• Pin to pin compatible to the Lucent 7583 family
Ordering Information
Applications
Part #
Description
• Central office (CO)
• Digital Loop Carrier (DLC)
• PBX Systems
CPC7583BA
CPC7583BB
CPC7583BC
10 Pole with protection SCR
10 Pole without protection SCR
10 Pole extra logic state with
protection SCR
10 Pole extra logic state without
protection SCR
• Digitally Added Main Line (DAML)
• Hybrid Fiber Coax (HFC)
• Fiber in the Loop (FITL)
• Pair Gain System
CPC7583BD
CPC7583BATR Tape and Reel Version
CPC7583BBTR Tape and Reel Version
CPC7583BCTR Tape and Reel Version
CPC7583BDTR Tape and Reel Version
• Channel Banks
Block Diagram
CPC7583BA
DS-CPC7583-RE
1
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CPC7583
Absolute Maximum Ratings are stress ratings. Functional op-
eration of the device at these or any other conditions beyond
those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to the absolute maximum
ratings for extended period may degrade the device and effect
its reliability.
Parameter
Min
-40
-40
5
Max
+110
+150
95
Units
˚C
˚C
%
˚C
Operating Temperature Range
Storage Temperature Range
Relative Humidity Range
Pin Soldering Temperature
(t=10 s max)
-
+260
+5V Power Supply
Battery Supply
Logic Input Voltage
Logic Input to Switch Output Isolation
Switch Isolation (SW1, SW2, SW3,
SW5, SW6, SW7, SW9,SW10)
Switch Isolation (SW4)
Switch Isolation (SW8)
-
-
-
-
-
7
-85
7
330
330
V
V
V
V
V
-
-
480
235
V
V
Electrical Characteristics TA = -40oC to +85oC (unless otherwise specified)
Minimum and maximum values are production testing requirements. Typical values are characteristic of the device and are the result
of engineering evaluations. Typical values are provided for information purposes only and are not part of the testing requirements.
Power Supply Specifications
Supply
Min
+4.5
-19
Typ
+5.0
-
Max
+5.5
-72
Unit
V
V
ESD Rating (HBM Model)
VDD
VBAT
1000
1
1 VBAT is used only as a reference for internal protection circuitry.
If VBAT rises above -10V, the device will enter an all off state and will remain in the all off state until the battery voltage drops below -15V.
Table 1. Break Switch, SW1 and SW2
PARAMETERS
CONDITIONS
SYMBOL
Isw
MIN
TYP
0.1
0.3
0.1
MAX
UNITS
µA
Off-state Leakage Current:
o
+25 C
Vsw (differential)= -320V to Gnd
Vsw (differential)= -60V to +260V
Vsw (differential)= -330V to Gnd
Vsw (differential)= -60V to +270V
Vsw (differential)= -310V to Gnd
Vsw (differential)= -60V to +250V
-
-
-
1
1
1
o
+85 C
Isw
µA
o
-40 C
Isw
µA
RDS (SW1,SW2):
ON
o
+25 C
TLINE= +/-10 mA, +/-40mA, TBAT= -2V
TLINE= +/-10 mA, +/-40mA, TBAT= -2V
TLINE= +/-10 mA, +/-40mA, TBAT= -2V
Per ON-resistance Test Condition of
SW1, SW2
∆ V
∆ V
∆ V
-
-
-
-
14.5
20.5
10.5
0.15
-
28
-
Ω
Ω
Ω
Ω
o
+85 C
o
-40 C
RDS Match
ON
Magnitude
RON SW1-RONSW2
0.8
DC Current Limit:
o
+25 C
Vsw (on) = +/- 10V
Vsw (on) = +/- 10V
Vsw (on) = +/- 10V
Break switches in ON state, ringing
access switches OFF, apply +/- 1000V
at 10/1000µs pulse, appropriate
secondary protection in place.
Isw
Isw
Isw
Isw
-
80
-
225
150
400
2.5
-
-
mA
mA
mA
A
o
+85 C
o
-40 C
425
-
Dynamic Current Limit:
(t=<0.5µs)
-
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (TLINE, RLINE) = +/-320V
Isw
Isw
Isw
-
-
-
-
-
0.1
0.3
0.1
200
1
1
1
-
µA
µA
Logic Inputs = Gnd
Vsw (TLINE, RLINE) = +/-330V
Logic Inputs = Gnd
Vsw (TLINE, RLINE) = +/-310V
Logic Inputs = Gnd
-
o
+85 C
o
-40 C
µA
dv/dt Sensitivity1
1 Applied voltage is 100 Vp-p square wave at 100Hz.
V/µs
Rev. E
2
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CPC7583
Table 2. Ring Return Switch, SW3
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current
o
+25 C
Vsw (differential)= -320V to Gnd
Vsw (differential)= -60V to +260V
Vsw (differential)= -330V to Gnd
Vsw (differential)= -60V to +270V
Vsw (differential)= -310V to Gnd
Vsw (differential)= -60V to +250V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
o
+85 C
o
-40 C
DC Current Limit
o
+25 C
Vsw (on) = +/- 10V
Vsw (on) = +/- 10V
Vsw (on) = +/- 10V
Break switches in ON state, Ringing
access switches OFF, Apply +/- 1000V
at 10/1000µs pulse, Appropriate
secondary protection in place.
Isw
Isw
Isw
Isw
-
-
-
-
120
80
210
2.5
-
-
-
-
mA
mA
mA
A
o
+85 C
o
-40 C
Dynamic Current Limit:
(t=<0.5µs)
RDSON
+25˚C
+85˚C
-40˚C
Isw (on) = +/-0mA, +/-10mA
Isw (on) = +/-0mA, +/-10mA
Isw (on) = +/-0mA, +/-10mA
∆ V
∆ V
∆ V
-
-
-
60
85
45
-
100
-
Ω
Ω
Ω
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (TRING, TLINE) = +/-320V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
Logic Inputs = Gnd
Vsw (TRING, TLINE) = +/-330V
Logic Inputs = Gnd
o
+85 C
o
-40 C
Vsw (TRING, TLINE) = +/-310V
Logic Inputs = Gnd
Table 3. Ringing Access Switch, SW4
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current
o
+25 C
Vsw (differential)= -255V to +210V
Vswitch (differential)= +255V to -210V
Vsw (differential)= -270V to +210V
Vsw (differential)= +270V to -210V
Vsw (differential)= -245V to +210V
Vsw (differential)= +245V to -210V
Isw (on) = +/- 1mA
Isw
Isw
Isw
-
-
-
-
.05
0.1
.05
1
1
1
µA
µA
µA
o
+85 C
o
-40 C
ON Voltage
Ring Generator Current
During Ring
-
-
1.5
0.1
3
0.25
V
mA
Vcc = 5V, INTESTin = 0
I
R
INTESTout = 0
Surge Current
Release Current
ON-resistance
-
-
-
-
-
-
-
-
2
-
12
A
µA
Ω
450
8.5
Isw (on) = +/-70mA, +/-80mA
∆ V
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (RRING, RLINE) = +/-320V
Isw
Isw
Isw
-
-
-
.05
0.1
.05
1
1
1
µA
µA
µA
Logic Inputs = Gnd
Vsw (RRING, RLINE) = +/-330V
Logic Inputs = Gnd
o
+85 C
o
-40 C
Vsw (RRING, RLINE) = +/-310V
Logic Inputs = Gnd
Rev. E
3
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CPC7583
Table 4. Loop Access Switches, SW5 and SW6
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
o
+25 C
Vsw (differential) = -320V to +Gnd
Vsw (differential) = -60V to +260V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
o
+85 C
Vsw (differential) = -330V to Gnd
Vsw (differential) = -60V to +270V
o
-40 C
Vsw (differential) = -310V to +Gnd
Vsw (differential) = -60V to +250V
RDS
ON
:
o
+25 C
Isw (on) = +/-5mA, +/-10mA
Isw (on) = +/-5mA, +/-10mA
Isw (on) = +/-5mA, +/-10mA
∆ V
∆ V
∆ V
-
-
-
35
50
26
-
70
-
Ω
Ω
Ω
o
+85 C
o
-40 C
DC Current Limit:
o
+25 C
Vsw (on) = +/-10V
Vsw (on) = +/-10V
Vsw (on) = +/-10V
Isw
Isw
Isw
140
100
210
-
-
250
mA
mA
mA
o
+85 C
80
-
o
-40 C
Dynamic Current LImit
(t=<0.5µs)
Break switches in ON state; ringing
access switches OFF; apply +/-1000V at
10/1000µs pulse; appropriate secondary
protection in place.
Isw
-
2.5
-
A
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (TTESTout, TLINE, RTESTout, RLINE) = +/-320V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
Logic Inputs = Gnd
o
+85 C
Vsw (TTESTout, TLINE, RTESTout, RLINE) = +/-330V
Logic Inputs = Gnd
o
-40 C
Vsw (TTESTout, TLINE, RTESTout, RLINE) = +/-310V
Logic Inputs = Gnd
Table 5. Ringing Test Return Switch SW7
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
o
+25 C
Vsw (differential)= -320V to Gnd
Vsw (differential)= -60V to +260V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
o
+85 C
Vsw (differential)= -330V to Gnd
Vsw (differential)= -60V to +270V
o
-40 C
Vsw (differential)= -310 to Gnd
Vsw (differential)= -60V to +250V
RDSON
+25˚C
+85˚C
-40˚C
Isw (on) = +/-0mA, +/-10mA
Isw (on) = +/-0mA, +/-10mA
Isw (on) = +/-0mA, +/-10mA
∆ V
∆ V
∆ V
-
-
-
60
85
45
-
100
-
Ω
Ω
Ω
DC Current Limit
o
+25 C
Vsw (on) = +/- 10V
Vsw (on) = +/- 10V
Vsw (on) = +/- 10V
Isw
Isw
Isw
-
-
-
120
80
210
-
-
-
mA
mA
mA
o
+85 C
o
-40 C
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (TRING, TTESTin) = +/-320V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
Logic Inputs = Gnd
o
+85 C
Vsw (TRING, TTESTin) = +/-330V
Logic Inputs = Gnd
o
-40 C
Vsw (TRING, TTESTin) = +/-310V
Logic Inputs = Gnd
Rev. E
4
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CPC7583
Table 6. Ringing Test Switch SW8
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
o
+25 C
Vsw (differential)= -60V to +175V
Vsw (differential)= +60V to -175V
Vsw (differential)= -60V to +175V
Vsw (differential)= +60V to -175V
Vsw (differential)= -60V to +175V
Vsw (differential)= +60V to -175V
Isw
Isw
Isw
-
-
-
.05
0.1
.05
1
1
1
µA
µA
µA
o
+85 C
o
-40 C
ON-resistance
ON- voltage
Release Current
Isw (on) = +/-70 mA, +/-80mA
Isw (on) = +/-1mA
-
∆ V
-
-
-
-
-
6
0.75
450
20
1.5
-
Ω
V
µA
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (RRING, RTESTin) = +/-320V
Isw
Isw
Isw
-
-
-
.05
0.1
.05
1
1
1
µA
µA
µA
Logic Inputs = Gnd
Vsw (RRING, RTESTin) = +/-330V
Logic Inputs = Gnd
o
+85 C
o
-40 C
Vsw (RRING, RTESTin) = +/-310V
Logic Inputs = Gnd
* Choice of secondary protector and series current-limit resistor should ensure these ratings are not exceeded.
Table 7. Test in Switches, SW9 and SW10
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Off-state Leakage Current:
o
+25 C
Vsw (differential)= -320V to Gnd
Vsw (differential)= -60V to +260V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
o
+85 C
Vsw (differential)= -330V to Gnd
Vsw (differential)= -60V to +270V
o
-40 C
Vsw (differential)= -310V to Gnd
Vsw (differential)= -60V to +250V
RDS
ON
+25 C
:
o
Isw(on) = +/-5 mA, +/-10mA
Isw(on) = +/-5 mA, +/-10mA
Isw(on) = +/-5 mA, +/-10mA
∆ V
∆ V
∆ V
-
-
-
35
50
26
-
70
-
Ω
Ω
Ω
o
+85 C
o
-40 C
DC Current Limit:
o
+25 C
Vsw (On) = +/-10V
Vsw (On) = +/-10V
Vsw (On) = +/-10V
Isw
Isw
Isw
-
80
-
160
110
210
-
-
mA
mA
mA
o
+85 C
o
-40 C
250
Logic Input to Switch Output Isolation:
o
+25 C
Vsw (TTESTin, RTESTin) = +/-320V
Isw
Isw
Isw
-
-
-
0.1
0.3
0.1
1
1
1
µA
µA
µA
Logic Inputs = Gnd
o
+85 C
Vsw (TTESTin, RTESTin) = +/-330V
Logic Inputs = Gnd
o
-40 C
Vsw (TTESTin, RTESTin) = +/-310V
Logic Inputs = Gnd
Rev. E
5
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CPC7583
Table 8. Additional Electrical Characteristics
PARAMETERS
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Digital Input Characteristics
Input Low Voltage
Input High Voltage
-
-
-
-
-
3.5
-
-
-
0.1
1.5
-
1
V
V
µA
Input Leakage Current (High)
V
V
V
V
= 5.5V, V
= 5V
= 5.5V, V
= 0V
= -75V,
= -75V,
I
I
DD
log
DD
log
BAT
log
Input Leakage Current (Low)
-
0.1
1
µA
BAT
log
Power Requirements
Power Dissipation
V
= 5V, V = -48V,
BAT
DD
Idle/Talk State or All Off State
I
, I
-
-
5.0
6.0
7.5
10
mW
mW
DD BAT
Ringing State or Test State
I
DD
V
V
Current
V
= 5V,
DD
DD
Idle/Talk State or All Off State
Ringing State or Test State
V
I
I
-
-
1.0
1.2
1.5
1.9
mA
mA
DD
DD
Current
= -48V,
BAT
BAT
Idle/Talk State or All Off State
Ringing State or Test State
I
I
-
-
4
4
10
10
µA
µA
BAT
BAT
Temperature Shutdown Requirements1
Shutdown Activation Temperature
Shutdown Circuit Hysteresis
o
o
-
-
-
-
110
10
125
-
150
25
C
C
1 Temperature shutdown flag (TSD) will be high during normal operation and low during temperature shutdown state.
Table 9. Make-Before-Break Operation (Ringing to Idle/Talk Transition)
Ring
Ring
Break Return Access
Switches Switch
All Other
Test
Switches
Switch
4
Ring
Testin
Testout TSD
State
Timing
1 & 2
3
5V
0V
0V
0V
0V
0V
Float Ringing
-
Open
Closed
Closed
Open
Closed
Closed
Open
Open
Float Make-before-break SW4 waiting for next zero current
crossing to turn off. Maximum
time is half of ringing. In this
transition state, current that is
limited to the dc break switch
current limit value will be sourced
from the ring node of the SLIC
0V
0V
0V
Float
Idle / Talk
Zero cross current has occurred
Closed
Open
Open
Open
Rev. E
6
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CPC7583
Table 10. Break-Before-Make Operation (Ringing to Idle/Talk Transition)
Ring
Ring
Break Return Access
Switches Switch
All Other
Access
Switches
Open
Open
Switch
4
Closed
Closed
Ring
5V
5V
Testin
0V
0V
Testout TSD
State
Ringing
All Off
Timing
-
1 & 2
Open
Open
3
0V
5V
Float
Float
Closed
Open
Hold this state for </= 25ms.
SW4 waiting for zero current to
turn off.
5V
0V
0V
0V
5V
0V
Float
Float
All Off
Zero current has occurred.
SW4 has opened.
Release Break Switches
Open
Open
Open
Open
Open
Open
Open
Idle/Talk
Closed
Alternate “Break-Before-Make” Operation
Note that the break-before-make operation can also be achieved using TSD as an input. In lines 2 & 3 of Table 10, instead of using the
logic input pins to force the “all off” state, force TSD to ground. This will override the logic inputs and also force the all off state. Hold
this state for 25 ms. During this 25 ms all off state, toggle the inputs from the 10 (ringing state) to 00 (idle/talk state). After 25 ms,
release TSD to return switch control to the input pins which will set the idle talk state.
When using the CPC7583 in this mode, forcing TSD to ground will override the INPUT pins and force an all off state. Setting TSD to
+5V will allow switch control via the logic INPUT pins. However, setting TSD to +5V will also disable the thermal shutdown mecha-
nism. This is not recommended. Therefore, to allow switch control via the logic INPUT pins, allow TSD to float.
Thus when using TSD as an input, the two recommended states are 0 (overrides logic input pins and forces all off state) and float
(allows switch control via logic input pins and thermal shutdown mechanism is active). This may require use of an open collector
buffer.
Table 11. Electrical Specifications, Protection Circuitry
PARAMETER
CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
Parameters Related to Diodes
(in Diode Bridge)
Voltage Drop @ Continuous
Current (50/60 Hz)
Voltage Drop @ Surge
Current
Apply +/-dc current limit of break
switches
Apply +/-dynamic current limit of
break swithces
Forward
Voltage
Forward
Voltage
-
-
2.8
5
3.5
-
V
V
Parameters Related to
Protection SCR1
Surge Current
Trigger Current (25˚C)
Hold Current (25˚C)
Trigger Current (85˚C)
Hold Current (85˚C)
Gate Trigger Voltage
Reverse Leakage Current
ON State Voltage1
-
-
-
-
-
-
-
-
-
-
60
110
35
70
-
-
-3
-5
*
-
-
-
A
mA
mA
mA
mA
V
µA
V
V
ITRIG
IHOLD
ITRIG
IHOLD
-
-
60
VBAT - 4
-
Trigger Current
VBAT - 2
1.0
V
-
-
-
-
BAT
0.5A t = 0.5 ms
2.0A t = 0.5 ms
V
-
-
on
-
1 Only for the CPC7583BA and CPC7583BC.
* Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
Rev. E
7
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CPC7583
Table 12. Truth Table for the CPC7583BA and CPC7583BB
INring
INtestin
INtestout
TSD
TESTin
Switches
Break
Switches
RingTest
Switches
Ring
Switches
TESTout
Switches
0V
0V
0V
5V
5V
0V
5V
5V
0V
0V
5V
0V
5V
5V
0V
5V
0V
5V
0V
0V
0V
5V
5V
5V
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
0V2
Off
Off
On
Off
Off
On
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off3
On4
Off5
Off6
Off7
On8
Off9
Off9
Off9
Don’t
Care
1
Don’t
Care
Don’t
Care
If TSD = 5V, the thermal shutdown mechanism is disabled.
If TSD if floating, the thermal shutdown mechanism is active.
Forcing TSD to ground overrides the logic input pins and forces an all off state.
Idle/Talk State.
2
3
4
5
6
7
8
TESTout state.
TESTin state.
Power Ringing State.
Ringing generator test state.
Simultaneous TESTout and TESTin state.
All OFF State
9
A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin
LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state
control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data
latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The
state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic
0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT
and LATCH.
Rev. E
8
www.clare.com
CPC7583
Table 13. Truth Table for the CPC7583BC and CPC7583BD
INring
INtestin
INtestout
TSD
TESTin
Switches
Break
Switches
RingTest
Switches
Ring
Switches
TESTout
Switches
0V
0V
0V
5V
5V
0V
5V
5V
0V
0V
5V
0V
5V
5V
0V
5V
0V
5V
0V
0V
0V
5V
5V
5V
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
0V2
Off
Off
On
Off
Off
On
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
On
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off3
On4
Off5
Off6
Off7
On8
Off9
On10
Off9
Don’t
Care
1
Don’t
Care
Don’t
Care
If TSD = 5V, the thermal shutdown mechanism is disabled.
If TSD if floating, the thermal shutdown mechanism is active.
Forcing TSD to ground overrides the logic input pins and forces an all off state.
Idle/Talk State.
TESTout state.
2
3
4
5
6
7
8
9
TESTin state.
Power Ringing State.
Ringing generator test state.
Simultaneous TESTout and TESTin state.
All OFF State
10 Simultaneous TESTout - Ring Test state.
A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin
LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state
control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data
latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The
state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic
0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT
and LATCH.
Rev. E
9
www.clare.com
CPC7583
Package Pinout
CPC7583
VBAT
FGND
1
SOG
1
Symbol
FGND
NC
Description
Fault ground.
28
SCR and
TRIP CKT
2
27 NC
26 NC
NC
2
No Connection.
NC
3
4
5
3
NC
No Connection.
NC
R
25
24
23
22
NC
4
NC
No Connection.
SW9
SW10
TTESTin
5
TTESTin
TBAT
Test (in) access on TIP.
Connect to TIP on SLIC side.
Connect to TIP on line side.
TBAT
RBAT
6
7
6
SW1
SW7
SW2
RLINE
TLINE
TRING
7
TLINE
8
21 NC
SW8
8
TRING
NC
Connect to return ground for ringing generator.
No connection.
SW3
R
NC
9
20
RING
9
SW4
TTESTout
RTESTout
10
19
18
17
SW5
SW6
10
11
12
13
TTESTout
NC
Test (out) access on TIP.
No connection.
NC 11
LATCH
INTESTin
VDD
12
Control
Logic
VDD
5V supply
INRING
16
15
13
TSD
Temperature shutdown pin. Can be used as a logic
level input or an output. See Tables 9, 10, 12 and13 for
more details. As an output, will read 5V when the
device is in its operational mod and 0V in the thermal
shutdown mode. To disable the thermal shutdown mode
mechanism, tie this pin to 5V (not recommended).
TSD
DGND
14
INTESTout
* Only the CPC7583BA and CPC7583BC
contain the protection SCR
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DGND
Digital ground
INTESTout
INRING
INTESTin
LATCH
RTESTout
RRING
NC
Logic level switch input control.
Logic level switch input control.
Logic level switch input control.
Data input control, active-high, transparent low.
Test (out) access on RING.
Connect to ringing generator.
No connection.
RLINE
RBAT
Connect to RING on line side.
Connect to RING on SLIC side.
Test (in) access on RING.
No connection.
RTESTin
NC
NC
No connection.
NC
No connection
VBAT
Battery voltage. Used as a reference for protection circuit.
Rev. E
10
www.clare.com
CPC7583
state contacts, use of a foldback or crowbar type sec-
ondary protector is recommended. With proper selection
of the secondary protector, a line card using the CPC7583
will meet all relevant ITU, LSSGR, FCC or UL protection
requirements.
Functional Description
Introduction
The CPC7583 has eight distinct states. Please consult the
truth tables in table 12 and 13 for version differences.
The CPC7583 operates from a +5V supply only. This gives
the device extremely low idle and active power dissipation
and allows use with virtually any range of battery voltage.
A battery voltage is also used by the CP7583 as a refer-
ence for the integrated protection circuit. In the event of a
loss of battery voltage, the CPC7583 will enter an “all off”
state.
• Idle/talk state (line break switches SW1, and SW2
closed). All other switches open.
• Ringing state, (ringing switches SW3, SW4 closed).
All other switches open.
• Loop access (loop access switches SW5, SW6
closed). All other switches open.
Switch Timing
• Ring generator test state (SW7, SW8 closed). All
The CPC7583 provides, when switching from the ringing
state to the idle/talk state, the ability to control the timing
when the ringing access switches SW3 and SW4 are re-
leased relative to the state of the line break switches SW1
and SW2 using simple logic level input. This is referred to
as a “make before break” or “break before make” opera-
tion. When the line break switch contacts (SW1, SW2) are
closed (or made) before the ringing access switch contact
(SW3, SW4) is opened (or broken), this is referred to a
‘make-before-break’operation. Break-before-make opera-
tion occurs when the ringing access contact (SW3, SW4)
is opened (broken) before the line break switch contacts
(SW1, SW2) are closed (made). With the CPC7583 the
“make before break” and “break before make” operations
can easily be selected by applying logic level inputs to
INTESTout, INRING and INTESTin of the device.
other switches open.
• SLIC test state Testin switches closed (SW9, SW10).
• Simultaneous Loop and SLIC access state. (SW9,
SW10, SW5 and SW6 closed). All other switches open.
• Simultaneous test out and ring test (SW5, SW6,
SW7, SW8 closed).All other switches open on the “BC”
abd “BD” version.
• All Off state (all switches open).
The CPC7583 offers break-before-make and make-before-
break switching with simple logic level input control. Solid
state switch construction means no impulse noise is gen-
erated when switching during ring cadence or ring trip, thus
eliminating the need for external “zero cross” switching cir-
cuitry. State control is via logic level input so no additional
driver circuitry is required. The line break switches SW1
and SW2 are linear switches that have exceptionally low
RDSON and excellent matching characteristics. The ring-
ing access switch SW4 has a breakdown voltage rating of
>480V which is sufficiently high, with proper protection, to
prevent breakdown in the presence of a transient fault con-
dition. (i.e., passing the transient on to the ring generator)
The logic sequences for either mode of operation are given
in Tables 9 and 10. Logic states and explanations are given
in Tables 12 and 13.
Break-before make operation can also be achieved using
pin 13 (TSD) as an input. In table 10 lines 2 and 3 it is
possible to induce the switches to “all off” by grounding pin
13 (TSD) instead of apply logic input to the pins. This has
the effect of overriding the logic inputs and forcing the de-
vice to the “all off” state. Hold this input state for 25ms.
During this hold period, toggle the inputs from the ringing
state to the idle/talk state. After the 25ms release pin 13
(TSD) to return the switch control to the input INTESTout, INRING,
INTESTin and reset the device to the idle/talk state.
Integrated into the CPC7583 is a diode bridge clamping
circuit, current limiting and thermal shutdown mechanism
to provide protection to the SLIC device during a fault con-
dition. Positive and negative surges are reduced by the
current limiting circuitry and steered to ground via diodes.
Power cross transients are also reduced by the current lim-
iting and thermal shutdown circuits.
Setting pin 13 (TSD) to +5V will allow switch control using
the logic inputs. This setting, however, will also disable the
thermal shutdown circuit and is therefore not recommended.
When using logic controls via the input pins (INTESTout, INRING
and INTESTin), pin 13 (TSD) should be allowed to float. As a
result the two recommended states when using pin 13
To protect the CPC7583 from an overvoltage fault condi-
tion, use of a secondary protector is required. The sec-
ondary protector must limit the voltage seen at the tip and
ring terminals to a level below the max breakdown volt-
age of the switches. To minimize the stress on the solid-
Rev. E
11
www.clare.com
CPC7583
(TSD) as a control are 0 which forces the device to the “all
off state” or float which allow logic inputs to remain active.
This may require use of an open collector buffer.
less negative the SCR on voltage, the SCR will not crow-
bar, however it will conduct fault currents to ground.
For power induction or power cross fault conditions, the
positive cycle of the transient is clamped to the diode drop
above ground and the fault current directed to ground. The
negative cycle of the transient will cause the SCR to con-
duct when the voltage exceeds the battery reference volt-
age by two to four volts, steering the current to ground.
Ring Access Switch Zero Cross Current Turn Off
After the application of a logic input to turn SW4 off, the
ring access switch is designed to delay the change in state
until the next zero crossing. Once on, the switch requires a
zero current cross to turn off and therefore should not be
used to switch a pure DC signal. The switch will remain in
the on state no matter what logic input until the next zero
crossing. These switching characteristics will reduce and
possibly eliminate overall system impulse noise normally
associated with ringing access switches. The attributes of
ringing access switch may make it possible to eliminate
the need for a zero cross switching scheme. A minimum
impedance of 300Ω in series with the ring generator is
recommended.
Current Limiting function
If a lightning strike transient occurs when the device in the
talk/idle state, the current is passed along the line to the
integrated protection circuitry and limited by the dynamic
current limit response of break switches SW1 and SW2.
When a 1000V 10x1000 pulse (LSSGR lightning) is ap-
plied to the line though a properly clamped external pro-
tector, the current seen at pins 6 (TBAT) and pin 23 (RBAT) will
be a pulse with a typical magnitude and duration of 2.5A
and < 0.5ms.
Power Supplies
If a power cross fault occurs with device in the talk/idle
state, the current is passed though the break switches SW1
and SW2 on to the integrated protection circuit and is lim-
ited by the dynamic DC current limit response of the two
break switches. The DC current limit, specified over tem-
perature, is between 80mA and 400mA and the circuitry
has a negative temperature coefficient. As a result, if the
device is subjected to extended heating due to power cross
Both a +5V supply and battery voltage are connected to
the CPC7583. CPC7583 switch state control is powered
exclusively by the +5V supply. As a result, the CPC7583
exhibits extremely low power dissipation during both active
and idle states.
Battery Voltage Monitor
The CPC7583 also uses the voltage reference to monitor
battery voltage. If battery voltage is lost, the CPC7583 will
immediately enter the “all off” state and remain in this state
until the battery voltage is restored. The device will also
enter the “all off” state if the battery voltage rises above –
10V and will remain there until the battery voltage drops
below –15V. This battery monitor feature draws a small
current from the battery (<1µA) and will add slightly to the
device’s overall power dissipation.
fault, the measured current at pin 6 (TBAT) and pin 23 (RBAT
)
will decrease as the device temperature increases. If the
device temperature rises sufficiently, the temperature shut-
down mechanism will activate and the device will default to
the “all off” state.
Temperature Shutdown
The thermal shutdown mechanism will activate when the
device temperature reaches a minimum of 110ϒC placing
the device in the “all off” state regardless of logic input.
During this thermal shutdown mode, pin 13 (TSD) will read
Protection
0V. Normal output of TSD is +V .
DD
Diode Bridge/SCR
The CPC7583 uses a combination of current limited break
switches, a diode bridge/SCR clamping circuit and a ther-
mal shutdown mechanism to protect the SLIC device or
other associated circuitry from damage during line tran-
sient events such as lightning. During a positive transient
condition, the fault current is conducted through the diode
bridge and to ground. During a negative transient of two or
four volts more negative than the battery, the SCR con-
ducts and faults are shunted to ground via the SCR and
diode bridge.
If presented with a short duration transient such as a light-
ning event, the thermal shutdown feature will not typically
activate. But in an extended power cross transient, the
device temperature will rise and the thermal shutdown will
activate forcing the switches to an “all off” state. At this
point the current measured at pin 6 (TBAT) and pin 23 (RBAT
)
will drop to zero. Once the device enters thermal shut-
down it will remain in the “all off” state until the temperature
of the device drops below the activation level of the ther-
mal shutdown circuit. This will return the device to the state
prior to thermal shutdown. If the transient has not passed,
current will flow at the value allowed by the dynamic DC
current limiting of the switches and heating will begin again,
reactivating the thermal shutdown mechanism. This cycle
Also, in order for the SCR to crowbar or foldback, the on
voltage (see Table 11) of the SCR must be less negative
than the battery reference voltage. If the battery voltage is
Rev. E
12
www.clare.com
CPC7583
of entering and exiting the thermal shutdown mode will
continue as long as the fault condition persists. If the mag-
nitude of the fault condition is great enough, the external
secondary protector could activate and shunt all current to
ground.
The thermal shutdown mechanism of the CPC7583 can
be disable by applying +VDD to pin 13 (TSD)
External Protection Elements
The CPC7583 requires only one overvoltage secondary pro-
tector on the loop side of the device. The integrated protec-
tion feature described above negates the need for protection
on the line side. The purpose of the secondary protector is to
limit voltage transients to levels that do not exceed the break-
down voltage or input-output isolation barrier of the CPC7583.
A foldback or crowbar type protector is recommended to mini-
mize stresses on the device.
Consult Clare’s app note, AN-100, “Designing Surge and
Power Fault Protection Circuits for Solid State Subscriber
Line Interfaces” for equations related to the specifications
of external secondary protectors, fused resistors, and PTCs.
Data Latch
The CPC7583 has an integrated data latch. The latch op-
eration is controlled by logic level input pin 18 (LATCH).
The data input of the latch is pin 15 (INTESTout), pin 16 (INRING
)
and pin 17 (INTESTin) of the device while the output of the
data latch is an internal node used for state control. When
LATCH control pin is at logic 0, the data latch is transpar-
ent and data control signals flow directly through to state
control. A change in input will be reflected in a change is
switch state. When LATCH control pin is at logic 1, the
data latch is now active and a change in input control will
not affect switch state. The switches will remain in the po-
sition they were in when the LATCH changed from logic 0
to logic 1 and will not respond to changes in input as long
as the latch is at logic 1. In addition, TSD input is not tied
to the data latch. Therefore, TSD is not affected by the
LATCH input and TSD input will override state control via
pin 15 (INTESTout), pin 16 (INRING) and pin 17 (INTESTin) and
the LATCH.
Rev. E
13
www.clare.com
CPC7583
Mechanical Dimensions
28 Pin SOIC
18.034+/-.127
(.710+/-.005)
10.312+/-.051
(.406+/-.003)
.330 x 45oMAX
(.013 x 45oMAX)
7.468+/-.127
(.294+/-.005)
3o- 7o
.250 Typ
(.010 Typ)
.813+/-.102
(.032+/-.004)
2.54+/-.127
(.100+/-.005)
1.27 Typ
(.050 Typ)
Dimensions
mm
(Inches)
Rev. E
14
www.clare.com
CPC7583
Notes:
Rev. E
15
www.clare.com
Worldwide Sales Offices
CLARE LOCATIONS
EUROPE
ASIA PACIFIC
Clare Headquarters
78 Cherry Hill Drive
Beverly, MA 01915
Tel: 1-978-524-6700
Fax: 1-978-524-4900
Toll Free: 1-800-27-CLARE
European Headquarters
CP Clare nv
Bampslaan 17
B-3500 Hasselt (Belgium)
Tel: 32-11-300868
Fax: 32-11-300890
Asian Headquarters
Clare
Room N1016, Chia-Hsin, Bldg II,
10F, No. 96, Sec. 2
Chung Shan North Road
Taipei, Taiwan R.O.C.
Tel: 886-2-2523-6368
Fax: 886-2-2523-6369
Clare Micronix Division
145 Columbia
Aliso Viejo, CA 92656-1490
Tel: 1-949-831-4622
Fax: 1-949-831-4628
France
Clare France Sales
Lead Rep
99 route de Versailles
91160 Champlan
France
Clare Switch Division
4315 N. Earth city Expressway
Earth City, MO 63045
Tel: 1-314-770-1832
Tel: 33 1 69 79 93 50
Fax: 33 1 69 79 93 59
Germany
Fax: 1-314-770-1812
Clare Germany Sales
ActiveComp Electronic GmbH
Mitterstrasse 12
SALES OFFICES
AMERICAS
85077 Manching
Germany
Tel: 49 8459 3214 10
Fax: 49 8459 3214 29
Americas Headquarters
Clare
78 Cherry Hill Drive
Beverly, MA 01915
Tel: 1-978-524-6700
Fax: 1-978-524-4900
Toll Free: 1-800-27-CLARE
Italy
C.L.A.R.E.s.a.s.
Via C. Colombo 10/A
I-20066 Melzo (Milano)
Tel: 39-02-95737160
Fax: 39-02-95738829
Eastern Region
Clare
P.O. Box 856
Mahwah, NJ 07430
Tel: 1-201-236-0101
Fax: 1-201-236-8685
Toll Free: 1-800-27-CLARE
Sweden
Clare Sales
Comptronic AB
Box 167
S-16329 Spånga
Tel: 46-862-10370
Fax: 46-862-10371
http://www.clare.com
Central Region
United Kingdom
Clare UK Sales
Marco Polo House
Cook Way
Bindon Road
Taunton
Clare Canada Ltd.
3425 Harvester Road, Suite 202
Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
Clare cannot assume responsibility for use of any circuitry other
than circuitry entirely embodied in this Clare product. No circuit
patent licenses nor indemnity are expressed or implied. Clare
reserves the right to change the specification and circuitry, with-
out notice at any time. The products described in this document
are not intended for use in medical implantation or other direct
life support applications where malfunction may result in direct
UK-Somerset TA2 6BG
Tel: 44-1-823 352541
Fax: 44-1-823 352797
Western Region
Clare
1852 West 11th Street, #348
Tracy, CA 95376
physical harm, injury or death to a person.
Tel: 1-209-832-4367
Fax: 1-209-832-4732
Toll Free: 1-800-27-CLARE
Canada
Clare Canada Ltd.
Specification: DS-CPC7583-RE
© Copyright 2001, Clare, Inc.
All rights reserved. Printed in USA.
8/1/01
3425 Harvester Road, Suite 202
Burlington, Ontario L7N 3N1
Tel: 1-905-333-9066
Fax: 1-905-333-1824
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