14535-00 [CLARE]
200-Column Cholesteric LCD Driver; 200列胆甾液晶显示驱动
| 型号： | 14535-00 |
| 厂家： | 
CLARE |
| 描述： | 200-Column Cholesteric LCD Driver |
| 文件： | 总20页 (文件大小：2392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MXED401
200-Column Cholesteric LCD Driver
FEATURES:
OVERVIEW:
• Drives Reflective-type Liquid Crystal
Displays
• Black-White or Gray-Scale
• Cholesteric LCD (ChLCD) Compatible
• 200 Output Channels, Cascadeable
• 192-Channel Mode
Clare introduces the MXED401, targeted
for the emerging non-volatile reflective LCD
market, specifically bi-stable and multi-stable
Cholesteric LCD’s. The MXED401 supports 200
phase-controlled voltage data outputs. This is
the first standard product driver for ChLCD display
panels.
• Token-Based Bi-directional Data
Transfer
• 6-Bit Data to support 64-Level
Gray-Scale
• ±2V to ±7V panel drive
• 4mA Minimum Source/Sink at ±7VOutput
Levels
• 2.5V to 5V logic supply
• 26 MHz clock frequency
• 4mA Minimum Source/Sink at ±7V Output
Levels
• Gold-Bumped Die @ 60 micron Output Pitch
FUNCTIONALDESCRIPTION:
The MXED401 driver functions as a level shifter with a resting state at ground potential. Proper
operation of the logic enables gray-scale capability. The output is a 128 Counter Clock (CCLK) event
where each channel is a low resistive switch to external symmetric (with respect to ground) voltage
supplies. Proper operation of the logic allows gray scale capability. The output is initially low (MV4)
from one to sixty-four CCLK times, then continuously high (PV4) for sixty-four CCLK times, returning
low for the balance of the 128 CCLK cycle (before returning to its quiescent value(VSS2)). The data
driver chip is manufactured in a high voltage (30 V) CMOS process andis available in gold-bumped-
die form.
The Token Bit Shift Register is used to control data latch timing for the Temporary Storage Register.
A token bit (initialized by SRIN input) is transferred sequentially among the 200 possible (internal)
outputs of the Shift register. This allows data to fill the Temporary Storage Register to in a Right to
Left fashion. When the Temporary Register is filled its contents may be transferred to the Output
Storage register via the LAT input. Output phase control is then accomplished by the Pulse Phase
Shift Logic, data then passes to the High Voltage Translator unit to control the three output switches
associated with each column output driver.
14580
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January 29, 2003
MXED401
FIGURE 1 - MXED401 BLOCK DIAGRAM
0197 0198 0199
00
01
02
PV4
VSS2
MV4
HIN=(PV4 – 4.0V)
XIN=4.75 TO 11.0V)
HIN
XIN
3-LEVEL OUTPUT STAGE
3
3
1
3
3
3
1
3
1
OUT0
LOGIC TO FORCE OUTPUT TO VSS2 AND HV TRANSLATOR INTERFACE
1
1
1
CCLK
CRB
INV
PULSE PHASE SHIFT LOGIC
6
6
1
6
6
1
6
6
1
6
6
1
6
6
1
6
6
1
LAT
OUTPUT STORAGE REGISTER (6 BITS X 200)
D(5:0)
TEMPORARY STORAGE REGISTER (6 BITS X 200)
SCLK
SHR
SEL200
SRIN
VDD1
VSS1
TOKEN BIT SHIFT REGISTER (1 BIT X 200)
SLIN
REN
5.0 VOLT
REGULATOR
PV4 – 4.0V
REGULATOR
HEN
HREF
TEST
CIRCUITRY
REG5V
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MXED401
MXED401 DATA SHEET
Table of Contents
FEATURES ....................................................................................................................1
OVERVIEW ....................................................................................................................1
FUNCTIONALDESCRIPTION .....................................................................................1
FIGURE 1 - MXED401 BLOCK DIAGRAM .................................................................2
TABLE 1 - ABSOLUTE MAXIMUM RATINGS ............................................................4
TABLE 2 - OPERATING CONDITIONS .......................................................................4
CIRCUIT DESCRIPTION ..............................................................................................5
FIGURE 2 - REGULATOR BLOCK DIAGRAM ...........................................................5
FIGURE 3 - EXAMPLE USING ON-CHIP REGULATOR............................................5
FIGURE 4 - EXAMPLE USING EXTERNAL BIAS......................................................5
FIGURE 5 - TYPICAL PIN VOLTAGEWAVEFORMS.................................................6
FIGURE 6 - HREF BLOCK DIAGRAM ........................................................................7
FIGURE 7 - EXAMPLE USING ON-CHIP HREF BIAS...............................................7
FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS ..........................................7
FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH .....................................8
FIGURE 10 -...................................................................................................................9
FIGURE 11 - ...................................................................................................................9
FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM ......................................... 10
FIGURE 13 THROUGH 15 - PHASE DETECTOR WAVEFORM EXAMPLES ........11
ELECTRICAL SPECIFICATIONS ........................................................................12-14
TABLE 3 - COLUMN DRIVER IC DESIGNATION TABLE ...................................... 15
TABLE 6 - AC CHARACTERISTICS ........................................................................ 16
FIGURE 16- OUTPUT WAVEFORMDEFINITION ................................................... 16
MECHANICAL SPECIFICATIONS ............................................................................ 17
DIE SPECIFICATIONS............................................................................................... 17
FIGURE 17 - DIE DIMENSIONAL DRAWING .......................................................... 18
TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER) ................................. 19
TABLE 5 - TRUTH TABLE (DATA LATCH) .............................................................. 19
ORDERING INFORMATION ...................................................................................... 20
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MXED401
ABSOLUTE MAXIMUM RATINGS
P a r a m e t e r
M in .
M a x .
7 . 0
U n it
S u p p l y v o l t a g e V D D 1
S u p p l y v o l t a g e P V 4
S u p p l y v o l t a g e M V 4
X IN i n p u t
-0.3
V
-0.3
9 . 0
V
-9.0
+ 0 . 3
V
-0.3
1 2 . 0
V
H IN i n p u t
P V 4 - 6 . 0
-0.3
P V 4 + 0 . 3
V D D 1 + 0 . 3
1 5 0
V
L o g i c i n p u t l e v e l s
S t o r a g e t e m p e r a t u r e
V
- 6 5
C e l s i u s
OPERATING CONDITIONS
P a r a m e t e r
M in .
2 . 5
M a x .
U n it
S u p p l y v o l t a g e V D D 1
S u p p l y V o l t a g e P V 4
S u p p l y V o l t a g e M V 4
H IN
5 . 5
V
V
V
2
7
-7
-2
P V 4 - 4 . 2
4 . 7 5
- 2 0
P V 4 - 3 . 8
X IN
1 1
8 0
V
Te m p e r a t u r e A m b i e n t
C e l s i u s
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MXED401
CIRCUIT DESCRIPTION
Voltage Regulator
This product may be operated from supplies as low as 2.5 Volts. The output drive transistors require
a voltage of 5.0 volts to 11.0 volts on the XIN pin to assure proper circuit operation. This bias voltage
may be developed on the chip or provided by the system designer. When XIN is provided externally,
the REN (Regulator ENable) pin is held low, and the FLYHI/FLYLO pins are left unconnected.
Systems lacking an available bias may use the on chip voltage regulator. The circuit is enabled by
forcing REN high (to VDD1). This will cause an on-chip oscillator/charge pump circuit to operate
continuously and output a somewhat regulated 5 volts at pin REG5V. A capacitor (CFLY=0.1uF) is
connected between pins FLYHI and FLYLO. A storage capacitor (CHOLD=1.0uF) is required on
REG5V. The XIN input is then connected to the REG5V output. The charge pump is capable of
driving 18 XIN loads so generally only one or two circuits are used as regulator sources. In systems
where more than one regulator circuit is enabled it is forbidden to short their respective HOLD
capacitors. Enabling the regulator causes an additional DC current of 65uA (130 uA maximum) to
flow from VDD1 to VSS1.
FIGURE 2 - REGULATOR BLOCK DIAGRAM
FIGURE 3 - EXAMPLE USING ON CHIP REGULATOR
FIGURE 4 - EXAMPLE USING EXTERNAL BIAS
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MXED401
FIGURE 5 - TYPICAL PIN VOLTAGE WAVEFORMS
HREF Bias Generator
The output stage requires a reference supply 3.8 to 4.2 volts lower than PV4 into each HIN input.
This may be provided by the system designer or generated on-chip. When HEN is held high, a bias
voltage is generated at the HREF output which is (PV4-4.0v). This generated voltage may then be
used to supply 6 HIN inputs. The HREF output must be stabilized by connecting a 0.1uF capacitor
between HREF and PV4. A separate stabilizing capacitor is required for each HREF used. It is
forbidden to connect any HREF pin to another HREF pin. Each enabled HREF output causes an
additional DC current of 60uA (130 uA maximum) to flow from PV4 to MV4.
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MXED401
FIGURE 6 - HREF BLOCK DIAGRAM
FIGURE 7 - EXAMPLE USING ON CHIP HREF BIAS
FIGURE 8 - EXAMPLE USING EXTERNAL HREF BIAS
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14580
MXED401
Data Input Procedure
A data synchronization bit is entered into the TOKEN bit shift register via the SRIN (or SLIN) on a
rising edge of SCLK. The token bit travels along the complete shift register path in order to control
data latching. The internal logic is shown below. Notice the use of the SCLK divider. SCLK frequency
is halved inside the IC to keep the current consumption to a minimum. The shift logic modifies the
input signals in a manner that requires input data (DAT5:0) to follow the SRIN synchronization bit by
2 SCLK rising edges. Initialization of the system is accomplished via the RB input pin. The 6-bit data
word is passed through the output register when pin LAT is LOW. When pin LAT is HIGH data is
latched in the output storage register.
The inputs SHR and SEL200 are set by the user to control SHift-Right (versus shift left) operation
and SELect 200 output configuration (versus 192 output configuration.). When SEL200 is LOW the
user ignores the output pads near the edge of the die. That is, ignore outputs O0-O3 and O196-
O199, use only outputs O4-O195. When SHR is HIGH data is loaded first into the lower number
outputs first and completes the load at the higher numbered outputs. For example, with SHR high
and SEL200 low the input data will load into register O4 first and complete the cycle by loading O195
on the last clock edge.
FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH
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MXED401
FIGURE 10 -
FIGURE 11 -
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MXED401
Phase Logic and Out0
The circuit has a 7-bit counter that is reset in a synchronous manner via the CRB (Counter-Reset-
Bar) and CCLK (Counter CLK) pins. The counter is “preset” to zero if the CRB pin is low when the
CCLK pin rises.
Each phase detector output is a 128 CCLK event. The INV pin will be assumed low for the purpose
of this discussion. Upon reset (via CRB) the output will be low. The output is always guaranteed to be
high continuously for 64 units of the 128 CCLK event. The output is also guaranteed to be low for 64
units of the 128 CCLK events, however, not usually continuously. The input data indicates which
event should be completed in order to allow the data to go high. For example, an input data word of
zero will cause the output to be low until the first rising edge of CCLK, then high for the subsequent
64 rising edges, then low again for the final 63 clocks. Notice that the output is always initially low for
at least one CCLK period. A fifty percent (50%) duty cycle is attained when 63 (2F-HEX) is the input
data; resulting in 64 units of low followed by 64 units of high.
The INV pin may invert the output from the above discussion. Pin INV must be high in order to
produce a 64 unit high followed by a 64 unit low pulse train. The OUT0 (OUTput ZERO) pin will
always command all outputs to zero volts potential (via the VSS2 input) irrespective of the individual
states of CCLK, CRB or data stored in the output storage register.
FIGURE 12 - SIMPLIFIED OUTPUT LOGIC DIAGRAM
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MXED401
FIGURES 13 - 15 - PHASE DETECTOR WAVEFORM EXAMPLES
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MXED401
DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Min
Max.
Unit
Condition
0.01
2.6
6.6
Vdd=2.5V Sclk=0MHz
Vdd=2.5V Sclk=26MHz
Vdd=3.3V Sclk=50MHz
Vdd=5.0V Sclk=50MHz
Logic supply current
IVDD1
mA
10.0
IDD1 due to REG5V ckt
PV4 supply current (DC)
IDDREG
130
uA
uA
REN=H (no XIN load)
HEN:L
IPV4DC1
60
PV4 supply current (DC)
XIN supply current (DC)
MV4 supply current (DC)
MV4 supply current(DC)
PV4 supply current(AC)
IMV4DC2
IXINDC
150
20
uA
uA
uA
uA
uA
HEN:H
IPV4DC1
IPV4DC2
IPV4AC
-60
HEN:L
-170
HEN:H
300
300
CCLK=2.5MHz
CCLK=2.5MHz
CCLK=2.5MHz
XIN current(AC)
IXINAC
IMV4AC
VIH
uA
uA
V
MV4 supply current(AC)
Logic input high voltage
Logic input low voltage
Logic output high voltage
Logic output low voltage
-450
VDD1-0.3
VIL
0.3
V
VOH
VOL
VDD1-0.5
V
IOH=1mA
IOL=-1mA
0.5
3
V
Logic input current high
level
IIH
IIL
3
uA
uA
Vinput=VDD1
Vinput=0V
Logic input current low
level
-3
-3
Output voltage high
Output voltage zero
VOH
VOO
+V4-0.02V
-0.020V
Iload=0
Iload=0
0.020V
PV4+-
0.02V
Output voltage low
VOL
Iload=0
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MXED401
DCELECTRICALCHARACTERISTICS(CONT.)
Parameter
Symbol
Min
Max.
Unit
Condition
REG5V fanout
HREF fanout
RFO
HFO
18
8
XIN loads
HIN loads
Output switch impedance
high
ZOH (1)
ZOO (1)
ZOL (1)
PV4-0.2V
-0.20V
Iload=-0.2mA (1)
Output switch impedance
zero
-0.2mA>Iload>0.2mA
(1)
0.20V
Output switch impedance
low
MV4+-
0.2V
Iload=0.2mA (1)
Output switch current high IOH
4
4
mA
mA
PV4=7,Vout=-7V
Output switch current sink
IOOL4
-4
-2
-4
Vout=4.0V, OUT0=H
Output switch current
source
IOOH4
IOOL2
IOOH4
mA
mA
mA
Vout=-4.0V,OUT0=H
Vout=2.0V, OUT0=H
Vout=-2.0V,OUT0=H
Output switch current sink
Output switch current
source
2
Output switch current low
IOL
mA
MV4=-7,Vout=+7V
(1) PV4 = 2V, MV4 = -2V
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MXED401
AC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
TSPWH
TSPWL
TSS
VDD1=>2.5V VDD1>3.2V
Unit
SCLK min pulse width high
SCLK min pulse width low
SCLK data setup time
SCLK data hold time
15
15
15
15
8
8
8
8
nS
nS
nS
nS
TSH
CCLK min pulse width high
CCLK min pulse width low
CCLK -CRB setup time
CCLK -CRB hold time
TCPWH
TCPWL
TCS
50
50
25
25
25
25
12
12
nS
nS
nS
nS
TCH
LAT min pulse width high
LAT min pulse width low
LAT fall after SCLK rise time
TLPWH
TLPWL
TSS
50
50
50
25
25
25
nS
nS
nS
LAT rise before SCLK rise
time
TSH
50
25
nS
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MXED401
COLUMN DRIVER IC DESIGNATION TABLE
S y m b o l N a m e
I/O
Designation
Function
O0 to O199
O
Column Drive Output
-
Output Gate
(Asynchronous)
OUT0
C R B
C C L K
INV
I
I
I
I
I
H:Vss2 ,
L:PV4, MV4
Counter Clear
Signal(synchronous)
L & CCLK Rising Edge: Counter Clear
H: Counter Enable L: disable
Pulse Phase Shifter
Counter Clock
Rising Edge : Count, Max 4MHz
L: Normal ,H: Invert (see Fig 14&15)
H : Latched, L: Transparent
Phase Shift Data Invert
Signal
Phase Shift Data Latch
Strobe
LAT
D[5:0]
S C L K
I
I
Phase Shift Data
Token Shift Clock
D(5) : MSB, D(0):LSB
Data entered on Rising Edges
H: Shift Right, Input is SRIN
L: Shift Left, Input is SLIN
S H R
I
I
Data Shift Direction
Data Output Select 200
or 192
H: SRIN to O000, (SHR:H) L: SRIN to
O004, (SHR:H)
S E L 2 0 0
Power Supply For Logic
System
V D D 1
V S S 1
P V 4
-
-
-
2.5 To 5.5V
0V
Logic Ground
Power Supply For LC
Drive
7 to 2V
Power Supply For LC
Drive
M V 4
-
-7 to -2V
SRIN
SLIN
HIN
I/O
I/O
I
Data Synchronization bit Input for SHR:H, Output for SHR:L
Data synchronization bit Input for SHR:L, Output for SHR:H
High Reference input
(PV4-4.0V) (see HREF/HIN also)
HREF source enable
signal
H E N
I
L: HREF not used , H: Enable HREF
H R E F
R E N
O
I
High Reference Output
Regulator Enable Input
(PV4-4.0V)Reference output
Enable:H, Disable:L
Voltage Regulator flying
capacitor.
0.1uF cap to FLYLO when REN:H
No connect when REN:L
FLYHI
-
Voltage Regulator flying 0.1uF cap to FLYHI when REN:H
FLYLO
R E G 5 V
XIN
-
O
I
capacitor.
No connect when REN:L
Regulated 5 volt output
1. 0uF cap to VSS1 When REN:H
Translator input bias
reference
Bias between +5.0V to +11.0V
V S S 2
R B
-
I
Output Driver Ground
Master Reset
0V
Reset :L , Normal:H
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MXED401
TABLE 6 - AC CHARACTERISTICS (See Fig. 16)
Parameter
Symbol
Min
Typ. Max. Unit
Condition
Shift Clk Frequency
Count Clk Frequency
Rising Time
26 MHz
VDD1 = 2.5V
VDD1=2.5V
SEE FIG. 16
SEE FIG. 16
4
5
5
MHz
us
Tr
-
-
Falling Time
Tf
us
PV4 Driver
Equivalent output resistance
PV4Ron
1.0 Kohm
Iout=200uA
Iout=200uA
MV4 Driver
Equivalent output resistance
MV4Ron
1.0 Kohm
us
PV4,MV4 Pulse Width
Output Delay Time
TPV4,TMV4
25
-
See Section 8
TBD
-
1
us
FIGURE 16 - OUTPUT WAVEFORM DEFINITION
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MXED401
MECHANICAL SPECIFICATIONS
DIE SPECIFICATIONS
Die Dimensions:
Measured from center of scribe to center of
"X" Dimension
"Y" Dimension
12830 µm
1760 µm
scribe
Measured from center of scribe to center of
scribe
Thickness
635 µm (nominal)
15±3 µm
Unthinned (non-back lapped wafer)
Gold Bump Height
Die Materials:
Passivation
Silicon Nitride (SiN)
45-75 HV
Silicon (Si)
Gold Bump Hardness
Wafer
Note: The active surface is sensitive to light. Cover with an opaque material after assembly.
COORDINATES RELATIVETOORIGIN(0, 0)AT MINIMUM PAD CENTER
LOCATION
Corners of Scribe Centers
Lower Left:
X = -115µm, Y = -205µm
X = 12715µm, Y = 1555µm
Upper Right:
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MXED401
FIGURE 17 - DIE DIMENSIONAL DRAWING
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MXED401
TABLE 4 - TRUTH TABLE (TOKEN BIT SHIFT REGISTER)
INPUT
Input-Output
Data to clock synchronization
SHR
H
SCLK
SEL200
SRIN
Input
SLIN
RisingEdge H
RisingEdge L
RisingEdge H
RisingEdge L
Output
Output
Input
D(5:0)sequenceO0,O1…O198,O199
D(5:0)sequenceO4,O5…O194,O195
D(5:0)sequenceO199,O198…O1,O0
D(5:0)sequenceO195,O194…O5,O4
H
Input
L
Output
Output
L
Input
TABLE 5 - TRUTH TABLE (DATA LATCH)
LAT
H
CONDITION
Latched
L
Open (Transparent)
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MXED401
ORDERING INFORMATION
MXED401
Ordering Part Number Package
14501-00
14526-00
14535-00
14539-00
Gold Bumped Die in Waffle Trays
Gold Bumped Die in Wafer Form
TCP (Tape Carrier Package) please consult factory
BGA (typically for prototyping only)
For additional information please visit our website at: www.clare.com
Clare, Inc. makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications
and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in Clare’s Standard Terms and Conditions of
Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability,
fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a person or severe property or environmental
damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
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