SA56_07 [CIRRUS]
PULSE WIDTH MODULATION AMPLIFIER; 脉冲宽度调制放大器
| 型号： | SA56_07 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | PULSE WIDTH MODULATION AMPLIFIER |
| 文件： | 总7页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-4&ꢀ8*%5)ꢀ.0%6-"5*0/ꢀ".1-*'*&3
SA56
M
I C R O T E C H N O L O G Y
)551ꢀꢁꢁ888ꢂ"1&9.*$305&$)ꢂ$0.ꢃꢃꢃꢄꢅꢆꢆꢇꢃꢈꢉꢊꢋ"1&9ꢃꢃꢃꢄꢅꢆꢆꢇꢃꢈꢉꢊꢋꢌꢍꢎꢏ
FEATURES
• DELIVERS UP TO 5A CONTINUOUS OUTPUT
• OPERATES AT SUPPLY VOLTAGES UP TO 60V
• NO “SHOOT-THROUGH” CURRENT
• THERMAL SHUTDOWN (OUTPUTS OFF) AT 160°C
• SHORTED LOAD PROTECTION (to VS or PGND or SHORTED
LOAD)
• NO BOOTSTRAP CAPACITORS REQUIRED
• PROGRAMMABLE ONBOARD PWM
APPLICATIONS
• DC BRUSH-TYPE MOTOR DRIVES
• POSITION AND VELOCITY SERVOMECHANISMS
• FACTORY AUTOMATION ROBOTS
• NUMERICALLY CONTROLLED MACHINERY
• COMPUTER PRINTERS AND PLOTTERS
23 PIN SIP
PACkAGE STYLE EX
DESCRIPTION
TheSA56isa5-amperePWMAmplifierdesignedformotion
controlapplications.Thedeviceisbuiltusingamulti-technology
processthatcombinesbipolarandCMOScontrolcircuitrywith
DMOS power devices in a single monolithic structure. Ideal
for driving DC and stepper motors, the SA56 accommodates
peak output currents up to 10 amperes. An innovative circuit
thatfacilitateslow-losssensingoftheoutputcurrenthasbeen
implemented. An on-board PWM oscillator and comparator
are used to convert an analog signal into PWM direction of
rotation and magnitude for motor control applications. TTL or
CMOSdigitalinputsallowdirectexternalcontrolin2-quadrant
or 4-quadrant modes.
FIGURE 1. BLOCK DIAGRAM
7%%
ꢀ7
74
ꢁꢂꢃ7
ꢌꢊꢀꢊꢅꢉꢊꢈꢃ
ꢅꢋꢊꢅꢌ
ꢅꢈ
ꢅꢆ
ꢅꢇ
ꢅꢂ
$
18.
18.
%*4"#-&
%*3
2ꢅ
2ꢈ
2ꢋ
2ꢌ
ꢈꢅꢊꢈꢈ
ꢈꢊꢋ
$POUSPMꢄMPHJD
BOE
18.ꢄ(FOFSBUPS
"
#
(BUFꢄ%SJWFꢄ
BOEꢄ
$POUSPMꢄ
065
*
ꢇ
4&/
065
ꢅꢀ
ꢅꢅ
ꢆ
73&'
'"6-5
5-*.
4$
ꢂ
4"ꢀꢂ
1VMTFꢄ8JEUIꢄ.PEVMBUJPO
"NQMJGJFS
ꢉꢊꢅꢃ
ꢅꢊꢈꢋ
1(/%
4*((/%
APEX MICROTECHNOLOGY CORPORATION • TELEPHONE (520) 690-8600 • FAX (520) 888-3329 • ORDERS (520) 690-8601 • EMAIL prodlit@apexmicrotech.com
1
ABSOLUTE MAXIMUM RATINGS
SPECIFICATIONS
SA56
SUPPLY VOLTAGE, VDD
SUPPLY VOLTAGE, VS
5.5V
60V
ABSOLUTE MAXIMUM RATINGS
PEAK OUTPUT CURRENT (100mS)
CONTINUOUS OUTPUT CURRENT
POWER DISSIPATION
10A
5A
125W
POWER DISSIPATION (TA = 25°C, Free Air)
JUNCTION TEMPERATURE, TJ(MAX)
ESD SUSCEPTIBILITY (Logic Pins Only)
STORAGE TEMPERATURE, TSTG
LEAD TEMPERATURE (Soldering, 10 sec.)
JUNCTION TEMPERATURE, TJ
10W
150°C
1500V
–40°C to +150°C
300°C
–40°C to +150°C
SPECIFICATIONS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VS
12
60
5.5
0.6
V
V
Ω
VDD
4.5
SWITCH ON RESISTANCE, RDS(ON)
N-Channel
SWITCH ON RESISTANCE, RDS(ON)
P-Channel
CLAMP DIODE FORWARD DROP, VCLAMP
LOGIC LOW INPUT VOLTAGE, VIL
Output Current = 5A
Output Current = 5A
Clamp Current = 5A
0.23
0.27
1.43
0.6
Ω
V
V
-0.5
0.8
LOGIC LOW INPUT CURRENT, IIL
LOGIC HIGH INPUT VOLTAGE, VIH
VIN = –0.1V
VIN = 5.5V
-10
2
+10
VDD
µA
V
LOGIC HIGH INPUT CURRENT, IIH
CURRENT SENSE OUTPUT
-10
180
.79
10
300
1.32
±5
±8
±8
µA
µA
mA
%
%
%
I
OUT = 1A
OUT = 5A
240
1.0
±1
I
CURRENT SENSE LINEARITY ERROR
1A ≤ IOUT ≤ 5A
100 mA ≤ IOUT ≤ 5A
5A ≤ IOUT ≤ 10A (Peak Currents only)
SHUTDOWN TEMPERATURE, TJSD
QUIESCENT SUPPLY CURRENT, IS
QUIESCENT SUPPLY CURRENT, IDD
OUTPUT TURN-ON DELAY TIME, tDon
OUTPUT TURN-ON SWITCHING TIME, ton
OUTPUT TURN-OFF DELAY TIMES, tDoff
Outputs Turn OFF
No Load, FSW = 100kHz 50% DUC
No Load, FSW = 100kHz 50% DUC
No Load
No Load
No Load
160
26
6
200
41
272
46
°C
mA
mA
ns
ns
ns
50
15
OUTPUT TURN-OFF SWITCHING TIME, toff No Load
ns
MINIMUM INPUT PULSE WIDTH, tp
(DIGITAL MODE)
No Load
140
ns
REFERENCE VOLTAGE
IREF = 1mA
2.3
1
2.5
2.7
1
V
mA
V
Vref OUTPUT CURRENT (Vref 2.5V), IREF
Source Only, No current sink capability
Load Current = 400µA
ANALOG INPUT RANGE FOR
FULL MODULATION
4
HIGH CURRENT SHUTDOWN RESPONSE Output shorted
(No bypass capacitor at SCin pin)
250
800
ns
THERMAL
RESISTANCE, Junction to Case
RESISTANCE, Junction to Air
TEMPERATURE RANGE, Case
Full Temperature Range
Full Temperature Range
1
°C/W
°C/W
°C
12.21
-40
125
NOTE: These specifications apply for VS = 50V and VDD = 5V at 25°C, unless otherwise specified.
2APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739
TYPICAL
PERFORMANCE GRAPHS
SA56
ꢁ7ꢀ4VQQMZꢀ$VSSFOUꢀꢂ*%%ꢃꢀWTꢀ4VQQMZꢀ7PMUBHFꢀꢂ74ꢃ
4VQQMZꢀ$VSSFOUꢀꢂ*4ꢃꢀWTꢀ4VQQMZꢀ7PMUBHFꢀꢂ74ꢃ
ꢀ4VQQMZꢀ$VSSFOUꢀꢂ*4ꢃꢀWTꢀ'SFRVFODZꢀ
ꢅꢊꢆ
ꢊꢏ
ꢈꢅꢇꢈ
ꢊꢆ
ꢊꢋ
ꢊꢄ
ꢇ
ꢅꢊꢋ
ꢅꢊꢄ
ꢅꢄꢇ
ꢅꢄꢏ
ꢅꢄꢆ
ꢅꢄꢋ
ꢄ
ꢈꢅꢇ
ꢈꢅꢐꢈ
ꢈꢅꢐ
ꢏ
ꢆ
ꢈꢅꢏꢈ
!ꢀꢋꢌꢀL)[ꢀꢈꢄꢍꢀ%6$
ꢋ
!ꢀꢋꢌꢀL)[ꢀꢈꢄꢍꢀ%6$
ꢄ
ꢈꢅꢏ
ꢄ
ꢊꢄ ꢋꢄ ꢌꢄ ꢆꢄ ꢈꢄ ꢏꢄ ꢐꢄ
74ꢁꢀꢂ7ꢃ
ꢄ
ꢊꢄ ꢋꢄ ꢌꢄ ꢆꢄ ꢈꢄ ꢏꢄ ꢐꢄ
74ꢁꢀꢂ7ꢃ
ꢄ
ꢈꢄ ꢊꢄꢄ ꢊꢈꢄ ꢋꢄꢄ ꢋꢈꢄ ꢌꢄꢄ ꢌꢈꢄ
'SFRVFODZꢁꢀꢂL)[ꢃ
ꢀꢁ7ꢀ4VQQMZꢀ$VSSFOUꢀꢂ*%%ꢃꢀWTꢀ'SFRVFODZ
4VQQMZꢀ$VSSFOUꢀꢂ74ꢃꢀWTꢀ5FNQFSBUVSF
ꢋꢄ
ꢁ7ꢀ4VQQMZꢀ$VSSFOUꢀꢂ7%%ꢃꢀWTꢀ5FNQFSBUVSF
ꢅꢄꢄꢏꢊꢈ
ꢐ
74ꢀꢎꢊꢋ7
ꢅꢄꢄꢏꢊꢄ
ꢅꢄꢄꢏꢄꢈ
ꢅꢄꢄꢏꢄꢄ
ꢅꢄꢄꢈꢉꢈ
ꢅꢄꢄꢈꢉꢄ
74ꢀꢎꢀꢏꢄ7
ꢊꢈ
ꢏꢅꢈ
74ꢀꢎꢀꢈꢄ7
ꢏ
74ꢀꢎꢀꢈꢄ7
74ꢀꢎꢀꢊꢋ7
ꢊꢄ
ꢈ
74ꢀꢎꢀꢏꢄ7
ꢈꢅꢈ
!ꢀꢋꢌꢀL)[ꢀꢈꢄꢀꢍꢀ%6$
!ꢀꢋꢌꢀL)[ꢀꢈꢄꢀꢍꢀ%6$
7%%ꢀꢎꢀꢈꢀ7
7%%ꢀꢎꢀꢈ7
ꢈ
ꢑꢈꢄ
ꢄ
ꢄ
ꢈꢄ
ꢊꢄꢄ
ꢄ
ꢈꢄ ꢊꢄꢄ ꢊꢈꢄ ꢋꢄꢄ ꢋꢈꢄ ꢌꢄꢄ ꢌꢈꢄ
'SFRVFODZꢁꢀꢂL)[ꢃ
ꢑꢈꢄ
ꢄ
ꢈꢄ
ꢊꢄꢄ
5FNQFSBUVSFꢁꢀꢂ$ꢃ
5FNQFSBUVSFꢁꢀꢂ$ꢃ
%6$ꢀWTꢀ"OBMPHꢀ*OQVU
$18.ꢀWTꢀ'48ꢀBUꢀ7BSZJOHꢀ5FNQFSBUVSFT
'SFRVFODZꢀWTꢀ$18.
ꢊꢄꢄ
ꢉꢄ
ꢇꢄ
ꢐꢄ
ꢏꢄ
ꢈꢄ
ꢆꢄ
ꢌꢄ
ꢋꢄ
ꢊꢄ
ꢄ
ꢊ.
ꢊꢄꢄ,
ꢊꢄ,
ꢊ,
ꢊ.
'48ꢀ!ꢀꢇꢈ$
"065
'48ꢀ!ꢀꢈꢄ$
ꢊꢄꢄ,
ꢊꢄ,
ꢊ,
'
48ꢀ!ꢀꢑꢋꢈ$
#065
7%%ꢀꢎꢀꢈ7ꢁꢀ74ꢀꢎꢀꢈꢄ7
ꢊ,
ꢄ
ꢊ
ꢋ
ꢌ
ꢆ
ꢊꢄꢄ
ꢊꢄ,
ꢊꢄꢄ
ꢊ,
ꢊꢄ,
"OBMPHꢀ*OQVUꢁꢀꢂ7ꢃ
$18.ꢁꢀꢂQ'ꢃ
$18.ꢁꢀꢂQ'ꢃ
-PBEꢀ$VSSFOUꢀWTꢀ5PUBMꢀ0Oꢀ3FTJTUBODF
.BYJNVNꢀ%VUZꢀ$ZDMFꢀGPS
$MBNQꢀ%JPEFꢀ'PSXBSEꢀ7PMUBHFꢀ%SPQ
ꢈ
-JOFBSꢀ0QFSBUJPOꢀJOꢀ"OBMPHꢀ.PEFꢀ
ꢄꢅꢈꢋꢈ
ꢊꢄꢄ
ꢆꢅꢈ
ꢆ
ꢄꢅꢈꢋ
ꢄꢅꢈꢊꢈ
ꢄꢅꢈꢊ
/PꢀMPBE
ꢉꢄ
ꢌꢅꢈ
ꢌ
řꢀꢈ"ꢀ-PBE
ꢇꢄ
ꢋꢅꢈ
ꢋ
ꢄꢅꢈꢄꢈ
ꢄꢅꢈ
ꢐꢄ
ꢊꢅꢈ
ꢊ
ꢄꢅꢆꢉꢈ
ꢏꢄ
ꢄꢅꢆꢉ
ꢄꢅꢈ
ꢄ
74ꢀꢎꢀꢏꢄ7ꢀ7%%ꢀꢎꢀꢈ7ꢀ
ꢈꢄ
ꢂ1ꢀBOEꢀ/ꢀ$IBOꢃꢀBUꢀꢊꢄꢄꢍꢀ%6$
ꢄꢅꢆꢇꢈ
ꢄ
ꢊꢄꢄ,
'SFRVFODZꢁꢀꢂL)[ꢃ
ꢋꢄꢄ,
ꢌꢄꢄ, ꢆꢄꢄ,
ꢄ
ꢄꢅꢈ
ꢊ
ꢊꢅꢈ
ꢄ
ꢊ
ꢋ
ꢌ
ꢆ
ꢈ
%JPEFꢀ'PSXBSEꢀ7PMUBHFꢁꢀ7'ꢀꢂ7ꢃ
-PBEꢀ$VSSFOUꢁꢀꢂ"ꢃ
APEX MICROTECHNOLOGY CORPORATION • TELEPHONE (520) 690-8600 • FAX (520) 888-3329 • ORDERS (520) 690-8601 • EMAIL prodlit@apexmicrotech.com
3
TYPICAL
PERFORMANCE GRAPHS
SA56
*
-0"%ꢀWTꢀ3%40/
*-0"%ꢀWTꢀ3%40/
*
-0"%ꢀWTꢀ*4&/4&
0.5
ꢏꢁꢄ
ꢏꢁꢂꢄ
ꢏꢁꢂ
ꢈꢁꢀ
ꢈ
RDSON = 125°C
3%40/ꢋꢒꢋꢈꢀꢄ°C
0.45
0.4
ꢈꢏꢏꢑꢋ%6$ꢋꢌ*4&/4&ꢋ"ꢍ
0.35
0.3
ꢏꢁꢉꢄ
ꢏꢁꢉ
ꢏꢁꢃ
ꢏꢁꢅ
ꢏꢁꢂ
ꢏꢁꢀ
ꢏ
0.25
0.2
ꢏꢁꢀꢄ
ꢏꢁꢀ
RDSON = -25°C
RDSON = 0°C
ꢏꢑꢋ%6$ꢋꢌ*4&/4&ꢋ#ꢍ
3%40/ꢋꢒꢋꢃꢄ°C
RDSON = 50°C
RDSON = 85°C
0.15
0.1
ꢏꢁꢈꢄ
ꢏꢁꢈ
3%40/ꢋꢒꢋꢄꢏ°C
3%40/ꢋꢒꢋꢏ°C
3%40/ꢋꢒꢋꢎꢀꢄ°C
ꢈꢏꢏꢑꢋ%6$ꢋGPSꢋ1ꢋ$IBOOFM
0.05
0
ꢏꢁꢏꢄ
ꢏ
ꢈꢏꢏꢑꢋ%6$ꢋGPSꢋ/ꢋ$IBOOFM
0
1
2
3
4
5
ꢅ
ꢄ
ꢏ
ꢀ
ꢂ
ꢅ
ꢏ
ꢈ
ꢀ
ꢉ
ꢂ
ꢄ
*-0"%ꢊꢋꢌ"ꢍ
*
-0"%ꢋꢌ"ꢍ
*-0"%ꢊꢋꢌ"ꢍ
*
-0"%ꢁ*4&/4&ꢀ3"5*0ꢀWTꢀ*-0"%
*
-0"%ꢁ*4&/4&ꢀWTꢀ*-0"%
ꢀ
*4&/4&ꢀWTꢀ*-0"%
ꢂꢃꢏꢏ
ꢂꢅꢏꢏ
ꢂꢂꢏꢏ
ꢂꢀꢏꢏ
ꢂꢏꢏꢏ
ꢉꢃꢏꢏ
ꢉꢅꢏꢏ
ꢂꢆꢏꢏ
ꢂꢅꢏꢏ
ꢂꢄꢏꢏ
ꢂꢂꢏꢏ
ꢂꢉꢏꢏ
ꢂꢀꢏꢏ
ꢂꢈꢏꢏ
ꢂꢏꢏꢏ
ꢉꢇꢏꢏ
ꢉꢃꢏꢏ
ꢈꢁꢀ
ꢈ
ꢎꢀꢄ$
ꢏ$
ꢈꢀꢄ$
ꢃꢄ$
ꢏꢑꢋ%6$ꢋꢌ*4&/4&ꢋ#ꢍ
ꢄꢏ$
ꢃꢄ$
ꢄꢏ$
ꢏꢁꢃ
ꢏꢁꢅ
ꢏꢁꢂ
ꢏꢁꢀ
ꢏ
ꢏ$
ꢈꢏꢏꢑꢋ%6$ꢋꢌ*4&/4&ꢋ"ꢍ
ꢈꢀꢄ$
ꢎꢀꢄ$
7BSZJOHꢋ5FNQFSBUVSFT
!ꢋꢏꢑꢋ%6$ꢊꢋ*4&/4&ꢋ#
!ꢋꢏꢑꢋ%6$ꢊꢋ*4&/4&ꢋ#
ꢏ
ꢈ
ꢀ
ꢉ
ꢂ
ꢄ
ꢏ
ꢀ
ꢂ
ꢏ
ꢈ
ꢀ
*
ꢉ
ꢂ
ꢄ
*-0"%ꢋꢌ"ꢍ
*
-0"%ꢊꢋꢌ"ꢍ
-0"%ꢊꢋꢌ"ꢍ
*
-0"%ꢁ*4&/4&ꢀ3"5*0ꢀWTꢀ*-0"%
73&'ꢀWTꢀ5&.1&3"563&
*
4&/4&ꢀWTꢀ*-0"%
ꢈꢁꢀ
ꢈ
ꢄꢏꢏꢏ
ꢂꢇꢏꢏ
ꢂꢃꢏꢏ
ꢂꢆꢏꢏ
ꢂꢅꢏꢏ
ꢂꢄꢏꢏ
ꢂꢂꢏꢏ
ꢂꢉꢏꢏ
ꢂꢀꢏꢏ
ꢂꢈꢏꢏ
ꢂꢏꢏꢏ
ꢀꢁꢂꢇꢄ
ꢀꢁꢂꢇꢂ
ꢀꢁꢂꢇꢉ
ꢀꢁꢂꢇꢀ
ꢀꢁꢂꢇꢈ
ꢀꢁꢂꢇ
ꢈꢀꢄ$
ꢃꢄ$
ꢎꢀꢄ$
ꢏ$
ꢃꢄ$
ꢄꢏ$
ꢏꢁꢃ
ꢏꢁꢅ
ꢏꢁꢂ
ꢏꢁꢀ
ꢏ
ꢄꢏ$
ꢀꢁꢂꢃꢇ
ꢀꢁꢂꢃꢃ
ꢀꢁꢂꢃꢆ
ꢀꢁꢂꢃꢅ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢂ
ꢏ$
ꢎꢀꢄ$
ꢈꢀꢄ$
7BSZJOHꢋ5FNQFSBUVSFT
!ꢋꢈꢏꢏꢑꢋ%6$ꢊꢋ*4&/4&ꢋ"
ꢈꢏꢏꢑꢋ%6$ꢋꢌ*4&/4&ꢋ"ꢍ
ꢎꢂꢏ ꢎꢀꢏ
ꢏ
ꢀꢏ ꢂꢏ ꢅꢏ ꢃꢏ ꢈꢏꢏ
ꢏ
ꢈ
ꢀ
ꢉ
ꢂ
ꢏ
ꢈ
ꢀ
ꢉ
ꢂ
ꢄ
5FNQFSBUVSFꢊꢋꢌ$ꢍ
*-0"%ꢊꢋꢌ"ꢍ
*-0"%ꢊꢋꢌ"ꢍ
4APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739
OPERATING
CONSIDERATIONS
SA56
GENERAL
Please read "SA56 Design Ideas" that covers the various
SA56 applications in considerable detail. Also see Application
Note1"GeneralOperatingConsiderations"whichcoversstabil-
ity, power supplies, heat sinking, mounting, and specification
interpretation. Visit www.apexmicrotech.com for design tools
that help automate tasks such as calculations for stability,
internal power dissipation, current limit, heat sink selection,
Apex's complete Application Notes library, Technical Seminar
Workbook and Evaluation Kits.
be logic low. When a junction temperature
exceeds approximately 160°C this pin will
change to logic high and the output will be
latched off. Grounding this pin disables over
temperature protection. This pin should be
left open if over temperature protection is
desired but the flag is not used.
Current Sense output and programmable
current limit. A current proportional to the
output current is sourced by this pin. Typi-
cally this pin is connected to a resistor for
programmable current limit or transconduc-
tance operation.
8
ISEN
GROUND PINS
The two SIGGND pins, 9 & 10, are for input signal grounds.
Pins 1 and 23, PGND, are power grounds. The PGND & SIGGND
pins are connected at one point inside the IC. It is also recom-
mendedtheuserconnectbothpinsatasinglepointontheboard
in a way that no current flows through that connection.
9,10 SIGGND
Groundconnectionforallinternaldigitaland
low-current analog circuitry.
11
FAULT
This pin latches high whenever the four
MOSFETs have been placed in the tristate
condition which occurs when either the
high-current or the thermal protection has
engaged.
An external timing capacitor is connected to
this pin to set the frequency of the internal
oscillator and ramp generator for analog
control mode. The capacitor value (pF)
= 4.05x107/FSW, where FSW = the desired
switching frequency. This pin is grounded
for digital control mode.
POWER SUPPLY BYPASSING
BypasscapacitorstopowersupplyterminalsVS andVDD must
be connected physically close to the pins to prevent erratic,
low-efficiency operation and excessive ringing at the outputs.
Electrolytic capacitors, at least 10 μF per output ampere are
requiredforsuppressingVS toPGND noise.Highqualityceramic
capacitors (X7R) 1 μF or greater should also be used. Only ca-
pacitorsratedforswitchingapplicationsshouldbeconsidered.
The bypass capacitors must be located as close to the power
supply pins as possible. Due to the very fast switching times
of the outputs, the inductance of 1 inch of circuit trace could
cause noticeable degradation in performance. The bypassing
requirements of VDD are less stringent, but still necessary. A
0.1 μF to 0.47 μF capacitor connected directly between the
VDD and SIGGND pins will suffice.
12
CPWM
13,14 VDD
5V supply for input logic and low voltage
analog circuitry.
15
16
VREF
DIR
Reference voltage. Can be used at low cur-
rent for biasing analog loop circuits.
Direction of rotation control; In 2 quadrant,
digital control, determines the active output
FETs.Thispinshouldbegroundedinanalog
control mode.
CMOS/TTL input for digital PWM control, or
1-4V analog input for duty cycle control in
analog control mode.
PIN DESCRIPTIONS
Pin # Name
1,23 PGND
Description
Powerhighcurrentgroundreturnpathofthe
motor.
Half bridge output B
High voltage supply
17
18
PWM
2,3
BOUT
DISABLE Following a fault, pulling the DISABLE pin
HIGH and then LOW will reset a latched
fault condition. (When pulled HIGH, all four
outputMOSFETsaredisabled. AlogicLOW
on this pin allows the four output FETs to
function normally.) When the DISABLE and
FAULT pins are tied to a microcontroller, the
FAULT pin will generate an interrupt in the
microcontroller, so that the interrupt, can in
turn, generate a pulse on the DISABLE pin.
When a fault occurs, the SA56 fault circuitry
will be reset.
4,5, VS
19,20
6
SC
Theshort-circuitprotectioncircuitswillsense
a direct short from either output (AOUT or
BOUT) to PGND or VS – as well as across the
load. If the high-current protection circuit
engagesitwillplaceallfourMOSFETsinthe
tristate state (high-impedance output). The
SC output, pin 6, will go HIGH though not
latch, thereby denoting that this protection
feature has been triggered.
7
TLIM
Temperature limit, CMOS. This pin can be
used as a flag for an over-temperature con-
dition. Under normal operation this pin will
21,22 AOUT
Half bridge output A
APEX MICROTECHNOLOGY CORPORATION • TELEPHONE (520) 690-8600 • FAX (520) 888-3329 • ORDERS (520) 690-8601 • EMAIL prodlit@apexmicrotech.com
5
OPERATING
CONSIDERATIONS
SA56
MODES OF OPERATION
The following chart shows the 3 modes of operation.
Mode
CPWM
PWM
DIR
AOUT
BOUT
pin 12
pin 17
pin 16
pins 21, 23
pins 2, 3
2 Quadrant – Analog Mode
Connect ca-
pacitor to set
frequency
Analog control
voltage
Low (SIGGND
)
Control voltage
greater than VREF
(AOUT – BOUT)< 0
average
Control voltage
:
greater than VREF
(BOUT – AOUT)> 0
average
:
(1 – 4V)
voltage
voltage
2 Quadrant – Digital Mode
SIGGND
SIGGND
SIGGND
Modulation In
Modulation In
High (VDD
)
High (VS)
PWM
PWM
High (VS)
DIR
Low (SIGGND
)
4 Quadrant – Digital Mode
High (VDD
)
Modulated In
DIR
4-QUADRANT - ANALOG MODE
2-QUADRANT - DIGITAL MODE
The SA56 can operate in 4-quadrant mode with analog or
digital inputs. In the analog mode, the capacitor from CPWM to
SIGGND sets the frequency of an internal triangular ramp sig-
nal. See Figure 2. An analog voltage applied to the PWM pin
is compared to a 2.5 volt reference within the SA56 thereby
governing the duty cycle of the output. Note that the analog
pin DIR pin 16 is connected to signal ground (SIGGND).
Two-quadrant operation of the FETs is realized by driving
PWM pin 17 of the SA56 with a digital PWM signal supplied
by a microcontroller or DSP, as depicted in Figure 3. When
using a digital modulation signal, connect the CPWM pin to
SIGGND to disable the internal oscillator and its companion
ramp generator.
A digital PWM signal applied to the PWM pin controls the
output duty cycle at one output pin while the other output pin is
held "HIGH". The input at the DIR pin (VDD or SIGGND) governs
the output behavior. If DIR is a logic HIGH, the AOUT output
will be held high and the BOUT output will be switched as the
complement of the PWM input signal. The average output at
AOUT will always be greater than at BOUT. Whereas if DIR is a
logic LOW, the BOUT output will be held "HIGH" and the AOUT
output will be switched.
74
7%%ꢄ
$ꢋ
$ꢊꢄ
$ꢉꢄ
$ꢂꢄ
ꢅꢄ
4$
ꢇꢄ
5-*.ꢄ
ꢂꢊꢁꢂꢋꢄ
7%%ꢄ
ꢂꢅꢄ
ꢂꢆꢄ
ꢂꢂꢄ
ꢋꢁꢈꢁꢂꢀꢁꢉꢃꢄ
%*3ꢄ
74ꢄ
.PUPS
%*4"#-&ꢄ
ꢉꢂꢁꢉꢉ
ꢉꢁꢊ
"
#
065
'"6-5ꢄ
18.ꢄ
73&'
4"ꢀꢁ
065
"OBMPHꢄ$POUSPM
7PMUBHFꢄꢌꢂꢍꢋ7ꢎ
ꢂꢇꢄ
ꢂꢈꢄ
ꢂꢉꢄ
Operating in two-quadrant mode reduces switching noise
and power dissipation, but limits the ability to control the motor
at very low speed.
ꢀꢁꢂꢃ
4*((/%
1(/%
ꢂꢁꢄꢉꢊ
$
18.ꢄ
*
4&/ꢄ
ꢆꢄ
74
7%%ꢄ
34&/4&ꢄ
$ꢋ
$ꢊꢄ
$ꢉꢄ
$ꢂꢄ
ꢅꢄ
4$
ꢇꢄ
5-*.ꢄ
ꢂꢊꢁꢂꢋꢄ
7%%ꢄ
'*(63&ꢂꢃꢄꢄꢄꢋm26"%3"/5ꢄ"/"-0(ꢄ01&3"5*0/
ꢂꢅꢄ
ꢂꢆꢄ
ꢋꢁꢈꢁꢂꢀꢁꢉꢃꢄ
%*3ꢄ
7%%ꢄPSꢄ4*((/%
74ꢄ
.PUPS
%*4"#-&ꢄ
ꢉꢂꢁꢉꢉ
ꢉꢁꢊ
OPERATING WITH DIGITAL INPUTS
"
#
065
ꢂꢂꢄ
ꢂꢇꢄ
ꢂꢈꢄ
ꢂꢉꢄ
'"6-5ꢄ
18.ꢄ
73&'
4"ꢀꢁ
065
Two and 4-quadrant operation are possible with the SA56
whendrivenwithadigitalPWMsignalfromamicrocontrolleror
DSP. When using a digital modulation signal, tie the CPWM pin
to SIGGND to disable the internal oscillator and ramp generator.
When operating in the digital mode, pulse widths should be no
less than 100 ns and the switching frequency should remain
less than 500 kHz. This will allow enough time for the output
MOSFETs to reach their full on and off states before receiving
a command to reverse state.
ꢀꢁꢂꢃ
+
4*((/%
1(/%
ꢂꢁꢄꢉꢊ
$
18.ꢄ
*
4&/ꢄ
ꢆꢄ
34&/4&ꢄ
'*(63&ꢂꢃꢄꢄꢄꢉꢌ26"%3"/5ꢄmꢄ%*(*5"-ꢄ.0%&
6APEX MICROTECHNOLOGY CORPORATION • 5980 NORTH SHANNON ROAD • TUCSON, ARIZONA 85741 • USA • APPLICATIONS HOTLINE: 1 (800) 546-2739
OPERATING
CONSIDERATIONS
SA56
Short-circuitprotection–Theshort-circuitprotectioncircuits
will sense a direct short from either output (AOUT or BOUT) to
PGND or VS – as well as across the load. If the high-current
protection circuit engages, it will place all four MOSFETs in
the tristate state (high-impedance output). The SC output, pin
6, will go HIGH though not latch, thereby denoting that this
protection feature has been triggered.
Over-current protection – When the current on the high side
goes above 10 amperes peak, the over-current circuit tristates
so that the four MOSFETs go into a latched fault condition.
Thermal protection – The thermal protection circuits will en-
gage if the temperature of any of the four MOSFETs reaches
approximately 160°C. If this occurs, the FAULT output pin will
go HIGH. If the thermal protection circuit engages, it will place
allfourMOSFETsinthetristatestate(high-impedanceoutput).
The TLIM output which is normally LOW will go HIGH, though
not latch, thereby denoting which of the protection features
has been triggered.
4 QUADRANT DIGITAL MODE
During four-quadrant operation a single digital PWM input
includesmagnitudeanddirectioninformation.ThedigitalPWM
input signal is applied to the DIR pin, as shown in Figure 4,
and the PWM pin is tied HIGH to VDD. Both pairs of output
MOSFETs will switch in a locked, complementary fashion.
With a 50% duty cycle the average voltage of outputs
AOUT and BOUT will be the same, which is half of VS so that the
average differential voltage over each period applied to the
load will therefore be zero.
Four-quadrant operation allows for smooth transitions
through zero current for low-speed applications. However,
powerdissipationisslightlyhigherthanintwo-quadrantopera-
tion since all four output MOSFETs must switch every cycle.
74
7%%ꢄ
$ꢋ
$ꢊꢄ
$ꢉꢄ
$ꢂꢄ
ꢅꢄ
4$
ꢇꢄ
5-*.ꢄ
ꢂꢊꢁꢂꢋꢄ
7%%ꢄ
ꢂꢅꢄ
ꢂꢆꢄ
ꢋꢁꢈꢁꢂꢀꢁꢉꢃꢄ
%*3ꢄ
74ꢄ
+
PROGRAMMABLE CURRENT LIMIT
.PUPS
%*4"#-&ꢄ
ꢉꢂꢁꢉꢉ
ꢉꢁꢊ
"
#
065
The ISEN pin sources a current proportional to the forward
output current of the active P channel output MOSFET. The
proportionalityisapproximately200microamperesperampere
of output current. Note that the ISEN output is blocked during
the switching transitions when current spikes are likely to be
significant.
ꢂꢂꢄ
ꢂꢇꢄ
ꢂꢈꢄ
ꢂꢉꢄ
'"6-5ꢄ
18.ꢄ
73&'
4"ꢀꢁ
065
7%%
ꢀꢁꢂꢃ
4*((/%
1(/%
ꢂꢁꢄꢉꢊ
$
18.ꢄ
*
4&/ꢄ
ꢆꢄ
34&/4&ꢄ
To create a programmable current limit, connect a resistor
from ISEN to SIGGND. If the voltage across this resistor exceeds
an internally-generated 2.75V threshold, all four output MOS-
FETs will be turned off for the remainder of the switching cycle.
A 2.7k-Ohm resistor will set the current limit at approximately
5 amperes.
'*(63&ꢂꢃꢄꢄꢄꢋꢌ26"%3"/5ꢄmꢄ%*(*5"-ꢄ.0%&
BRAkING – DIGITAL MODE
Under digital control, the SA56 can rapidly decelerate the
motor by shunting the winding currents through the output
MOSFETs. Logic LOW on the PWM input both A and B out-
puts high. The motor winding current circulates through the on
resistance of the MOSFETs quickly slowing the motor.
The winding current can be monitored with the ISEN pin
during the braking of the motor. However, the current during
braking circulates in the normal forward direction through one
output MOSFET and is in the reverse in the other MOSFET.
The current sense feature can measure only forward currents.
The logic input on the DIR pin dictates which output MOSFET
is used for sensing the forward current during braking.
The ISEN output can also be used for maintaining a current
control loop in torque motor applications.
CURRENT SENSE LINEARITY CALCULATION
The current sense linearity is specified in the table on page
2 and is calculated using the method described below:
a) Define a straight line (y = mx + b) joining the two end data
points where, m is the slope and b is the offset or zero
crossover. Calculate the slope m and offset c using the
extreme data points. Assume ISENSE in the y axis and ILOAD
in the x axis.
b) Calculate linear ISEN (or ideal ISENSE value, ISIDEAL) using
the straight line equation derived in step (a) for the ILOAD
data points.
c) Determine deviation from linear ISEN (step (b) and actual
measured ISENSE value (ISACTUAL) as shown below:
PROTECTION CIRCUITS
The most severe condition for any power device is a direct,
hard-wired ("screwdriver") short from an output to ground.
Whiletheshort-circuitprotectionwilllatchtheoutputMOSFETs
within 500 ns (typical), the die and package may be required to
dissipate up to 500 Watts of power until the protection circuits
are activated.
*4*%&"-ꢀmꢀ*4"$56"-
-JOFBSJUZꢀ&SSPSꢀꢁꢂꢃꢀꢄ
Yꢀꢅꢆꢆ
*4*%&"-
Thisenergycanbedestructive, particularlyathigheroperat-
ingvoltages,sosoundthermaldesigniscriticaliffaulttolerance
is to be established in the design. The VS and PGND pins may
become very hot during this period of high current.
Thermal and short-circuit protection are included in the
SA56 to prevent damage in the event that faults occur as
described below:
ThisdataIsheeOtThasbeen LcarefullyOcheckOedandIisbe•lieveLdtobereliab(le,h0owever0, nore0spon•sibAilityis5assu)med8for3possibleiOnacDcuracies(or2om)ission0s.A6ll spec•ificatiAonsLarerosubjiect topchangeiwithoeutno.tice.
SA56U REV A FEBRUARY 2007 © 2007 Apex Microtechnology Corp.
7
相关型号：
SA57000-25UK
IC VREG 2.5 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PBGA5, WL-CSP-5, Fixed Positive Single Output LDO Regulator
NXP
SA57000-28D-G
IC VREG 2.8 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PDSO5, 1.60 MM, PLASTIC, MO-178, SOT-680-1, SO-5, Fixed Positive Single Output LDO Regulator
NXP
SA57000-28UK
IC VREG 2.8 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PBGA5, WL-CSP-5, Fixed Positive Single Output LDO Regulator
NXP
SA57000-29D
IC VREG 2.9 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PDSO5, 1.60 MM, PLASTIC, MO-178, SOT-680-1, SO-5, Fixed Positive Single Output LDO Regulator
NXP
SA57000-29UK
IC VREG 2.9 V FIXED POSITIVE LDO REGULATOR, 0.12 V DROPOUT, PBGA5, WL-CSP-5, Fixed Positive Single Output LDO Regulator
NXP
SA57000-30D,115
SA57000-XX - CapFREE (tm) 150 mA, low noise, low dropout regulator with thermal protection SOP 5-Pin
NXP
©2020 ICPDF网 联系我们和版权申明