EP7312_05 [CIRRUS]
High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced; 高性能，低功耗的系统级芯片， SDRAM和增强与SDRAM和增强
| 型号： | EP7312_05 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | High-performance, Low-power, System-on-chip with SDRAM & Enhanced with SDRAM & Enhanced |
| 文件： | 总64页 (文件大小：1303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EP7312 Data Sheet
High-performance,
Low-power, System-on-chip
with SDRAM & Enhanced
Digital Audio Interface
FEATURES
®
❑ ARM 720T Processor
— ARM7TDMI CPU Operating at Speeds of 74 and
90 MHz
— 8 kBytes of Four-way Set-associative Cache
— MMU with 64-entry TLB
OVERVIEW
— Thumb™ Code Support Enabled
❑ Ultra low power
™
The Cirrus Logic EP7312 is designed for ultra-low-power
— 90 mW at 74 MHz Typical
portable and line-powered applications such as portable
consumer entertainment devices, home and car audio juke box
systems, and general purpose industrial control applications, or
any device that features the added capability of digital audio
compression & decompression. The core-logic functionality of
the device is built around an ARM720T processor with
8 kBytes of four-way set-associative unified cache and a write
buffer. Incorporated into the ARM720T is an enhanced
memory management unit (MMU) which allows for support of
— 108 mW at 90 MHz Typical
— <.03 mW in the Standby State
❑ Advanced Audio Decoder/decompression Capability
— Supports bit streams with adaptive bit rates.
— Allows for support of multiple audio decompression
algorithms (MP3, WMA, AAC, Audible, etc.).
®
®
sophisticated operating systems like Microsoft Windows
®
CE and Linux .
(cont.)
(cont.)
BLOCK DIAGRAM
Digital
Audio
Interface
EPB Bus
Clocks &
Tim ers
ARM720T
ICE-JTAG
Power
Managem ent
Serial
Interrupts,
Interface
PW M & GPIO
ARM7TDMI CPU Core
8 KB
Cache
W rite
Buffer
Keypad&
Touch
Screen I/F
(2) UARTs
w/ IrDA
Boot
ROM
Bus
Bridge
MMU
Internal Data Bus
Mem ory Controller
SRAM I/F SDRAM I/F
On-chip SRAM
48 KB
LCD
Controller
MaverickKeyTM
MEMORY and STORAGE
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
AUG ‘05
DS508F1
http://www.cirrus.com
EP7312
High-Performance, Low-Power System on Chip
FEATURES (cont)
❑ 48 KBytes of On-chip SRAM
❑ Internal Peripherals
— Two 16550-compatible UARTs
— IrDA Interface
™
❑ MaverickKey IDs
— 32-bit unique ID can be used for DRM-compliant 128-
bit random ID.
— Two PWM Interfaces
— Real-time Clock
❑ Available in 74 and 90 MHz clock speeds.
❑ LCD controller
— Two General-purpose 16-bit Timers
— Interrupt Controller
— Boot ROM
— Interfaces directly to a single-scan panel monochrome
STN LCD.
— Interfaces to a single-scan panel color STN LCD with
minimal external glue logic.
❑ Full JTAG Boundary Scan and Embedded ICE® Support
❑ Integrated Peripheral Interfaces
❑ Package
— 208-Pin LQFP
— 256-Ball PBGA
— 204-Ball TFBGA
— 32-bit SDRAM Interface, Up to 2 External Banks
— 8/32/16-bit SRAM/FLASH/ROM Interface
❑ The fully static EP7312 is optimized for low power
dissipation and is fabricated using a 0.25 micron CMOS
process.
— Digital Audio Interface provides glueless interface to
low-power DACs, ADCs, and CODECs.
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
— 8×8 Keypad Scanner
— 27 General-purpose Input/Output Pins
— Dedicated LED Flasher Pin from the RTC
OVERVIEW (cont.)
The EP7312 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
operating, idle and standby.
The EP7312 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, high quality ADCs, DACs, or
CODECs such as the Cirrus Logic CS53L32A, CS43L42, and
CS42L50 are easily added to an EP73xx design via the DAI.
Some of these devices feature digital bass and treble boost,
digital volume control and compressor-limiter functions.
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
Simply by adding desired memory and peripherals to the
highly integrated EP7312 completes a low-power system
solution. All necessary interface logic is integrated on-chip.
2
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES ...........................................................................................................................................1
OVERVIEW ...........................................................................................................................................1
Description of the EP7312’s Components, Functionality, and Interfaces ....................................6
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID ......................................................................................................................................6
Memory Interfaces .................................................................................................................................................6
Digital Audio Capability .........................................................................................................................................7
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7
Digital Audio Interface (DAI) ..................................................................................................................................7
CODEC Interface ..................................................................................................................................................8
SSI2 Interface ........................................................................................................................................................8
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
64-Key Keypad Interface .......................................................................................................................................8
Interrupt Controller ................................................................................................................................................9
Real-Time Clock ....................................................................................................................................................9
PLL and Clocking ..................................................................................................................................................9
DC-to-DC Converter Interface (PWM) .................................................................................................................10
Timers .................................................................................................................................................................10
General Purpose Input/Output (GPIO) ................................................................................................................10
Hardware Debug Interface ..................................................................................................................................10
LED Flasher ........................................................................................................................................................10
Internal Boot ROM ...............................................................................................................................................10
Packaging ............................................................................................................................................................10
Pin Multiplexing ...................................................................................................................................................11
System Design ....................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................13
Absolute Maximum Ratings .................................................................................................................................13
Recommended Operating Conditions .................................................................................................................13
DC Characteristics ..............................................................................................................................................13
Timings ...............................................................................................................................................15
Timing Diagram Conventions ....................................................................................................................15
Timing Conditions ......................................................................................................................................15
SDRAM Interface ................................................................................................................................................16
SDRAM Load Mode Register Cycle ..........................................................................................................17
SDRAM Burst Read Cycle .........................................................................................................................18
SDRAM Burst Write Cycle .........................................................................................................................19
SDRAM Refresh Cycle ..............................................................................................................................20
Static Memory .....................................................................................................................................................21
Static Memory Single Read Cycle .............................................................................................................22
Static Memory Single Write Cycle .............................................................................................................23
Static Memory Burst Read Cycle ...............................................................................................................24
Static Memory Burst Write Cycle ...............................................................................................................25
SSI1 Interface ......................................................................................................................................................26
SSI2 Interface ......................................................................................................................................................27
LCD Interface ......................................................................................................................................................28
JTAG Interface .....................................................................................................................................................29
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
3
EP7312
High-Performance, Low-Power System on Chip
Packages ............................................................................................................................................30
208-Pin LQFP Package Characteristics ............................................................................................................. 30
EP7312
208-Pin LQFP ............................................................................................................................30
208-Pin LQFP Pin Diagram ................................................................................................................................ 31
EP7312 ...............................................................................................................................................31
208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32
204-Ball TFBGA Package Characteristics .......................................................................................................... 38
204-Ball TFBGA Pinout (Top View) ..................................................................................................................... 39
204-Ball TFBGA Ball Listing ............................................................................................................................... 40
256-Ball PBGA Package Characteristics ............................................................................................................ 46
256-Ball PBGA Pinout (Top View) ....................................................................................................................... 48
256-Ball PBGA Ball Listing ................................................................................................................................. 49
JTAG Boundary Scan Signal Ordering ............................................................................................................... 54
CONVENTIONS .................................................................................................................................60
Acronyms and Abbreviations .............................................................................................................................. 60
Units of Measurement ......................................................................................................................................... 60
General Conventions .......................................................................................................................................... 61
Pin Description Conventions ............................................................................................................................... 61
Ordering Information .......................................................................................................................62
Environmental, Manufacturing, & Handling Information ..............................................................62
Revision History ...............................................................................................................................63
4
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Fully-Configured EP7312-Based System ...................................................................................................12
Figure 2. Legend for Timing Diagrams .........................................................................................................................15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................17
Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18
Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19
Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24
Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25
Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26
Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27
Figure 13. LCD Controller Timing Measurement ..........................................................................................................28
Figure 14. JTAG Timing Measurement .........................................................................................................................29
Figure 15. 208-Pin LQFP Package Outline Drawing ....................................................................................................30
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram ..........................................................................31
Figure 17. 204-Ball TFBGA Package ............................................................................................................................38
Figure 18. 256-Ball PBGA Package ..............................................................................................................................46
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6
Table 2. Static Memory Interface Pin Assignments ........................................................................................................6
Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7
Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table 5. DAI Interface Pin Assignments .........................................................................................................................7
Table 6. CODEC Interface Pin Assignments ..................................................................................................................8
Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8
Table 8. Serial Interface Pin Assignments ......................................................................................................................8
Table 9. LCD Interface Pin Assignments ........................................................................................................................8
Table 10. Keypad Interface Pin Assignments .................................................................................................................9
Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9
Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9
Table 13. PLL and Clocking Pin Assignments ................................................................................................................9
Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10
Table 15. General Purpose Input/Output Pin Assignments ..........................................................................................10
Table 16. Hardware Debug Interface Pin Assignments ................................................................................................10
Table 17. LED Flasher Pin Assignments ......................................................................................................................10
Table 18. DAI/SSI2/CODEC Pin Multiplexing ...............................................................................................................11
Table 19. Pin Multiplexing .............................................................................................................................................11
Table 20. 208-Pin LQFP Numeric Pin Listing ...............................................................................................................32
Table 21. 204-Ball TFBGA Ball Listing .........................................................................................................................40
Table 22. 256-Ball PBGA Ball Listing ...........................................................................................................................49
Table 23. JTAG Boundary Scan Signal Ordering .........................................................................................................54
Table 24. Acronyms and Abbreviations ........................................................................................................................60
Table 25. Unit of Measurement .....................................................................................................................................60
Table 26. Pin Description Conventions .........................................................................................................................61
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
5
EP7312
High-Performance, Low-Power System on Chip
Description of the EP7312’s Components, Functionality, and Interfaces
The following sections describe the EP7312 in more detail.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7312 through the use of laser probing
technology. These IDs can then be used to match secure
copyrighted content with the ID of the target device the
EP7312 is powering, and then deliver the copyrighted
information over a secure connection. In addition, secure
transactions can benefit by also matching device IDs to server
IDs. MaverickKey IDs provide a level of hardware security
required for today’s Internet appliances.
Processor Core - ARM720T
The EP7312 incorporates an ARM 32-bit RISC micro
controller that controls a wide range of on-chip peripherals.
The processor utilizes a three-stage pipeline consisting of
fetch, decode and execute stages. Key features include:
•
•
ARM (32-bit) and Thumb (16-bit compressed) instruction
sets
Memory Interfaces
Enhanced MMU for Microsoft Windows CE and other
operating systems
There are two main external memory interfaces. The first one
is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-mode
capability, with six chip selects decoding six 256 MB sections
of addressable space. For maximum flexibility, each bank can
be specified to be 8-, 16-, or 32-bits wide. This allows the use
of 8-bit-wide boot ROM options to minimize overall system
cost. The on-chip boot ROM can be used in product
manufacturing to serially download system code into system
FLASH memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-leading
code density. shows the Static Memory Interface pin
assignments.
•
•
8 KB of 4-way set-associative cache.
Translation Look Aside Buffers with 64 Translated Entries
Power Management
The EP7312 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
• Operating — This state is the full performance state.
All the clocks and peripheral logic are enabled.
• Idle — This state is the same as the Operating State,
except the CPU clock is halted while waiting for an
event such as a key press.
• Standby — This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key press
can wake-up the processor.
Table 2. Static Memory Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
Table 1 shows the power management pin assignments.
nCS[5:0]
O
O
Chip select out
Address output
Table 1. Power Management Pin Assignments
A[27:0]
D[31:0]
I/O Data I/O
Pin Mnemonic
I/O
Pin Description
nMOE/nSDCAS
nMWE/nSDWE
(Note)
(Note)
O
O
ROM expansion OP enable
BATOK
I
Battery ok input
ROM expansion write enable
External power supply sense
input
nEXTPWR
I
Halfword access select
output
HALFWORD
O
nPWRFL
I
I
Power fail sense input
WORD
O
O
Word access select output
Transfer direction
nBATCHG
Battery changed sense input
WRITE/nSDRAS
(Note)
™
MaverickKey Unique ID
Note: Pins are multiplexed. See Table 19 on page 11 for
more information.
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
6
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide SDRAM
interface that allows direct connection of up to two banks of
SDRAM, totaling 512 Mb. To assure the lowest possible power
consumption, the EP7312 supports self-refresh SDRAMs,
which are placed in a low-power state by the device when it
enters the low-power Standby State. Table 3 shows the
SDRAM Interface pin assignments.
communication interface directly. Table 4 shows the UART pin
assignments.
Table 4. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
I/O
Pin Description
TXD[1]
O
I
UART 1 transmit
Table 3. SDRAM Interface Pin Assignments
RXD[1]
CTS
UART 1 receive
Pin Mnemonic
I/O
Pin Description
I
UART 1 clear to send
UART 1 data carrier detect
UART 1 data set ready
UART 2 transmit
DCD
I
SDCLK
O
O
O
O
O
SDRAM clock output
DSR
I
SDCKE
SDRAM clock enable output
SDRAM chip select out
SDRAM RAS signal output
SDRAM CAS control signal
TXD[2]
RXD[2]
LEDDRV
PHDIN
O
I
nSDCS[1:0]
UART 2 receive
WRITE/nSDRAS
nMOE/nSDCAS
(Note 2)
(Note 2)
O
I
Infrared LED drive output
Photo diode input
SDRAM write enable control
signal
nMWE/nSDWE
(Note 2)
O
A[27:15]/DRA[0:12] (Note 1)
A[14:13]/DRA[12:14]
PD[7:6]/SDQM[1:0] (Note 2)
SDQM[3:2]
O
O
SDRAM address
Digital Audio Interface (DAI)
SDRAM internal bank select
The EP7312 integrates an interface to enable a direct
connection to many low cost, low power, high quality audio
converters. In particular, the DAI can directly interface with
the Crystal‚ CS43L41/42/43 low-power audio DACs and the
Crystal‚ CS53L32 low-power ADC. Some of these devices
feature digital bass and treble boost, digital volume control and
compressor-limiter functions. Table 5 shows the DAI Interface
pin assignments.
I/O SDRAM byte lane mask
SDRAM byte lane mask
I/O Data I/O
O
D[31:0]
Note: 1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See Table 19 on page 11 for
more information.
Table 5. DAI Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
Digital Audio Capability
SCLK
O
O
I
Serial bit clock
The EP7312 uses its powerful 32-bit RISC processing engine
to implement audio decompression algorithms in software. The
nature of the on-board RISC processor, and the availability of
efficient C-compilers and other software development tools,
ensures that a wide range of audio decompression algorithms
can easily be ported to and run on the EP7312
SDOUT
SDIN
Serial data out
Serial data in
LRCK
O
I
Sample clock
MCLKIN
MCLKOUT
Master clock input
Master clock output
O
Universal Asynchronous
Receiver/Transmitters (UARTs)
Note: See Table 18 on page 11 for information on pin
multiplexes.
The EP7312 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte FIFOs
for receiving and transmitting data. The UARTs support bit
rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder
can be optionally switched into the RX/TX signals to/from
UART 1 to enable these signals to drive an infrared
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
7
EP7312
High-Performance, Low-Power System on Chip
CODEC Interface
Synchronous Serial Interface
The EP7312 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
communications systems. The CODEC interface is
multiplexed to the same pins as the DAI and SSI2. Table 6
shows the CODEC Interface Pin Assignments.
The EP7312 Synchronous Serial Interface has these features:
•
ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
•
Selectable serial clock polarity
Table
assignments.
8 shows the Synchronous Serial Interface pin
Table 6. CODEC Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
Table 8. Serial Interface Pin Assignments
PCMCLK
O
O
I
Serial bit clock
PCMOUT
PCMIN
Serial data out
Serial data in
Frame sync
Pin Mnemonic
I/O
Pin Description
ADCLK
O
I
SSI1 ADC serial clock
SSI1 ADC serial input
SSI1 ADC serial output
SSI1 ADC chip select
SSI1 ADC sample clock
PCMSYNC
O
ADCIN
ADCOUT
nADCCS
SMPCLK
O
O
O
Note: See Table 18 on page 11 for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the DAI and CODEC
interfaces through a multiplexer. The SSI2 Interface has these
features:
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM. The LCD controller has these features:
•
•
•
•
Synchronous clock speeds of up to 512 kHz
Separate 16 entry TX and RX half-word wide FIFOs
Half empty/full interrupts for FIFOs
•
•
•
•
•
Interfaces directly to a single-scan panel monochrome STN
LCD
Separate RX and TX frame sync signals for asymmetric
traffic
Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Table 7 shows the SSI2 Interface pin assignments.
Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
Table 7. SSI2 Interface Pin Assignments
Video frame buffer size programmable up to
128 KB
Pin Mnemonic
I/O
Pin Description
Bits per pixel of 1, 2, or 4 bits
SSICLK
I/O
O
Serial bit clock
Table 9 shows the LCD Interface pin assignments.
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
Serial data out
I
Serial data in
Table 9. LCD Interface Pin Assignments
I/O
I/O
Transmit frame sync
Receive frame sync
Pin Mnemonic
I/O
Pin Description
CL1
O
O
O
O
O
LCD line clock
Note: See Table 18 on page 11 for information on pin
multiplexes.
CL2
LCD pixel clock out
DD[3:0]
FRM
M
LCD serial display data bus
LCD frame synchronization pulse
LCD AC bias drive
64-Key Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7312. A dedicated 8-bit column driver output generates
8
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
strobes for each keyboard column signal. The pins of Port A,
when configured as inputs, can be selectively OR'ed together
to provide a keyboard interrupt that is capable of waking the
system from a STANDBY or IDLE state. The Keypad
Interface has these features:
Real-Time Clock
The EP7312 contains a 32-bit Real Time Clock (RTC) that can
be written to and read from in the same manner as the timer
counters. It also contains a 32-bit output match register which
can be programmed to generate an interrupt.
•
•
•
Column outputs can be individually set high with the
remaining bits left at high-impedance
•
Driven by an external 32.768 kHz crystal oscillator
Table 12 shows the Real-Time Clock pin assignments.
Column outputs can be driven all-low, all-high, or all-high-
impedance
Table 12. Real-Time Clock Pin Assignments
Keyboard interrupt driven by OR'ing together all Port A
bits
Pin Mnemonic
Pin Description
•
•
Keyboard interrupt can be used to wake up the system
RTCIN
Real-Time Clock Oscillator Input
Real-Time Clock Oscillator Output
Real-Time Clock Oscillator Power
Real-Time Clock Oscillator Ground
8×8 keyboard matrix usable with no external logic, extra
keys can be added with minimal glue logic
RTCOUT
VDDRTC
VSSRTC
Table 10 shows the Keypad Interface Pin Assignments.
Table 10. Keypad Interface Pin Assignments
Pin Mnemonic
I/O
Pin Description
PLL and Clocking
COL[7:0]
O
Keyboard scanner column drive
The EP7312 processor and peripheral clocks have these
features:
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the same
time, a fixed priority system determines the order in which
they are handled. The EP7312 interrupt controller has two
interrupt types: interrupt request (IRQ) and fast interrupt
request (FIQ). The interrupt controller has the ability to control
interrupts from 22 different FIQ and IRQ sources. The
Interrupt controller has these features:
•
•
Processor and peripheral clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
Programmable clock speeds allow the peripheral bus to run
at 18 MHz when the processor is set to 18 MHz and at
36 MHz when the processor is set to 36, 49 or 74 MHz, and
at 45 MHz when the processor is set to 90 MHz.
Table 13 shows the PLL and clocking pin assignments.
Table 13. PLL and Clocking Pin Assignments
Pin Mnemonic
Pin Description
•
•
•
Supports 22 interrupts from a variety of sources (such as
UARTs, SSI1, and key matrix.)
MOSCIN
Main Oscillator Input
Routes interrupt sources to the ARM720T’s IRQ or FIQ
(Fast IRQ) inputs
MOSCOUT
VDDOSC
VSSOSC
Main Oscillator Output
Main Oscillator Power
Main Oscillator Ground
Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
Table 11 shows the interrupt controller pin assignments.
.
Table 11. Interrupt Controller Pin Assignments
Pin Mnemonic
I/O
Pin Description
nEINT[2:1]
I
I
I
I
External interrupt
EINT[3]
External interrupt
nEXTFIQ
External Fast Interrupt input
Media change interrupt input
nMEDCHG/nBROM
(Note)
Note: Pins are multiplexed. See Table 19 on page 11 for
more information.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
9
EP7312
High-Performance, Low-Power System on Chip
DC-to-DC Converter Interface (PWM)
Table 16. Hardware Debug Interface Pin Assignments
•
Provides two 96 kHz clock outputs with programmable
duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a positive or negative DC to DC converter
Pin Mnemonic
I/O
Pin Description
TCLK
I
I
JTAG clock
Table 14 shows the DC-to-DC Converter Interface pin
assignments.
TDI
JTAG data input
TDO
nTRST
TMS
O
I
JTAG data output
JTAG async reset input
JTAG mode select
Table 14. DC-to-DC Converter Interface Pin Assignments
I
Pin Mnemonic
I/O
Pin Description
DRIVE[1:0]
I/O
I
PWM drive output
PWM feedback input
LED Flasher
FB[1:0]
A dedicated LED flasher module can be used to generate a low
frequency signal on Port D pin 0 for the purpose of blinking an
LED without CPU intervention. The LED flasher feature is
ideal as a visual annunciator in battery powered applications,
such as a voice mail indicator on a portable phone or an
appointment reminder on a PDA. Table 17 shows the LED
Flasher pin assignments.
Timers
•
•
Internal (RTC) timer
Two internal 16-bit programmable hardware count-down
timers
General Purpose Input/Output (GPIO)
•
•
•
•
Software adjustable flash period and duty cycle
Operates from 32 kHz RTC clock
•
•
Three 8-bit and one 3-bit GPIO ports
Supports scanning keyboard matrix
Will continue to flash in IDLE and STANDBY states
4 mA drive current
Table 15 shows the GPIO pin assignments.
Table 17. LED Flasher Pin Assignments
Table 15. General Purpose Input/Output Pin Assignments
Pin Mnemonic
I/O
Pin Description
Pin Mnemonic
I/O
Pin Description
PD[0]/LEDFLSH
(Note)
O
LED flasher driver
PA[7:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO port A
PB[7:0]
GPIO port B
GPIO port D
GPIO port D
GPIO port D
GPIO port E
GPIO port E
Note: Pins are multiplexed. See Table 19 on page 11 for
more information.
PD[0]/LEDFLSH
PD[5:1]
(Note)
(Note)
Internal Boot ROM
PD[7:6]/SDQM[1:0]
The internal 128-byte Boot ROM facilitates download of saved
code to the on-board SRAM/FLASH.
PE[1:0]/BOOTSEL[1:0] (Note)
PE[2]/CLKSEL (Note)
Packaging
Note: Pins are multiplexed. See Table 19 on page 11 for
more information.
The EP7312 is available in a 208-pin LQFP package, 256-ball
PBGA package, or a 204-ball TFBGA package.
Hardware Debug Interface
•
Full JTAG boundary scan and Embedded ICE® support
Table 16 shows the Hardware Debug Interface pin
assignments.
10
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 19 shows the pins that have been multiplexed in the
EP7312.
Pin Multiplexing
Table 18 shows the pin multiplexing of the DAI, SSI2 and the
CODEC. The selection between SSI2 and the CODEC is
controlled by the state of the SERSEL bit in SYSCON2. The
choice between the SSI2, CODEC, and the DAI is controlled
by the DAISEL bit in SYSCON3 (see the EP7312 User’s
Manual for more information).
Table 19. Pin Multiplexing
Signal
Block
Signal
Block
nMOE
Static Memory
Static Memory
Static Memory
Static Memory
Static Memory
GPIO
nSDCAS
SDRAM
nMWE
nSDWE
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
Table 18. DAI/SSI2/CODEC Pin Multiplexing
WRITE
A[27:15]
A[14:13]
PD[7:6]
nSDRAS
DRA[0:12]
DRA[13:14]
SDQM[1:0]
Pin
Mnemonic
I/O
DAI
SSI2
CODEC
SSICLK
I/O
O
I
SCLK
SDOUT
SDIN
SSICLK
SSITXDA
SSIRXDA
PCMCLK
PCMOUT
PCMIN
SSITXDA
SSIRXDA
SSITXFR
SSIRXFR
BUZ
System
Configuration
System
Configuration
RUN
CLKEN
Interrupt
Controller
Boot ROM
select
I/O
I
LRCK
SSITXFR PCMSYNC
SSIRXFR p/u
nMEDCHG
PD[0]
nBROM
MCLKIN
MCLKOUT
GPIO
GPIO
LEDFLSH
BOOTSEL[1:0]
LED Flasher
O
System
Configuration
PE[1:0]
System
Configuration
PE[2]
GPIO
CLKSEL
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
11
EP7312
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding desired
memory and peripherals to the highly integrated EP7312
completes a low-power system solution. All necessary
interface logic is integrated on-chip.
CRYSTAL
CRYSTAL
MOSCIN
RTCIN
DD[0-3]
CL1
LCD
CL2
FRM
M
COL[0-7]
KEYBOARD
PA[0-7]
D[0-31]
A[0-27]
PB[0-7]
nMOE
WRITE
PD[0-7]
DC
INPUT
PE[0-2]
POWER
SUPPLY UNIT
SDRAS/
SDCAS
AND
COMPARATORS
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
×16
SDRAM
×16
SDRAM
SDCS[0]
BATTERY
SDQM[0-3]
WAKEUP
SDCS[1]
×16
×16
SDRAM
SDRAM
SDQM[0-3]
DRIVE[0-1]
FB[0-1]
DC-TO-DC
CONVERTERS
nCS[0]
nCS[1]
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
CODEC/SSI2/
DAI
×16
FLASH
×16
FLASH
×16
FLASH
×16
FLASH
IR LED AND
PHOTODIODE
LEDDRV
PHDIN
CS[n]
WORD
RXD[[1/2]
TXD[1/2]
DSR
2× RS-232
TRANSCEIVERS
EXTERNAL MEMORY-
MAPPED EXPANSION
BUFFERS
CTS
DCD
ADCCLK
nADCCS
ADCOUT
ADCIN
nCS[2]
nCS[3]
ADC
DIGITIZER
BUFFERS
AND
LEDFLSH
ADDITIONAL I/O
SMPCLK
LATCHES
Figure 1. A Fully-Configured EP7312-Based System
Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI.
12
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage
DC I/O Supply Voltage (Pad Ring)
DC Pad Input Current
2.9 V
3.6 V
10 mA/pin; 100 mA cumulative
Storage Temperature, No Power
–40°C to +125°C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage
DC I/O Supply Voltage (Pad Ring)
DC Input / Output Voltage
2.5 V 0.2 V
2.3 V - 3.5 V
O–I/O supply voltage
Extended -20°C to +70°C; Commercial 0°C to +70°C;
Industrial -40°C to +85°C
Operating Temperature
DC Characteristics
All characteristics are specified at V
= 2.5 V, V
= 3.3 V and V = 0 V over an operating temperature of 0°C to +70°C
DDIO SS
DDCORE
for all frequencies of operation. The current consumption figures have test conditions specified per parameter.”
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
0.65 × VDDIO
VSS − 0.3
VDDIO + 0.3
0.25 × VDDIO
VDDIO = 2.5 V
VDDIO = 2.5 V
VIH
CMOS input high voltage
CMOS input low voltage
-
-
V
V
VIL
Schmitt trigger positive going
threshold
VT+
-
-
2.1
V
Schmitt trigger negative going
threshold
VT-
0.8
-
-
-
V
V
Vhst
Schmitt trigger hysteresis
0.1
0.4
VIL to VIH
CMOS output high voltagea
Output drive 1a
Output drive 2a
VDD – 0.2
-
-
-
-
-
-
V
V
V
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
VOH
VOL
2.5
2.5
CMOS output low voltagea
Output drive 1a
Output drive 2a
-
-
-
-
-
-
0.3
0.5
0.5
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
VIN = VDD or GND
IIN
Input leakage current
-
-
-
1.0
µA
µA
Bidirectional 3-state leakage
currentb c
VOUT = VDD or GND
IOZ
25
100
CIN
Input capacitance
Output capacitance
8
8
-
-
10.0
10.0
pF
pF
COUT
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
13
EP7312
High-Performance, Low-Power System on Chip
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CI/O
Transceiver capacitance
8
-
10.0
pF
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDSTANDBY
@ 25 C
-
-
77
41
-
-
µA
µA
VIL = GND 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDSTANDBY
@ 70 C
-
-
-
-
570
111
VIL = GND 0.1 V
Only nPOR, nPWRFAIL,
nURESET, PE0, PE1, and RTS
are driven, while all other float,
VIH = VDD 0.1 V,
Standby current consumption1
IDDSTANDBY
@ 85 C
-
-
-
-
1693
163
µA
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
VIL = GND 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD 0.1 V, VIL
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDidle
-
-
6
10
-
-
mA
at 74 MHz
= GND 0.1 V
Both oscillators running, CPU
static, Cache enabled, LCD
disabled, VIH = VDD 0.1 V, VIL
Idle current consumption1
Core, Osc, RTC @2.5 V
I/O @ 3.3 V
IDDIDLE
-
-
7
11
-
-
mA
V
at 90 MHz
= GND 0.1 V
Minimum standby voltage for
state retention, internal SRAM
cache, and RTC operation only
VDDSTANDBY
Standby supply voltage
2.0
-
-
a.
b.
c.
Refer to the strength column in the pin assignment tables for all package types.
Assumes buffer has no pull-up or pull-down resistors.
The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.
Note: 1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V
2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be
compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).
2) Pull-up current = 50 µA typical at VDD = 3.3 V.
14
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
C l o c k
H i g h t o L o w
H i g h / L o w t o H i g h
B u s C h a n g e
B u s V a l i d
U n d e f i n e d / I n v a l i d
V a l i d B u s t o T r i s t a t e
B u s / S i g n a l O m i s s i o n
Figure 2. Legend for Timing Diagrams
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at
V
= 3.1 - 3.5 V and V = 0 V over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF. The timing values are
DDIO
SS
referenced to 1/2 V
.
DD
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
15
EP7312
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for
the timings of each of the SDRAM modes.
Parameter
Symbol
tCSa
Min
Typ
Max
Unit
SDCLK falling edge to SDCS assert delay time
SDCLK falling edge to SDCS deassert delay time
SDCLK falling edge to SDRAS assert delay time
SDCLK falling edge to SDRAS deassert delay time
SDCLK falling edge to SDRAS invalid delay time
SDCLK falling edge to SDCAS assert delay time
SDCLK falling edge to SDCAS deassert delay time
SDCLK falling edge to ADDR transition time
SDCLK falling edge to ADDR invalid delay time
SDCLK falling edge to SDMWE assert delay time
SDCLK falling edge to SDMWE deassert delay time
DATA transition to SDCLK falling edge time
0
− 3
1
2
2
3
1
4
2
0
1
2
1
0
-
4
10
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCSd
tRAa
tRAd
− 3
2
10
7
tRAnv
tCAa
− 2
− 5
− 3
− 2
− 3
− 4
2
5
tCAd
3
tADv
5
tADx
5
tMWa
tMWd
tDAs
5
4
-
tDAh
SDCLK falling edge to DATA transition hold time
SDCLK falling edge to DATA transition delay time
1
-
-
tDAd
0
-
15
16
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
SDCLK
tCSa
tCSd
tRAd
tCAd
SDCS
tRAa
SDRAS
tCAa
SDCAS
tADv
tADx
ADDR
DATA
SDQM
tMWa
tMWd
SDMWE
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
17
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
SDCLK
tCSa
tCSa
tCSd
tCSd
SDCS
SDRAS
SDCAS
ADDR
tRAa
tRAd
tRAnv
tCAa
tCAd
tADv
tADv
ADRAS
ADCAS
tDAs
tDAs
tDAs
tDAs
D1
D2
D3
D4
DATA
tDAh
tDAh
tDAh
tDAh
SDQM
[0:3]
SDMWE
Figure 4. SDRAM Burst Read Cycle Timing Measurement
Note: 1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
18
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
SDCLK
tCSa
tCSa
tCSd
tCSd
SDCS
tRAa
tRAd
SDRAS
SDCAS
tCAa
tCAd
tADv
tADv
ADDR
ADCAS
ADRAS
tDAd
tDAd
tDAd
tDAd
DATA
SDQM
D1
D2
D3
D4
0
tMWa
tMWd
SDMWE
Figure 5. SDRAM Burst Write Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
19
EP7312
High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
SDCLK
tCSa
tCSd
SDCS
tRAa
tRAd
SDRAS
tCAd
tCAa
SDCAS
SDATA
ADDR
SDQM
[3:0]
SDMWE
Figure 6. SDRAM Refresh Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
20
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Static Memory
Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the
values for the timings of each of the Static Memory modes.
Parameter
Symbol
tCSd
tCSh
tAd
Min
Typ
Max
Unit
EXPCLK rising edge to nCS assert delay time
EXPCLK falling edge to nCS deassert hold time
EXPCLK rising edge to A assert delay time
EXPCLK falling edge to A deassert hold time
EXPCLK rising edge to nMWE assert delay time
EXPCLK rising edge to nMWE deassert hold time
EXPCLK falling edge to nMOE assert delay time
EXPCLK falling edge to nMOE deassert hold time
EXPCLK falling edge to HALFWORD deassert delay time
EXPCLK falling edge to WORD assert delay time
EXPCLK rising edge to data valid delay time
EXPCLK falling edge to data invalid delay time
Data setup to EXPCLK falling edge time
2
2
4
3
3
3
3
2
2
2
8
6
-
8
7
20
20
16
19
10
10
10
10
20
16
21
30
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
tAh
10
6
tMWd
tMWh
tMOEd
tMOEh
tHWd
tWDd
tDv
6
7
7
8
8
13
15
-
tDnv
tDs
tDh
EXPCLK falling edge to data hold time
-
-
3
tWRd
tEXs
EXPCLK rising edge to WRITE assert delay time
EXPREADY setup to EXPCLK falling edge time
EXPCLK falling edge to EXPREADY hold time
5
-
11
-
23
0
tEXh
-
-
0
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
21
EP7312
High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF-
WORD
tWDd
WORD
tDs
tDh
D
tEXs
tEXh
EXPRDY
tWRd
WRITE
Figure 7. Static Memory Single Read Cycle Timing Measurement
Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Address, Halfword, Word, and Write hold state until next cycle.
22
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAd
A
tMWd
tMWh
nMWE
nMOE
tHWd
HALF-
WORD
tWDd
WORD
tDv
D
tEXs
tEXh
EXPRDY
WRITE
Figure 8. Static Memory Single Write Cycle Timing Measurement
Note: 1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
3. Address, Data, Halfword, Word, and Write hold state until next cycle.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
23
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAd
tAh
tAh
A
nMWE
tMOEd
tMOEh
nMOE
tHWd
HALF
WORD
tWDd
WORD
D
tDs tDh
tDs tDh
tDs tDh
tDs tDh
tEXs
tEXh
EXPRDY
WRITE
tWRd
Figure 9. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
24
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK
tCSd
tCSh
nCS
tAh
tAh
tAh
tAd
A
tMWd
tMWd
tMWd
tMWd
tMWh
tMWh
tMWh
tMWh
nMWE
nMOE
tHWd
HALF
WORD
tWDd
WORD
D
tDv
tDnv
tDv
tDnv
tDv
tDnv
tDv
tEXs
tEXh
EXPRDY
WRITE
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
4. Address, Data, Halfword, Word, and Write hold state until next cycle.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
25
EP7312
High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
Symbol
tCd
Min
Max
Unit
ADCCLK falling edge to nADCCSS deassert delay time
ADCIN data setup to ADCCLK rising edge time
ADCIN data hold from ADCCLK rising edge time
ADCCLK falling edge to data valid delay time
ADCCLK falling edge to data invalid delay time
9
-
10
15
14
13
3
ms
ns
ns
ns
ns
tINs
tINh
-
tOvd
tOd
− 7
− 2
ADC
CLK
tCd
nADC
CSS
tINs
tINh
ADCIN
tOvd
tOd
ADC
OUT
Figure 11. SSI1 Interface Timing Measurement
26
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tclkrf
Min
Max
Unit
SSICLK period (slave mode)
SSICLK high time
185
925
925
3
2050
1025
1025
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSICLK low time
SSICLK rise/fall time
tFRd
SSICLK rising edge to RX and/or TX frame sync high time
SSICLK rising edge to RX and/or TX frame sync low time
SSIRXFR and/or SSITXFR period
-
3
tFRa
-
8
tFR_per
tRXs
960
3
990
7
SSIRXDA setup to SSICLK falling edge time
SSIRXDA hold from SSICLK falling edge time
SSICLK rising edge to SSITXDA data valid delay time
SSITXDA valid time
tRXh
3
7
tTXd
-
2
tTXv
960
990
tclk_per
tclk_high
tclk_low
SSI
CLK
tclkrf
tFR_per
tFRd
tFRa
SSIRXFR/
SSITXFR
tRXh
tRXs
SSI
RXDA
D7
D2
D2
D1
D1
D0
D0
tTXd
SSI
TXDA
D7
tTXv
Figure 12. SSI2 Interface Timing Measurement
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
27
EP7312
High-Performance, Low-Power System on Chip
LCD Interface
Parameter
Symbol
tCL1d
tCL2d
tFRMd
tMd
Min
Max
Unit
CL[2] falling to CL[1] rising delay time
CL[1] falling to CL[2] rising delay time
CL[1] falling to FRM transition time
CL[1] falling to M transition time
− 10
80
25
3,475
10,425
20
ns
ns
ns
ns
ns
300
− 10
− 10
tDDd
CL[2] rising to DD (display data) transition time
20
CL[2]
tCL2d
tCL1d
CL[1]
FRM
tFRMd
tMd
M
tDDd
DD [3:0]
Figure 13. LCD Controller Timing Measurement
28
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
JTAG Interface
Parameter
Symbol
tclk_per
tclk_high
tclk_low
tJPs
Min
Max
Units
TCK clock period
2
1
1
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
-
0
tJPh
-
3
tJPco
-
10
12
19
tJPzx
JTAG port high impedance to valid output
JTAG port valid output to high impedance
-
tJPxz
-
tclk_per
tclk_high
tclk_low
TCK
tJPh
tJPs
TMS
TDI
tJPzx
tJPco
tJPxz
TDO
Figure 14. JTAG Timing Measurement
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
29
EP7312
High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.80 (1.094)
28.20 (1.110)
29.60 (1.165)
30.40 (1.197)
EP7312
208-Pin LQFP
0.50
(0.0197)
BSC
Pin 1 Indicator
Pin 208
Pin 1
1.35 (0.053)
1.45 (0.057)
1.00 (0.039) BSC
0.45 (0.018)
0.75 (0.030)
0.09 (0.004)
0.20 (0.008)
0° MIN
7° MAX
0.05 (0.002)
0.15 (0.006)
1.40 (0.055)
1.60 (0.063)
Figure 15. 208-Pin LQFP Package Outline Drawing
Note: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Drawing above does not reflect exact package pin count.
3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
4) For pin locations, please see Figure 16. For pin descriptions see the EP7312 User’s Manual.
30
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
D[25]
A[25]/DRA[2]
D[26]
A[26]/DRA[1]
D[27]
A[27]/DRA[0]
104
103
102
101
100
99
157
158
159
160
161
162
163
164
VDDOSC
MOSCIN
MOSCOUT
VSSOSC
WAKEUP
nPWRFL
VSSIO
98
D[28]
97
A[6]
D[6]
A[5]
D[5]
VDDIO
VSSIO
A[4]
D[4]
A[3]
D[3]
A[2]
VSSIO
D[2]
A[1]
D[1]
A[0]
D[29]
96
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
D[30]
95
D[31]
94
BUZ
93
COL[0]
92
COL[1]
91
TCLK
90
VDDIO
89
COL[2]
88
COL[3]
87
COL[4]
86
COL[5]
85
COL[6]
84
COL[7]
83
FB[0]
82
EP7312
D[0]
VSSIO
81
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
FRM
FB[1]
80
SMPCLK
79
ADCOUT
78
208-Pin LQFP
ADCCLK
77
DRIVE[0]
76
(Top View)
DRIVE[1]
75
VDDIO
74
M
VSSIO
73
DD[3]
DD[2]
VSSIO
DD[1]
DD[0]
VDDCORE
72
VSSCORE
71
nADCCS
70
ADCIN
69
SSIRXFR
68
nSDCS[1]
SSIRXDA
67
nSDCS[0]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCKE
SSITXDA
66
SSITXFR
65
VSSIO
64
SSICLK
63
PD[0]/LEDFLSH
62
PD[1]
61
SDCLK
PD[2]
60
nMWE/nSDWE
nMOE/nSDCAS
VSSIO
PD[3]
59
TMS
58
VDDIO
57
nCS[0]
nCS[1]
nCS[2]
nCS[3]
PD[4]
56
PD[5]
55
PD[6]/SDQM[0]
54
PD[7]/SDQM[1]
53
nCS[4]
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Note: 1. N/C should not be grounded but left as no connects.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
31
EP7312
High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table 20. 208-Pin LQFP Numeric Pin Listing
Pin
No.
Reset
State
†
Signal
Type
Description
Strength
1
2
3
4
5
nCS[5]
VDDIO
VSSIO
1
Low
O
Chip select 5
Digital I/O power, 3.3 V
I/O ground
Pad Pwr
Pad Gnd
EXPCLK
WORD
1
1
I
Expansion clock input
Word access select output
Low
Low
O
Transfer direction / SDRAM
RAS signal output
6
7
WRITE/nSDRAS
RUN/CLKEN
1
1
O
O
Run output / clock enable
output
Low
8
EXPRDY
TXD[2]
RXD[2]
TDI
1
1
I
Expansion port ready input
UART 2 transmit data output
UART 2 receive data input
JTAG data input
9
High
O
10
11
12
I
with p/u*
I
VSSIO
Pad Gnd
I/O ground
‡
13
14
15
16
17
18
19
PB[7]
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
1
1
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO port B
GPIO port B
GPIO port B
GPIO port B
GPIO port B
GPIO port B
GPIO port B
Input
‡
Input
‡
Input
‡
Input
‡
Input
‡
Input
‡
Input
‡
20
21
22
PB[0]
VDDIO
TDO
I/O
Pad Pwr
O
GPIO port B
Digital I/O power, 3.3 V
JTAG data out
Input
‡
1
1
1
1
1
1
1
1
1
Input
‡
23
24
25
26
27
28
29
30
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO port A
GPIO port A
GPIO port A
GPIO port A
GPIO port A
GPIO port A
GPIO port A
GPIO port A
Input
‡
Input
‡
Input
‡
Input
‡
Input
‡
Input
‡
Input
‡
Input
31
32
33
34
35
36
37
LEDDRV
TXD[1]
VSSIO
PHDIN
CTS
1
1
1
Low
High
High
O
IR LED drive
UART 1 transmit data out
I/O ground
O
Pad Gnd
I
I
I
I
Photodiode input
UART 1 clear to send input
UART 1 receive data input
UART 1 data carrier detect
RXD[1]
DCD
32
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
†
Signal
Type
Description
Strength
38
39
40
41
42
43
44
DSR
I
I
I
I
I
I
I
UART 1 data set ready input
Test mode select input
Test mode select input
External interrupt
nTEST[1]
nTEST[0]
EINT[3]
With p/u*
With p/u*
nEINT[2]
nEINT[1]
nEXTFIQ
External interrupt input
External interrupt input
External fast interrupt input
GPIO port E / clock input
mode select
‡
45
46
PE[2]/CLKSEL
1
1
1
I/O
I/O
Input
GPIO port E / boot mode
select
‡
PE[1]/BOOTSEL[1]
Input
GPIO port E / Boot mode
select
‡
47
48
49
PE[0]/BOOTSEL[0]
VSSRTC
I/O
RTC Gnd
O
Input
Real time clock ground
Real time clock oscillator
output
RTCOUT
Real time clock oscillator
input
50
RTCIN
I
51
52
VDDRTC
N/C
RTC power
Real time clock power, 2.5 V
GPIO port D / SDRAM byte
lane mask
53
54
PD[7]/SDQM[1]
PD[6]/SDQM[0]
1
1
Low
Low
I/O
I/O
GPIO port D / SDRAM byte
lane mask
55
56
57
58
59
60
61
PD[5]
PD[4]
VDDIO
TMS
1
1
Low
Low
I/O
I/O
GPIO port D
GPIO port D
Pad Pwr
I
Digital I/O power, 3.3 V
JTAG mode select
GPIO port D
with p/u*
PD[3]
PD[2]
PD[1]
1
1
1
Low
Low
Low
I/O
I/O
GPIO port D
I/O
GPIO port D
GPIO port D / LED blinker
output
62
63
PD[0]/LEDFLSH
SSICLK
1
1
Low
I/O
I/O
‡
DAI/CODEC/SSI2 serial clock
Input
64
65
VSSIO
Pad Gnd
I/O
I/O ground
SSITXFR
1
1
Low
Low
DAI/CODEC/SSI2 serial clock
DAI/CODEC/SSI2 serial data
output
66
SSITXDA
O
DAI/CODEC/SSI2 serial data
input
67
68
SSIRXDA
SSIRXFR
I
‡
I/O
DAI/CODEC/SSI2 frame sync
Input
69
70
71
72
73
74
ADCIN
nADCCS
VSSCORE
VDDCORE
VSSIO
I
SSI1 ADC serial input
SSI1 ADC chip select
Core ground
1
High
O
Core ground
Core Pwr
Pad Gnd
Pad Pwr
Core power, 2.5 V
I/O ground
VDDIO
Digital I/O power, 3.3 V
High /
Low
75
76
DRIVE[1]
DRIVE[0]
2
2
I/O
I/O
PWM drive output
PWM drive output
High /
Low
77
78
ADCCLK
ADCOUT
1
1
Low
Low
O
O
SSI1 ADC serial clock
SSI1 ADC serial data output
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
33
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
†
Signal
Type
Description
Strength
79
80
81
82
SMPCLK
FB[1]
1
Low
O
SSI1 ADC sample clock
PWM feedback input
I/O ground
I
VSSIO
FB[0]
Pad Gnd
I
PWM feedback input
Keyboard scanner column
drive
83
84
85
86
87
88
COL[7]
COL[6]
COL[5]
COL[4]
COL[3]
COL[2]
1
1
1
1
1
1
High
High
High
High
High
High
O
O
O
O
O
O
Keyboard scanner column
drive
Keyboard scanner column
drive
Keyboard scanner column
drive
Keyboard scanner column
drive
Keyboard scanner column
drive
89
90
VDDIO
TCLK
Pad Pwr
I
Digital I/O power, 3.3 V
JTAG clock
Keyboard scanner column
drive
91
92
COL[1]
COL[0]
1
1
High
High
O
O
Keyboard scanner column
drive
93
94
95
96
97
98
BUZ
D[31]
D[30]
D[29]
D[28]
VSSIO
1
1
1
1
1
Low
Low
Low
Low
Low
O
I/O
Buzzer drive output
Data I/O
I/O
Data I/O
I/O
Data I/O
I/O
Data I/O
Pad Gnd
I/O ground
System byte address /
SDRAM address
99
A[27]/DRA[0]
D[27]
2
1
2
1
2
Low
Low
Low
Low
Low
O
I/O
O
100
101
102
103
Data I/O
System byte address /
SDRAM address
A[26]/DRA[1]
D[26]
I/O
O
Data I/O
System byte address /
SDRAM address
A[25]/DRA[2]
104
105
D[25]
1
1
Low
Low
I/O
O
Data I/O
HALFWORD
Halfword access select output
System byte address /
SDRAM address
106
A[24]/DRA[3]
1
Low
O
107
108
109
VDDIO
VSSIO
D[24]
—
—
Pad Pwr
Pad Gnd
I/O
Digital I/O power, 3.3 V
I/O ground
1
1
1
1
1
1
1
Low
Data I/O
System byte address /
SDRAM address
110
111
112
113
114
A[23]/DRA[4]
D[23]
Low
Low
Low
Low
Low
Low
O
I/O
O
Data I/O
System byte address /
SDRAM address
A[22]/DRA[5]
D[22]
I/O
O
Data I/O
System byte address /
SDRAM address
A[21]/DRA[6]
115
116
D[21]
I/O
Data I/O
VSSIO
Pad Gnd
I/O ground
System byte address /
SDRAM address
117
A[20]/DRA[7]
1
Low
O
34
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
†
Signal
Type
Description
Strength
118
119
120
121
D[20]
1
1
1
1
1
Low
Low
Low
Low
Low
I/O
O
Data I/O
System byte address /
SDRAM address
A[19]/DRA[8]
D[19]
I/O
O
Data I/O
System byte address /
SDRAM address
A[18]/DRA[9]
122
123
124
125
D[18]
VDDIO
VSSIO
nTRST
I/O
Pad Pwr
Pad Gnd
I
Data I/O
Digital I/O power, 3.3 V
I/O ground
JTAG async reset input
System byte address /
SDRAM address
126
127
128
129
130
131
132
133
134
A[17]/DRA[10]
D[17]
1
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
Low
O
I/O
O
Data I/O
System byte address /
SDRAM address
A[16]/DRA[11]
D[16]
I/O
O
Data I/O
System byte address /
SDRAM address
A[15]/DRA[12]
D[15]
I/O
O
Data I/O
System byte address /
SDRAM address
A[14]/DRA[13]
D[14]
I/O
O
Data I/O
System byte address /
SDRAM address
A[13]/DRA[14]
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
D[13]
A[12]
D[12]
A[11]
VDDIO
VSSIO
D[11]
A[10]
D[10]
A[9]
1
1
1
1
Low
Low
Low
Low
I/O
Data I/O
System byte address
Data I/O
O
I/O
O
System byte address
Digital I/O power, 3.3 V
I/O ground
Pad Pwr
Pad Gnd
1
1
1
1
1
1
1
1
Low
Low
Low
Low
Low
Low
Low
Low
I/O
Data I/O
O
System byte address
Data I/O
I/O
O
System byte address
Data I/O
D[9]
I/O
A[8]
O
System byte address
Data I/O
D[8]
I/O
A[7]
O
System byte address
I/O ground
VSSIO
D[7]
Pad Gnd
1
Low
I/O
I
Data I/O
nBATCHG
Battery changed sense input
External power supply sense
input
152
nEXTPWR
I
153
154
BATOK
nPOR
I
I
Battery OK input
Schmitt
Schmitt
Power-on reset input
Media change interrupt input /
internal ROM boot enable
155
nMEDCHG/nBROM
I
156
157
158
159
160
nURESET
VDDOSC
MOSCIN
I
User reset input
Oscillator power in, 2.5 V
Main oscillator input
Main oscillator output
Oscillator Ground
Oscillator Power
I
MOSCOUT
VSSOSC
O
Oscillator Ground
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
35
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
†
Signal
Type
Description
Strength
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
WAKEUP
nPWRFL
A[6]
Schmitt
I
System wake up input
Power fail sense input
System byte address
Data I/O
I
1
1
1
1
Low
Low
Low
Low
O
D[6]
I/O
A[5]
Out
System byte address
Data I/O
D[5]
I/O
VDDIO
VSSIO
A[4]
Pad Pwr
Digital I/O power, 3.3 V
I/O ground
Pad Gnd
1
1
2
1
2
Low
Low
Low
Low
Low
O
System byte address
Data I/O
D[4]
I/O
A[3]
O
System byte address
Data I/O
D[3]
I/O
A[2]
O
System byte address
I/O ground
VSSIO
D[2]
Pad Gnd
1
2
1
2
1
Low
Low
Low
Low
Low
I/O
Data I/O
A[1]
O
System byte address
Data I/O
D[1]
I/O
O
A[0]
System byte address
Data I/O
D[0]
I/O
VSSCORE
VDDCORE
VSSIO
VDDIO
CL[2]
CL[1]
Core ground
Core Pwr
Pad ground
Pad Power
O
Core ground
Core power, 2.5 V
I/O ground
Digital I/O power, 3.3 V
LCD pixel clock out
LCD line clock
1
1
Low
Low
O
LCD frame synchronization
pulse
186
FRM
1
Low
O
187
188
189
190
191
192
193
194
195
196
197
198
199
200
M
1
1
1
Low
Low
Low
O
I/O
LCD AC bias drive
LCD serial display data
LCD serial display data
I/O ground
DD[3]
DD[2]
I/O
VSSIO
DD[1]
Pad Gnd
I/O
1
1
1
1
2
2
Low
Low
High
High
Low
Low
LCD serial display data
LCD serial display data
SDRAM chip select 1
SDRAM chip select 0
SDRAM byte lane mask
SDRAM byte lane mask
Digital I/O power, 3.3 V
I/O ground
DD[0]
I/O
nSDCS[1]
nSDCS[0]
SDQM[3]
SDQM[2]
VDDIO
VSSIO
SDCKE
SDCLK
O
O
I/O
I/O
Pad Pwr
Pad Gnd
I/O
2
2
Low
Low
SDRAM clock enable output
SDRAM clock out
I/O
ROM, expansion write
enable/ SDRAM write enable
control signal
201
202
nMWE/nSDWE
nMOE/nSDCAS
1
1
High
High
O
O
ROM, expansion OP
enable/SDRAM CAS control
signal
203
204
205
VSSIO
nCS[0]
nCS[1]
Pad Gnd
I/O ground
Chip select 0
Chip select 1
1
1
High
High
O
O
36
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin
No.
Reset
State
†
Signal
Type
Description
Strength
206
207
208
nCS[2]
nCS[3]
nCS[4]
1
1
1
High
High
High
O
O
O
Chip select 2
Chip select 3
Chip select 4
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
† Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
37
EP7312
High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
TOP VIEW
BOTTOM VIEW
Ø0.08 M C
Ø0.15 M C A B
Ø0.25~0.35(204X)
A1 CORNER
A1 CORNER
1
2 3 4 5 6 7 8 9 10 1112 13 14 15 16 17 18 19 20
20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
V
W
Y
U
V
W
Y
A
0.65
12.35
B
13±0.05
)
C
0.15(4X
Substrate Thickness :
0.36
Ball Pitch :
0.65
0.3
Ball Diameter :
Mold Thickness :
SEATING PLANE
C
0.53
Figure 17. 204-Ball TFBGA Package
38
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
nMWE/ SDQM[2
A
B
C
D
E
VDDIO EXPCLK nCS[3] nCS[1]
nSDCS[1] DD[2]
FRM
CL[1]
GNDCORE D[1]
A[2]
D[4]
A[5] nPWRFL MOSCOUT GNDIO
GNDIO
GNDIO
A
B
C
D
E
nSDWE
]
nMOE/
nSDCAS
WORD VDDIO nCS[5] nCS[2]
RUN/
SDCKE nSDCS[0] DD[1]
M
CL[2]
D[0]
A[0]
A[1]
D[2]
D[3]
A[3]
A[4]
D[5]
D[6] WAKEUP MOSCIN
A[6] GNDOSC VDDOSC
GNDIO
GNDIO
GNDIO nURESET
EXPRDY VDDIO
nCS[4] nCS[0] SDCLK SDQM[3] DD[0]
DD[3]
VDDCORE
BATOK
nPOR
A[7]
CLKEN
PB[7]
RXD[2] VDDIO
GNDIO nBATCHG
WRITE/
TXD[2]
nMEDCHG/n
nEXTPWR
BROM
PB[4]
PB[3]
PB[1]
PA[7]
PA[4]
PA[1]
D[9]
nSDRAS
F
PB[6]
PB[2]
TDO
TDI
D[7]
D[8]
A[8]
A[9]
D[10]
D[11]
A[12]
F
G
H
J
PB[5]
PB[0]
PA[6]
VDDIO
G
H
J
A[10]
A[11]
D[14]
D[12]
D[13]
A[13]/
DRA[14]
PA[5]
PA[2]
A[14]/
DRA[13]
K
L
D[15]
K
L
A[16]/
DRA[11]
TXD[1] LEDDRV PA[3]
VDDIO
A[15]/
D[16]
A[17]/
M
N
P
R
RXD[1]
CTS
PA[0]
nTRST
M
N
P
R
DRA[12] DRA[10]
A[18]/
DRA[9]
DSR nTEST[1] PHDIN
D[17]
D[18]
D[19]
A[20]/
DRA[7]
EINT[3] nEINT[2] DCD
PE2/
D[20]
A[19]/
DRA[8]
A[21]/
DRA6
nEXTFIQ
nTEST[0]
D[22]
D[23]
CLKSEL
PE[1]/
BOOT
PE[0]/
A[22]/
DRA5
T
BOOT nEINT[1]
D[21]
T
SEL[1] SEL[0]
HALF
A[23]/
DRA4
U
V
GNDRTC RTCOUT RTCIN
D[24]
VDDIO
VDDIO
U
V
WORD
PD[7]/
SSIRXD
A
A[26]/
A[24]/
DRA3
VDDRTC GNDIO GNDIO
GNDIO GNDIO GNDIO
PD[4] PD[2] SSICLK
nADCCS
VDDIO
ADCCLK COL[7] COL[4] TCLK BUZ
D[29]
VDDIO
D[26]
SDQM[1]
DRA[1]
PD[6]/
SDQM[0]
A[27]/
DRA[0]
W
TMS
PD[1] SSITXFR SSIRXFR GNDCORE DRIVE[1] ADCOUT FB[0] COL[5] COL[2] COL[0] D[30]
D[25]
W
PD[0]/
A[25]/
DRA[2]
Y
GNDIO GNDIO GNDIO
PD[5]
PD[3]
LED SSITXDA ADCIN VDDCORE DRIVE[0] SMPCLK FB[1] COL[6] COL[3] COL[1] D[31]
FLSH
D[28]
D[27]
VDDIO
Y
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
39
EP7312
High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing
The list is ordered by ball location.
Table 21. 204-Ball TFBGA Ball Listing
Reset
State
†
Ball Location
Name
Type
Description
Strength
Digital I/O power,
3.3 V
A1
VDDIO
Pad power
A2
EXPCLK
nCS[3]
nCS[1]
1
1
1
1
2
1
1
1
1
I
Expansion clock input
Chip select 3
A3
High
High
High
Low
High
Low
Low
Low
O
A4
O
Chip select 1
A5
nMWE/nSDWE
SDQM[2]
nSDCS[1]
DD[2]
O
ROM, expansion write enable/ SDRAM write enable control signal
SDRAM byte lane mask
SDRAM chip select 2
LCD serial display data
LCD frame synchronization pulse
LCD line clock
A6
O
A7
O
A8
O
A9
FRM
O
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
CL[1]
O
VSSCORE
D[1]
Core ground
Core ground
1
2
1
1
Low
Low
Low
Low
I/O
Data I/O
A[2]
O
System byte address
Data I/O
D[4]
I/O
A[5]
O
System byte address
Power fail sense input
Main oscillator out
nPWRFL
MOSCOUT
VSSIO
VSSIO
VSSIO
WORD
VDDIO
nCS[5]
nCS[2]
nMOE/nSDCAS
SDCKE
nSDCS[0]
DD[1]
I
O
Pad ground
I/O ground
Pad ground
I/O ground
Pad ground
I/O ground
1
Low
O
Word access select output
Digital I/O power, 3.3 V
Chip select 5
B2
Pad power
B3
1
1
1
2
1
1
1
1
1
2
2
Low
High
High
Low
High
Low
Low
Low
Low
Low
Low
O
O
B4
Chip select 2
B5
O
ROM, expansion OP enable/SDRAM CAS control signal
SDRAM clock enable output
SDRAM chip select 0
LCD serial display data
LCD AC bias drive
B6
O
B7
O
B8
O
B9
M
O
B10
B11
B12
B13
CL[2]
0
LCD pixel clock out
Data I/O
D[0]
I/O
O
A[1]
System byte address
Data I/O
D[3]
I/O
40
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
B14
A[4]
1
1
Low
Low
O
System byte address
Data I/O
B15
B16
B17
B18
B19
B20
C1
D[6]
I/O
WAKEUP
MOSCIN
VSSIO
VSSIO
Schmitt
I
System wake up input
Main oscillator input
I/O ground
I
Pad ground
Pad ground
I/O ground
nURESET
RUN/CLKEN
EXPRDY
Schmitt
I
0
I
User reset input
1
1
Low
Run output / clock enable output
Expansion port ready input
C2
Digital I/O power,
3.3 V
C3
VDDIO
Pad power
C4
nCS[4]
nCS[0]
SDCLK
SDQM[3]
DD[0]
1
1
2
2
1
1
High
High
Low
Low
Low
Low
O
Chip select 4
C5
O
Chip select 0
C6
O
SDRAM clock out
SDRAM byte lane mask
LCD serial display data
LCD serial display data
Digital core power, 2.5 V
System byte address
Data I/O
C7
O
C8
O
C9
DD[3]
O
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
VDDCORE
A[0]
Core power
2
1
2
1
1
Low
Low
Low
Low
Low
O
D[2]
I/O
A[3]
O
System byte address
Data I/O
D[5]
I/O
A[6]
O
System byte address
PLL ground
VSSOSC
VDDOSC
VSSIO
BATOK
Oscillator ground
Oscillator power
Pad ground
I
Oscillator power in, 2.5V
I/O ground
Battery ok input
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
41
EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
Schmitt
1
C20
nPOR
PB[7]
I
I
Power-on reset input
GPIO port B
‡
D1
Input
D2
RXD[2]
VDDIO
VSSIO
I
UART 2 receive data input
Digital I/O power, 3.3V
I/O ground
D3
Pad power
D18
D19
D20
Pad ground
nBATCHG
A[7]
I
Battery changed sense input
System byte address
1
1
Low
O
‡
E1
PB[4]
I
GPIO port B
Input
E2
TXD[2]
1
1
High
Low
O
O
I
UART 2 transmit data output
E3
WRITE/nSDRAS
nMEDCHG/nBROM
nEXTPWR
D[9]
Transfer direction / SDRAM RAS signal output
Media change interrupt input / internal ROM boot enable
External power supply sense input
Data I/O
E18
E19
E20
I
1
1
Low
I/O
‡
F1
F2
PB[3]
PB[6]
I/O
I/O
GPIO port B
GPIO port B
Input
‡
1
Input
F3
TDI
with p/u*
I
JTAG data input
Data I/O
F18
F19
F20
D[7]
A[8]
D[10]
1
1
1
Low
Low
Low
I/O
O
System byte address
Data I/O
I/O
‡
G1
PB[1]
PB[2]
PB[5]
D[8]
1
1
1
1
I/O
I/O
I/O
I/O
Input
‡
G2
GPIO port B
GPIO port B
Data I/O
Input
‡
G3
Input
‡
G18
Input
G19
G20
A[9]
1
1
Low
Low
O
System byte address
Data I/O
D[11]
I/O
‡
H1
PA[7]
TDO
PB[0]
1
1
1
I/O
O
GPIO port A
JTAG data out
GPIO port B
Input
‡
H[2]
H[3]
Input
‡
I/O
Input
H[18]
H19
A[10]
D[12]
A[12]
1
1
1
Low
Low
Low
O
I/O
O
System byte address
Data I/O
H20
System byte address
‡
J1
PA[4]
1
I/O
GPIO port A
Input
42
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
‡
J2
PA[5]
PA[6]
1
1
I/O
I/O
GPIO port A
GPIO port A
Input
‡
J3
Input
J18
J19
J20
A[11]
D[13]
1
1
1
Low
Low
Low
O
I/O
O
System byte address
Data I/O
A[13]/DRA[14]
PA[1]
System byte address / SDRAM address
GPIO port A
‡
K1
K2
1
1
I/O
I/O
Input
‡
PA[2]
GPIO port A
Input
K3
VDDIO
Pad power
Digital I/O power, 3.3V
Data I/O
K18
K19
K20
L1
D[14]
1
1
1
1
1
Low
Low
Low
High
Low
I/O
O
A[14]/DRA[13]
D[15]
System byte address / SDRAM address
Data I/O
I/O
O
TXD[1]
UART 1 transmit data out
IR LED drive
L2
LEDDRV
O
‡
L3
PA[3]
1
I/O
GPIO port A
Input
L18
L19
L20
M1
VDDIO
D[16]
Pad power
Digital I/O power, 3.3V
1
1
Low
Low
I/O
Data I/O
A[16]/DRA[11]
RXD[1]
CTS
O
I
System byte address / SDRAM address
UART 1 receive data input
UART 1 clear to send input
M2
I
‡
M3
PA[0]
1
I/O
GPIO port A
Input
M18
M19
M20
N1
A[15]/DRA[12]
A[17]/DRA[10]
nTRST
1
1
Low
Low
O
O
I
System byte address / SDRAM address
System byte address / SDRAM address
JTAG async reset input
UART 1 data set ready input
Test mode select input
Photodiode input
DSR
I
N2
nTEST[1]
PHDIN
With p/u*
I
N3
I
N18
N19
N20
P1
D[17]
1
1
1
Low
Low
Low
I/O
I/O
O
I
Data I/O
D[19]
Data I/O
A[18]/DRA[9]
EINT[3]
System byte address / SDRAM address
External interrupt
P2
nEINT[2]
DCD
I
External interrupt input
UART 1 data carrier detect
Data I/O
P3
I
P18
P19
D[18]
1
1
Low
Low
I/O
O
A[20]/DRA[7]
System byte address / SDRAM address
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
43
EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
P20
D[20]
1
Low
I/O
I
Data I/O
R1
R2
nEXTFIQ
External fast interrupt input
‡
PE[2]/CLKSEL
1
I/O
GPIO port E / clock input mode select
Input
R3
nTEST[0]
A[19]/DRA[8]
D[22]
With p/u*
I
Test mode select input
R18
R19
R20
1
1
1
Low
Low
Low
O
System byte address / SDRAM address
Data I/O
I/O
O
A[21]/DRA[6]
System byte address / SDRAM address
‡
T1
T2
PE[1]/BOOTSEL[1]
PE[0]/BOOTSEL[0]
1
1
I/O
I/O
GPIO port E / boot mode select
GPIO port E / boot mode select
Input
‡
Input
T3
nEINT[1]
D[21]
I
External interrupt input
Data I/O
T18
T19
T20
U1
1
1
1
Low
Low
Low
I/O
D[23]
I/O
Data I/O
A[22]/DRA[5]
VSSRTC
RTCOUT
RTCIN
O
System byte address / SDRAM address
Real time clock ground
Real time clock oscillator output
Real time clock oscillator input
Halfword access select output
Data I/O
RTC ground
U2
O
U3
I/O
U18
U19
U20
V1
HALFWORD
D[24]
1
1
1
Low
Low
Low
O
I/O
O
A[23]/DRA[4]
VDDRTC
VSSIO
System byte address / SDRAM address
Real time clock power, 2.5V
I/O ground
RTC power
Pad ground
Pad ground
I/O
V2
V3
VSSIO
I/O ground
V4
PD[7]/SDQM[1]
PD[4]
1
1
1
Low
Low
Low
GPIO port D / SDRAM byte lane mask
GPIO port D
V5
I/O
V6
PD[2]
I/O
GPIO port D
‡
V7
SSICLK
1
I/O
DAI/CODEC/SSI2 serial clock
Input
V8
SSIRXDA
nADCCS
VDDIO
ADCCLK
COL[7]
COL[4]
TCLK
I/O
DAI/CODEC/SSI2 serial data input
SSI1 ADC chip select
Digital I/O power, 3.3V
SSI1 ADC serial clock
Keyboard scanner column drive
Keyboard scanner column drive
JTAG clock
V9
1
High
O
V10
V11
V12
V13
V14
V15
V16
Pad power
1
1
1
Low
High
High
O
O
O
I
BUZ
1
1
Low
Low
O
I/O
Buzzer drive output
D[29]
Data I/O
44
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
V17
A[26]/DRA[1]
2
Low
O
System byte address / SDRAM address
Digital I/O power,
3.3 V
V18
V19
VDDIO
VDDIO
Pad power
Digital I/O power,
3.3 V
Pad power
V20
W1
W2
W3
W4
W5
W6
W7
A[24]/DRA[3]
VSSIO
‘
Low
O
System byte address / SDRAM address
I/O ground
Pad ground
VSSIO
Pad ground
I/O ground
VSSIO
Pad ground
I/O ground
PD[6]/SDQM[0]
TMS
1
Low
I/O
I
GPIO port D / SDRAM byte lane mask
JTAG mode select
with p/u*
PD[1]
1
1
Low
Low
I/O
I/O
GPIO port D
SSITXFR
DAI/CODEC/SSI2 frame sync
‡
W8
SSIRXFR
VSSCORE
DRIVE[1]
1
I/O
Core Ground
I/O
DAI/CODEC/SSI2 frame sync
Core Ground
Input
W9
High /
Low
W10
2
1
PWM drive output
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Y1
ADCOUT
FB[0]
Low
O
SSI1 ADC serial data output
PWM feedback input
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
I
COL[5]
COL[2]
COL[0]
D[30]
1
1
1
1
2
1
High
High
High
Low
Low
Low
O
O
O
I/O
A[27]/DRA[0]
D[26]
O
System byte address / SDRAM address
Data I/O
I/O
VDDIO
D[25]
Pad power
Digital I/O power, 3.3V
Data I/O
1
Low
I/O
VSSIO
Pad ground
I/O ground
Y2
VSSIO
Pad ground
I/O ground
Y3
VSSIO
Pad ground
I/O ground
Y4
PD[5]
1
1
1
1
Low
Low
Low
Low
I/O
GPIO port D
Y5
PD[3]
I/O
GPIO port D
Y6
PD[0]/LEDFLSH
SSITXDA
ADCIN
I/O
GPIO port D / LED blinker output
DAI/CODEC/SSI2 serial data output
SSI1 ADC serial input
Digital core power, 2.5V
Y7
O
Y8
I
Y9
VDDCORE
Core power
‡
Y10
DRIVE[0]
2
I/O
PWM drive output
Input
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
45
EP7312
High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
Y11
SMPCLK
FB[1]
1
Low
O
SSI1 ADC sample clock
PWM feedback input
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
I
COL[6]
COL[3]
COL[1]
D[31]
1
1
1
1
1
1
2
High
High
High
Low
Low
Low
Low
O
O
O
I/O
I/O
D[28]
Data I/O
D[27]
I/O
Data I/O
A[25]/DRA[2]
VDDIO
O
System byte address / SDRAM address
Digital I/O power, 3.3V
Pad power
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
† Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
256-Ball PBGA Package Characteristics
Figure 18. 256-Ball PBGA Package
Note: 1) For pin locations see Table 22.
2) Dimensions are in millimeters (inches), and controlling dimension is millimeter
3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information.
46
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
0.85 (0.034)
±0.05 (.002)
17.00 (0.669)
±0.20 (.008)
0.40 (0.016)
±0.05 (.002)
Pin 1 Corner
15.00 (0.590)
±0.20 (.008)
D1
30° TYP
Pin 1 Indicator
17.00 (0.669)
±0.20 (.008)
E1
15.00 (0.590)
±0.20 (.008)
2 Layer
0.36 (0.014)
±0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669)
Pin 1 Corner
1.00 (0.040)
1.00 (0.040)
REF
E
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
1.00 (0.040)
REF
A
B
C
D
E
F
G
H
J
1.00 (0.040)
17.00 (0.669)
K
L
M
N
P
R
T
0.50
R
BOTTOM VIEW
3 Places
JEDEC #: MO-151
Ball Diameter: 0.50 mm 0.10 mm
17 ¥ 17 ¥ 1.61 mm body
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
47
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
VDDIO
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
MOSCOUT VDDOSC
VSSIO
A
B
C
D
E
nMOE/
nSDCAS
nCS[5]
VDDIO
VDDIO
EXPCLK
EXPRDY
PB[7]
nCS[3]
VSSIO
VSSIO
TDI
VDDIO
VSSIO
nCS[2]
VSSIO
nSDCS[1]
VSSIO
DD[2]
VSSIO
CL[1]
VDDIO
CL[2]
VDDCORE
VSSIO
VSSRTC
A[0]
D[1]
VSSIO
D[4]
A[2]
VSSIO
nPWRFL
VSSOSC
VSSRTC
A[7]
A[4]
VDDIO
MOSCIN
VSSIO
BATOK
A[8]
A[5]
WAKEUP
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
nTRST
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
nPOR
D[7]
nURESET
nEXTPWR
D[8]
VDDIO
VDDIO
WORD
TXD[2]
PB[4]
VSSIO
VDDIO
WRITE/
nSDRAS
nMWE/
nSDWE
nSDCS[0]
SDQM[2]
SDCKE
VSSRTC
PB[2]
nMEDCHG/
nBROM
RXD[2]
PB[5]
nCS[0]
VSSIO
FRM
D[5]
D[9]
D[10]
RUN/
CLKEN
F
PB[3]
VSSIO
TDO
DD[3]
A[1]
D[6]
nBATCHG
A[9]
D[11]
D[12]
D[14]
D[16]
VDDIO
VDDIO
D[13]
F
G
H
J
PB[1]
VDDIO
PA[5]
PB[6]
PA[6]
VSSCore
PB[0]
DD[0]
D[3]
VSSRTC
A[10]
G
H
J
A[13]/
DRA[14]
PA[7]
VSSIO
VSSIO
VSSIO
VDDIO
VDDIO
VSSIO
VSSIO
PD[4]
PA[4]
VSSRTC
VSSRTC
ADCIN
VSSRTC
DRIVE[1]
ADCCLK
VDDIO
ADCOUT
VSSRTC
VSSRTC
COL[4]
COL[6]
FB[0]
A[11]
A[12]
D[15]
A[17]/
DRA[10]
A[16]/
DRA[11]
A[15]/
DRA[12]
A[14]/
DRA[13]
PA[3]
PA[1]
PA[2]
PA[0]
TXD[1]
EINT[3]
VSSRTC
VDDIO
PD[2]
CTS
D[17]
K
L
LEDDRV
RXD[1]
nTEST[0]
nEXTFIQ
VSSRTC
RTCIN
PHDIN
DSR
DCD
nTEST[1]
VSSRTC
TCLK
D[31]
D[20]
VSSRTC
D[27]
D[19]
D[18]
VDDIO
K
L
PE[2]/
CLKSEL
PD[0]/
LEDFLSH
A[22]/
DRA[5]
A[21]/
DRA[6]
A[18]/
DRA[9]
A[19]/
DRA[8]
nEINT[1]
PE[0]/
BOOTSEL[0]
A[23]/
DRA[4]
A[20]/
DRA[7]
M
N
P
R
T
nEINT[2]
TMS
PD[5]
SSITXFR
SSIRXDA
VSSIO
COL[0]
COL[2]
VDDIO
COL[3]
COL[5]
VSSIO
D[26]
VSSIO
D[30]
BUZ
D[21]
D[23]
VDDIO
M
N
P
R
T
PE[1]/
BOOTSEL[1]
VDDIO
VSSIO
PD[1]
PD[3]
SMPCLK
VSSIO
COL[7]
FB[1]
D[29]
HALFWORD
VDDIO
D[22]
D[24]
VDDIO
D[25]
RTCOUT
VDDIO
VDDIO
SSITXDA
SSICLK
VSSIO
VSSIO
COL[1]
VDDIO
A[27]/
DRA[0]
A[25]/
DRA[2]
A[24]\
DRA[3]
nADCCS
VDDIO
PD[7]/
SDQM[1]
PD[6]/
SDQM[0]
A[26]/
DRA[1]
VDDRTC
SSIRXFR VDDCORE DRIVE[0]
D[28]
VSSIO
48
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table 22. 256-Ball PBGA Ball Listing
Reset
State
†
Ball Location
Name
Type
Description
Strength
A1
A2
VDDIO
nCS[4]
nCS[1]
SDCLK
SDQM[3]
DD[1]
Pad power
Digital I/O power, 3.3 V
Chip select 4
1
1
2
2
1
1
High
High
Low
Low
Low
Low
O
A3
O
Chip select 1
A4
O
SDRAM clock out
SDRAM byte lane mask
LCD serial display data
LCD AC bias drive
Digital I/O power, 3.3 V
Data I/O
A5
O
A6
O
A7
M
O
A8
VDDIO
D[0]
Pad power
A9
1
1
2
Low
Low
Low
I/O
A10
A11
A12
A13
A14
A15
A16
B1
D[2]
I/O
Data I/O
A[3]
O
System byte address
Digital I/O power, 3.3V
System byte address
Main oscillator out
Oscillator power in, 2.5 V
I/O ground
VDDIO
A[6]
Pad power
1
Low
O
MOSCOUT
VDDOSC
VSSIO
nCS[5]
VDDIO
nCS[3]
nMOE/nSDCAS
VDDIO
nSDCS[1]
DD[2]
O
Oscillator power
Pad ground
1
Low
O
Chip select 5
B2
Pad power
Digital I/O power, 3.3 V
Chip select 3
B3
1
1
High
High
O
B4
O
Pad power
O
ROM, expansion OP enable/SDRAM CAS control signal
Digital I/O power, 3.3 V
SDRAM chip select 1
LCD serial display data
LCD line clock
B5
B6
1
1
1
High
Low
Low
B7
O
B8
CL[1]
O
B9
VDDCORE
D[1]
Core power
I/O
Digital core power, 2.5V
Data I/O
B10
B11
B12
B13
B14
B15
B16
C1
1
Low
Low
Low
Low
A[2]
2
O
System byte address
System byte address
System byte address
System wake up input
Digital I/O power, 3.3 V
User reset input
A[4]
1
1
O
A[5]
O
WAKEUP
VDDIO
nURESET
VDDIO
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
Schmitt
I
Pad power
I
Schmitt
1
Pad power
I
Digital I/O power, 3.3V
Expansion clock input
I/O ground
C2
C3
Pad ground
Pad power
Pad ground
Pad ground
Pad ground
Pad power
Pad ground
Pad ground
Pad ground
Pad power
Pad ground
C4
Digital I/O power, 3.3 V
I/O ground
C5
C6
I/O ground
C7
I/O ground
C8
Digital I/O power, 3.3 V
I/O ground
C9
C10
C11
C12
C13
I/O ground
I/O ground
Digital I/O power, 3.3 V
I/O ground
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
49
EP7312
High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
C14
C15
C16
D1
VSSIO
nPOR
Pad ground
I/O ground
Schmitt
I
Power-on reset input
External power supply sense input
nEXTPWR
WRITE/nSDRAS
EXPRDY
VSSIO
I
1
1
Low
O
Transfer direction / SDRAM RAS signal output
Expansion port ready input
I/O ground
D2
I
D3
Pad ground
D4
VDDIO
Pad power
Digital I/O power, 3.3V
Chip select 2
D5
nCS[2]
1
1
1
1
High
High
High
Low
O
D6
nMWE/nSDWE
nSDCS[0]
CL[2]
O
ROM, expansion write enable/ SDRAM write enable control signal
SDRAM chip select 2
LCD pixel clock out
D7
O
D8
O
D9
VSSRTC
D[4]
Core ground
Real time clock ground
Data I/O
D10
D11
D12
D13
D14
D15
D16
E1
1
Low
I/O
nPWRFL
MOSCIN
VDDIO
I
Power fail sense input
Main oscillator input
I
Pad power
Digital I/O power, 3.3V
I/O ground
VSSIO
Pad ground
D[7]
1
1
Low
Low
I/O
I/O
I
Data I/O
D[8]
Data I/O
RXD[2]
UART 2 receive data input
‡
E2
PB[7]
1
I
GPIO port B
Input
E3
E4
TDI
WORD
VSSIO
with p/u*
1
I
JTAG data input
Low
O
Word access select output
E5
Pad ground
I/O ground
E6
nCS[0]
1
2
1
2
1
High
Low
Low
Low
Low
O
Chip select 0
E7
SDQM[2]
FRM
O
SDRAM byte lane mask
E8
O
LCD frame synchronization pulse
E9
A[0]
O
System byte address
E10
E11
E12
E13
E14
E15
E16
D[5]
I/O
Data I/O
VSSOSC
VSSIO
Oscillator ground
PLL ground
Pad ground
I/O ground
nMEDCHG/nBROM
VDDIO
D[9]
I
Pad power
I/O
Media change interrupt input / internal ROM boot enable
Digital I/O power, 3.3V
Data I/O
1
1
Low
Low
D[10]
I/O
Data I/O
‡
F1
F2
PB[5]
PB[3]
1
1
I
I
GPIO port B
GPIO port B
Input
‡
Input
F3
F4
VSSIO
TXD[2]
RUN/CLKEN
VSSIO
SDCKE
DD[3]
Pad ground
I/O ground
1
1
High
Low
O
UART 2 transmit data output
Run output / clock enable output
I/O ground
F5
O
F6
Pad ground
F7
2
1
2
1
Low
Low
Low
Low
O
SDRAM clock enable output
LCD serial display data
System byte address
Data I/O
F8
O
F9
A[1]
O
F10
F11
F12
D[6]
I/O
VSSRTC
BATOK
RTC ground
I
Real time clock ground
Battery OK input
50
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
F13
F14
F15
F16
nBATCHG
VSSIO
D[11]
I
Battery changed sense input
I/O ground
Pad ground
I/O
1
1
Low
Data I/O
VDDIO
Pad power
Digital I/O power, 3.3V
‡
G1
G2
G3
PB[1]
VDDIO
TDO
I
Pad power
O
GPIO port B
Input
Digital I/O power, 3.3V
JTAG data out
‡
1
1
1
Input
‡
G4
G5
PB[4]
PB[6]
I
I
GPIO port B
GPIO port B
Input
‡
Input
G6
G7
VSSCore
VSSRTC
DD[0]
D[3]
Core ground
Core ground
RTC ground
Real time clock ground
LCD serial display data
Data I/O
G8
1
1
Low
Low
O
G9
I/O
G10
G11
G12
G13
G14
G15
G16
VSSRTC
A[7]
RTC ground
Real time clock ground
System byte address
System byte address
System byte address
I/O ground
1
1
1
Low
Low
Low
O
A[8]
O
A[9]
O
Pad ground
I/O
VSSIO
D[12]
1
1
Low
Low
Data I/O
D[13]
I/O
Data I/O
‡
H1
PA[7]
1
1
I/O
GPIO port A
Input
‡
H2
H3
H4
PA[5]
VSSIO
PA[4]
I/O
Pad ground
I/O
GPIO port A
I/O ground
Input
‡
1
1
1
1
GPIO port A
Input
‡
H5
H6
H7
PA[6]
PB[0]
PB[2]
I/O
I/O
I/O
GPIO port A
GPIO port B
GPIO port B
Input
‡
Input
‡
Input
H8
VSSRTC
VSSRTC
A[10]
RTC ground
Real time clock ground
Real time clock ground
System byte address
System byte address
System byte address
H9
RTC ground
H10
H11
H12
H13
H14
H15
H16
1
1
1
1
Low
Low
Low
Low
O
A[11]
O
A[12]
O
A[13]/DRA[14]
VSSIO
O
Pad ground
I/O
System byte address / SDRAM address
I/O ground
Data I/O
Data I/O
D[14]
1
1
Low
Low
D[15]
I/O
‡
J1
PA[3]
1
1
I/O
GPIO port A
Input
‡
J2
J3
J4
PA[1]
VSSIO
PA[2]
I/O
Pad ground
I/O
GPIO port A
I/O ground
Input
‡
1
GPIO port A
Input
‡
J5
J6
PA[0]
1
1
I/O
O
GPIO port A
Input
TXD[1]
High
UART 1 transmit data out
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
51
EP7312
High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
J7
J8
CTS
VSSRTC
VSSRTC
A[17]/DRA[10]
A[16]/DRA[11]
A[15]/DRA[12]
A[14]/DRA[13]
nTRST
I
UART 1 clear to send input
Real time clock ground
Real time clock ground
RTC ground
J9
RTC ground
J10
J11
J12
J13
J14
J15
J16
K1
1
1
1
1
Low
Low
Low
Low
O
System byte address / SDRAM address
System byte address / SDRAM address
System byte address / SDRAM address
System byte address / SDRAM address
JTAG async reset input
Data I/O
O
O
O
I
D[16]
1
1
1
Low
Low
Low
I/O
D[17]
I/O
Data I/O
LEDDRV
PHDIN
O
IR LED drive
K2
I
Photodiode input
K3
VSSIO
Pad ground
I/O ground
K4
DCD
I
UART 1 data carrier detect
Test mode select input
External interrupt
K5
nTEST[1]
EINT[3]
VSSRTC
ADCIN
With p/u*
I
K6
I
K7
RTC ground
Real time clock ground
SSI1 ADC serial input
Keyboard scanner column drive
JTAG clock
K8
I
K9
COL[4]
1
High
O
K10
K11
K12
K13
K14
K15
K16
L1
TCLK
I
D[20]
1
1
1
Low
Low
Low
I/O
Data I/O
D[19]
I/O
Data I/O
D[18]
I/O
Data I/O
VSSIO
Pad ground
I/O ground
VDDIO
Pad power
Digital I/O power, 3.3V
Digital I/O power, 3.3V
UART 1 receive data input
UART 1 data set ready input
Digital I/O power, 3.3V
External interrupt input
VDDIO
Pad power
RXD[1]
I
L2
DSR
I
L3
VDDIO
Pad power
I
L4
nEINT[1]
‡
L5
PE[2]/CLKSEL
1
1
I/O
GPIO port E / clock input mode select
Input
L6
L7
VSSRTC
PD[0]/LEDFLSH
VSSRTC
RTC ground
Real time clock ground
Low
I/O
GPIO port D / LED blinker output
Real time clock ground
L8
Core ground
L9
COL[6]
1
1
High
Low
O
Keyboard scanner column drive
Data I/O
L10
L11
L12
L13
L14
L15
L16
M1
M2
M3
D[31]
I/O
VSSRTC
RTC ground
Real time clock ground
A[22]/DRA[5]
A[21]/DRA[6]
VSSIO
1
1
Low
Low
O
System byte address / SDRAM address
System byte address / SDRAM address
I/O ground
O
Pad ground
A[18]/DRA[9]
A[19]/DRA[8]
nTEST[0]
nEINT[2]
1
1
Low
Low
O
System byte address / SDRAM address
System byte address / SDRAM address
Test mode select input
O
With p/u*
I
I
External interrupt input
VDDIO
Pad power
Digital I/O power, 3.3V
‡
M4
M5
PE[0]/BOOTSEL[0]
TMS
1
I
I
GPIO port E / Boot mode select
JTAG mode select
Input
with p/u*
52
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
M6
M7
VDDIO
Pad power
I/O
Digital I/O power, 3.3V
SSITXFR
1
2
Low
DAI/CODEC/SSI2 frame sync
High /
Low
M8
DRIVE[1]
I/O
PWM drive output
M9
FB[0]
COL[0]
I
PWM feedback input
Keyboard scanner column drive
Data I/O
M10
M11
M12
M13
M14
M15
M16
N1
1
1
High
Low
O
D[27]
I/O
VSSIO
Pad ground
I/O ground
A[23]/DRA[4]
VDDIO
1
Low
O
System byte address / SDRAM address
Digital I/O power, 3.3V
Pad power
A[20]/DRA[7]
D[21]
1
1
Low
Low
O
I/O
I
System byte address / SDRAM address
Data I/O
nEXTFIQ
External fast interrupt input
‡
N2
PE[1]/BOOTSEL[1]
1
I/O
GPIO port E / boot mode select
Input
N3
N4
VSSIO
VDDIO
PD[5]
Pad ground
Pad power
I/O
I/O ground
Digital I/O power, 3.3V
GPIO port D
N5
1
1
Low
Low
N6
PD[2]
I/O
GPIO port D
N7
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
I/O
DAI/CODEC/SSI2 serial data input
SSI1 ADC serial clock
SSI1 ADC sample clock
Keyboard scanner column drive
Data I/O
N8
1
1
1
1
1
1
Low
Low
High
Low
Low
Low
O
N9
O
N10
N11
N12
N13
N14
N15
N16
P1
O
I/O
D[26]
I/O
Data I/O
HALFWORD
VSSIO
D[22]
O
Halfword access select output
I/O ground
Pad ground
I/O
1
1
Low
Low
Data I/O
D[23]
I/O
Data I/O
VSSRTC
RTCOUT
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
D[24]
RTC ground
O
Real time clock ground
Real time clock oscillator output
I/O ground
P2
P3
Pad ground
Pad ground
Pad power
Pad ground
Pad ground
Pad power
Pad ground
Pad power
Pad ground
Pad ground
Pad power
Pad ground
I/O
P4
I/O ground
P5
Digital I/O power, 3.3V
I/O ground
P6
P7
I/O ground
P8
Digital I/O power, 3.3V
I/O ground
P9
P10
P11
P12
P13
P14
P15
P16
R1
Digital I/O power, 3.3V
I/O ground
I/O ground
Digital I/O power
I/O ground
1
Low
Data I/O
VDDIO
RTCIN
VDDIO
PD[4]
Pad power
I/O
Digital I/O power, 3.3V
Real time clock oscillator input
Digital I/O power, 3.3V
GPIO port D
R2
Pad power
I/O
R3
1
1
Low
Low
R4
PD[1]
I/O
GPIO port D
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
53
EP7312
High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Reset
State
†
Ball Location
Name
Type
Description
Strength
R5
R6
SSITXDA
nADCCS
VDDIO
1
1
Low
O
DAI/CODEC/SSI2 serial data output
SSI1 ADC chip select
High
O
R7
Pad power
Digital I/O power, 3.3V
R8
ADCOUT
COL[7]
1
1
1
1
1
2
2
Low
High
High
High
Low
Low
Low
O
SSI1 ADC serial data output
Keyboard scanner column drive
Keyboard scanner column drive
Keyboard scanner column drive
Data I/O
R9
O
R10
R11
R12
R13
R14
R15
R16
T1
COL[3]
O
COL[1]
O
D[30]
I/O
A[27]/DRA[0]
A[25]/DRA[2]
VDDIO
O
System byte address / SDRAM address
System byte address / SDRAM address
Digital I/O power, 3.3V
O
Pad power
O
A[24]/DRA[3]
VDDRTC
PD[7]/SDQM[1]
PD[6]/SDQM[0]
PD[3]
1
Low
System byte address / SDRAM address
Real time clock power, 2.5V
RTC power
I/O
T2
1
1
1
Low
Low
Low
GPIO port D / SDRAM byte lane mask
GPIO port D / SDRAM byte lane mask
GPIO port D
T3
I/O
T4
I/O
‡
T5
SSICLK
1
1
I/O
DAI/CODEC/SSI2 serial clock
Input
‡
T6
T7
T8
SSIRXFR
VDDCORE
DRIVE[0]
I/O
Core power
I/O
DAI/CODEC/SSI2 frame sync
Core power, 2.5V
Input
High /
Low
2
1
PWM drive output
T9
FB[1]
COL[5]
VDDIO
BUZ
I
PWM feedback input
Keyboard scanner column drive
Digital I/O power, 3.3V
Buzzer drive output
Data I/O
T10
T11
T12
T13
T14
T15
T16
High
O
Pad power
1
1
2
1
Low
Low
Low
Low
O
D[28]
I/O
O
A[26]/DRA[1]
D[25]
System byte address / SDRAM address
Data I/O
I/O
VSSIO
Pad ground
I/O ground
*
“With p/u” means with internal pull-up of 100 KOhms on the pin.
† Strength 1 = 4 ma
Strength 2 = 12 ma
‡
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
JTAG Boundary Scan Signal Ordering
Table 23. JTAG Boundary Scan Signal Ordering
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
1
4
5
6
7
B3
A2
B1
E3
C1
B1
C2
E4
D1
F5
nCS[5]
EXPCLK
O
I/O
O
1
3
WORD
6
WRITE/nSDRAS
RUN/CLKEN
O
8
O
10
54
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
8
C2
E2
D2
F3
D1
F2
E1
F1
G2
G1
H3
H1
J3
D2
F4
E1
E2
G5
F1
G4
F2
H7
G1
H6
H1
H5
H2
H4
J1
EXPRDY
TXD2
I
O
13
14
16
17
20
23
26
29
32
35
38
41
44
47
50
53
56
59
62
65
67
69
70
71
72
73
74
75
76
77
78
79
80
9
10
13
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
40
41
42
43
44
45
RXD2
PB[7]
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
PB[6]
PB[5]
PB[4]
PB[3]
PB[2]
PB[1]
PB[0]
PA[7]
PA[6]
J2
PA[5]
J1
PA[4]
L3
PA[3]
K2
K1
M3
L2
J4
PA[2]
J2
PA[1]
J5
PA[0]
K1
J6
LEDDRV
TXD1
L1
O
N3
M2
M1
P3
N1
N2
R3
P1
P2
T3
R1
R2
K2
J7
PHDIN
CTS
I
I
L1
K4
L2
K5
M1
K6
M2
L4
N1
L5
RXD1
DCD
I
I
DSR
I
nTEST1
nTEST0
EINT3
nEINT2
nEINT1
nEXTFIQ
PE[2]/CLKSEL
I
I
I
I
I
I
I/O
PE[1]/
BOOTSEL[1]
46
T1
N2
I/O
83
47
53
54
55
T2
V4
W4
Y4
M4
T2
T3
N5
PE[0]/BOOTSEL0
PD[7]/SDQM[1]
PD[6/SDQM[0]]
PD[5]
I/O
I/O
I/O
I/O
86
89
92
95
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
55
EP7312
High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
56
59
V5
Y5
R3
T4
PD[4]
PD[3]
I/O
I/O
I/O
I/O
O
98
101
104
107
110
122
125
126
128
131
134
136
138
140
141
142
144
146
148
150
152
154
156
158
160
163
166
169
172
174
177
179
182
184
187
189
191
194
60
V6
N6
PD[2]
61
W6
R4
PD[1]
62
Y6
L7
PD[0]/LEDFLSH
SSIRXFR
ADCIN
68
W8
T6
I/O
I
69
Y8
K8
70
V9
R6
nADCCS
DRIVE1
DRIVE0
ADCCLK
ADCOUT
SMPCLK
FB1
O
75
W10
Y10
V11
W11
Y11
Y12
Y11
Y12
Y13
W13
V13
Y14
W14
Y15
W15
V15
Y16
W16
V16
Y17
Y16
Y18
V17
W18
Y19
Y20
U18
V209
U19
U20
M8
I/O
I/O
O
76
T8
77
N8
78
R8
O
79
N9
O
80
T9
I
82
M9
FB0
I
83
R9
COL7
O
84
L9
COL6
O
85
T10
K9
COL5
O
86
COL4
O
87
R10
N10
R11
M10
T12
L10
R12
N11
T13
R13
M11
T14
N12
R14
T15
N13
R16
P15
M13
COL3
O
88
COL2
O
91
COL1
O
92
COL0
O
93
BUZ
O
94
D[31]
I/O
I/O
I/O
I/O
Out
I/O
O
95
D[30]
96
D[29]
97
D[28]
99
A[27]/DRA[0]
D[27]
100
101
102
103
104
105
106
109
110
A[26]/DRA[1]
D[26]
I/O
O
A[25]/DRA[2]
D[25]
I/O
O
HALFWORD
A[24]/DRA[3]
D[24]
O
I/O
O
A[23]/DRA[4]
56
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
111
112
113
114
115
117
118
119
120
121
122
126
127
128
129
130
131
132
133
134
135
136
137
138
141
142
143
144
145
146
147
148
150
151
152
153
154
155
T19
T20
R19
R20
T18
P19
P20
R18
N19
N20
P18
M19
N18
L20
L19
M18
K20
K19
K18
J20
N16
L12
N15
L13
M16
M15
K11
L16
K12
L15
K13
J10
D[23]
A[22]/DRA[5]
D[22]
I/O
O
196
199
201
204
206
209
211
214
216
219
221
224
226
229
231
234
236
239
241
244
246
249
251
254
256
259
261
264
266
269
271
274
276
279
280
281
282
283
I/O
O
A[21]/DRA[6]
D[21]
I/O
O
A[20]/DRA[7]
D[20]
I/O
O
A[19]/DRA[8]
D[19]
I/O
O
A[18]/DRA[9]
D[18]
I/O
O
A[17]/DRA[10]
D[17]
J16
I/O
O
J11
A[16]/DRA[11]
D[16]
J15
I/O
O
J12
A[15]/DRA[12]
D[15]
H16
J13
I/O
O
A[14]/DRA[13]
D[14]
H15
H13
G16
H12
G15
H11
F15
H10
E16
G13
E15
G12
D16
G11
D15
F13
C16
F12
C15
E13
I/O
O
A[13]/DRA[14]
D[13]
J19
I/O
O
H20
H19
J18
A[12]
D[12]
I/O
O
A[11]
G20
H18
F20
G19
E20
F19
G18
D20
F18
D19
E19
C19
C20
E18
D[11]
I/O
O
A[10]
D[10]
I/O
O
A[9]
D[9]
I/O
O
A[8]
D[8]
I/O
O
A[7]
D[7]
I/O
I
nBATCHG
nEXTPWR
BATOK
I
I
nPOR
I
nMEDCHG/nBROM
I
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
57
EP7312
High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP
Pin No.
TFBGA PBGA
Signal
Type
Position
Ball
Ball
156
161
162
163
164
165
166
169
170
171
172
173
175
176
177
178
179
184
185
186
187
188
189
191
192
193
194
195
196
199
200
201
202
204
205
206
207
208
B20
B16
A16
C15
B15
A15
C14
B14
A14
C13
B13
A13
C12
B12
A12
C11
B11
B10
A10
A9
B16
B14
D11
A13
F10
B13
E10
B12
D10
A11
G9
B11
A10
F9
nURESET
WAKEUP
nPWRFL
A[6]
I
284
285
286
287
289
292
294
297
299
302
304
307
309
312
314
317
319
322
324
326
328
330
333
336
339
342
344
346
349
352
355
358
360
362
364
366
368
370
I
I
O
D[6]
I/O
O
A[5]
D[5]
I/O
O
A[4]
D[4]
I/O
O
A[3]
D[3]
I/O
O
A[2]
D[2]
I/O
O
A[1]
B10
E9
D[1]
I/O
O
A[0]
A9
D[0]
I/O
O
D8
CL2
B8
CL1
O
E8
FRM
O
B9
A7
M
O
C9
F8
DD[3]
O
A8
B7
DD[2]
O
B8
A6
DD[1]
O
C8
G8
B6
DD[0]
O
A7
nSDCS[1]
nSDCS[0]
SDQM[3]
SDQM[2]
SDCKE
SDCLK
nMWE/nSDWE
nMOE/nSDCAS
nCS[0]
nCS[1]
nCS[2]
nCS[3]
nCS[4]
O
B7
D7
O
C7
A5
I/O
I/O
I/O
I/O
O
A6
E7
B6
F7
C6
A4
A5
D6
B5
B4
O
C5
E6
O
A4
A3
O
B4
D5
O
A3
B3
O
C4
A2
O
58
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
1) See EP7312 Users’ Manual for pin naming / functionality.
2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
59
EP7312
High-Performance, Low-Power System on Chip
Table 24. Acronyms and Abbreviations (Continued)
CONVENTIONS
Acronym/
Definition
This section presents acronyms, abbreviations, units of
measurement, and conventions used in this data sheet.
Abbreviation
TAP
TLB
test access port
Acronyms and Abbreviations
translation lookaside buffer
Table 24 lists abbreviations and acronyms used in this data
sheet.
UART
universal asynchronous receiver
Table 24. Acronyms and Abbreviations
Units of Measurement
Acronym/
Definition
Table 25. Unit of Measurement
Abbreviation
Symbol
Unit of Measure
A/D
analog-to-digital
degree Celsius
°C
fs
ADC
CODEC
D/A
analog-to-digital converter
coder / decoder
sample frequency
hertz (cycle per second)
kilobits per second
kilobyte (1,024 bytes)
kilohertz
Hz
digital-to-analog
kbps
KB
DMA
EPB
FCS
FIFO
FIQ
direct-memory access
embedded peripheral bus
frame check sequence
first in / first out
kHz
kΩ
kilo Ohm
Mbps
MB
MBps
MHz
µA
megabits (1,048,576 bits) per second
megabyte (1,048,576 bytes)
megabytes per second
megahertz (1,000 kilohertz)
microampere
fast interrupt request
general purpose I/O
in circuit test
GPIO
ICT
IR
infrared
IRQ
standard interrupt request
Infrared Data Association
Joint Test Action Group
liquid crystal display
light-emitting diode
µF
microfarad
IrDA
JTAG
LCD
LED
LQFP
LSB
MIPS
MMU
MSB
PBGA
PCB
PDA
PLL
µW
µs
microwatt
microsecond (1,000 nanoseconds)
milliampere
mA
mW
ms
milliwatt
low profile quad flat pack
least significant bit
millisecond (1,000 microseconds)
nanosecond
ns
millions of instructions per second
memory management unit
most significant bit
V
volt
W
watt
plastic ball grid array
printed circuit board
personal digital assistant
phase locked loop
p/u
pull-up resistor
RISC
RTC
SIR
reduced instruction set computer
Real-Time Clock
slow (9600–115.2 kbps) infrared
static random access memory
synchronous serial interface
SRAM
SSI
60
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
General Conventions
Hexadecimal numbers are presented with all letters in
uppercase and a lowercase “h” appended or with a 0x at the
beginning. For example, 0x14 and 03CAh are hexadecimal
numbers. Binary numbers are enclosed in single quotation
marks when in text (for example, ‘11’ designates a binary
number). Numbers not indicated by an “h”, 0x or quotation
marks are decimal.
Registers are referred to by acronym, with bits listed in
brackets separated by a colon (:) (for example, CODR[7:0]),
and are described in the EP7312 User’s Manual. The use of
“TBD” indicates values that are “to be determined,” “n/a”
designates “not available,” and “n/c” indicates a pin that is a
“no connect.”
Pin Description Conventions
Abbreviations used for signal directions are listed in Table 26.
Table 26. Pin Description Conventions
Abbreviation
Direction
I
Input
O
I/O
Output
Input or Output
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
61
EP7312
High-Performance, Low-Power System on Chip
Ordering Information
Model
EP7312-CB
Temperature
Package
0 to +70 °C
EP7312-CB-90 (90 MHz)
EP7312-IB
256-pin PBGA, 17mm X 17mm
-40 to +85 °C.
0 to +70 °C
EP7312-IB-90 (90 MHz)
EP7312-CR
EP7312-CR-90 (90 MHz)
EP7312-IR
204-pin TFBGA, 13mm X 13mm
-40 to +85 °C.
0 to +70 °C
EP7312-IR-90 (90 MHz)
EP7312-CV
EP7312-CV-90 (90 MHz)
EP7312-IV
208-pin LQFP.
-40 to +85 °C.
0 to +70 °C
EP7312-IV-90 (90 MHz)
EP7312-CVZ (Lead Free)
Environmental, Manufacturing, & Handling Information
Model Number
EP7312-CB
Peak Reflow Temp
MSL Rating*
Max Floor Life
EP7312-CB-90 (90 MHz)
EP7312-IB
EP7312-IB-90 (90 MHz)
EP7312-CR
EP7312-CR-90 (90 MHz)
EP7312-IR
225 °C
3
7 Days
EP7312-IR-90 (90 MHz)
EP7312-CV
EP7312-CV-90 (90 MHz)
EP7312-IV
EP7312-IV-90 (90 MHz)
EP7312-CVZ (Lead Free)
260 °C
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
62
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
EP7312
High-Performance, Low-Power System on Chip
Revision History
Revision
PP5
Date
Changes
JAN 2004
AUG 2005
Preliminary release. Updated SDRAM timing.
Updated ordering information. Added MSL data.
F1
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
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Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation.
DS508F1
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
63
EP7312
High-Performance, Low-Power System on Chip
64
©Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
DS508F1
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