EP7209_技术文档

EP7209

TABLE OF CONTENTS

1. CONVENTIONS ...................................................................................................................... 10

1.1 Acronyms and Abbreviations ............................................................................................ 10

1.2 Units of Measurement ...................................................................................................... 11

1.3 General Conventions ........................................................................................................ 11

1.4 Pin Description Conventions ............................................................................................. 11

2. PIN INFORMATION ................................................................................................................ 12

2.1 208-Pin LQFP Pin Diagram .............................................................................................. 12

2.2 Pin Descriptions ................................................................................................................ 13

2.2.1 External Signal Functions

................................................................................... 13

2.2.2 SSI/Codec/DAI Pin Multiplexing ............................................................................ 16

2.2.3 Output Bi-Directional Pins .................................................................................... 17

3. FUNCTIONAL DESCRIPTION ............................................................................................... 18

3.1 CPU Core .......................................................................................................................... 19

3.2 State Control ..................................................................................................................... 20

3.2.1 Standby State .......................................................................................................... 20

3.2.1.1 UART in Standby State ............................................................................... 21

3.2.2 Idle State ................................................................................................................. 22

3.2.3 Keyboard Interrupt ................................................................................................... 22

3.3 Resets ............................................................................................................................... 23

3.4 Clocks ............................................................................................................................... 23

3.4.1 On-Chip PLL ............................................................................................................ 23

3.4.1.1 Characteristics of the PLL Interface ............................................................ 24

3.4.2 External Clock Input (13 MHz) ................................................................................ 24

3.4.3 Dynamic Clock Switching When in the PLL Clocking Mode .................................... 26

3.5 Interrupt Controller ............................................................................................................ 26

3.5.1 Interrupt Latencies in Different States ..................................................................... 28

3.5.1.1 Operating State ........................................................................................... 28

3.5.1.2 Standby State .............................................................................................. 28

3.6 EP7209 Boot ROM .......................................................................................................... 29

3.7 Memory and I/O Expansion Interface ............................................................................... 30

3.8 CL-PS6700 PC Card Controller Interface ......................................................................... 31

3.9 Endianness ....................................................................................................................... 33

3.10 Internal UARTs (Two) and SIR Encoder ......................................................................... 34

3.11 Serial Interfaces .............................................................................................................. 34

3.11.1 Codec Sound Interface .......................................................................................... 36

3.11.2 Digital Audio Interface ........................................................................................... 37

3.11.2.1 DAI Operation ............................................................................................ 38

3.11.2.2 DAI Frame Format ..................................................................................... 38

3.11.2.3 DAI Signals ................................................................................................ 38

3.11.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) .......... 39

3.11.4 Master/Slave SSI2 (Synchronous Serial Interface 2) ........................................... 39

3.11.4.1 Read Back of Residual Data ..................................................................... 42

3.11.4.2 Support for Asymmetric Traffic .................................................................. 42

3.11.4.3 Continuous Data Transfer ......................................................................... 43

3.11.4.4 Discontinuous Clock .................................................................................. 43

3.11.4.5 Error Conditions ........................................................................................ 43

3.11.4.6 Clock Polarity ............................................................................................ 43

3.12 LCD Controller with Support for On-Chip Frame Buffer .................................................. 43

3.13 Timer Counters ............................................................................................................... 45

3.13.1 Free Running Mode ............................................................................................... 46

3.13.2 Prescale Mode ...................................................................................................... 46

3.14 Real Time Clock .............................................................................................................. 46

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3.14.1 Characteristics of the Real Time Clock Interface ................................................... 46

3.15 Dedicated LED Flasher ................................................................................................... 47

3.16 Two PWM Interfaces ....................................................................................................... 47

3.17 Boundary Scan ................................................................................................................ 47

3.18 In-Circuit Emulation ......................................................................................................... 48

3.18.1 Introduction ............................................................................................................ 48

3.18.2 Functionality ........................................................................................................... 48

3.19 Maximum EP7209-Based System .................................................................................. 48

4. MEMORY MAP ....................................................................................................................... 50

5. REGISTER DESCRIPTIONS .................................................................................................. 51

5.1 Internal Registers .............................................................................................................. 51

5.1.1 PADR Port A Data Register ..................................................................................... 54

5.1.2 PBDR Port B Data Register ..................................................................................... 54

5.1.3 PDDR Port D Data Register .................................................................................... 54

5.1.4 PADDR Port A Data Direction Register ................................................................... 54

5.1.5 PBDDR Port B Data Direction Register ................................................................... 54

5.1.6 PDDDR Port D Data Direction Register ................................................................... 55

5.1.7 PEDR Port E Data Register ..................................................................................... 55

5.1.8 PEDDR Port E Data Direction Register ................................................................... 55

5.2 SYSTEM Control Registers ............................................................................................... 56

5.2.1 SYSCON1 The System Control Register 1 ............................................................. 56

5.2.2 SYSCON2 System Control Register 2 ..................................................................... 59

5.2.3 SYSCON3 System Control Register 3 ..................................................................... 61

5.2.4 SYSFLG1 — The System Status Flags Register .................................................... 62

5.2.5 SYSFLG2 System Status Register 2 ....................................................................... 64

5.3 Interrupt Registers ............................................................................................................. 65

5.3.1 INTSR1 Interrupt Status Register 1 ......................................................................... 65

5.3.2 INTMR1 Interrupt Mask Register 1 .......................................................................... 67

5.3.3 INTSR2 Interrupt Status Register 2 ......................................................................... 67

5.3.4 INTMR2 Interrupt Mask Register 2 .......................................................................... 68

5.3.5 INTSR3 Interrupt Status Register 3 ......................................................................... 68

5.3.6 INTMR3 Interrupt Mask Register 3 .......................................................................... 68

5.4 Memory Configuration Registers ....................................................................................... 69

5.4.1 MEMCFG1 Memory Configuration Register 1 ......................................................... 69

5.4.2 MEMCFG2 Memory Configuration Register 2 ......................................................... 69

5.5 Timer/Counter Registers ................................................................................................... 71

5.5.1 TC1D Timer Counter 1 Data Register ..................................................................... 71

5.5.2 TC2D Timer Counter 2 Data Register ..................................................................... 71

5.5.3 RTCDR Real Time Clock Data Register .................................................................. 71

5.5.4 RTCMR Real Time Clock Match Register ............................................................... 71

5.6 LEDFLSH Register ............................................................................................................ 72

5.7 PMPCON Pump Control Register ..................................................................................... 73

5.8 CODR — The CODEC Interface Data Register ................................................................ 74

5.9 UART Registers ................................................................................................................ 74

5.9.1 UARTDR1–2 UART1–2 Data Registers .................................................................. 74

5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers .................................. 75

5.10 LCD Registers ................................................................................................................. 77

5.10.1 LCDCON — The LCD Control Register ................................................................. 77

5.10.2 PALLSW Least Significant Word — LCD Palette Register .................................... 78

5.10.3 PALMSW Most Significant Word — LCD Palette Register .................................... 78

5.10.4 FBADDR LCD Frame Buffer Start Address ........................................................... 79

5.11 SSI Register .................................................................................................................... 79

5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register .................................. 79

5.12 STFCLR Clear all ‘Start Up Reason’ flags location ......................................................... 80

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5.13 ‘End Of Interrupt’ Locations ............................................................................................ 81

5.13.1 BLEOI Battery Low End of Interrupt ...................................................................... 81

5.13.2 MCEOI Media Changed End of Interrupt .............................................................. 81

5.13.3 TEOI Tick End of Interrupt Location ...................................................................... 81

5.13.4 TC1EOI TC1 End of Interrupt Location ................................................................. 81

5.13.5 TC2EOI TC2 End of Interrupt Location ................................................................. 82

5.13.6 RTCEOI RTC Match End of Interrupt .................................................................... 82

5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt .................................. 82

5.13.8 COEOI Codec End of Interrupt Location ............................................................... 82

5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................ 82

5.13.10 SRXEOF End of Interrupt Location ..................................................................... 82

5.14 State Control Registers ................................................................................................... 82

5.14.1 STDBY Enter the Standby State Location ............................................................. 82

5.14.2 HALT Enter the Idle State Location ....................................................................... 82

5.15 SS2 Registers ................................................................................................................. 83

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ......................................... 83

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte ............................... 83

5.16 DAI Register Definitions .................................................................................................. 83

5.16.1 DAI Control Register ............................................................................................. 84

5.16.1.1 DAI Enable (DAIEN) .................................................................................. 85

5.16.1.2 DAI Interrupt Generation ........................................................................... 85

5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ................................. 85

5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................. 85

5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) .............................. 86

5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) .............................. 86

5.16.1.7 Loop Back Mode (LBM) ............................................................................. 86

5.16.2 DAI Data Registers ................................................................................................ 87

5.16.2.1 DAI Data Register 0 .................................................................................. 87

5.16.2.2 DAI Data Register 1 .................................................................................. 88

5.16.2.3 DAI Data Register 2 .................................................................................. 88

5.16.3 DAI Status Register ............................................................................................... 89

5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS) ................... 89

5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS) ................... 89

5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS) ...................... 89

5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS) ...................... 90

5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU) ........................... 90

5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO) ............................. 90

5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU) .............................. 90

5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO) ................................ 90

5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF) ................................. 90

5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE) ........................... 90

5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF) .................................. 91

5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE) .............................. 91

5.16.3.13 FIFO Operation Completed Flag (FIFO) ................................................. 91

6. ELECTRICAL SPECIFICATIONS .......................................................................................... 93

6.1 Absolute Maximum Ratings .............................................................................................. 93

6.2 Recommended Operating Conditions .............................................................................. 93

6.3 DC Characteristics ............................................................................................................ 93

6.4 AC Characteristics ............................................................................................................ 95

6.5 I/O Buffer Characteristics ................................................................................................ 102

6.6 JTAG Bandary Scan Signal Ordering ............................................................................. 102

7. TEST MODES ....................................................................................................................... 106

7.1 Oscillator and PLL Bypass Mode .................................................................................... 106

7.2 Oscillator and PLL Test Mode ......................................................................................... 106

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7.3 Debug/ICE Test Mode .................................................................................................... 107

7.4 Hi-Z (System) Test Mode ............................................................................................... 107

7.5 Software Selectable Test Functionality .......................................................................... 107

8. PIN INFORMATION .............................................................................................................. 108

8.1 208-Pin LQFP Pin Diagram ............................................................................................. 108

8.2 208-Pin LQFP Numeric Pin Listing ................................................................................. 109

8.3 256-Pin PBGA Pin Diagram ............................................................................................ 112

8.4 256-Ball PBGA Ball Listing .............................................................................................. 113

8.4.1 PBGA Ground Connections ................................................................................... 116

9. PACKAGE SPECIFICATIONS ............................................................................................. 117

9.1 208-Pin LQFP Package Outline Drawing ....................................................................... 117

9.2 EP7209 256-Ball PBGA (17 × 17 × 1.53-mm Body) Dimensions .................................. 118

10. ORDERING INFORMATION ............................................................................................... 119

11. APPENDIX A: BOOT CODE .............................................................................................. 120

12. INDEX ................................................................................................................................. 125

LIST OF FIGURES

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram............................................. 12

Figure 2. EP7209 Block Diagram.................................................................................................. 19

Figure 3. State Diagram ................................................................................................................ 20

Figure 4. CLKEN Timing Entering the Standby State ................................................................... 25

Figure 5. CLKEN Timing Entering the Standby State ................................................................... 25

Figure 6. Codec Interrupt Timing................................................................................................... 36

Figure 7. DAI Interface .................................................................................................................. 37

Figure 8. EP7209 Rev C - Digital Audio Interface Timing – MSB/Left Justified format................ 38

Figure 9. SSI2 Port Directions in Slave and Master Mode............................................................ 40

Figure 10. Residual Byte Reading................................................................................................. 42

Figure 11. Video Buffer Mapping................................................................................................... 45

Figure 12. A Maximum EP7209 Based System ............................................................................ 49

Figure 13. Consecutive Memory Read Cycles with Minimum Wait States.................................... 97

Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States................................. 98

Figure 15. Consecutive Memory Write Cycles with Minimum Wait States.................................... 99

Figure 16. LCD Controller Timings.............................................................................................. 100

Figure 17. SSI Interface for AD7811/2 ........................................................................................ 100

Figure 18. SSI Timing Interface for MAX148/9............................................................................ 101

Figure 19. SSI2 Interface Timings............................................................................................... 101

Figure 20. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram......................................... 108

Figure 21. 256-Ball Plastic Ball Grid Array Diagram ................................................................... 112

LIST OF TABLES

Table 1. Acronyms and Abbreviations........................................................................................... 10

Table 2. Unit of Measurement....................................................................................................... 11

Table 3. Pin Description Conventions ........................................................................................... 11

Table 4. External Signal Functions................................................................................................ 13

Table 5. SSI/Codec/DAI Pin Multiplexing...................................................................................... 16

Table 6. Output Bi-Directional Pins ............................................................................................... 17

Table 7. Peripheral Status in Different Power Management States.............................................. 21

Table 8. Exception Priority Handling ............................................................................................. 26

Table 9. Interrupt Allocation in the First Interrupt Register............................................................ 27

Table 10. Interrupt Allocation in the Second Interrupt Register..................................................... 27

Table 11. Interrupt Allocation in the Third Interrupt Register......................................................... 27

Table 12. External Interrupt Source Latencies.............................................................................. 29

Table 13. Chip Select Address Ranges After Boot From On-Chip Boot ROM.............................. 29

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Table 14. Boot Options ................................................................................................................. 30

Table 15. CL-PS6700 Memory Map.............................................................................................. 31

Table 16. Space Field Decoding................................................................................................... 32

Table 19. Serial Interface Options................................................................................................. 35

Table 20. Serial-Pin Assignments................................................................................................. 35

Table 21. ADC Interface Operation Frequencies.......................................................................... 39

Table 17. Effect of Endianness on Read Operations.................................................................... 41

Table 18. Effect of Endianness on Write Operations .................................................................... 41

Table 22. Instructions Supported in JTAG Mode .......................................................................... 47

Table 23. Device ID Register ........................................................................................................ 48

Table 24. EP7209 Memory Map in External Boot Mode............................................................... 50

Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode)............. 52

Table 26. EP7209 Internal Registers (Big Endian Mode) ............................................................. 54

Table 27. SYSCON1..................................................................................................................... 56

Table 28. SYSCON2..................................................................................................................... 59

Table 29. SYSCON3..................................................................................................................... 61

Table 30. SYSFLG........................................................................................................................ 62

Table 31. SYSFLG2...................................................................................................................... 64

Table 32. INTSR1 ......................................................................................................................... 65

Table 34. INTSR3 ......................................................................................................................... 68

Table 35. Values of the Bus Width Field....................................................................................... 70

Table 36. Values of the Wait State Field at 13 MHz and 18 MHz................................................. 70

Table 37. Values of the Wait State Field at 36 MHz ..................................................................... 70

Table 38. MEMCFG ...................................................................................................................... 71

Table 39. LED Flash Rates........................................................................................................... 72

Table 40. LED Duty Ratio ............................................................................................................. 72

Table 41. PMPCON ...................................................................................................................... 73

Table 42. Sense of PWM control lines.......................................................................................... 73

Table 43. UARTDR1-2 UART1-2.................................................................................................. 74

Table 44. UBRLCR1-2 UART1-2 .................................................................................................. 75

Table 45. LCDCON....................................................................................................................... 77

Table 46. Gray Scale Value to Color Mapping.............................................................................. 79

Table 47. SYNCIO ........................................................................................................................ 80

Table 48. DAI Control Register ..................................................................................................... 84

Table 49. DAI Data Register 0 ...................................................................................................... 87

Table 50. DAI Data Register 1 ...................................................................................................... 88

Table 51. DAI Control, Data and Status Register Locations......................................................... 91

Table 52. absolute Maximum Ratings........................................................................................... 93

Table 53. Recommended Operating Conditions........................................................................... 93

Table 54. DC Characteristics ........................................................................................................ 93

Table 55. AC Timing Characteristics............................................................................................. 95

Table 56. Timing Characteristics................................................................................................... 96

Table 57. I/O Buffer Output Characteristics ................................................................................ 102

Table 58. 208-Pin LQFP Numeric Pin Listing ............................................................................. 102

Table 59. EP7209 Hardware Test Modes................................................................................... 106

Table 60. Oscillator and PLL Test Mode Signals........................................................................ 107

Table 61. Software Selectable Test Functionality....................................................................... 107

Table 62. 208-Pin LQFP Numeric Pin Listing ............................................................................. 109

Table 63. 256-Ball PBGA Ball Listing.......................................................................................... 113

Table 64. PBGA Balls to Connect to Ground (V_SS) .................................................................... 116

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1. CONVENTIONS

Acronym/

Abbreviation

Definition

This section presents acronyms, abbreviations,

units of measurement, and conventions used in this

data sheet.

LCD

liquid crystal display.

light-emitting diode.

LED

LQFP

LSB

low profile quad flat pack.

least significant bit.

1.1

Acronyms and Abbreviations

Table 1 lists abbreviations and acronyms used in

this data sheet.

millions of instructions per sec-

ond.

MIPS

MMU

MSB

PBGA

PCB

PDA

PIA

memory management unit.

most significant bit.

Acronym/

Definition

Abbreviation

plastic ball grid array.

printed circuit board.

personal digital assistant.

peripheral interface adapter.

phase locked loop.

AC

alternating current.

analog-to-digital.

A/D

ADC

analog-to-digital converter.

complementary metal oxide

semiconductor.

CMOS

PLL

PSU

p/u

power supply unit.

CODEC

CPU

D/A

coder/decoder.

pull-up resistor.

central processing unit.

digital-to-analog.

RAM

random access memory.

reduced instruction set com-

puter.

DC

direct current.

RISC

DMA

EPB

FCS

FIFO

GPIO

ICT

direct-memory access.

embedded peripheral bus.

frame check sequence.

first in/first out.

ROM

RTC

SIR

read-only memory.

Real Time Clock.

slow (9600–115.2 kbps) infrared.

static random access memory.

synchronous serial interface.

test access port.

SRAM

SSI

general purpose I/O.

in circuit test.

TAP

TLB

IR

infrared.

translation lookaside buffer.

IrDA

JTAG

Infrared Data Association.

Joint Test Action Group.

universal asynchronous

receiver.

UART

Table 1. Acronyms and Abbreviations

Table 1. Acronyms and Abbreviations (cont.)

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1.2

Units of Measurement

1.3

General Conventions

Hexadecimal numbers are presented with all letters

in uppercase and a lowercase ‘h’ appended or with

a 0x at the beginning. For example, 0x14 and

03CAh are hexadecimal numbers. Binary numbers

are enclosed in single quotation marks when in text

(for example, ‘11’ designates a binary number).

Numbers not indicated by an ‘h’, 0x or quotation

marks are decimal.

Symbol

Unit of Measure

degree Celsius

°C

Hz

hertz (cycle per second)

kilobits per second

kilobyte (1,024 bytes)

kilohertz

kbits/s

kbyte

kHz

kΩ

kilohm

Mbps

Mbyte

MHz

µA

megabits (1,048,576 bits) per second

megabyte (1,048,576 bytes)

megahertz (1,000 kilohertz)

microampere

Registers are referred to by acronym, as listed in

the tables on the previous page, with bits listed in

brackets MSB-to-LSB separated by a colon (:) (for

example, CODR[7:0]), or LSB-to-MSB separated

by a hyphen (for example, CODR[0–2]).

µF

microfarad

µW

µs

microwatt

The use of ‘tbd’ indicates values that are ‘to be de-

termined’, ‘n/a’ designates ‘not available’, and

‘n/c’ indicates a pin that is a ‘no connect’.

microsecond (1,000 nanoseconds)

milliampere

mA

mW

ms

milliwatt

1.4

Pin Description Conventions

millisecond (1,000 microseconds)

nanosecond

Abbreviations used for signal directions are listed

in Table 3.

ns

V

volt

W

watt

Abbreviation

Direction

I

Input

Table 2. Unit of Measurement

O

Output

I/O

Input or Output

Table 3. Pin Description Conventions

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2. PIN INFORMATION

2.1 208-Pin LQFP Pin Diagram

D[25]

A[25]

D[26]

A[26]

D[27]

A[27]

VSSIO

D[28]

D[29]

D[30]

D[31]

BUZ

COL[0]

COL[1]

TCLK

VDDIO

COL[2]

COL[3]

COL[4]

COL[5]

COL[6]

COL[7]

FB[0]

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

VDDOSC

MOSCIN

MOSCOUT

VSSOSC

WAKEUP

NPWRFL

A[6]

D[6]

A[5]

D[5]

VDDIO

VSSIO

A[4]

D[4]

A[3]

D[3]

A[2]

VSSIO

D[2]

A[1]

D[1]

A[0]

D[0]

VSSIO

FB[1]

EP7209

208-Pin LQFP

VSSCORE

VDDCORE

VSSIO

VDDIO

CL[2]

SMPCLK

ADCOUT

ADCCLK

DRIVE[0]

DRIVE[1]

VDDIO

VSSIO

VDDCORE

VSSCORE

NADCCS

ADCIN

SSIRXFR

SSIRXDA

SSITXDA

SSITXFR

VSSIO

SSICLK

PD[0]/LEDFLSH

PD[1]

PD[2]

PD[3]

TMS

VDDIO

PD[4]

PD[5]

PD[6]

PD[7]

CL[1]

FRM

M

DD[3]

DD[2]

VSSIO

DD[1]

DD[0]

N/C

VDDIO

VSSIO

N/C

(Top View)

N/C

NMWE

NMOE

VSSIO

NCS[0]

NCS[1]

NCS[2]

NCS[3]

NCS[4]

Notes:

1)For package specifications, please see 208--Pin LQFP Package Outline Drawing on page 117

2)N/C should not be grounded but left as no connects

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

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2.2

Pin Descriptions

Table 4 describes the function of all the external signals to the EP7209. Note that all output signals are tri-

stateable to enable the Hi-Z test modes to be supported.

2.2.1

External Signal Functions

Function

Signal

Name

Signal

Description

Data bus

D[0:31]

A[0:27]

I/O

O

32-bit system data bus for memory and I/O interface

28 bits of system byte address during memory and expansion cycles

Whenever the EP7209 is in the Standby State, the external address and data

buses are driven low. The RUN signal is used internally to force these buses to

be driven low. This is done to prevent peripherals that are powered-down from

draining current. Also, the internal peripheral’s signals get set to their Reset

State.

Address bus

nMOE

nMWE

O

Memory output enable, active low

Memory write enable, active low

nCS[0:3]

nCS[4:5]

Chip select; active low, SRAM-like chip selects for expansion

Chip select; active low, CS for expansion or for CL-PS6700 select

Expansion port ready; external expansion devices drive this low to extend the

bus cycle. This is used to insert wait states for an external bus cycle.

EXPRDY

WRITE

I

O

Write strobe, low during reads, high during writes from the EP7209

To do write accesses of different sizes Word and Half-Word must be externally

decoded. The encoding of these signals is as follows:

Access Size

Word

Half-Word

1

*

0

1

0

Half-Word

Byte

Memory

Interface

0

WORD/

HALFWORD

O

The core will generate an address. When doing a read, the ARM core will

select the appropriate byte channels. When doing a write, the correct bytes

will have to be enabled depending on the above signals and the least signifi-

cant bits of the address bus.

The ARM architecture does not support unaligned accesses. For a read using

x 32 memory, it is assumed that you will ignore bits 1 and 0 of the address bus

and perform a word read (or in power critical systems decode the relevant bits

depending on the size of the access). If an unaligned read takes place, the

core will rotate the resulting data in the register. For more information on this

behavior see the LDR instruction in the ARM7TDMI data sheet.

Expansion clock rate is the same as the CPU clock for 13 MHz and 18 MHz. It

runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is

used as the clock input.

EXPCLK

I/O

Table 4. External Signal Functions

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Function

Signal

Name

Signal

Description

Media changed input; active low, deglitched. Used as a general purpose FIQ

interrupt during normal operation. It is also used on power up to configure the

processor to either boot from the internal Boot ROM, or from external memory.

When low, the chip will boot from the internal Boot ROM.

nMEDCHG/

nBROM

I

Interrupts

nEXTFIQ

EINT[3]

I

External active low fast interrupt request input

External active high interrupt request input

Two general purpose, active low interrupt inputs

nEINT[1:2]

Power fail input; active low, deglitched input to force system into the Standby

State

nPWRFL¹

I

Main battery OK input; falling edge generates a FIQ, a low level in the Standby

State inhibits system start up; deglitched input

1

BATOK

Power

Management

External power sense; must be driven low if the system is powered by an

external source

nEXTPWR

New battery sense; driven low if battery voltage falls below the "no-battery"

threshold; it is a deglitched input

1

nBATCHG

Power-on reset input. This signal is not deglitched. When active it completely

resets the entire system, including all the RTC registers. Upon power-up, the

signal must be held active low for a minimum of 100 µsec after Vdd has set-

tled. During normal operation, nPOR needs to be held low for at least one

clock cycle of the selected clock speed (i.e., when running at 13 MHz, the

pulse width of nPOR needs to be > 77 nsec).

nPOR

I

Note that nURESET, RUN/CLKEN, TEST(0), TEST(1), PE(0), PE(1), PE(2),

DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are all latched on rising

edge of nPOR.

This pin is programmed to either output the RUN signal or the CLKEN signal.

The CLKENSL bit is used to configure this pin. When RUN is selected, the pin

will be high when the system is active or idle, low while in the Standby State.

When CLKEN is selected, the pin will only be driven low when in the Standby

State (For RUN, see Table 6).

RUN/CLKEN

I/O

State Control

Wake up deglitched input signal; rising edge forces system into the Operating

State from the Standby State; active after an nPOR reset. The wakeup signal

can not be used to exit Idle, only Standby. Wakeup must wait at least 2 sec-

onds before it goes high for it to be detected by the CPU. It must also be held

high for at least 125 µsec to guarantee its detection. Toggling wakeup after its

first detection has no effect (i.e., it is ignored).

1

I

WAKEUP

User reset input; active low deglitched input from user reset button.

This pin is also latched upon the rising edge of nPOR and read along with the

input pins nTEST[0:1] to force the device into special test modes. nURESET

does not reset the RTC.

1

nURESET

DAI, Codec or

SSI2

SSICLK

SSITXFR

SSITXDA

I/O

O

DAI/Codec/SSI2 clock signal

DAI/Codec/SSI2 serial data output frame/synchronization pulse output

DAI/Codec/SSI2 serial data output

Interface

(See Table 5 for

SSI2/Codec/DAI

Pin Multiplexing)

DAI/Codec/SSI2 serial data input

SSIRXDA

SSIRXFR

I

SSI2 serial data input frame/synchronization pulse

DAI external clock input

I/O

Table 4. External Signal Functions (cont.)

14

DS453PP2

EP7209

Function

Signal

Name

Signal

Description

ADCCLK

nADCCS

ADCOUT

ADCIN

SMPCLK

LEDDRV

PHDIN

TXD[1:2]

RXD[1:2]

DSR

O

I

Serial clock output

Chip select for ADC interface

Serial data output

ADC

Interface

(SSI1)

Serial data input

O

I

Sample clock output

Infrared LED drive output (UART1)

Photo diode input (UART1)

RS232 UART1 and 2 TX outputs

RS232 UART1 and 2 RX inputs

RS232 DSR input

O

I

IrDA and

RS232

Interfaces

I

DCD

I

RS232 DCD input

CTS

I

RS232 CTS input

LCD serial display data; pins can be used on power up to read the ID of some

LCD modules (See Table 6).

DD[0:3]

I/O

CL[1]

CL[2]

FRM

O

LCD line clock

LCD

LCD pixel clock

LCD frame synchronization pulse output

LCD AC bias drive

M

COL[0:7]

BUZ

Keyboard column drives (SYSCON1)

Buzzer drive output (SYSCON1)

Keyboard &

Buzzer drive

LED Flasher

PD[0]/

LEDFLSH

LED flasher driver — multiplexed with Port D bit 0. This pin can provide up to

4 mA of drive current.

O

Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY input); also

used as keyboard row inputs

PA[0:7]

I/O

Port B I/O. All eight Port B bits can be used as GPIOs.

When the PC CARD1 or 2 control bits in the SYSCON2 register are de-

asserted, PB[0] and PB[1] are available for GPIO. When asserted, these port

bits are used as the PRDY signals for connected CL-PS6700 PC Card Host

Adapter devices.

PB[0]/PRDY1

PB[1]/PRDY2

PB[2:7]

I/O

PD[0:7]

I/O

Port D I/O

General

Purpose I/O

PE[0]/

BOOTSEL[0]

Port E I/O (3 bits only). Can be used as general purpose I/O during normal

operation.

During power-on reset, PE[0] and PE[1] are inputs and are latched by the ris-

ing edge of nPOR to select the memory width that the EP7209 will use to read

from the boot code storage device (i.e., external 8-bit-wide FLASH bank).

PE[1]/

BOOTSEL[1]

I/O

During power-on reset, PE[2] is latched by the rising edge of nPOR to select

the clock mode of operation (i.e., either the PLL or external 13 MHz clock

mode).

PE[2]/

CLKSEL

PWM drive outputs. These pins are inputs on power up to determine what

polarity the output of the PWM should be when active. Otherwise, these pins

are always an output (See Table 6).

DRIVE[0:1]

FB[0:1]

I/O

I

PWM

Drives

PWM feedback inputs

Table 4. External Signal Functions (cont.)

DS453PP2

15

EP7209

Function

Signal

Name

Signal

Description

TDI

TDO

I

O

I

JTAG data in

JTAG data out

JTAG mode select

JTAG clock

Boundary

Scan

TMS

TCLK

nTRST

I

JTAG async reset

Test mode select inputs. These pins are used in conjunction with the power-on

latched state of nURESET to select between the various device test models.

Test

nTEST[0:1]

I

MOSCIN

I

Main 3.6864 MHz oscillator for 18.432 MHz–73.728 MHz PLL

MOSCOUT

O

Oscillators

RTCIN

I

Real Time Clock 32.768 kHz oscillator

RTCOUT

O

No connects

N/C

No connects should be left as no connects; do not connect to ground

Table 4. External Signal Functions (cont.)

1. All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least two clock periods. Therefore, the

input signal must be active for at least ~125 µs to be detected cleanly.

NOTE:

The RTC crystal must be populated for the device to function properly.

2.2.2

SSI/Codec/DAI Pin Multiplexing

SSI2

Codec

PCMCLK

PCMSYNC

PCMOUT

PCMIN

DAI

SCLK

LRCK

SDOUT

SDIN

Direction

I/O

Strength

SSICLK

1

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

I/O

Output

Input

I/O

p/u*

MCLK

1

*

p/u = use an ~10 k pull-up

The selection between SSI2 and the codec is controlled by the state of the SERSEL bit in SYSCON2 (See

SYSCON2 System Control Register 2). The choice between the SSI2, codec, and the DAI is controlled by

the DAISEL bit in SYSCON3 (See SYSCON3 System Control Register 3).

Table 5. SSI/Codec/DAI Pin Multiplexing

16

DS453PP2

EP7209

2.2.3

Output Bi-Directional Pins

RUN

The RUN pin is looped back in to skew the address and data bus from each other.

Drive [0:1]

Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be

when active.

DD[3:0]

DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules.

NOTE:

The above output pins are implemented as bi-directional pins to enable the output side of the pad to

be monitored and hence provide more accurate control of timing or duration:

Table 6. Output Bi-Directional Pins

DS453PP2

17

EP7209

•

Digital Audio Interface (DAI) for connection to

CD-quality DACs and codecs.

3. FUNCTIONAL DESCRIPTION

The EP7209 device is a single-chip embedded con-

troller designed to be used in low cost and ultra-

low-power digital audio players. Operating at

74 MHz, the EP7209 delivers approximately

66 Dhrystone 2.1 MIPS of sustained performance

(74 MIPS peak). This is approximately the same as

a 100 MHz Pentium-based PC.

•

Interrupt controller

Advanced system state control and power man-

agement.

•

Two full-duplex 16550A compatible UARTs

with 16-byte transmit and receive FIFOs.

IrDA SIR protocol controller capable of speeds

up to 115.2 kbps.

The EP7209 contains the following functional

blocks:

Programmable 1-, 2-, or 4-bit-per-pixel LCD

controller with 16-level gray scaler.

•

ARM720T processor which consists of the fol-

lowing functional sub-blocks:

Programmable frame buffer start address, al-

lowing a system to be built using only internal

SRAM for memory.

-

ARM7TDMI CPU core (which supports

the logic for the Thumb instruction set, core

debug, enhanced multiplier, JTAG, and the

Embedded ICE) running at a dynamically

programmable clock speed of 18 MHz,

36 MHz, 49 MHz, or 74 MHz.

•

On-chip boot ROM programmed with serial

load boot sequence.

•

Two 16-bit general purpose timer counters.

Memory Management Unit (MMU) com-

patible with the ARM710 core (providing

address translation and a 64 entry transla-

tion lookaside buffer) with added support

for Windows CE.

A 32-bit Real Time Clock (RTC) and compar-

ator.

•

Dedicated LED flasher pin driven from the

RTC with programmable duty ratio (multi-

plexed with a GPIO pin).

-

8 kbytes of unified instruction and data

cache with a four-way set associative cache

controller.

Two synchronous serial interfaces for Micro-

wire or SPI peripherals such as ADCs, one sup-

porting both the master and slave mode and the

other supporting only the master mode.

Write buffer

•

38,400 bytes (0x9600) of on-chip SRAM that

can be shared between the LCD controller and

general application use.

•

Full JTAG boundary scan and Embedded ICE

support.

Two programmable pulse-width modulation

interfaces.

Memory interfaces for up to 6 independent

256 Mbyte expansion segments with program-

ming wait states.

An interface to one or two Cirrus Logic CL-

PS6700 PC Card controller devices to support

two PC Card slots.

27 bits of general purpose I/O - multiplexed to

provide additional functionality where neces-

sary.

18

DS453PP2

EP7209

•

Oscillator and phase locked loop (PLL) to gen-

erate the core clock speeds of 18.432 MHz,

36.864 MHz, 49.152 MHz, and 73.728 MHz

from an external 3.6864 MHz crystal, with an

alternative external clock input (used in

13 MHz mode).

3.1

CPU Core

The ARM720T consists of an ARM7TDMI 32-bit

RISC processor, a unified cache, and a memory

management unit (MMU). The cache is four-way

set associative with 8-kbytes organized as 512 lines

of 4 words. The cache is directly connected to the

ARM7TDMI, and therefore caches the virtual ad-

dress from the CPU. When the cache misses, the

MMU translates the virtual address into a physical

address. A 64-entry translation lookaside buffer

(TLB) is utilized to speed the address translation

process and reduce bus traffic necessary to read the

page table. The MMU saves power by only trans-

lating the cache misses.

A low power 32.768 kHz oscillator.

The EP7209 design is optimized for low power dis-

sipation and is fabricated on a fully static

0.25 micron CMOS process. It is available in a

256-ball PBGA or a 208-pin LQFP package.

Figure 2 shows a simplified block diagram of the

EP7209. All external memory and peripheral de-

vices are connected to the 32-bit data bus using the

external 28-bit address bus and control signals.

See the ARM720T Data sheet for a complete de-

scription of the various logic blocks that make up

the processor, as well as all internal register infor-

mation.

13-MHZ INPUT

INTERNAL DATA BUS

3.6864 MHZ

PLL

D[0:31]

ARM720T

32.768-KHZ

OSCILLATOR

32.768 KHZ

ARM7TDMI

CPU CORE

MEMORY CONTROLLER

CL-PS6700

NPOR, RUN,

RESET, WAKEUP

PB[0:1], NCS[4:5]

INTFC.

STATE CONTROL

8-KBYTE

CACHE

EXPCLK, WORD, NCS[0:3],

EXPRDY, WRITE

EXPANSION

CONTROL

POWER

MANAGEMENT

BATOK, NEXTPWR

PWRFL, BATCHG

MMU

EINT[1:3], FIQ,

MEDCHG

INTERRUPT

CONTROLLER

WRITE

INTERNAL ADDRESS BUS

BUFFER

A[0:27],

FLASHING LED DRIVE

RTC

DRA[0:12]

LCD

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (0:7)

BUZZER DRIVE

DMA

TEST AND

DEVELOPMENT

ICE-JTAG

GPIO

TIMER

COUNTERS (2)

LCD

CONTROLLER

PWM

LCD DRIVE

DC-TO-DC

ON-CHIP

BOOT ROM

SSI1 (ADC)

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

ADCCS

ON-CHIP SRAM

38,400 BYTES

LED AND

PHOTODIODE

IrDA

DAI

ASYNC

EPB BRIDGE

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

SSIRSFR

UART1

UART2

INTERFACE 1

SSI2

EPB BUS

ASYNC

INTERFACE 2

CODEC

Figure 2. EP7209 Block Diagram

DS453PP2

19

EP7209

3.2

State Control

3.2.1

Standby State

The EP7209 supports the following Power Man-

agement States: Operating, Idle, and Standby (see

Figure 3). The normal program execution state is

the Operating State; this is a full performance state

where all of the clocks and peripheral logic are en-

abled. The Idle State is the same as the Operating

State with the exception of the CPU clock being

halted, and an interrupt or wakeup will return it

back to the Operating State. The Standby State has

the lowest power consumption, selecting this mode

shuts down the main oscillator, leaving only the

Real Time Clock and its associated logic powered.

It is important when the EP7209 is in Standby that

all power and ground pins remain connected to

power and ground in order to have a proper system

wake-up. The only state that Standby can transition

to is the Operating State.

The Standby State equates to the system being

switched "off" (i.e., no display, and the main oscil-

lator is shut down). When the 18.432–73.72 MHz

mode is selected, the PLL will be shut down. In the

13 MHz mode, if the CLKENSL bit is set low, then

the CLKEN signal will be forced low and can, if re-

quired, be used to disable an external oscillator.

In the Standby State, all the system memory and

state is maintained and the system time is kept up-

to-date. The PLL/on-chip oscillator or external os-

cillator is disabled and the system is static, except

for the low power watch crystal (32 kHz) oscillator

and divider chain to the RTC and LED flasher. The

RUN signal is driven low and this signal can be

used externally in the system to power down other

system modules.

Whenever the EP7209 is in the Standby State, the

external address and data buses are forced low in-

ternally by the RUN signal. This is done to prevent

peripherals that are powered-down from draining

current. Also, the internal peripheral’s signals get

set to their Reset State.

Interrupt or rising wakeup

Standby

Operating

Write to standby location,

power fail, or user reset

When first powered, or reset by the nPOR (Power

On Reset, active low) signal, the EP7209 is forced

into the Standby State. This is known as a cold re-

set, and when leaving the Standby State after a cold

reset, external wake up is the only way to wake up

the device. When leaving the Standby State after

non-cold reset conditions (i.e., the software has

forced the device into the Standby State), the tran-

sition to the Operating State can be caused by a ris-

ing edge on the WAKEUP input signal or by an

enabled interrupt. Normally, when entering the

Standby State from the Operating State, the soft-

ware will leave some interrupt sources enabled.

nPOR, power fail,

or user reset

Write to halt location

Idle

Figure 3. State Diagram

In the description below, the RUN/CLKEN pin can

be used either for the RUN functionality, or the

CLKEN functionality to allow an external oscilla-

tor to be disabled in the 13 MHz mode. Either RUN

or CLKEN functionality can be selected according

to the state of the CLKENSL bit in the SYSCON2

register. Table 7 on the following page shows pe-

ripheral status in various power management

states.

NOTE:

The CPU cannot be awakened by the TINT,

WEINT, and BLINT interrupts when in the

Standby State.

20

DS453PP2

EP7209

Address (W/B)

UARTs

Operating

Idle

Standby

nPOR

RESET

nURESET

RESET

On

Off

On

Off

Reset

Off

Reset

On

Reset

On

LCD FIFO

LCD

ADC Interface

SSI2 Interface

DAI Interface

Codec

Off

Timers

On

Off

RTC

LED Flasher

DC-to-DC

CPU

Reset

Off

Reset

Off

Interrupt Control

PLL/CLKEN Signal

On

Off

Table 7. Peripheral Status in Different Power Management States

Typically, software writes to the Standby internal

and either the nEXTPWR input pin is low or the

memory location to cause the transition from the BATOK input pin is high. This prevents the system

Operating State to the Standby State. Before enter- from starting when the power supply is inadequate

ing the Standby State, if external I/O devices (such (i.e., the main batteries are low), corresponding to

as the CL-PS6700s connected to nCS[4] or nCS[5]) a low level on nPWRFL or BATOK.

are in use, the software must check to ensure that

From the Standby State, if the WAKEUP signal is

they are idle before issuing the write to the Standby

applied with no clock except the 32 kHz clock run-

State location.

ning, the EP7209 will be initialized into a state

Before entering the Standby State, the software

must properly disable the DAI. Failing to do so will

result in higher than expected power consumption

in the Standby State, as well as unpredictable oper-

where it is ready to start and is waiting for the CPU

to start receiving its clock. The CPU will still be

held in reset at this point. After the first clock is ap-

plied, there will be a delay of about eight clock cy-

ation of the DAI. The DAI can be re-enabled after cles before the CPU is enabled. This delay is to

transitioning back to the Operating State.

allow the clock to the CPU time to settle.

The system can also be forced into the Standby

State by hardware if the nPWRFL or nURESET in-

puts are forced low. The only exit from the Standby

State is to the Operating State.

3.2.1.1 UART in Standby State

During the Standby State, the UARTs are disabled

and cannot detect any activity (i.e., start bit) on the

receiver. If this functionality is required then this

can be accomplished in software by the following

method:

The system will only transition to the Operating

State from the Standby State under the following

conditions: when the nPWRFL input pin is high

DS453PP2

21

EP7209

1) Permanently connect the RX pin to one of the

active low external interrupt pins.

ter (refer to the SYSCON2 Register Description

for details).

2) Ensure that on entry to the Standby State, the

chosen interrupt source is not masked, and

the UART is enabled.

•

If the KBWEN bit (SYSCON2 bit 3) is set

low, then a keypress will cause a transition

from a power saving state only if the key-

board interrupt is non-masked (i.e., the inter-

rupt mask register 2 (INTMR2 bit 0) is high).

3) Send a preamble that consists of one start bit,

8 bits of zero, and one stop bit. This will

cause the EP7209 to wake and execute the

enabled interrupt vector.

•

When KBWEN is high, a keypress will cause

the device to wake up regardless of the state

of the interrupt mask register. This is called

the “Keyboard Direct Wakeup’ mode. In this

mode, the interrupt request may not get ser-

viced. If the interrupt is masked (i.e., the in-

terrupt mask register 2 (INTMR2 bit 0) is

low), the processor simply starts re-execut-

ing code from where it left off before it en-

tered the power saving state. If the interrupt

is non-masked, then the processor will ser-

vice the interrupt.

The UART will automatically be re-enabled

when the processor re-enters the Operating State,

and the preamble will be received. Since the

UART was not awake at the start of the pream-

ble, the timing of the sample point will be off-

center during the preamble byte. However, the

next byte transmitted will be correctly aligned.

Thus, the actual first real byte to be received by

the UART will get captured correctly.

3.2.2

Idle State

•

When the KBD6 bit (SYSCON2 bit 1) is low,

all 8 of Port A inputs are OR’ed together to

produce the internal wakeup signal and key-

board interrupt request. This is the default re-

set state.

If in the Operating State, the Idle State can be en-

tered by writing to a special internal memory lo-

cation (HALT) in the EP7209. If an interrupt

occurs, the EP7209 will return immediately back

to the Operating State and execute the next in-

struction. The WAKEUP signal can not be used

to exit the Idle State. It is only used to exit the

Standby State.

When the KBD6 bit (SYSCON2 bit 1) is

high, only the lowest 6 bits of Port A are

OR’ed together to produce the internal wake-

up signal and keyboard interrupt request. The

two most significant bits of Port A are avail-

able as GPIO when this bit is set high.

In the Idle State, the device functions just like it

does when in the Operating State. However, the

CPU clock is halted while it waits for an event

such as a key press to generate an interrupt. The

PLL (in 18.432–73.728 MHz mode) or the exter-

nal 13 MHz clock source always remains active

in the Idle State.

In the case where KBWEN is low and the

INTMR2 bit 0 is low, it will only be possible to

wakeup the device by using the external WAKE-

UP pin or another enabled interrupt source. The

keyboard interrupt capability allows an OS to use

either a polled or interrupt-driven keyboard rou-

tine, or a combination of both.

3.2.3

Keyboard Interrupt

For the case of the keyboard interrupt, the fol-

lowing options are available and are selectable

according to bits 1 and 3 of the SYSCON2 regis-

22

DS453PP2

EP7209

NOTE:

The keyboard interrupt is NOT deglitched.

cept for the RTC). In general, a system reset will

clear all registers and nSTBY will disable all pe-

ripherals that require a main clock. The following

peripherals are always disabled by a low level on

nSTBY: two UARTs and IrDA SIR encoder, timer

counters, telephony codec, and the two SSI inter-

faces. In addition, when in the Standby State, the

LCD controller and PWM drive are also disabled.

3.3

Resets

There are three asynchronous resets to the EP7209:

nPOR, nPWRFL and nURESET. If any of these are

active, a system reset is generated internally. This

will reset all internal registers in the EP7209 except

the RTC data and match registers. These registers

are only cleared by nPOR allowing the system time

to be preserved through a user reset or power fail

condition.

When operating from an external 13 MHz oscilla-

tor which has become disabled in the Standby State

by using the CLKEN signal (i.e., with CLKENSL

= 0), the oscillator must be stable within 0.125 sec

from the rising edge of the CLKEN signal.

Any reset will also reset the CPU and cause it to

start execution at the reset vector when the EP7209

returns to the Operating State.

3.4

Clocks

Internal to the EP7209, three different signals are

used to reset storage elements. These are nPOR,

nSYSRES and nSTBY. nPOR is an external signal.

nSTBY is equivalent to the external RUN signal.

There are two clocking modes for the EP7209. Ei-

ther an external clock input can be used or the on-

chip PLL. The clock source is selected by a strap-

ping option on Port E, pin 2 (PE[2]). If PE[2] is

high at the rising edge of nPOR (i.e., upon power-

up), the external clock mode is selected. If PE[2] is

low, then the on-chip PLL mode is selected. After

power-up, PE[2] can be used as a GPIO.

nPOR (Power On Reset, active low) is the highest

priority reset signal. When active (low), it will reset

all storage elements in the EP7209. nPOR active

forces nSYSRES and nSTBY active. nPOR will

only be active after the EP7209 is first powered up

and not during any other resets. nPOR active will

clear all flags in the status register except for the

cold reset flag (CLDFLG) bit, which is set.

The EP7209 device contains several separate sec-

tions of logic, each clocked according to its own

clock frequency requirements. When the EP7209 is

in external clock mode, the actual frequencies at

the peripherals will be different than when in PLL

mode. See each peripheral device section for more

details. The section below describes the clocking

for both the ARM720T and address/data bus.

nSYSRES (System Reset, active low) is generated

internally to the EP7209 if nPOR, nPWRFL or

nURESET are active. It is the second highest prior-

ity reset signal, used to asynchronously reset most

internal registers in the EP7209. nSYSRES active

forces nSTBY and RUN low. nSYSRES is used to

reset the EP7209 and force it into the Standby State

with no co-operation from software. The CPU is

also reset.

3.4.1

On-Chip PLL

The ARM720T clock can be programmed to

18.432 MHz, 36.864 MHz, 49.152 MHz or

73.728 MHz with the PLL running at twice the

The nSTBY and RUN signals are high when the

EP7209 is in the Operating or Idle States and low

when in the Standby State. The main system clock

is valid when nSTBY is high. The nSTBY signal

will disable any peripheral block that is clocked

from the master clock source (i.e., everything ex-

highest possible

CPU

clock frequency

(147.456 MHz). The PLL uses an external

3.6864 MHz crystal. By chip default, the on-chip

PLL is used and configured such that the

ARM720T and address/data buses run at

18.432 MHz.

DS453PP2

23

EP7209

When the clock frequency is selected to be

36 MHz, both the ARM720T and the address/data

buses are clocked at 36 MHz. When the clock fre-

quency is selected higher than 36 MHz, only the

ARM720T gets clocked at this higher speed. The

address/data will be fixed at 36 MHz. The clock

frequency used is selected by programming the

CLKCTL[1:0] bits in the SYSCON3 register. The

clock frequency selection does not effect the EPB.

Therefore, all the peripheral clocks are fixed, re-

gardless of the clock speed selected for the

ARM720T.

upon the crystal specifications. The total sum of

the capacitance of the traces between the

EP7209’s clock pins, the capacitors, and the

crystal leads should be subtracted from the

crystal’s specifications when determining the

values for the loading capacitors.

•

The crystal should have a maximum 100 ppm

frequency drift over the chip’s operating tem-

perature range.

Alternatively, a digital clock source can be used to

drive the MOSCIN pin of the EP7209. With this

approach, the voltage levels of the clock source

should match that of the Vdd supply for the

EP7209’s pads (i.e. the supply voltage level used to

drive all of the non-Vdd core pins on the EP7209).

The output clock pin (i.e., MOSCOUT) should be

left floating.

NOTE:

After modifying the CLKCTL[1:0] bits, the

next instruction should always be a ‘NOP’.

3.4.1.1 Characteristics of the PLL Interface

When connecting a crystal to the on-chip PLL in-

terface pins (i.e. MOSCIN and MOSCOUT), the

crystal and circuit should conform to the following

requirements:

3.4.2

External Clock Input (13 MHz)

An external 13 MHz crystal oscillator can be used

to drive all of the EP7209. When selected the

ARM720T and the address/data buses both get

clocked at 13 MHz. The fixed clock sources to the

various peripherals will have different frequencies

than in the PLL mode. In this configuration, the

PLL will not be used at all.

•

The 3.6864 MHz frequency should be created

by the crystals fundamental tone (i.e., it should

be a fundamental mode crystal).

•

A start-up resistor is not necessary, since one is

provided internally.

Start-up loading capacitors may be placed on

each side of the external crystal and ground.

Their value should be in the range of 10 pF.

However, their values should be selected based

NOTE:

When

operating

at

13 MHz,

the

CLKCTL[1:0] bits should not be changed

from their default value of ‘00’.

24

DS453PP2

EP7209

13 MHz

CLKEN

Figure 4. CLKEN Timing Entering the Standby State

EXPCLK

(internal)

RUN

CLKEN

Interrupt /

WAKEUP

Figure 5. CLKEN Timing Entering the Standby State

DS453PP2

25

EP7209

FIQs have a higher priority than IRQs. If two inter-

rupts are received from within the same group (IRQ

or FIQ), the order in which they are serviced must

be resolved in software. The priorities are listed in

Table 9. All interrupts are level sensitive; that is,

they must conform to the following sequence.

3.4.3 Dynamic Clock Switching When in the

PLL Clocking Mode

The clock frequency used for the CPU and the bus-

es is controlled by programming the CLKCTL[1:0]

bits in the SYSCON3 register. When this occurs,

the state controller switches from the current to the

new clock frequency as soon as possible without

causing a glitch on the clock signals. The glitch-

free clock switching logic waits until the clock that

is currently in use and the newly programmed clock

source are both low, and then switches from the

previous clock to the new clock without a glitch on

the clocks.

1) The interrupting device (either external or in-

ternal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the interrupt mask

register, then either a FIQ or an IRQ will be as-

serted by the interrupt controller. (A descrip-

tion for each bit in this register can be found in

INTSR1 Interrupt Status Register 1).

3) If interrupts are enabled the processor will

jump to the appropriate address.

3.5

Interrupt Controller

When unexpected events arise during the execution

of a program (i.e., interrupt or memory fault) an ex-

ception is usually generated. When these excep-

tions occur at the same time, a fixed priority system

determines the order in which they are handled.

Table 8 shows the priority order of all the excep-

tions.

4) Interrupt dispatch software reads the interrupt

status register to establish the source(s) of the

interrupt and calls the appropriate interrupt ser-

vice routine(s).

5) Software in the interrupt service routine will

clear the interrupt source by some action spe-

cific to the device requesting the interrupt (i.e.,

reading the UART RX register).

Priority

Exception

Reset

Highest

The interrupt service routine may then re-enable in-

terrupts, and any other pending interrupts will be

serviced in a similar way. Alternately, it may return

to the interrupt dispatch code, which can check for

any more pending interrupts and dispatch them ac-

cordingly. The “End of Interrupt” type interrupts

are latched. All other interrupt sources (i.e., exter-

nal interrupt source) must be held active until its re-

spective service routine starts executing. See ‘End

.

Data Abort

FIQ

IRQ

Prefetch Abort

Undefined Instruction,

Software Interrupt

Lowest

Table 8. Exception Priority Handling

The EP7209 interrupt controller has two interrupt

types: interrupt request (IRQ) and fast interrupt re- of Interrupt’ Locations for more details.

quest (FIQ). The interrupt controller has the ability

Table 9, Table 10 and Table 11 show the names

to control interrupts from 22 different FIQ and IRQ

and allocation of interrupts in the EP7209.

sources. Of these, seventeen are mapped to the IRQ

input and five sources are mapped to the FIQ input.

26

DS453PP2

EP7209

Interrupt Bit in INTMR1 and

INTSR1

Name

Comment

FIQ

IRQ

0

1

EXTFIQ

BLINT

External fast interrupt input (nEXTFIQ pin)

Battery low interrupt

2

WEINT

MCINT

CSINT

EINT1

Tick Watchdog expired interrupt

Media changed interrupt

3

4

Codec sound interrupt

5

External interrupt input 1 (nEINT[1] pin)

External interrupt input 2 (nEINT[2] pin)

External interrupt input 3 (EINT[3] pin)

TC1 underflow interrupt

6

EINT2

7

EINT3

8

TC1OI

9

TC2OI

TC2 underflow interrupt

10

11

12

13

14

15

RTCMI

TINT

RTC compare match interrupt

64 Hz tick interrupt

UTXINT1

URXINT1

UMSINT

SSEOTI

Internal UART1 transmit FIFO empty interrupt

Internal UART1 receive FIFO full interrupt

Internal UART1 modem status changed interrupt

Synchronous serial interface 1 end of transfer interrupt

Table 9. Interrupt Allocation in the First Interrupt Register

Interrupt

Bit in INTMR2 and

Name

Comment

INTSR2

IRQ

0

1

KBDINT

SS2RX

Key press interrupt

Master/slave SSI 16 bytes received

Master/slave SSI 16 bytes transmitted

UART2 transmit FIFO empty interrupt

UART2 receive FIFO full interrupt

2

SS2TX

12

13

UTXINT2

URXINT2

Table 10. Interrupt Allocation in the Second Interrupt Register

Interrupt

Bit in INTMR3 and

Name

Comment

DAI interface interrupt

INTSR3

FIQ

0

DAIINT

Table 11. Interrupt Allocation in the Third Interrupt Register

DS453PP2

27

EP7209

the OS cannot meet this requirement, there will be

a risk of data over/underflow occurring. Idle State

3.5.1

Interrupt Latencies in Different

States

When leaving the Idle State as a result of an inter-

rupt, the CPU clock is restarted after approximately

two clock cycles. However, there is still potentially

up to 20 µsec latency as described in the first sec-

tion above, unless the code is written to include at

least two single cycle instructions immediately af-

ter the write to the IDLE register (in which case the

latency drops to a few microseconds). This is im-

portant, as the Idle State can only be left because of

a pending interrupt, which has to be synchronized

by the processor before it can be serviced.

3.5.1.1 Operating State

The ARM720T processor checks for a low level on

its FIQ and IRQ inputs at the end of each instruc-

tion. The interrupt latency is therefore directly re-

lated to the amount of time it takes to complete

execution of the current instruction when the inter-

rupt condition is detected. First, there is a one to

two clock cycle synchronization penalty. For the

case where the EP7209 is operating at 13 MHz

with a 16-bit external memory system, and instruc-

tion sequence stored in one wait state FLASH

memory, the worst case interrupt latency is

251 clock cycles. This includes a delay for cache

line fills for instruction prefetches, and a data abort

occurring at the end of the LDM instruction, and

the LDM being non-quad word aligned. In addi-

tion, the worst-case interrupt latency assumes that

LCD DMA cycles to support a panel size of 320 x

240 at 4 bits-per-pixel, 60 Hz refresh rate, is in

progress.

3.5.1.2 Standby State

In the Standby State, the latency will depend on

whether the system clock is shut down and if the

FASTWAKE bit in the SYSCON3 register is set. If

the system is configured to run from the internal

PLL clock, then the PLL will always be shut down

when in the Standby State. In this case, if the

FASTWAKE bit is cleared, then there will be a la-

tency of between 0.125 sec to 0.25 sec. If the

FASTWAKE bit is set, then there will be a latency

of between 250 µsec to 500 µsec. If the system is

running from the external clock (at 13 MHz), with

the CLKENSL bit in SYSCON2 set to 0, then the

latency will also be between 0.125 sec and 0.25 sec

to allow an external oscillator to stabilize. In the

case of a 13 MHz system where the clock is not dis-

abled during the Standby State (CLKENSL = 1),

then the latency will be the same as described in the

Idle State section above.

This would give a worst-case interrupt latency of

about 19.3 µs for the ARM720T processor operat-

ing at 13 MHz in this system. For those interrupt

inputs which have de-glitching, this figure is in-

creased by the maximum time required to pass

through the deglitcher, which is approximately 125

µs (2 cycle of the 16.384 kHz clock derived from

the RTC oscillator). This would create an absolute

worst case latency of approximately 141 µs. If the

ARM720T is run at 36 MHz or greater and/or

32 bit wide external memory, the 19.3 µs value will

be reduced.

Whenever the EP7209 is in the Standby State, the

external address and data buses are driven low. The

RUN signal is used internally to force these buses

to be driven low. This is done to prevent peripher-

als that are power-down from draining current. Al-

so, the internal peripheral’s signals get set to their

Reset State.

All the serial data transfer peripherals included in

the EP7209 (except for the master-only SSI1) have

local buffering to ensure a reasonable interrupt la-

tency response requirement for the OS of 1 ms or

less. This assumes that the maximum data rates de-

scribed in this specification are complied with. If

28

DS453PP2

EP7209

Table 12 summarizes the five external interrupt transition on the external WAKEUP pin in order to

sources and the effect they have on the processor

interrupts.

actually start the boot sequence.

The effect of booting from the on-chip Boot ROM

is to reverse the decoding for all chip selects inter-

nally. Table 13 shows this decoding. The control

signal for the boot option is latched by nPOR,

which means that the remapping of addresses and

bus widths will continue to apply until nPOR is as-

serted again. After booting from the Boot ROM,

the contents of the Boot ROM can be read back

from address 0x00000000 onwards, and in normal

state of operation the Boot ROM contents can be

read back from address range 0x70000000.

3.6

EP7209 Boot ROM

The 128 bytes of on-chip Boot ROM contain a in-

struction sequence that initializes the device and

then configures UART1 to receive 2048 bytes of

serial data that will then be placed in the on-chip

SRAM. Once the download is complete, execution

jumps to the start of the on-chip SRAM. This

would allow, for example, code to be downloaded

to program system FLASH during a product’s

manufacturing process. See Appendix A: Boot

Code for details of the ROM Boot Code with com-

ments to describe the stages of execution.

Address Range

Chip Select

CS[7]

(Internal only)

0000.0000–0FFF.FFFF

Selection of the Boot ROM option is determined by

the state of the nMEDCHG pin during a power on

reset. If nMEDCHG is high while nPOR is active,

then the EP7209 will boot from an external memo-

ry device connected to CS[0] (normal boot mode).

If nMEDCHG is low, then the boot will be from the

on-chip ROM. Note that in both cases, following

the de-assertion of power on reset, the EP7209 will

be in the Standby State and requires a low-to-high

1000.0000–1FFF.FFFF

CS[6]

(Internal only)

2000.0000–2FFF.FFFF

3000.0000–3FFF.FFFF

4000.0000–4FFF.FFFF

5000.0000–5FFF.FFFF

6000.0000–6FFF.FFFF

7000.0000–7FFF.FFFF

nCS[5]

nCS[4]

nCS[3]

nCS[2]

nCS[1]

nCS[0]

Table 13. Chip Select Address Ranges After Boot From

On-Chip Boot ROM

Interrupt

Input State

Operating State

Latency

Idle State

Latency

Standby State Latency

nEXTFIQ

Not deglitched; must be Worst case latency Worst case

Including PLL/osc. settling time, approx.

0.25 sec when FASTWAKE = 0, or

approx. 500 µsec when FASTWAKE = 1,

or = Idle State if in 13 MHz mode with

CLKENSL set

active for 20 µs to be

detected

of 20 µsec

20 µsec: if only

single cycle

instructions, less

than 1 µsec

nEINT1–2

Not deglitched

Worst case latency As above

of 20 µsec

As above

EINT3

Worst case latency As above

As above

of 20 µsec

nMEDCHG Deglitched by 16 kHz

clock; must be active

for at least 125 µs to be

detected

Worst case latency Worst case

As above (note difference if in 13 MHz

mode with CLKENSL set)

of 141 µsec

80 µsec: if only

single cycle

instructions,

125 µsec

Table 12. External Interrupt Source Latencies

DS453PP2

29

EP7209

fore nCS is released to allow DMA and refreshes to

take place. This can significantly improve bus

bandwidth to devices such as ROMs which support

page mode. When SQAEN = 0, all accesses to

memory are by random access without nCS being

de-asserted between accesses. Again nCS is de-as-

serted after four consecutive accesses to allow

DMAS.

3.7

Memory and I/O Expansion Interface

Six separate linear memory or expansion segments

are decoded by the EP7209, two of which can be re-

served for two PC Card cards, each interfacing to a

separate single CL-PS6700 device. Each segment

is 256 Mbytes in size. Two additional segments

(i.e., in addition to these six) are dedicated to the

on-chip SRAM and the on-chip ROM. The on-chip

ROM space is fully decoded, and the SRAM space Bits 5 and 6 of the SYSCON2 register independent-

is fully decoded up to the maximum size of the vid- ly enable the interfaces to the CL-PS6700 (PC Card

eo frame buffer programmed in the LCDCON reg-

ister (128 kbytes). Beyond this address range the

SRAM space is not fully decoded (i.e., any access-

slot drivers). When either of these interfaces are en-

abled, the corresponding chip select (nCS4 and/or

nCS5) becomes dedicated to that CL-PS6700 inter-

es beyond 128 kbyte range get wrapped around to face. The state of SYSCON2 bit 5 determines the

within 128 kbyte range). Any of the six segments function of chip select nCS4 (i.e., CL-PS6700 in-

are configured to interface to a conventional

SRAM-like interface, and can be individually pro-

grammed to be 8-, 16-, or 32-bits wide, to support

page mode access, and to execute from 1 to 8 wait

states for non-sequential accesses and 0 to 3 for

burst mode accesses. The zero wait state sequential

access feature is designed to support burst mode

ROMs. For writable memory devices which use the

nMWE pin, zero wait state sequential accesses are

not permitted and one wait state is the minimum

which should be programmed in the sequential

field of the appropriate MEMCFG register. Bus cy-

cles can also be extended using the EXPRDY input

signal.

terface or standard chip select functionality); bit 6

controls nCS5 in a similar way. There is no interac-

tion between these bits.

For applications that require a display buffer small-

er than 38,400 bytes, the on-chip SRAM can be

used as the frame buffer.

The width of the boot device can be chosen by se-

lecting values of PE[1] and PE[0] during power on

reset. These inputs are latched by the rising edge of

nPOR to select the boot option.

PE[1]

PE[0]

Boot Block

(nCS0)

0

1

0

1

0

1

32-bit

8-bit

Page mode access is accomplished by setting

SQAEN = 1, which enables accesses of the form

one random address followed by three sequential

addresses, etc., while keeping nCS asserted. These

sequential bursts can be up to four words long be-

16-bit

Undefined

Table 14. Boot Options

30

DS453PP2

EP7209

chip selects are used to select the device to be ac-

cessed. The space field is made directly from the

A26 and A27 CPU address bits, according to the

decode shown in Table 16. The size field is forced

to 11 if a word access is required, or to 00 if a byte

access is required. This avoids the need to config-

ure the interface after a reset. On the second clock

cycle, the remaining 16 bits of the PC Card address

are multiplexed out onto the lower 16 bits of the

data bus. If the transaction selected is a CL-PS6700

register transaction, or a write to the PC Card (as-

suming there is space available in the CL-PS6700’s

internal write buffer) then the access will continue

on the following two clock cycles. During these

following two clock cycles the upper and lower

halves of the word to be read or written will be put

onto the lower 16 bits of the main data bus.

3.8

CL-PS6700 PC Card Controller

Interface

Two of the expansion memory areas are dedicated

to supporting up to two CL-PS6700 PC Card con-

troller devices. These are selected by nCS4 and

nCS5 (once enabled by bits 5 and 6 of SYSCON2).

For efficient, low power operation, both address

and data are carried on the lower 16 bits of the

EP7209 data bus. Accesses are initiated by a write

or read from the area of memory allocated for nCS4

or nCS5. The memory map within each of these ar-

eas is segmented to allow different types of PC

Card accesses to take place, for attribute, I/O, and

common memory space. The CL-PS6700 internal

registers are memory mapped within the address

space as shown in Table 15.

NOTE:

It must be noted that, due to the operating

speed of the CL-PS6700, this interface is

supported only for processor speeds of

13 and 18 MHz.

The ‘ptype’ signal on the CL-PS6700s should be

connected to the EP7209’s WRITE output pin.

During PC Card accesses, the polarity of this pin

changes and it becomes low to signify a write and

high to signify a read. It is valid with the first half

word of the address. During the second half word

of the address it is always forced high to indicate to

the CL-PS6700 that the EP7209 has initiated either

the write or read.

A complete description of the protocol and AC tim-

ing characteristics can be found in the CL-PS6700

data sheet. A transaction is initiated by an access to

the nCS4 or nCS5 area. The chip select is asserted,

and on the first clock, the upper 10 bits of the PC

Card address, along with 6 bits of size, space, and

slot information are put out onto the lower 16 bits

of the EP7209’s data bus. Only word (i.e., 4-byte)

and single-byte accesses are supported, and the slot

field is hardcoded to 11, since the slot field is de-

fined as a ‘Reserved field’ by the CL-PS6700. The

The PRDY signals from each of the two CL-

PS6700 devices are connected to Port B bits 0 and

1, respectively. When the PC CARD1 or PC

CARD2 control bits in the SYSCON2 register are

Access Type

Addresses for CL-PS6700 Interface 1

Addresses for CL-PS6700 Interface 2

0x50000000– 0x53FFFFFF

0x54000000–0x57FFFFFF

Attribute

0x40000000–0x43FFFFFF

0x44000000–0x47FFFFFF

0x48000000–0x4BFFFFFF

0x4C000000–0x4FFFFFFF

I/O

Common memory

CL-PS6700 registers

0x58000000–0x5BFFFFFF

0x5C000000–0x5FFFFFFF

Table 15. CL-PS6700 Memory Map

DS453PP2

31

EP7209

de-asserted, these port bits are available for GPIO.

When asserted, these port bits are used as the

PRDY signals. When the PRDY signal is de-assert-

ed (i.e., low), it indicates that the CL-PS6700 is

busy accessing its card. If a PC CARD access is at-

tempted while the device is busy, the PRDY signal

will cause the EP7209’s CPU to be stalled. The

EP7209’s CPU will have to wait for the card to be-

come available. DMA transfers to the LCD can still

continue in the background during this period of

time (as described below). The EP7209 can access

the registers in the CL-PS6700, regardless of the

state of the PRDY signal. If the EP7209 needs to

access the PC CARD via the CL-PS6700, it waits

until the PRDY signal is high before initiating a

transfer request. Once a request is sent, the PRDY

signal indicates if data is available.

that DMA transfers to the LCD controller can con-

tinue in the background.

In the case of a PC Card read, the PRDY signal

from the CL-PS6700 will be de-asserted until the

read data is ready. At this point, it will be reasserted

and the access will be completed in the same way

as for a register access. In the case of a byte access,

only one 16-bit data transfer will be required to

complete the access. While the PRDY signal is de-

asserted, the chip select to the CL-PS6700 will be

de-asserted and the main bus will be released so

that DMA transfers to the LCD controller can con-

tinue in the background.

The EP7209 will re-arbitrate for control of the bus

when the PRDY signal is reasserted to indicate that

the read or write transaction can be completed. The

CPU will always be stalled until the PC Card ac-

cess is completed.

In the case of a PC Card write, writes can be posted

to the CL-PS6700 device, with the same timing as

CL-PS6700 internal register writes. Writes will

normally be completed by the CL-PS6700 device

independent of the EP7209 processor activity. If a

posted write times out, or fails to complete for any

other reason, then the CL-PS6700 will issue an in-

terrupt (i.e., a WR_FAIL interrupt). In the case

where the CL-PS6700 write buffer is already full,

A card read operation may be split into a request

cycle and a data cycle, or it may be combined into

a single request/data transfer cycle. This depends

on whether the data requested from the card is

available in the prefetch buffer (internal to the CL-

PS6700).

The request portion of the cycle, for a card read, is

the PRDY signal will be de-asserted (i.e., driven similar to the request phase for a card write (de-

low) and the transaction will be stalled pending an scribed above). If the requested data is available in

available slot in the buffer. In this case, the

the prefetch buffer, the CL-PS6700 asserts the

EP7209’s CPU will be stalled until the write can be PRDY signal before the rising edge of the third

posted successfully. While the PRDY signal is de- clock and the EP7209 continues the cycle to read

asserted, the chip select to the CL-PS6700 will be the data. Otherwise, the PRDY signal is de-asserted

de-asserted and the main bus will be released so

and the request cycle is stalled. The EP7209 may

Space Field Value

PC CARD Memory Space

Attribute

00

01

10

11

I/O

Common memory

CL-PS6700 registers

Table 16. Space Field Decoding

32

DS453PP2

EP7209

then allow the DMA address generator to gain con- bit in the SYSCON1 register, when the CL-PS6700

trol of the bus, to allow LCD refreshes to continue.

is used. The reason for this is that the PC Card in-

When the CL-PS6700 is ready with the data, it as- terface and CL-PS6700 internal write buffers need

serts the PRDY signal. The EP7209 then arbitrates

for the bus and, once the request is granted, the sus-

pended read cycle is resumed. The EP7209 re-

sumes the cycle by asserting the appropriate chip

select, and data is transferred on the next two

clocks if a word read (one clock if a byte read).

to be clocked after the EP7209 has completed its

bus cycles.

A GPIO signal from the EP7209 can be connected

to the PSLEEP pin of the CL-PS6700 devices to al-

low them to be put into a power saving state before

the EP7209 enters the Standby State. It is essential

There is no support within the EP7209 for detecting that the software monitor the appropriate status

time-outs. The CL-PS6700 device must be pro- registers within the CL-PS6700s to ensure that

grammed to force the cycle to be completed (with there are no pending posted bus transactions before

invalid data for a read) and then generate an inter- the Standby State is entered. Failure to do this will

rupt if a read or write access has timed out (i.e.,

RD_FAIL or WR_FAIL interrupt). The system

software can then determine which access was not

successfully completed by reading the status regis-

ters within the CL-PS6700.

result in incomplete PC Card accesses.

3.9 Endianness

The EP7209 uses a Little Endian configuration for

internal registers. However, it is possible to con-

nect the device to a Big Endian external memory

system. The Big-endian/Little-endian bit in the

ARM720T control register sets whether the

EP7209 treats words in memory as being stored in

Big Endian or Little Endian format. Memory is

viewed as a linear collection of bytes numbered up-

wards from zero. Bytes 0 to 3 hold the first stored

word, bytes 4 to 7 the second, and so on. In the Lit-

tle Endian scheme, the lowest numbered byte in a

word is considered to be the least significant byte

of the word and the highest numbered byte is the

most significant. Byte 0 of the memory system

should be connected to data lines 7 through 0

(D[7:0]) in this scheme. In the Big Endian scheme

the most significant byte of a word is stored at the

lowest numbered byte, and the least significant

byte is stored at the highest numbered byte. There-

fore, Byte 0 of the memory system should be con-

nected to data lines 31 through 24 (D[31:24]). Load

and store are the only instructions affected by the

Endianness.

The CL-PS6700 has support for DMA data trans-

fers. However, DMA is supported only by software

emulation because the DMA address generator

built into the EP7209 is dedicated to the LCD con-

troller interface. If DMA is enabled within the CL-

PS6700, it will assert its PDREQ signal to make a

DMA request. This can be connected to one of the

EP7209’s external interrupts and be used to inter-

rupt the CPU so that the software can service the

DMA request under program control.

Each of the CL-PS6700 devices can generate an in-

terrupt PIRQ. The PIRQ output is open drain on the

CL-PS6700 devices, so if there are two CL-PS6700

devices they may be wire OR’ed to the same inter-

rupt which can be connected to one of the

EP7209’s active low external interrupt sources. On

the receipt of an interrupt, the CPU can read the in-

terrupt status registers on the CL-PS6700 devices

to determine the cause of the interrupt.

All transactions are synchronized to the EXPCLK

output from the EP7209 in 18.432 MHz mode or

the external 13 MHz clock. The EXPCLK should

be permanently enabled, by setting the EXCKEN

Tables 17 and 18 demonstrate the behavior of the

EP7209 in Big and Little Endian mode, including

the effect of performing non-aligned word access-

DS453PP2

33

EP7209

es. The register definition section of this specifica-

tion defines the behavior of the internal EP7209

er can be optionally switched in to the TX and RX

signals of UART1, so that these can be used to

registers in the Big Endian mode in more detail. For drive an infrared interface directly. If the SIR pro-

further information, refer to ARM Application Note

61, Big and Little Endian Byte Addressing.

tocol encoder is enabled, the UART TXD1 line is

held in the passive state and transitions of the

RXD1 line will have no effect. The IrDA output pin

is LEDDRV, and the input from the photodiode is

PHDIN. Modem status lines will cause an interrupt

(which can be masked) irrespective of whether the

SIR interface is being used.

3.10 Internal UARTs (Two) and SIR

Encoder

The EP7209 contains two built-in UARTs that of-

fers similar functionality to National Semiconduc-

tor’s 16C550A device. Both UARTs can support

bit rates of up to 115.2 kbits/s and include two 16-

byte FIFOs: one for receive and one for transmit.

Both the UARTs operate in a similar manner to the

industry standard 16C550A. When CTS is deas-

serted on the UART, the UART does not stop shift-

ing the data. It relies on software to take

appropriate action in response to the interrupt gen-

erated.

One of the UARTs (UART1) supports the three

modem control input signals CTS, DSR and DCD.

The additional RI input, and RTS and DTR output

modem control lines are not explicitly supported

but can be implemented using GPIO ports in the

EP7209. UART2 has only the RX and TX pins.

Baud rates supported for both the UARTs are de-

pendent on frequency of operation. When operat-

ing from the internal PLL, the interface supports

various baud rates from 115.2 kbps downwards.

The master clock frequency is chosen so that most

of the required data rates are obtainable exactly.

When operating with a 13.0 MHz external clock

source, the baud rates generated will have a slight

error, which is less than or equal to 0.75%. The

rates obtainable from the 13 MHz clock include

9.6 k, 19.2 k, 38 k, 58 k and 115.2 kbps. See

UBRLCR1-2 UART1-2 Bit Rate and Line Control

Registers for full details of the available bit rates in

the 13 MHz mode.

UART operation and line speeds are controlled by

the UBLCR1 (UART bit rate and line control).

Three interrupts can be generated by UART1: RX,

TX, and modem status interrupts. Only two can be

generated by UART2: RX and TX. The RX inter-

rupt is asserted when the RX FIFO becomes half

full or if the FIFO is non-empty for longer than

three character length times with no more charac-

ters being received. The TX interrupt is asserted if

the TX FIFO buffer reaches half empty. The mo-

dem status interrupt for UART1 is generated if any

of the modem status bits change state. Framing and

parity errors are detected as each byte is received

and pushed onto the RX FIFO. An overrun error

3.11 Serial Interfaces

In addition to the two UARTs, the EP7209 offers

generates an RX interrupt immediately. All error the following serial interfaces shown in Table 19.

bits can be read from the 11-bit wide data register.

The FIFOs can also be programmed to be one byte

depth only (i.e., like a conventional 16450 UART

with double buffering).

The inputs/outputs of three of the serial interfaces

(DAI, codec, and SSI2) are multiplexed onto a sin-

gle set of external interface pins. If the DAISEL bit

of SYSCON3 is low, then either SSI2 or the codec

interface will be selected to connect to the external

pins. When bit 0 of SYSCON2 (SERSEL) is high,

then the codec is connected to the external pins,

when low the master/slave SSI2 is connected to

The EP7209 also contains an IrDA (Infrared Data

Association) SIR protocol encoder as a post-pro-

cessing stage on the output of UART1. This encod-

34

DS453PP2

EP7209

these pins. When the DAISEL bit is set high, the

DAI interface is connected to the external pins. On

power up, both the DAISEL and SERSEL bits are

reset low, thus the master/slave SSI2 will be con-

nected to these pins (and configured for slave mode

operation to avoid external drive clashes).

Table 20 contains pin definition information for the

three multiplexed interfaces.

The internal names given to each of the three inter-

faces are unique to help differentiate them from

each other. The sections below that describe each

of the three interfaces will use their respective

unique internal pin names for clarity.

Type

Comments

Master mode only

Referred To As

ADC Interface

SSI2 Interface

DAI Interface

Max. Transfer Speed

128 kbits/s

SPI/Microwire 1

SPI/Microwire 2

DAI Interface

Master/slave mode

512 kbits/s

1.536 Mbits/s

64 kbits/s

CD quality DACs and ADCs

Only for use in the PLL clock mode

Codec Interface

Table 19. Serial Interface Options

No.

LQFP

External

Pin Name

SSI2

Slave Mode

(Internal Name)

SSI2

Master Mode

Codec

Internal Name

DAI

Internal Name

Strength

SSICLK = serial bit

clock; Input

PCMCLK =

Output

SCLK =

Output

63

65

66

67

68

SSICLK

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

Output

Input

1

SSKTXFR = TX

frame sync; Input

PCMSYNC = Output

PCMOUT = Output

PCMIN = Input

LRCK = Output

SDOUT = Output

SDIN = Input

MCLK

SSITXDA = TX data;

Output

SSIRXDA = RX data;

Input

SSIRXFR = RX

frame sync; Input

p/u

Output

1

(use a 10k pull-up)

Table 20. Serial-Pin Assignments

DS453PP2

35

EP7209

NOTE:

Both the CDENRX and CDENTX enable bits

should be asserted in tandem for data to be

transmitted or received. The reason for this

is that the interrupt generation will occur

1 msec after one of the FIFOs is enabled.

For example: If the receive FIFO gets

enabled first and the transmit FIFO at a later

time, the interrupt will occur 1 msec after the

receive FIFO is enabled. After the first inter-

rupt occurs, the receive FIFO will be half full.

However, it will not be possible to know how

full the transmit FIFO will be since it was

enabled at a later time. Thus, it is possible to

unintentionally overwrite data already in the

transmit FIFO (See Figure 6).

3.11.1 Codec Sound Interface

The codec interface allows direct connection of a

telephony type codec to the EP7209. It provides all

the necessary clocks and timing pulses and per-

forms a parallel to serial conversion or vice versa

on the data stream to or from the external codec de-

vice. The interface is full duplex and contains two

separate data FIFOs (16 deep by 8-bits wide, one

for the receive data, another for the transmit data).

Data is transferred to or from the codec at

64 kbits/s. The data is either written to or read from

the appropriate 16 byte FIFO. If enabled, a codec

interrupt (CSINT) will be generated after every

8 bytes are transferred (FIFO half full/empty). This

means the interrupt rate will be every 1 msec, with

a latency of 1 msec.

After the CDENRX and CDENTX enable bits get

asserted, the corresponding FIFOs become en-

abled. When both FIFOs are disabled, the FIFO sta-

tus flag CRXFE is set and CTXFF is cleared so that

the FIFOs appear empty. Additionally, if the

CDENTX bit is low, the PCMOUT output is dis-

abled. Asserting either of the two enable bits causes

the sync and interrupt generation logic to become

active; otherwise they are disabled to conserve

power.

Transmit and receive modes are enabled by assert-

ing high both the CDENRX and CDENTX codec

enable bits in the SYSCON1 register.

CDENRX

CDENTX

CSINT

1 ms

Figure 6. Codec Interrupt Timing

36

DS453PP2

EP7209

Data is loaded into the transmit FIFO by writing to

the CODR register. At the beginning of a transmit

cycle, this data is loaded into a shift/load register.

Just prior to the byte being transferred out, PCM-

SYNC goes high for one PCMCLK cycle. Then the

data is shifted out serially to PCMOUT, MSB first,

(with the MSB valid at the same time PCMSYNC

is asserted). Data is shifted on the rising edge of the

PCMCLK output.

3.11.2 Digital Audio Interface

The DAI interface provides a high quality digital

audio connection to DAI compatible audio devices.

The DAI is a subset of I2S audio format that is sup-

ported by a number of manufacturers.

The DAI interface produces one 128-bit frame at

the audio sample frequency using a bit clock and

frame sync signal. Digital audio data is transferred,

full duplex, via separate transmit and receive data

lines. The bit clock frequency is either fixed at

9.216 MHz or set via an externally supplied MCLK

signal.

Receiving of data is performed by taking data in se-

rially through PCMIN, again MSB first, shifting it

through the shift/load register and loading the com-

plete byte into the receive FIFO. If there is no data

available in the transmit FIFO, then a zero will be

loaded into the shift/load register. Input data is

sampled on the falling edge of PCMCLK. Data is

read from the CODR register.

The DAI interface contains separate transmit and

receive FIFO’s. The transmit FIFO’s are 8 audio

samples deep and the receive FIFO’s are 12 audio

samples deep.

DAI ADC

SCLK

LRCK

SDATA

MCLK

7209

SDIN

DAI DAC

SCLK

LRCK

SDOUT

MCLK

LRCK

SDATA

MCLK

CLOCK

GEN

Figure 7. DAI Interface

DS453PP2

37

EP7209

tions from low to high the next 16-bits make up the

right side of an audio sample.

3.11.2.1 DAI Operation

Following reset, the DAI logic is disabled. To en-

able the DAI, the applications program should first

clear the emergency underflow and overflow status

bits, which are set following the reset, by writing a

1 to these register bits (in the DAISR register).

Next, the DAI control register should be pro-

grammed with the desired mode of operation using

a word write. The transmit FIFOs can either be

“primed” by writing up to eight 16-bit values each,

or can be filled by the normal interrupt service rou-

tine which handles the DAI FIFOs. Finally, the

FIFOs for each channel must be enabled via writes

to DAIDR2. At this point, transmission/reception

of data begins on the transmit (SDOUT) and re-

ceive (SDIN) pins. This is synchronously con-

trolled by the 9.216 MHz (6.5 MHz in 13 MHz

mode) internal clock or the externally supplied bit

clock (SCLK), and the serial frame clock (LRCK).

3.11.2.3 DAI Signals

MCLK

oversampled clock. Used as an in-

put to the EP7209 for generating the

DAI timing. This signal is also usu-

ally used as an input to a DAC/ADC

as an oversampled clock. This sig-

nal is fixed at 256 times the audio

sample frequency.

SCLK

LRCK

bit clock. Used as the bit clock input

into the DAC/ADC. This signal is

fixed at 128 times the audio sample

frequency.

frame sync. Used as a frame syn-

chronization

input

to

the

DAC/ADC. This signal is fixed at

the audio sample frequency. This

signal is clocked out on the negative

going edge of SCLK.

3.11.2.2 DAI Frame Format

Each DAI frame is 128 bits long and is comprises

one audio sample. Of this 128-bit frame, only

32 bits are actually used for digital audio data. The

remaining bits are output as zeros. The LRCK sig-

nal is used as a frame synchronization signal. Each

transition of LRCK delineates the left and right

halves of an audio sample. When LRCK transi-

tions from high to low the next 16-bits make up the

left side of an audio sample. When LRCK transi-

SDOUT digital audio data out. Used for

sending playback data to a DAC.

This signal is clocked out on the

negative going edge of the SCLK

output.

SDIN

digital audio input. Used for receiv-

ing record data from an ADC. This

signal is latched by the EP7209 on

the positive going edge of SCLK.

128 SCLKs

Left Channel

Right Channel

LRCK

SCLK

MSB

LSB

MSB

LSB

SDATAO

SDATAI

-1 -2 -3 -4 -5

+5 +4 +3 +2 +1

-1 -2 -3 -4

+5 +4 +3 +2 +1

LSB

-1 -2 -3 -4

Figure 8. EP7209 Rev C - Digital Audio Interface Timing – MSB/Left Justified format

38

DS453PP2

EP7209

SYSCON3 is clear. When ADCCON is set, up to

16 bits of configuration command can be sent, as

specified in the SYNCIO register. The input chan-

nel is captured by a 16-bit shift register. The clock

and synchronization pulses are activated by a write

to the output shift register. During transfers the

SSIBUSY (synchronous serial interface busy) bit

in the system status flags register is set. When the

transfer is complete and valid data is in the 16-bit

read shift register, the SSEOTI interrupt is asserted

and the SSIBUSY bit is cleared.

3.11.3 ADC Interface — Master Mode Only

SSI1 (Synchronous Serial Interface)

The first synchronous serial interface allows inter-

facing to the following peripheral devices:

•

In the default mode, the device is compatible

with the MAXIM MAX148/9 in external clock

mode. Similar SPI or Microwire compatible de-

vices can be connected directly to the EP7209.

•

In the extended mode and with negative-edge

triggering selected (the ADCCON and ADC-

CKNSEN bits are set, respectively, in the

SYSCON3 register), this device can be inter-

faced to Analog Devices’ AD7811/12 chip us-

ing nADCCS as a common RFS/TFS line.

An additional sample clock (SMPCLK) can be en-

abled independently and is set at twice the transfer

clock frequency.

This interface has no local buffering capability and

is only intended to be used with low bandwidth in-

terfaces, such as for a touch-screen ADC interface.

•

Other features of the devices, including power

management, can be utilized by software and

the use of the GPIO pins.

3.11.4 Master/Slave SSI2 (Synchronous

Serial Interface 2)

The clock output frequency is programmable and

only active during data transmissions to save pow-

er. There are four output frequencies selectable,

which will be slightly different depending whether

the device is operating in a 13 MHz mode or a

18.432 MHz–73.728 MHz mode (see Table 21).

The required frequency is selected by program-

ming the corresponding bits 16 and 17 in the

SYSCON1 register. The sample clock (SMPCLK)

always runs at twice the frequency of the shift

clock (ADCCLK). The output channel is fed by an

8-bit shift register when the ADCCON bit of

A second SPI/Microwire interface with full mas-

ter/slave capability is provided by the EP7209.

Data rates in slave mode are theoretically up to

512 kbits/s, full duplex, although continuous oper-

ation at this data rate will give an interrupt rate of

2 kHz, which is too fast for many operating sys-

tems. This would require a worst case interrupt re-

sponse time of less than 0.5 msec and would cause

loss of data through TX underruns and RX over-

runs.

SYSCON1

bit 17

SYSCON1

bit 16

13.0 MHz Operation ADCCLK

18.432–73.728 MHz Operation

ADCCLK Frequency (kHz)

Frequency (kHz)

0

1

0

1

0

1

4.2

16.9

67.7

135.4

4

16

64

128

Table 21. ADC Interface Operation Frequencies

DS453PP2

39

EP7209

The interface is fully capable of being clocked at

512 kHz when in slave mode. However, it is antic-

ipated that external hardware will be used to frame

the data into packets. Therefore, although the data

would be transmitted at a rate of 512 kbits/s, the

sustained data rate would in fact only be

85.3 kbits/s (i.e., 1 byte every 750 µsec). At this

data rate, the required interrupt rate will be greater

than 1 msec, which is acceptable.

pendently enable the transmit and receive sides of

the interface.

The master/slave SSI is synchronous, full duplex,

and capable of supporting serial data transfers be-

tween two nodes. Although the interface is byte-

oriented, data is loaded in blocks of two bytes at a

time. Each data byte to be transferred is marked by

a frame sync pulse, lasting one clock period, and

located one clock prior to the first bit being trans-

ferred. Direction of the SSI2 ports, in slave and

master mode, is shown in Figure 9.

There are separate half-word-wide RX and TX

FIFOs (16 half-words each) and corresponding in-

terrupts which are generated when the FIFO’s are

half-full or half-empty as appropriate. The inter-

rupts are called SS2RX and SS2TX, respectively.

Register SS2DR is used to access the FIFOs.

Data on the link is sent MSB first and coincides

with an appropriate frame sync pulse, of one clock

in duration, located one clock prior to the first data

bit sent (i.e., MSB). It is not possible to send data

There are five pins to support this SSI port: SSIRX- LSB first.

DA, SSITXFR, SSICLK, SSITXDA, and SSIRX-

When operating in master mode, the clock frequen-

FR. The SSICLK, SSIRXDA, SSIRXFR, and

SSITXFR signals are inputs and the SSITXDA sig-

nal is an output in slave mode. In the master mode,

SSICLK, SSITXDA, SSITXFR, and SSIRXFR are

outputs and SSIRXDA is an input. Master mode is

enabled by writing a one to the SS2MAEN bit

(SYSCON2[9]). When the master/slave SSI is not

required, it can be disabled to save power by writ-

ing a zero to the SS2TXEN and the SS2RXEN bits

(SYSCON2[4] [7]). When set, these two bits inde-

cy is selected to be the same as the ADC interface’s

(master mode only SSI1) — that is, the frequencies

are selected by the same bits 16 and 17 of the

SYSCON1 register (i.e., the ADCKSEL bits).

Thus, the maximum frequency in master mode is

128 kbits/s. The interface will support continuous

transmission at this rate assuming that the OS can

respond to the interrupts within 1 msec to prevent

over/underruns.

Master 7209

SSIRXFR

SSITXFR

SSICLK

Slave 7209

SSIRXFR

SSITXFR

SSICLK

SSITXDA

SSIRXDA

SSITXDA

Figure 9. SSI2 Port Directions in Slave and Master Mode

40

DS453PP2

EP7209

Address

(W/B)

Data in

Memory

(as seen

by the

Byte Lanes to Memory/Ports/Registers

R0 Contents

Big Endian Memory

Little Endian Memory

7:0 15:8 23:16 31:24 7:0 15:8 23: 16 31: 24

Big

Little

Endian

EP7209)

Word + 0 (W) 11223344

Word + 1 (W) 11223344

Word + 2 (W) 11223344

Word + 3 (W) 11223344

Word + 0 (H) 11223344

Word + 1 (H) 11223344

Word + 2 (H) 11223344

Word + 3 (H) 11223344

Word + 0 (B) 11223344

Word + 1 (B) 11223344

Word + 2 (B) 11223344

Word + 3 (B) 11223344

44

dc

44

33

dc

33

dc

22

dc

22

dc

11

dc

44

dc

33

dc

33

dc

22

dc

22

dc

11

dc

11

11223344 11223344

44112233 44112233

33441122 33441122

22334411 22334411

00001122 00003344

22000011 44000033

00003344 00001122

44000033 22000011

00000011 00000044

00000022 00000033

00000033 00000022

00000044 00000011

NOTE:

dc = don’t care

Table 17. Effect of Endianness on Read Operations

Address

(W/B)

Register

Contents

Byte Lanes to Memory/Ports/Registers

Big Endian Memory Little Endian Memory

7:0

44

15:8

33

44

23:16

22

31:24

11

7:0

44

15:8

33

44

23:16

22

31:24

11

Word + 0 (W)

Word + 1 (W)

Word + 2 (W)

Word + 3 (W)

Word + 0 (H)

Word + 1 (H)

Word + 2 (H)

Word + 3 (H)

Word + 0 (B)

Word + 1 (B)

Word + 2 (B)

Word + 3 (B)

11223344

22

11

22

11

22

11

22

11

22

11

22

11

44

33

44

33

44

NOTE:

Bold indicates active byte lane.

Table 18. Effect of Endianness on Write Operations

DS453PP2

41

EP7209

NOTE:

To allow synchronization to the incoming

slave clock, the interface enable bits will not

take effect until one SSICLK cycle after they

are written and the value read back from

SYSCON2. The enable bits reflect the real

status of the enables internally. Hence, there

will be a delay before the new value pro-

grammed to the enable bits can be read

back.

will have been stored in the most significant byte of

the next half-word to be clocked into the FIFO.

NOTE:

All the writes/reads to the FIFO are done

word at a time (data on the lower 16 bits is

valid and upper 16 bits are ignored).

Software manually pops the residual byte into the

RX FIFO by writing to the SS2POP location (the

value written is ignored). This write will strobe the

The timing diagram for this interface can be found

in the AC Characteristics section of this document. RX FIFO write signal, causing the residual byte to

be written into the FIFO.

3.11.4.1 Read Back of Residual Data

3.11.4.2 Support for Asymmetric Traffic

All writes to the transmit FIFO must be in half-

words (i.e., in units of two bytes at a time). On the

The interface supports asymmetric traffic (i.e., un-

receive side, it is possible that an odd number of balanced data flow). This is accomplished through

bytes will be received. Bytes are always loaded into

the receive FIFO in pairs, so in the case of a single

separate transmit and receive frame sync control

lines. In operation, the receiving node receives a

residual byte remaining at the end of a transmis- byte of data on the eight clocks following the asser-

sion, it will be necessary for the software to read the

byte separately. This is done by reading the status

of two bits in the SYSFLG2 register to determine

the validity of the residual data. These two bits

tion of the receive frame sync control line. In a sim-

ilar fashion, the sending node can transmit a byte of

data on the eight clocks following the assertion of

the transmit frame sync pulse. There is no correla-

(RESVAL, RESFRM) are both set high when a re- tion in the frequency of assertions of the RX and

sidual is valid; RESVAL is cleared on either a new TX frame sync control lines (SSITXFR and

transmission or on reading of the residual bit by SSIRXFR). Hence, the RX path may bear a greater

software. RESFRM is cleared only on a new trans-

data throughput than the TX path, or vice versa.

mission. By popping the residual byte into the RX Both directions, however, have an absolute maxi-

FIFO and then reading the status of these bits it is mum data throughput rate determined by the maxi-

possible to determine if a residual bit has been cor-

rectly read.

Figure 10 illustrates this procedure. The sequence

Residual bit valid

is as follows: read the RESVAL bit, if this is a 0, no

action needs to be taken. If this is a 1, then pop the

00

11

New RX byte received

residual byte into the FIFO by writing to the

SS2POP location. Then read back the two status

bits RESVAL and RESFRM. If these bits read back

Pop FIFO

01, then the residual byte popped into the FIFO is

valid and can be read back from the SS2DR regis-

ter. If the bits are not 01, then there has been anoth-

er transmission received since the residual read

procedure has been started. The data item that has

been popped to the top of the FIFO will be invalid

and should be ignored. In this case, the correct byte

New RX byte

received

01

Figure 10. Residual Byte Reading

42

DS453PP2

EP7209

mum possible clock frequency, assuming that the

interrupt response of the target OS is sufficiently

quick.

3.11.4.6 Clock Polarity

Clock polarity is fixed. TX data is presented on the

bus on the rising edge of the clock. Data is latched

into the receiving device on the falling edge of the

clock. The TX pin is held in a tristate condition

when not transmitting.

3.11.4.3 Continuous Data Transfer

Data bytes may be sent/received in a contiguous

manner without interleaving clocks between bytes.

The frame sync control line(s) are eight clocks

apart and aligned with the clock representing bit D0

of the preceding byte (i.e., one bit in advance of the

MSB).

3.12 LCD Controller with Support for On-

Chip Frame Buffer

The LCD controller provides all the necessary con-

trol signals to interface directly to a single panel

multiplexed LCD. The panel size is programmable

and can be any width (line length) from 32 to

1024 pixels in 16 pixel increments. The total video

frame buffer size is programmable up to 128

kbytes. This equates to a theoretical maximum pan-

el size of 1024 x 256 pixels in 4-bits-per-pixel

mode. The video frame buffer can be located in any

portion of memory controlled by the chip selects.

Its start address will be fixed at address 0x0000000

within each chip select. The start address of the

LCD video frame buffer is defined in the FBAD-

DR[3:0] register. These bits become the most sig-

nificant nibble of the external address bus. The

default start address is 0xC000 0000 (FBADDR =

0xC). A system built using the on-chip SRAM

(OCSR), will then serve as the LCD video frame

buffer and miscellaneous data store. The LCD vid-

eo frame buffer start address should be set to 0x6 in

this option. Programming of the register FBADDR

is only permitted when the LCD is disabled (this is

to avoid possible cycle corruption when changing

the register contents while a LCD DMA cycle is in

progress). There is no hardware protection to pre-

vent this. It is necessary for the software to disable

the LCD controller before reprogramming the

FBADDR register. Full address decoding is pro-

vided for the OCSR, up to the maximum video

frame buffer size programmable into the LCDCON

register. Beyond this, the address is wrapped

around. The frame buffer start address must not be

programmed to 0x4 or 0x5 if either CL-PS6700 in-

3.11.4.4 Discontinuous Clock

In order to save power during the idle times, the

clock line is put into a static low state. The master

is responsible for putting the link into the Idle State.

The Idle State will begin one clock, or more, after

the last byte transferred and will resume at least one

clock prior to the first frame sync assertion. To dis-

able the clock, the TX section is turned off.

In Master mode, the EP7209 does not support the

discontinuous clock.

3.11.4.5 Error Conditions

RX FIFO overflows are detected and conveyed via

a status bit in the SYSFLG2 register. This register

should be accessed at periodic intervals by the ap-

plication software. The status register should be

read each time the RX FIFO interrupts are generat-

ed. At this time the error condition (i.e., overrun

flag) will indicate that an error has occurred but

cannot convey which byte contains the error. Writ-

ing to the SRXEOF register location clears the

overrun flag. TX FIFO underflow condition is de-

tected and conveyed via a bit in the SYSFLG2 reg-

ister, which is accessed by the application software.

A TX underflow error is cleared by writing data to

be transmitted to the TX FIFO.

DS453PP2

43

EP7209

terface is in use (PCMEN1 or PCMEN2 bits in the

SYSCON2 register are enabled). FBADDR should

never be programmed to 0x7 or 0x8, as these are

the locations for the on-chip Boot ROM and inter-

nal registers.

latency is the total number of cycles from when the

DMA request appears to when the first DMA data

word actually becomes available at the FIFO.

DMA has the highest priority, so it will always hap-

pen next in the system. The maximum number of

cycles required is 36 from the point at which the

DMA request occurs to the point at which the STM

is complete, then another 6 cycles before the data

actually arrives at the FIFO from the first DMA

read. This creates a total of 42 cycles. Assuming

the frame buffer is located in 32-bit wide, the worst

case latency is almost exactly 3.2 µs, with 13 MHz

page mode cycles. With each cycle consuming

~77 ns (i.e., 1/1 MHz), the value of 3.2 µs comes

from 42 cycles x 77 ns/cycle = ~3.23 µsec. If 16-bit

wide, then the worst case latency will double. In

this case, the maximum permissible display size

will be halved, to approx. 320 x 240 pixels, assum-

ing the same pixel depth and refresh rate has to be

maintained. If the frame buffer is to be stored in

static memory, then further calculations must be

performed. If 18 MHz mode is selected, and 32-bit

The screen is mapped to the video frame buffer as

one contiguous block where each horizontal line of

pixels is mapped to a set of consecutive bytes or

words in the video RAM. The video frame buffer

can be accessed word wide as pixel 0 is mapped to

the LSB in the buffer such that the pixels are ar-

ranged in a Little Endian manner.

The pixel bit rate, and hence the LCD refresh rate,

can be programmed from 18.432 MHz to 576 kHz

when operating in 18.432–73.728 MHz mode, or

13 MHz to 203 kHz when operating from a

13 MHz clock. The LCD controller is programmed

by writing to the LCD control register (LCDCON).

The LCDCON register should not be repro-

grammed while the LCD controller is enabled.

The LCD controller also contains two 32-bit palette

registers, which allow any 4-, 2-, or 1-bit pixel val- wide, then the worst case latency will be 2.26 µsec

ue to be mapped to any of the 15 gray scale values

available. The required DMA bandwidth to support

a ½ VGA panel displaying 4-bits-per-pixel data at

(i.e., 42 cycles x 54 nsec/cycle). If 36 MHz mode is

selected, and 32-bit wide, then the worst case laten-

cy drops down to 1.49 µs. This calculation is a little

an 80 Hz refresh rate is approximately more complex for 36 MHz mode of operation. The

6.2 Mbytes/sec. Assuming the frame buffer is

stored in a 32-bit wide the maximum theoretical

bandwidth available is 86 Mbytes/sec at

36.864 MHz, or 29.7 Mbytes/sec at 13 MHz.

total number of cycles = (12 x 4) + 7 = 55. Thus, 55

x 27 ns = ~1.49 µsec.

Figure 11 shows the organization of the video map

for all combinations of bits per pixel.

The LCD controller uses a nine stage 32-bit wide

FIFO to buffer display data. The LCD controller re-

quests new data when there are five words remain-

ing in the FIFO. This means that for a ½ VGA

display at 4-bits-per-pixel and 80 Hz refresh rate,

the maximum allowable DMA latency is approxi-

mately 3.25 µsec ((5 words x 8 bits/byte)/(640 x

240 x 4bpp x 80 Hz)) = 3.25 µsec). The worst-case

The refresh rate is not affected by the number of

bits per pixel; however the LCD controller fetches

twice the data per refresh for 4-bits-per-pixel com-

pared to 2-bits-per-pixel. The main reason for re-

ducing the number of bits per pixel is to reduce the

power consumption of the memory where the video

frame buffer is mapped.

44

DS453PP2

EP7209

timer counter under flows (i.e., reaches 0), it will

assert its appropriate interrupt. The timer counters

can be read at any time. The clock source and mode

are selectable by writing to various bits in the sys-

tem control register. When run from the internal

PLL, 512 kHz and 2 kHz rates are provided. When

using the 13 MHz external source, the default fre-

quencies will be 541 kHz and 2.115 kHz, respec-

tively. However, only in non-PLL mode, an

optional divide by 26 frequency can be generated

3.13 Timer Counters

Two identical timer counters are integrated into the

EP7209. These are referred to as TC1 and TC2.

Each timer counter has an associated 16-bit

read/write data register and some control bits in the

system control register. Each counter is loaded with

the value written to the data register immediately.

This value will then be decremented on the second

active clock edge to arrive after the write (i.e., after

the first complete period of the clock). When the

Pixel 1 Pixel 2 Pixel 3 Pixel 4

Gray scale

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

4 Bits per pixel

Pixel 1 Pixel 2 Pixel 3 Pixel 4

Gray scale Gray scale Gray scale Gray scale

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

2 Bits per pixel

Pixel 1 Pixel 2 Pixel 3 Pixel 4

Gray scale Gray scale Gray scale Gray scale

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

1 Bit per pixel

Figure 11. Video Buffer Mapping

DS453PP2

45

EP7209

(thus generating a 500 kHz frequency when using

the 13 MHz source). This divider is enabled by set-

read twice to ensure a valid and stable reading. This

also applies when reading back the RTCDIV field

ting the OSTB (Operating System Timing Bit) in of the SYSCON1 register, which reflects the status

the SYSCON2 register (bit 12). When this bit is set of the six LSBs of the RTC counter.

high to select the 500 kHz mode, the 500 kHz fre-

3.14.1 Characteristics of the Real Time

quency is routed to the timers instead of the

Clock Interface

541 kHz clock. This does not affect the frequencies

derived for any of the other internal peripherals.

When connecting a crystal to the RTC interface

pins (i.e., RTCIN and RTCOUT), the crystal and

circuit should conform to the following require-

ments:

The timer counters can operate in two modes: free

running or pre-scale.

3.13.1 Free Running Mode

•

The 32.768 kHz frequency should be created

by the crystals fundamental tone (i.e., it should

be a fundamental mode crystal)

In the free running mode, the counter will wrap

around to 0xFFFF when it under flows and it will

continue to count down. Any value written to TC1

or TC2 will be decremented on the second edge of

the selected clock.

•

A start-up resistor is not necessary, since one is

provided internally.

Start-up loading capacitors may be placed on

each side of the external crystal and ground.

Their value should be in the range of 10 pF.

However, their values should be selected based

upon the crystal specifications. The total sum of

the capacitance of the traces between the

EP7209’s clock pins, the capacitors, and the

crystal leads should be subtracted from the

crystal’s specifications when determining the

values for the loading capacitors.

3.13.2 Prescale Mode

In the prescale mode, the value written to TC1 or

TC2 is automatically re-loaded when the counter

under flows. Any value written to TC1 or TC2 will

be decremented on the second edge of the selected

clock. This mode can be used to produce a pro-

grammable frequency to drive the buzzer (i.e., with

TC1) or generate a periodic interrupt.

3.14 Real Time Clock

•

The crystal should have a maximum 5 ppm fre-

quency drift over the chip’s operating tempera-

ture range.

The EP7209 contains a 32-bit Real Time Clock

(RTC). This can be written to and read from in the

same way as the timer counters, but it is 32 bits

wide. The RTC is always clocked at 1 Hz, generat-

ed from the 32.768 kHz oscillator. It also contains

a 32-bit output match register, this can be pro-

grammed to generate an interrupt when the time in

the RTC matches a specific time written to this reg-

ister. The RTC can only be reset by an nPOR cold

reset. Because the RTC data register is updated

from the 1 Hz clock derived from the 32 kHz

source, which is asynchronous to the main memory

system clock, the data register should always be

Thevoltageforthecrystalmustbe2.5 V+0.2 V.

Alternatively, a digital clock source can be used to

drive the RTCIN pin of the EP7209. With this ap-

proach, the voltage levels of the clock source

should match that of the Vdd supply for the

EP7209’s pads (i.e., the supply voltage level used

to drive all of the non-Vdd core pins on the

EP7209) (i.e., RTCOUT). The output clock pin

should be left floating.

46

DS453PP2

EP7209

3.15 Dedicated LED Flasher

3.17 Boundary Scan

The LED flasher feature enables an external pin IEEE 1149.1 compliant JTAG is provided with the

(PD[0]/LEDFLSH) to be toggled at a programma- EP7209. Table 22 shows what instructions are sup-

ble rate and duty ratio, with the intention that the

external pin is connected to an LED. This module

is driven from the RTCs 32.768 kHz oscillator and

works in all running modes because no CPU inter-

vention is needed once its rate and duty ratio have

been configured (via the LEDFLSH register). The

LED flash rate period can be programmed for 1, 2,

3, or 4 seconds. The duty ratio can be programmed

such that the mark portion can be 1/16, 2/16, 3/16,

…, 16/16 of the full cycle. The external pin can

provide up to 4 mA of drive current.

ported in the EP7209.

Instruction

Code

Description

EXTEST

Places the selected

0000 scan chain in test

mode.

SCAN_N

Connects the Scan

Path Register between

TDI and TDO

0010

SAMPLE/PRELOAD

NOTE: This instruc-

tion is included for

product testing only

and should never be

used.

0011

3.16 Two PWM Interfaces

IDCODE

BYPASS

Connects the ID regis-

1110 ter between TDI and

TDO

Two Pulse Width Modulator (PWM) duty ratio

clock outputs are provided by the EP7209. When

the device is operating from the internal PLL, the

PWM will run at a frequency of 96 kHz. These sig-

nals are intended for use as drives for external DC-

to-DC converters in the Power Supply Unit (PSU)

subsystem. External input pins that would normally

be connected to the output from comparators mon-

itoring the external DC-to-DC converter output are

also used to enable these clocks. These are the

FB[0:1] pins. The duty ratio (and hence PWMs on

time) can be programmed from 1 in 16 to 15 in 16.

The sense of the PWM drive signal (active high or

low) is determined by latching the state of this

drive signal during power on reset (i.e., a pull-up on

the drive signal will result in a active low drive out-

put, and visa versa). This allows either positive or

negative voltages to be generated by the external

DC-to-DC converter. PWMs are disabled by writ-

ing zeros into the drive ratio fields in the PMPCON

Pump Control register.

Connects a 1-bit shift

register bit TDI and

TDO

1111

Table 22. Instructions Supported in JTAG Mode

The INTEST function will not be supported for the

EP7209.

Additional user-defined instructions exist, but

these are not relevant to board-level testing. For

further information please refer to the ARM DDI

0087E ARM720T Data Sheet.

As there are additional scan-chains within the

ARM720T processor, it is necessary to include a

scan-chain select function — shown as SCAN_N

in Table 22. To select a particular scan chain, this

function must be input to the TAP controller, fol-

lowed by the 4-bit scan-chain identification code.

The identification code for the boundary scan chain

is 0011.

NOTE:

To maximize power savings, the drive ratio

fields should be used to disable the PWMs,

instead of the FB pins. The clocks that

source the PWMs are disabled when the

drive ratio fields are zeroed.

Note that it is only necessary to issue the SCAN_N

instruction if the device is already in the JTAG

mode. The boundary scan chain is selected as the

DS453PP2

47

EP7209

default on test-logic reset and any of the system re-

sets.

by the ARM processor. Execution is halted when

either a match occurs between the values pro-

grammed into the ICEBreaker and the values cur-

rently appearing on the address bus, data bus, and

the various control signals. Any bit can be masked

to remove it from the comparison. Either unit can

be programmed as a watchpoint (monitoring data

accesses) or a breakpoint (monitoring instruction

fetches).

The contents of the device ID-register for the

EP7209 are shown in Table 23. This is equivalent

to 0x0F0F0F0F. Note this is the ID-code for the

ARM720T processor.

3.18 In-Circuit Emulation

3.18.1 Introduction

Using one of these watchpoint units, an unlimited

number of software breakpoints (in RAM) can be

supported by substitution of the actual code.

EmbeddedICE is an extension to the architecture of

the ARM family of processors, and provides the

ability to debug cores that are deeply embedded

into systems. It consists of three parts:

NOTE:

The EXTERN[1:0] signals from the ICE-

Breaker module are not wired out in this

device. This mechanism is used to allow

watchpoints to be dependent on an external

event. This behavior can be emulated in

software via the ICEBreaker control regis-

ters.

1) A set of extensions to the ARM core

2) The EmbeddedICE macrocell, to provide ac-

cess the extensions from the outside world

3) The EmbeddedICE interface to provide com-

munication from the EmbeddedICE macrocell

and the host computer

A more detailed description is available in the

ARM Software Development Toolkit User Guide

and Reference Manual. The ICEBreaker module

and its registers are fully described in the

ARM7TDMI Data Sheet.

The EmbeddedICE macrocell is programmed, in a

serial fashion, through the TAP controller on the

ARM via the JTAG interface. The EmbeddedICE

macrocell is by default disabled to minimize power

usage, and must be enabled at boot-up to support

this functionality.

3.19 Maximum EP7209-Based System

A maximum configured system using the EP7209

is shown in Figure 12. This system assumes the

ROMs are 16-bit wide devices. The keyboard may

be connected to more GPIO bits than shown to al-

low greater than 64 keys, however these extra pins

will not be wired into the WAKEUP pin function-

ality.

3.18.2 Functionality

The ICEBreaker module consists of two real-time

watchpoint units together with a control and status

register. One or both of the units can be pro-

grammed to halt the execution of the instructions

Version

Part number

Manufacturer ID

0

1

0

1

0

1

0

1

Table 23. Device ID Register

48

DS453PP2

EP7209

CRYSTAL

MOSCIN

RTCIN

DD[3:0]

CL1

CL2

FM

M

LCD

nCS[4]

PB0

EXPCLK

COL[7:0]

KEYBOARD

D[31:0]

A[27:0]

PA[7:0]

PB[7:0]

CL-PS6700

PC CARD

CONTROLLER

PC CARD

SOCKET

nMOE

WRITE

PD[7:0]

PE[2:0]

DC

INPUT

POWER

SUPPLY UNIT

AND

nPOR

nPWRFL

BATOK

COMPARATORS

nEXTPWR

nBATCHG

RUN

BATTERY

WAKEUP

DRIVE[1:0]

FB[1:0]

DC-TO-DC

CONVERTERS

nCS[0]

nCS[1]

DAISSI-

CLK

CODEC/SSI2/

DAI

×16

FLASH

×16

FLASH

SSITXFR

SSITXDA

SSIRXDA

×16

FLASH

×16

FLASH

IR LED AND

PHOTODIODE

LEDDRV

PHDIN

CS[n]

WORD

RXD1/2

TXD1/2

DSR

2× RS-232

TRANSCEIVERS

EXTERNAL MEMORY-

MAPPED EXPANSION

BUFFERS

CTS

DCD

ADCCLK

nADCCS

ADCOUT

ADCIN

NCS[2]

NCS[3]

ADC

DIGITIZER

BUFFERS

AND

LEDFLSH

ADDITIONAL I/O

SMPCLK

LATCHES

NOTE:

A system can only use one of the following

peripheral interfaces at any given time:

SSI2, codec, or DAI.

Figure 12. A Maximum EP7209 Based System

DS453PP2

49

EP7209

Table 24 shows how the 4-Gbyte address range of

the ARM720T processor (as configured within this

chip) is mapped in the EP7209. The memory map

shown assumes that two CL-PS6700 PC Card con-

trollers are connected. If this functionality is not re-

quired, then the nCS[4] and nCS[5] memory is

available. The external boot ROM is not fully de-

coded (i.e., the boot code will repeat within the

256-Mbyte space from 0x70000000 to

0x80000000). See Table 13 on page 29 for the

memory map when booted from on chip boot

ROM. The SRAM is fully decoded up to a maxi-

mum size of 128 kbytes. Access to any location

above this range will be wrapped to within the

range.

4. MEMORY MAP

The lower 2 GByte of the address space is allocated

to memory. The 2 GByte less 8 k for internal regis-

ters is not accessible in the EP7209. The MMU in

the EP7209 should be programmed to generate an

abort exception for access to this area.

Internal peripherals are addressed through a set of

internal memory locations from hex address

8000.0000 to 8000.3FFF. These are known as the

internal registers in the EP7209. In Table 24, the

memory map from 0x8000.000 to 0x8000.1FFF

contains registers that are compatible with the CL-

PS7111 (see Table 24). These were included for

backward compatibility and are referred to as old

internal registers.

Address

Contents

Reserved

Size

0xF000.0000

0xE000.0000

0xD000.0000

0xC000.0000

0x8000.4000

256 Mbytes

~1 Gbyte

Reserved

Unused

Internal registers (new)

0x8000.2000

0x8000.0000

8 kbytes

Internal registers (old)

(from 7111)

0x7000.0000

0x6000.0000

0x5000.0000

0x4000.0000

0x3000.0000

0x2000.0000

0x1000.0000

0x0000.0000

Boot ROM (nCS[7])

SRAM (nCS[6])

128 bytes

38,400 bytes

4 x 64 Mbytes

256 Mbytes

PCMCIA-1 (nCS[5])

PCMCIA-0 (nCS[4])

Expansion (nCS[3])

Expansion (nCS[2])

ROM Bank 1 (nCS[1])

ROM Bank 0 (nCS[0])

Table 24. EP7209 Memory Map in External Boot Mode

50

DS453PP2

EP7209

itly defined in the internal area are legal and will

have no effect. Reads from bits not explicitly de-

fined in the internal area are legal but will read un-

defined values. All the internal addresses should

only be accessed as 32-bit words and are always on

a word boundary, except for the PIO port registers,

which can be accessed as bytes. Address bits in the

range A[0:5] are not decoded (except for Ports

A–D), this means each internal register is valid for

64 bytes (i.e., the SYSFLG1 register appears at lo-

cations 0x8000.0140 to 0x8000.017C). There are

some gaps in the register map for backward com-

patibility reasons, but registers located next to a

gap are still only decoded for 64 bytes.

5. REGISTER DESCRIPTIONS

5.1 Internal Registers

Table 25 shows the Internal Registers of the

EP7209 that are compatible with the CL-PS7111

when the CPU is configured to a Little Endian

Memory System. Table 26 shows the differences

that occur when the CPU is configured to a Big En-

dian Memory System for byte-wide access to Ports

A, B, and D. All the internal registers are inherently

Little Endian (i.e., the least significant byte is at-

tached to bits 7 to 0 of the data bus). Hence, the sys-

tem Endianness affects the addresses required for

byte accesses to the internal registers, resulting in a

reversal of the byte address required to read/write a

particular byte within a register. Note that the inter-

nal registers have been split into two groups – the

“old” and the “new”. The old ones are the same as

that used in CL-PS7111 and are there for compati-

bility. The new registers are for accessing the addi-

tional functionality of the DAI interface and the

LED flasher.

The GPIO port registers are byte-wide and can be

accessed as a word but not as a half-word. These

registers additionally decode A[0:1]. All addresses

are in hexadecimal notation.

NOTE:

All byte-wide registers should be accessed

as words (except Port A to Port D registers,

which are designed to work in both word and

byte modes).

All registers bit alignment starts from the

LSB of the register (i.e., they are all right shift

justified).

There is no effect on the register addresses for word

accesses. Bits A[0:1] of the internal address bus are

only decoded for Ports A, B, and D (to allow

read/write to individual ports). For all other regis-

ters, bits A[0:1] are not decoded, so that byte reads

will return the whole register contents onto the

EP7209’s internal bus, from where the appropriate

byte (according to the Endianness) will be read by

the CPU. To avoid the additional complexity, it is

preferable to perform all internal register accesses

as word operations, except for ports A to D which

are explicitly designed to operate with byte access-

es, as well as with word accesses.

The registers which interact with the 32 kHz

clock or which could change during read-

back (i.e., RTC data registers, SYSFLG1

register (lower 6-bits only), the TC1D and

TC2D data registers, port registers, and

interrupt status registers), should be read

twice and compared to ensure that a stable

value has been read back.

All internal registers in the EP7209 are reset

(cleared to zero) by a system reset (i.e., nPOR,

nRESET, or nPWRFL signals becoming active),

and the Real Time Clock data register (RTCDR)

and match register (RTCMR), which are only reset

by nPOR becoming active. This ensures that the

system time preserved through a user reset or pow-

er fail condition. In the following register descrip-

tions, Little Endian is assumed.

An 8 k segment of memory in the range

0x8000.0000 to 0x8000.3FFF is reserved for inter-

nal use in the EP7209. Accesses in this range will

not cause any external bus activity unless debug

mode is enabled. Writes to bits that are not explic-

DS453PP2

51

EP7209

Address

Name

PADR

Default

RD/WR

RW

—

Size

8

Comments

Port A data register

0x8000.0000

0x8000.0001

0x8000.0002

0x8000.0003

0x8000.0040

0x8000.0041

0x8000.0042

0x8000.0043

0x8000.0080

0x8000.00C0

0x8000.0100

0x8000.0140

0x8000.0180

0x8000.01C0

0x8000.0240

0x8000.0280

0x8000.02C0

0

PBDR

8

Port B data register

—

8

Reserved

PDDR

0

RW

—

8

Port D data register

PADDR

PBDDR

—

8

Port A data direction register

Port B data direction register

Reserved

8

PDDDR

PEDR

0

RW

RD

8

Port D data direction register

Port E data register

3

PEDDR

SYSCON1

SYSFLG1

MEMCFG1

MEMCFG2

INTSR1

INTMR1

LCDCON

3

Port E data direction register

System control register 1

System status flags register 1

32

RW

RD

Expansion memory configuration register 1

Expansion memory configuration register 2

Interrupt status register 1

RW

Interrupt mask register 1

LCD control register

Read/Write register sets and reads data to

TC1

0x8000.0300

0x8000.0340

TC1D

TC2D

0

RW

16

Read/Write register sets and reads data to

TC2

0x8000.0380

0x8000.03C0

0x8000.0400

0x8000.0440

0x8000.0480

0x8000.04C0

RTCDR

RTCMR

—

0

RW

32

12

8

Real Time Clock data register

Real Time Clock match register

PWM pump control register

CODEC data I/O register

PMPCON

CODR

0

UARTDR1

UBLCR1

0

16

32

UART1 FIFO data register

0

UART1 bit rate and line control register

Synchronous serial I/O data register for mas-

ter only SSI

0x8000.0500

0x8000.0540

0x8000.0580

SYNCIO

PALLSW

PALMSW

0

RW

32

Least significant 32-bit word of LCD palette

register

Most significant 32-bit word of LCD palette

register

0x8000.05C0

0x8000.0600

0x8000.0640

0x8000.0680

0x8000.06C0

STFCLR

BLEOI

MCEOI

TEOI

—

WR

—

Write to clear all start up reason flags

Write to clear battery low interrupt

Write to clear media changed interrupt

Write to clear tick and watchdog interrupt

Write to clear TC1 interrupt

TC1EOI

Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode)

52

DS453PP2

EP7209

Address

0x8000.0700

0x8000.0740

Name

TC2EOI

RTCEOI

Default

RD/WR

WR

Size

—

Comments

—

Write to clear TC2 interrupt

WR

—

Write to clear RTC match interrupt

Write to clear UART modem status changed

interrupt

0x8000.0780

UMSEOI

—

WR

—

0x8000.07C0

0x8000.0800

0x8000.0840

COEOI

HALT

—

WR

—

Write to clear CODEC sound interrupt

Write to enter the Idle State

STDBY

Write to enter the Standby State

Write will have no effect, read is undefined

0x8000.0880–

0x8000.0FFF

Reserved

0x8000.1000

0x8000.1100

0x8000.1140

0x8000.1240

0x8000.1280

FBADDR

SYSCON2

SYSFLG2

INTSR2

0xC

0

RW

RD

RW

4

LCD frame buffer start address

System control register 2

16

24

16

0

System status register 2

0

Interrupt status register 2

INTMR2

0

Interrupt mask register 2

0x8000.12C0–

0x8000.147F

Write will have no effect, read is undefined

Reserved

0x8000.1480

0x8000.14C0

0x8000.1500

0x8000.1600

0x8000.16C0

0x8000.1700

UARTDR2

UBLCR2

SS2DR

0

RW

WR

16

32

16

—

UART2 Data Register

UART2 bit rate and line control register

Master/slave SSI2 data Register

Write to clear RX FIFO overflow flag

Write to pop SSI2 residual byte into RX FIFO

Write to clear keyboard interrupt

0

SRXEOF

SS2POP

KBDEOI

—

Do not write to this location. A write will

cause the processor to go into an unsup-

ported power savings state.

0x8000.1800

Reserved

—

WR

—

0x8000.1840–

0x8000.1FFF

Write will have no effect, read is undefined

Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode) (cont.)

DS453PP2

53

EP7209

Big Endian Mode

0x8000.0003

0x8000.0002

0x8000.0001

0x8000.0000

0x8000.0043

0x8000.0042

0x8000.0041

0x8000.0040

0x0000.0080

0X8000.0000

Name

PADR

PBDR

—

Default

RD/WR

RW

—

Size

Comments

Port A Data Register

0

8

3

Port B Data Register

Reserved

PDDR

PADDR

PBDDR

—

0

RW

—

Port D Data Register

Port A data Direction Register

Port B Data Direction Register

Reserved

PDDDR

PEDR

PEDDR

0

RW

Port D Data Direction Register

Port E Data Register

Port E Data Direction Register

Table 26. EP7209 Internal Registers (Big Endian Mode)

NOTE:

The following Register Descriptions refer to Little Endian Mode Only

5.1.1

PADR Port A Data Register

ADDRESS: 0x8000.0000

Values written to this 8-bit read/write register will be output on Port A pins if the corresponding data

direction bits are set high (port output). Values read from this register reflect the external state of Port

A, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.2

PBDR Port B Data Register

ADDRESS: 0x8000.0001

Values written to this 8-bit read/write register will be output on Port B pins if the corresponding data

direction bits are set high (port output). Values read from this register reflect the external state of Port

B, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.3

PDDR Port D Data Register

ADDRESS: 0x8000.0003

Values written to this 8-bit read/write register will be output on Port D pins if the corresponding data

direction bits are set low (port output). Values read from this register reflect the external state of Port

D, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.4

PADDR Port A Data Direction Register

ADDRESS: 0x8000.0040

Bits set in this 8-bit read/write register will select the corresponding pin in Port A to become an output,

clearing a bit sets the pin to input. All bits are cleared by a system reset.

5.1.5

PBDDR Port B Data Direction Register

ADDRESS: 0x8000.0041

Bits set in this 8-bit read/write register will select the corresponding pin in Port B to become an output,

clearing a bit sets the pin to input. All bits are cleared by a system reset.

54

DS453PP2

EP7209

5.1.6

PDDDR Port D Data Direction Register

ADDRESS: 0x8000.0043

Bits cleared in this 8-bit read/write register will select the corresponding pin in Port D to become an

output, setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output

by default.

5.1.7

PEDR Port E Data Register

ADDRESS: 0x8000.0080

Values written to this 3-bit read/write register will be output on Port E pins if the corresponding data

direction bits are set high (port output). Values read from this register reflect the external state of Port

E, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.8

PEDDR Port E Data Direction Register

ADDRESS: 0x8000.00C0

Bits set in this 3-bit read/write register will select the corresponding pin in Port E to become an output,

clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default.

DS453PP2

55

EP7209

5.2

SYSTEM Control Registers

5.2.1

SYSCON1 The System Control Register 1

ADDRESS: 0x8000.0100

23

22

21

20

IRTXM

12

19

WAKEDIS

15

SIREN

7

14

CDENRX

6

13

CDENTX

5

11

DBGEN

3:0

LCDEN

4

TC2S

TC2M

TC1S

TC1M

Keyboard scan

The system control register is a 21-bit read/write register which controls all the general configuration

of the EP7209, as well as modes etc. for peripheral devices. All bits in this register are cleared by a

system reset. The bits in the system control register SYSCON1 are defined in Table 27.

Bit

Description

0:3

Keyboard scan: This 4-bit field defines the state of the keyboard column drives. The following

table defines these states.

Keyboard Scan

Column

0

1

All driven high

All driven low

2–7

8

All high impedance (tristate)

Column 0 only driven high all others high impedance

Column 1 only driven high all others high impedance

Column 2 only driven high all others high impedance

Column 3 only driven high all others high impedance

Column 4 only driven high all others high impedance

Column 5 only driven high all others high impedance

Column 6 only driven high all others high impedance

Column 7 only driven high all others high impedance

9

10

11

12

13

14

15

4

5

6

7

8

TC1M: Timer counter 1 mode. Setting this bit sets TC1 to prescale mode, clearing it sets free run-

ning mode.

TC1S: Timer counter 1 clock source. Setting this bit sets the TC1 clock source to 512 kHz, clear-

ing it sets the clock source to 2 kHz.

TC2M: Timer counter 2 mode. Setting this bit sets TC2 to prescale mode, clearing it sets free run-

ning mode.

TC2S: Timer counter 2 clock source. Setting this bit sets the TC2 clock source to 512 kHz, clear-

ing it sets the clock source to 2 kHz.

UART1EN: Internal UART enable bit. Setting this bit enables the internal UART.

Table 27. SYSCON1

56

DS453PP2

EP7209

Bit

Description

9

BZTOG: Bit to drive (i.e., toggle) the buzzer output directly when software mode of operation is

selected (i.e., bit BZMOD = 0). See the BZMOD and BUZFREQ (SYSCON1) bits for more

details.

10

BZMOD: This bit selects the buzzer drive mode. When BZMOD = 0, the buzzer drive output pin

is connected directly to the BZTOG bit. This is the software mode. When BZMOD = 1, the buzzer

drive is in the hardware mode. Two hardware sources are available to drive the pin. They are the

TC1 or a fixed internally generated clock source. The selection of which source is used to drive

the pin is determined by the state of the BUZFREQ bit in the SYSCON2 register. If the TC1 is

selected, then the buzzer output pin is connected to the TC1 under flow bit. The buzzer output

pin changes every time the timer wraps around. The frequency depends on what was pro-

grammed into the timer. See the description of the BUZFREQ and BZTOG bits (SYSCON2) for

more details.

11

DBGEN: Setting this bit will enable the debug mode. In this mode, all internal accesses are out-

put as if they were reads or writes to the expansion memory addressed by nCS5. nCS5 will still

be active in its standard address range. In addition the internal interrupt request and fast interrupt

request signals to the ARM720T processor are output on Port E, bits 1 and 2. Note that these bits

must be programmed to be outputs before this functionality can be observed. The clock to the

CPU is output on Port E, Bit 0 to enable individual accesses to be distinguished. For example, in

debug mode:

nCS5 = nCS5 or internal I/O strobe

PE0 = CLK

PE1 = nIRQ

PE2 =nFIQ

12

13

LCDEN: LCD enable bit. Setting this bit enables the LCD controller.

CDENTX: Codec interface enable TX bit. Setting this bit enables the codec interface for data

transmission to an external codec device.

14

CDENRX: Codec interface enable RX bit. Setting this bit enables the codec interface for data

reception from an external codec device.

NOTE: Both CDENRX and CDENTX need to be enabled/disabled in tandem, otherwise data may

be lost.

15

SIREN: HP SIR protocol encoding enable bit. This bit will have no effect if the UART is not

enabled.

16:17

ADCKSEL: Microwire / SPI peripheral clock speed select. This two bit field selects the frequency

of the ADC sample clock; this is twice the frequency of the synchronous serial ADC interface

clock. The table below shows the available frequencies for operation when in PLL mode. These

bits are also used to select the shift clock frequency for the SSI2 interface when set into master

mode. The frequencies obtained in 13.0 MHz mode can be found in Table 21.

ADCKSEL

ADC Sample Frequency

ADC Clock Frequency

(kHz) — SMPCLK

(kHz) — ADCCLK

00

01

10

11

8

4

32

16

128

256

64

128

Table 27. SYSCON1 (cont.)

DS453PP2

57

EP7209

Bit

Description

18

EXCKEN: External expansion clock enable. If this bit is set, the EXPCLK is enabled continu-

ously; it is the same speed and phase as the CPU clock and will free run all the time the main

oscillator is running if this bit is set. This bit should not be left set all the time for power consump-

tion reasons. If the system enters the Standby State, the EXPCLK will become undefined. If this

bit is clear, EXPCLK will be active during memory cycles to expansion slots that have external

wait state generation enabled only.

19

20

WAKEDIS: Setting this bit disables waking up from the Standby State, via the wakeup input.

IRTXM: IrDA TX mode bit. This bit controls the IrDA encoding strategy. Clearing this bit means

each zero bit transmitted is represented as a pulse of width 3/16th of the bit rate period. Setting

this bit means each zero bit is represented as a pulse of width 3/16th of the period of 115,200-bit

rate clock (i.e., 1.6 µsec regardless of the selected bit rate). Setting this bit will use less power,

but will probably reduce transmission distances.

Table 27. SYSCON1 (cont.)

58

DS453PP2

EP7209

5.2.2

SYSCON2 System Control Register 2

ADDRESS: 0x8000.1100

15

Reserved

7

14

BUZFREQ

6

13

CLKENSL

5

12

OSTB

4

11:10

9

SS2MAEN

1

8

Reserved

UART2EN

0

3

2

SS2RXEN

PC CARD2

PC CARD1

SS2TXEN

KBWEN

Reserved

KBD6

SERSEL

This register is an extension of SYSCON1, containing additional control for the EP7209, for compat-

ibility with CL-PS7111. The bits of this second system control register are defined below. The

SYSCON2 register is reset to all 0s on power up.

Bit

Description

0

SERSEL:The only affect of this bit is to select either SSI2 or the codec to interface to the external

pins. See the table below for the selection options.

NOTE: If the DAISEL bit of SYSCON3 is set, then it overrides the state of the SERSEL

bit, and thus the external pins are connected to the DAI interface.

SERSEL Value

Selected Serial Device to

External Pins

0

1

Master/slave SSI2

Codec

1

3

KBD6: The state of this bit determines how many of the Port A inputs are OR’ed together to cre-

ate the keyboard interrupt. When zero (the reset state), all eight of the Port A inputs will generate

a keyboard interrupt. When set high, only Port A bits 0 to 5 will generate an interrupt from the

keyboard. It is assumed that the keyboard row lines are connected into Port A.

KBWEN: When the KBWEN bit is high, the EP7209 will awaken from a power saving state into

the Operating State when a high signal is on one of Port A’s inputs (irrespective of the state of the

interrupt mask register). This is called the Keyboard Direct Wakeup mode. In this mode, the inter-

rupt request does not have to get serviced. If the interrupt is masked (i.e., the interrupt mask reg-

ister 2 (INTMR2) bit 0 is low), the processor simply starts re-executing code from where it left off

before it entered the power saving state. If the interrupt is non-masked, then the processor will

service the interrupt.

4

5

SS2TXEN: Transmit enable for the synchronous serial interface 2. The transmit side of SSI2 will

be disabled until this bit is set. When set low, this bit also disables the SSICLK pin (to save

power) in master mode, if the receive side is low.

PC CARD1: Enable for the interface to the CL-PS6700 device for PC Card slot 1. The main effect

of this bit is to reassign the functionality of Port B, bit 0 to the PRDY input from the CL-PS6700

devices, and to ensure that any access to the nCS4 address space will be according to the

CL-PS6700 interface protocol.

6

PC CARD2: Enable for the interface to the CL-PS6700 device for PC Card slot 2. The main effect

of this bit is to reassign the functionality of Port B, bit 1 to the PRDY input from the CL-PS6700

devices, and to ensure that any access to the nCS5 address space will be according to the

CL-PS6700 interface protocol.

Table 28. SYSCON2

DS453PP2

59

EP7209

Bit

Description

7

SS2RXEN: Receive enable for the synchronous serial interface 2. The receive side of SSI2 will

be disabled until this bit is set. When both SSI2TXEN and SSI2RXEN are disabled, the SSI2

interface will be in a power saving state.

8

9

UART2EN: Internal UART2 enable bit. Setting this bit enables the internal UART2.

SS2MAEN: Master mode enable for the synchronous serial interface 2. When low, SSI2 will be

configured for slave mode operation. When high, SSI2 will be configured for master mode opera-

tion. This bit also controls the directionality of the interface pins.

12

OSTB: This bit (operating system timing bit) is for use only with the 13 MHz clock source mode.

Normally it will be set low, however when set high it will cause a 500 kHz clock to be generated

for the timers instead of the 541 kHz which would normally be available. The divider to generate

this frequency is not clocked when this bit is set low.

13

14

CLKENSL: CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin.

When high, the RUN signal will be output on RUN/CLKEN.

BUZFREQ: The BUZFREQ bit is used to select which hardware source will be used as the

source to drive the buzzer output pin. When BUZFREQ = 0, the buzzer signal generated from the

on-chip timer (TC1) is output. When BUZFREQ = 1, a fixed frequency clock is output (500 Hz

when running from the PLL, 528 Hz in the 13 MHz external clock mode). See the BZMOD and

the BZTOG bits (SYSCON2) for more details.

Table 28. SYSCON2 (cont.)

60

DS453PP2

EP7209

5.2.3

SYSCON3 System Control Register 3

ADDRESS: 0x8000eeg.2200

15

Reserved

7

14

Reserved

6

13

Reserved

5

12

Reserved

4

11

Reserved

3

10

Reserved

2

9

DAIEN

1

8

FASTWAKE

0

VERSN[2]

Reserved

VERSN[1]

Reserved

VERSN[0]

Reserved

ADCCKNSEN

DAISEL

CLKCTL1

CLKCTL0

ADCCON

This register is an extension of SYSCON1 and SYSCON2, containing additional control for the

EP7209. The bits of this third system control register are defined in Table 29.

Bit

Description

0

ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be

used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte

SYNCIO(7:0) only is used for compatibility with the CL-PS7111. When this bit = 1, the ADC Con-

figuration Extension field in the SYNCIO register is used for ADC Configuration data and the

value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit).

1:2

CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling.

The table below lists the available options.

CLKCTL(1:0)

Value

Processor

Frequency

Memory Bus

Frequency

Wait State

Scaling

00

01

10

11

18.432 MHz

36.864 MHz

49.152 MHz

73.728 MHz

18.432 MHz

36.864 MHz

1

2

NOTE:

To determine the number of wait states programmed refer to Table 36 and Table 37.

When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from the

default value of ‘00’. Under no circumstances should the CLKCTL bits be changed

using a buffered write.

3

4

DAIPSEL: When set selects the DAI Interface. This defaults to either the SSI (i.e., DAISEL bit is

low).

ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the

ADCCLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the

opposite edges are used.

5:7

8

VERSN[0:2]: Additional read-only version bits — will read ‘000’.

FASTWAKE: When set, the device will wake from the Standby State within one to two cycles of a

4 kHz clock. This bit is cleared at power up, and thus the device first starts using the default one

to two cycles of the 8 Hz clock.

9

DAIEN: This bit enables the Digital Audio Interface when set (i.e., when DAIEN is high).

Table 29. SYSCON3

DS453PP2

61

EP7209

5.2.4

SYSFLG1 — The System Status Flags Register

ADDRESS: 0x8000.0140

31:30

VERID

23

29

ID

28

BOOTBIT1

21:16

27

BOOTBIT0

23

26

SSIBUSY

22

URXFE1

11

UTXFF1

15

URXFE1

14

RTCDIV

13

UTXFF1

12

CLDFLG

7:4

PFFLG

3

RSTFLG

2

NBFLG

1

UBUSY1

0

DID

WUON

WUDR

DCDET

MCDR

The system status flags register is a 32-bit read only register, which indicates various system infor-

mation. The bits in the system status flags register SYSFLG1 are defined in Table 30.

Bit

Description

0

1

MCDR: Media changed direct read. This bit reflects the INVERTED non-latched status of the

media changed input.

DCDET: This bit will be set if a non-battery operated power supply is powering the system (it is

the inverted state of the nEXTPWR input pin).

2

3

WUDR: Wake up direct read. This bit reflects the non-latched state of the wakeup signal.

WUON: This bit will be set if the system has been brought out of the Standby State by a rising

edge on the wakeup signal. It is cleared by a system reset or by writing to the HALT or STDBY

locations.

4:7

DID: Display ID nibble. This 4-bit nibble reflects the latched state of the four LCD data lines. The

state of the four LCD data lines is latched by the LCDEN bit, and so it will always reflect the last

state of these lines before the LCD controller was enabled. These bits identify the LCD display

panel fitted.

8

CTS: This bit reflects the current status of the clear to send (CTS) modem control input to

UART1.

9

DSR: This bit reflects the current status of the data set ready (DSR) modem control input to

UART1.

10

11

12

13

14

DCD: This bit reflects the current status of the data carrier detect (DCD) modem control input to

UART1.

UBUSY1: UART1 transmitter busy. This bit is set while UART1 is busy transmitting data, it is

guaranteed to remain set until the complete byte has been sent, including all stop bits.

NBFLG: New battery flag. This bit will be set if a low to high transition has occurred on the

nBATCHG input, it is cleared by writing to the STFCLR location.

RSTFLG: Reset flag. This bit will be set if the RESET button has been pressed, forcing the

nURESET input low. It is cleared by writing to the STFCLR location.

PFFLG: Power Fail Flag. This bit will be set if the system has been reset by the nPWRFL input

pin, it is cleared by writing to the STFCLR location.

Table 30. SYSFLG

62

DS453PP2

EP7209

Bit

Description

15

CLDFLG: Cold start flag. This bit will be set if the EP7209 has been reset with a power on reset,

it is cleared by writing to the STFCLR location.

16:21

RTCDIV: This 6-bit field reflects the number of 64 Hz ticks that have passed since the last incre-

ment of the RTC. It is the output of the divide by 64 chain that divides the 64 Hz tick clock down

to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output.

22

23

URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the RX holding register is empty. If the FIFO is enabled the URXFE bit will be set when the

RX FIFO is empty.

UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART1 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the TX holding register is full. If the FIFO is enabled the UTXFF bit will be set when the TX

FIFO is full.

24

25

26

CRXFE: Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty.

CTXFF: Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full.

SSIBUSY: Synchronous serial interface busy bit. This bit will be set while data is being shifted in

or out of the synchronous serial interface, when clear data is valid to read.

27:28

BOOTBIT0–1: These bits indicate the default (power-on reset) bus width of the ROM interface.

See Memory Configuration Registers for more details on the ROM interface bus width. The state

of these bits reflect the state of Port E[0:1] during power on reset, as shown in the table below.

PE[1]

PE[0]

Boot option

(BOOTBIT1)

(BOOTBIT0)

0

1

0

1

0

1

32-bit

8-bit

16-bit

Reserved

29

ID: Will always read ‘1’ for the EP7209 device.

30:31

VERID: Version ID bits. These 2 bits determine the version id for the EP7209. Will read ‘10’ for

the initial version.

Table 30. SYSFLG (cont.)

DS453PP2

63

EP7209

5.2.5

SYSFLG2 System Status Register 2

ADDRESS: 0x8000.1140

23

UTXFF2

5

22

URXFE2

4

21:12

Reserved

3

11

UBUSY2

2

10:7

Reserved

1

6

CKMODE

0

SS2TXUF

SS2TXFF

SS2RXFE

RESFRM

RESVAL

SS2RXOF

This register is an extension of SYSFLG1, containing status bits for backward compatibility with CL-

PS7111. The bits of the second system status register are defined in Table 31.

Bit

Description

0

SS2RXOF: Master/slave SSI2 RX FIFO overflow. This bit is set when a write is attempted to a full

RX FIFO (i.e., when RX is still receiving data and the FIFO is full). This can be cleared in one of

two ways:

1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.

2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock

cycle after it is disabled)

1

2

3

4

5

6

RESVAL: Master/slave SSI2 RX FIFO residual byte present, cleared by popping the residual

byte into the SSI2 RX FIFO or by a new RX frame sync pulse.

RESFRM: Master/slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame

sync pulse.

SS2RXFE: Master/slave SSI2 RX FIFO empty bit. This will be set if the 16 x 16 RX FIFO is

empty.

SS2TXFF: Master/slave SSI2 TX FIFO full bit. This will be set if the 16 x 16 TX FIFO is full. This

will get cleared when data is removed from the FIFO or the EP7209 is reset.

SS2TXUF: Master/slave SSI2 TX FIFO Underflow bit. This will be set if there is attempt to trans-

mit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data.

CKMODE: This bit reflects the status of the CLKSEL (PE[2]) input, latched during nPOR. When

low, the PLL is running and the chip is operating in 18.432–73.728 MHz mode. When high the

chip is operating from an external 13 MHz clock.

11

22

UBUSY2: UART2 transmitter busy. This bit is set while UART2 is busy transmitting data; it is

guaranteed to remain set until the complete byte has been sent, including all stop bits.

URXFE2: UART2 receiver FIFO empty. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the RX holding register contains is empty. If the FIFO is enabled the URXFE bit will be set

when the RX FIFO is empty.

23

UTXFF2: UART2 transmit FIFO full. The meaning of this bit depends on the state of the UFI-

FOEN bit in the UART2 bit rate and line control register. If the FIFO is disabled, this bit will be set

when the TX holding register is full. If the FIFO is enabled the UTXFF bit will be set when the TX

FIFO is full.

Table 31. SYSFLG2

64

DS453PP2

EP7209

5.3

Interrupt Registers

5.3.1

INTSR1 Interrupt Status Register 1

ADDRESS: 0x8000.0240

15

SSEOTI

7

14

UMSINT

6

13

URXINT1

5

12

UTXINT1

4

11

TINT

3

10

RTCMI

2

9

8

TC2OI

1

TC1OI

0

EINT3

EINT2

EINT1

CSINT

MCINT

WEINT

BLINT

EXTFIQ

The interrupt status register is a 32-bit read only register. The interrupt status register reflects the cur-

rent state of the first 16 interrupt sources within the EP7209. Each bit is set if the appropriate interrupt

is active. The interrupt assignment is given in Table 32.

Bit

Description

0

1

EXTFIQ: External fast interrupt. This interrupt will be active if the nEXTFIQ input pin is forced low

and is mapped to the FIQ input on the ARM720T processor.

BLINT: Battery low interrupt. This interrupt will be active if no external supply is present (nEXT-

PWR is high) and the battery OK input pin BATOK is forced low. This interrupt is de-glitched with

a 16 kHz clock, so it will only generate an interrupt if it is active for longer than 125 µsec. It is

mapped to the FIQ input on the ARM720T processor and is cleared by writing to the BLEOI loca-

tion.

NOTE:

BLINT is disabled during the Standby State.

2

3

WEINT: Tick Watch dog expired interrupt. This interrupt will become active on a rising edge of the

periodic 64 Hz tick interrupt clock if the tick interrupt is still active (i.e., if a tick interrupt has not

been serviced for a complete tick period). It is mapped to the FIQ input on the ARM720T proces-

sor and the TEOI location

NOTE:

WEINT is disabled during the Standby State.

Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728–18.432 MHz modes).

Watchdog timer is turned off during the Standby State.

MCINT: Media changed interrupt. This interrupt will be active after a rising edge on the nMED-

CHG input pin has been detected, This input is de-glitched with a 16 kHz clock so it will only gen-

erate an interrupt if it is active for longer than 125 µsec. It is mapped to the FIQ input on the

ARM7TDMI processor and is cleared by writing to the MCEOI location. On power-up, the Media

change pin (nMEDCHG) is used as an input to force the processor to either boot from the internal

Boot ROM, or from external memory. After power-up, the pin can be used as a general purpose

FIQ interrupt pin.

4

5

6

7

CSINT: Codec sound interrupt, generated when the data FIFO has reached half full or empty

(depending on the interface direction). It is cleared by writing to the COEOI location.

EINT1: External interrupt input 1. This interrupt will be active if the nEINT1 input is active (low) it

is cleared by returning nEINT1 to the passive (high) state.

EINT2: External interrupt input 2. This interrupt will be active if the nEINT2 input is active (low) it

is cleared by returning nEINT2 to the passive (high) state.

EINT3: External interrupt input 3. This interrupt will be active if the EINT3 input is active (high) it

is cleared by returning EINT3 to the passive (low) state.

Table 32. INTSR1

DS453PP2

65

EP7209

Bit

Description

8

TC1OI: TC1 under flow interrupt. This interrupt becomes active on the next falling edge of the

timer counter 1 clock after the timer counter has under flowed (reached zero). It is cleared by

writing to the TC1EOI location.

9

TC2OI: TC2 under flow interrupt. This interrupt becomes active on the next falling edge of the

timer counter 2 clock after the timer counter has under flowed (reached zero). It is cleared by

writing to the TC2EOI location.

10

RTCMI: RTC compare match interrupt. This interrupt becomes active on the next rising edge of

the 1 Hz Real Time Clock (one second later) after the 32-bit time written to the Real Time Clock

match register exactly matches the current time in the RTC. It is cleared by writing to the RTCEOI

location.

11

12

TINT: 64 Hz tick interrupt. This interrupt becomes active on every rising edge of the internal

64 Hz clock signal. This 64 Hz clock is derived from the 15-stage ripple counter that divides the

32.768 kHz oscillator input down to 1 Hz for the Real Time Clock. This interrupt is cleared by writ-

ing to the TEOI location.

NOTE:

TINT is disabled/turned off during the Standby State.

UTXINT1: Internal UART1 transmit FIFO half-empty interrupt. The function of this interrupt

source depends on whether the UART1 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is

clear in the UART1 bit rate and line control register), this interrupt will be active when there is no

data in the UART1 TX data holding register and be cleared by writing to the UART1 data register.

If the FIFO is enabled this interrupt will be active when the UART1 TX FIFO is half or more empty,

and is cleared by filling the FIFO to at least half full.

13

URXINT1: Internal UART1 receive FIFO half full interrupt. The function of this interrupt source

depends on whether the UART1 FIFO is enabled. If the FIFO is disabled this interrupt will be

active when there is valid RX data in the UART1 RX data holding register and be cleared by

reading this data. If the FIFO is enabled this interrupt will be active when the UART1 RX FIFO is

half or more full or if the FIFO is non empty and no more characters have been received for a

three character time out period. It is cleared by reading all the data from the RX FIFO.

14

15

UMSINT: Internal UART1 modem status changed interrupt. This interrupt will be active if either of

the two modem status lines (CTS or DSR) change state. It is cleared by writing to the UMSEOI

location.

SSEOTI: Synchronous serial interface end of transfer interrupt. This interrupt will be active after a

complete data transfer to and from the external ADC has been completed. It is cleared by read-

ing the ADC data from the SYNCIO register.

Table 32. INTSR1 (cont.)

66

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EP7209

5.3.2

INTMR1 Interrupt Mask Register 1

ADDRESS: 0x8000.0280

15

SSEOTI

7

14

UMSINT

6

13

URXINT

5

12

UTXINT

4

11

TINT

3

10

RTCMI

2

9

8

TC2OI

1

TC1OI

0

EINT3

EINT2

EINT1

CSINT

MCINT

WEINT

BLINT

EXTFIQ

This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of

the first 16 interrupt sources within the EP7209. The four shaded interrupts all generate a fast interrupt

request to the ARM720T processor (FIQ), this will cause a jump to processor virtual address

0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will cause a

jump to processor virtual address 0000.00018. Setting the appropriate bit in this register enables the

corresponding interrupt. All bits are cleared by a system reset. Please refer to INTSR1 Interrupt Sta-

tus Register 1 for individual bit details.

5.3.3

INTSR2 Interrupt Status Register 2

ADDRESS: 0x8000.1240

15:14

13

URXINT2

12

11:3

2

1

0

Reserved

UTXINT2

Reserved

SS2TX

SS2RX

KBDINT

This register is an extension of INTSR1, containing status bits for backward compatibility with CL-

PS7111. The interrupt status register also reflects the current state of the new interrupt sources within

the EP7209. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in

Table 33.

Bit

Description

0

KBDINT: Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the log-

ical OR of the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the

SYSCON2 register. The interrupt request is latched, and can be de-asserted by writing to the

KBDEOI location.

NOTE:

KBDINT is not deglitched.

1

2

SS2RX: Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is gener-

ated when RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX

FIFO is emptied or one SSI2 clock after RX is disabled.

SS2TX: Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is gen-

erated when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the

FIFO with more data or disabling the TX. One synchronization clock required when disabling the

TX side before it takes effect.

12

UTXINT2: UART2 transmit FIFO half empty interrupt. The function of this interrupt source

depends on whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in

the UART2 bit rate and line control register), this interrupt will be active when there is no data in

the UART2 TX data holding register and be cleared by writing to the UART2 data register. If the

FIFO is enabled this interrupt will be active when the UART2 TX FIFO is half or more empty, and

is cleared by filling the FIFO to at least half full.

DS453PP2

67

EP7209

Bit

Description

13

URXINT2: UART2 receive FIFO half full interrupt. The function of this interrupt source depends

on whether the UART2 FIFO is enabled. If the FIFO is disabled this interrupt will be active when

there is valid RX data in the UART2 RX data holding register and be cleared by reading this data.

If the FIFO is enabled this interrupt will be active when the UART2 RX FIFO is half or more full or

if the FIFO is non empty and no more characters have been received for a three character time

out period. It is cleared by reading all the data from the RX FIFO.

Table 33. INSTR2 (cont.)

5.3.4

INTMR2 Interrupt Mask Register 2

ADDRESS: 0x8000.1280

15:14

13

URXINT2

12

11:3

2

1

0

Reserved

UTXINT2

Reserved

SS2TX

SS2RX

KBDINT

This register is an extension of INTMR1, containing interrupt mask bits for the backward compatibility

with the CL-PS7111. Please refer to INTSR2 for individual bit details.

5.3.5

INTSR3 Interrupt Status Register 3

ADDRESS: 0x8000.2240

7:1

Reserved

0

DAIINT

This register is an extension of INTSR1 and INTSR2 containing status bits for the new features of the

EP7209. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in

Table 34.

Bit

Description

0

MCPINT: DAI interface interrupt. The cause must be determined by reading the DAI status regis-

ter. It is mapped to the FIQ interrupt on the ARM720T processor

Table 34. INTSR3

5.3.6

INTMR3 Interrupt Mask Register 3

ADDRESS: 0x8000.2280

7:1

Reserved

0

DAIINT

This register is an extension of INTMR1 and INTMR2, containing interrupt mask bits for the new fea-

tures of the EP7209. Please refer to INTSR3 for individual bit details.

68

DS453PP2

EP7209

5.4

Memory Configuration Registers

5.4.1

MEMCFG1 Memory Configuration Register 1

ADDRESS: 0x8000.0180

31:24

23:16

15:8

7:0

nCS[0] configuration

nCS[3] configuration

nCS[2] configuration

nCS[1] configuration

Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (nCS[6])

is used internally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum

wait state operation. nCS[7] is used for the on-chip Boot ROM and the configuration field is hardwired

for 8-bit wide, minimum wait state operation. Data written to the configuration fields for either nCS[6]

or nCS7 will be ignored. Two of the chip selects (nCS[4:5]) can be used to access two CL-PS6700

PC CARD controller devices, and when either of these interfaces is enabled, the configuration field

for the appropriate chip select in the MEMCFG2 register is ignored. When the PC CARD1 or 2 control

bit in the SYSCON2 register is disabled, then nCS[4] and nCS[5] are active as normal and can be

programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the six

external chip selects are active for 256 Mbytes and the timing and bus transfer width can be pro-

grammed individually. This is accomplished by programming the six byte-wide fields contained in two

32-bit registers, MEMCFG1 and MEMCFG2. All bits in these registers are cleared by a system reset

(except for the nCS[6] and nCS[7] configurations).

The Memory Configuration Register 1 is a 32-bit read/write register which sets the configuration of

the four expansion and ROM selects nCS[0:3]. Each select is configured with a 1-byte field starting

with expansion select 0.

5.4.2

MEMCFG2 Memory Configuration Register 2

ADDRESS: 0x8000.01C0

31:24

(Boot ROM)

7

23:16

(Local SRAM)

6

15:8

nCS[5] configuration

5:2

7:0

nCS[4] configuration

1:0

CLKENB

SQAEN

Wait States Field

Bus width

The Memory Configuration Register 2 is a 32-bit read/write register which sets the configuration of

the two expansion and ROM selects nCS[4:5]. Each select is configured with a 1-byte field starting

with expansion select 4.

Each of the six non-reserved byte fields for chip select configuration in the memory configuration reg-

isters are identical and define the number of wait states, the bus width, enable EXPCLK output during

accesses and enable sequential mode access. This byte field is defined below. This arrangement ap-

plies to nCS[0:3], and nCS[4:5] when the PC CARD enable bits in the SYSCON2 register are not set.

The state of these bits is ignored for the Boot ROM and local SRAM fields in the MEMCFG2 register.

Table 35 defines the bus width field. Note that the effect of this field is dependent on the two BOOTBIT

bits that can be read in the SYSFLG1 register. All bits in the memory configuration register are cleared

by a system reset and the state of the BOOTBIT bits are determined by Port E bits 0 and 1 on the

EP7209 during power-on reset. The state of PE[1] and PE[0] determine whether the EP7209 is going

to boot from either 32-bit wide, 16-bit wide or 8-bit wide ROMs.

Table 36 shows the values for the wait states for random and sequential wait states at 13 and 18 MHz

bus rates. At 36 MHz bus rate, the encoding becomes more complex. Table 37 preserves compati-

bility with the previous devices, while allowing the previously unused bit combinations to specify more

variations of random and sequential wait states.

DS453PP2

69

EP7209

Bus Width Field BOOTBIT1

BOOTBIT0

Expansion Transfer Mode

Port E bits 1,0 during

NPOR reset

Low, Low

Low, High

High, Low

00

01

10

11

00

01

10

11

00

01

10

11

0

1

0

1

0

32-bit wide bus access

16-bit wide bus access

8-bit wide bus access

Reserved

8-bit wide bus access

Reserved

32-bit wide bus access

16-bit wide bus access

32-bit wide bus access

Reserved

8-bit wide bus access

Table 35. Values of the Bus Width Field

Value

No. of Wait States

Random

Sequential

00

01

10

11

4

3

2

1

3

2

1

0

Table 36. Values of the Wait State Field at 13 MHz and 18 MHz

Bit 3

Bit 2

Bit 1

Bit 0

Wait States

Random

Sequential

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

3

2

1

0

Table 37. Values of the Wait State Field at 36 MHz

70

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EP7209

Bit

Description

6

7

SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a

quad word boundary to take advantage of faster access times from devices that support page

mode. The sequential access will be faulted after four words (to allow video refresh cycles to

occur), even if the access is part of a longer sequential access. In addition, when this bit is not

set, non-sequential accesses will have a single idle cycle inserted at least every four cycles so

that the chip select is de-asserted periodically between accesses for easier debug.

CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during

accesses to the selected expansion device. This will provide a timing reference for devices that

need to extend bus cycles using the EXPRDY input. Back to back (but not necessarily page

mode) accesses will result in a continuous clock. This bit will only affect EXPCLK when the PLL

is being used (i.e., in 73.728–18.432 MHz mode). When operating in 13 MHz mode, the EXPCLK

pin is an input so it is not affected by this register bit. To save power internally, it should always be

set to zero when operating in 13 MHz mode.

Table 38. MEMCFG

See the AC Electrical Specification section for more detail on bus timing.

The memory area decoded by CS[6] is reserved for the on-chip SRAM, hence this does not require

a configuration field in MEMCFG2. It is automatically set up for 32-bit wide, no wait state accesses.

For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses.

Chip selects nCS[4] and nCS[5] are used to select two CL-PS6700 PC CARD controller devices.

These have a multiplexed 16-bit wide address/data interface, and the configuration bytes in the

MEMCFG2 register have no meaning when these interfaces are enabled.

5.5

Timer/Counter Registers

5.5.1

TC1D Timer Counter 1 Data Register

ADDRESS: 0x8000.0300

The timer counter 1 data register is a 16-bit read/write register which sets and reads data to TC1. Any

value written will be decremented on the next rising edge of the clock.

5.5.2

TC2D Timer Counter 2 Data Register

ADDRESS: 0x8000.0340

The timer counter 2 data register is a 16-bit read/write register which sets and reads data to TC2. Any

value written will be decremented on the next rising edge of the clock.

5.5.3

RTCDR Real Time Clock Data Register

ADDRESS: 0x8000.0380

The Real Time Clock data register is a 32-bit read/write register, which sets and reads the binary time

in the RTC. Any value written will be incremented on the next rising edge of the 1 Hz clock. This reg-

ister is reset only by nPOR.

5.5.4

RTCMR Real Time Clock Match Register

ADDRESS: 0x8000.03C0

The Real Time Clock match register is a 32-bit read/write register, which sets and reads the binary

match time to RTC. Any value written will be compared to the current binary time in the RTC, if they

match it will assert the RTCMI interrupt source. This register is reset only by nPOR.

DS453PP2

71

EP7209

5.6

LEDFLSH Register

ADDRESS: 0x8000.22C0

6

5:2

1:0

Enable

Duty ratio

Flash rate

The output is enabled whenever LEDFLSH[6] = 1. When enabled, PDDDR[0] needs to be configured

as an output pin and the bit cleared to ‘0’ (See PDDDR Port D Data Direction Register). When the

LED Flasher is disabled, the pin defaults to being used as Port D bit 0. Thus, this will ensure that the

LED will be off when disabled.

The flash rate is determined by the LEDFLSH[1:0] bits, in the following way:

LEDFLSH[1:0]

Flash Period (sec)

00

01

10

11

1

2

3

4

Table 39. LED Flash Rates

LEDFLSH[5:2]

Duty Ratio

LEDFLSH[5:2]

Duty Ratio

(time on : time off)

0000

0001

0010

0011

0100

0101

0110

0111

01:15

02:14

03:13

04:12

05:11

06:10

07:09

08:08

1000

1001

1010

1011

1100

1101

1110

1111

09:07

10:06

11:05

12:04

13:03

14:02

15:01

16:00 (continually on)

Table 40. LED Duty Ratio

72

DS453PP2

EP7209

5.7

PMPCON Pump Control Register

ADDRESS: 0x8000.0400

11:8

7:4

3:0

Drive 0 from battery ratio

Drive 1 pump ratio

Drive 0 from AC source ratio

The Pulse Width Modulator (PWM) pump control register is a 16-bit read/write register which sets and

controls the variable mark space ratio drives for the two PWMs. All bits in this register are cleared by

a system reset. (The top four bits are unused. They should be written as zeroes, and will read as un-

defined).

Bit

Description

0:3

4:7

Drive 0 from battery: This 4-bit field controls the ‘on’ time for the Drive 0 PWM pump while the

system is powered from batteries. Setting these bits to 0 disables this pump, setting these bits to

1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio etc. up to a 15:16 duty

ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an 18.432 MHz

master clock, or 101.6 kHz when operating from the 13 MHz source.

Drive 0 from AC: This 4-bit field controls the ‘on’ time for the Drive 0 DC to DC pump while the

system is powered from a non-battery type power source. Setting these bits to 0 disables this

pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty

ratio, etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when

operating with an 18.432 MHz master clock, or 101.6 kHz when operating from the 13 MHz

source.

NOTE:

The EP7209 monitors the power supply input pins (i.e., BATOK and NEXTPWR) to

determine which of the above fields to use.

8:11

Drive 1 pump ratio: This 4-bit field controls the ‘on’ time for the drive1 PWM pump. Setting these

bits to 0 disables this pump, setting these bits to 1 allows the pump to be driven in a 1:16 duty

ratio, 2 in a 2:16 duty ratio, etc. up to a 15:16 duty ratio. An 8:16 duty ratio results in a square

wave of 96 kHz when operating with an 18.432 MHz master clock, or 101.6 kHz when operating

from the 13 MHz source.

Table 41. PMPCON

The state of the output drive pins is latched during power on reset, this latched value is used to de-

termine the polarity of the drive output. The sense of the PWM control lines is summarized in

Table 42.

Initial State of Drive 0 or

Drive 1 During Power on Reset

Sense of Drive 0

or Drive 1

Polarity of Bias

Voltage

Low

Active high

Active low

+ve

-ve

High

Table 42. Sense of PWM control lines

External input pins that would normally be connected to the output from comparators monitoring the

PWM output are also used to enable these clocks. These are the FB[0:1] pins.When FB[0] is high,

the PWM is disabled. The same applies to FB[1]. They are read upon power-up.

NOTE: To maximize power savings, the drive ratio fields should be used to disable the PWMs,

instead of the FB pins. The clocks that source the PWMs are disabled when the drive ratio

fields are zeroed.

DS453PP2

73

EP7209

5.8

CODR — The CODEC Interface Data Register

ADDRESS: 0x8000.0440

The CODR register is an 8-bit read/write register, to be used with the codec interface. This is selected

by the appropriate setting of bit 0 (SERSEL) of the SYSCON2 register. Data written to or read from

this register is pushed or popped onto the appropriate 16-byte FIFO buffer. Data from this buffer is

then serialized and sent to or received from the codec sound device. When the codec is enabled, the

codec interrupt CSINT is generated repetitively at 1/8th of the byte transfer rate and the state of the

FIFOs can be read in the system flags register. The net data transfer rate to/from the codec device is

8 kBytes/s, giving an interrupt rate of 1 kHz.

5.9

UART Registers

UARTDR1–2 UART1–2 Data Registers

5.9.1

ADDRESS: 0x8000.0480 and 0x8000.1480

10

9

8

7:0

OVERR

PARERR

FRMERR

RX data

The UARTDR registers are 11-bit read and 8-bit write registers for all data transfers to or from the

internal UARTs 1 and 2.

Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled.

If not it is stored in a one byte holding register. This write will initiate transmission from the UART.

The UART data read registers are made up of the 8-bit data byte received from the UART together

with three bits of error status. If the FIFO is enabled, data read from this register is popped from the

16 byte data RX FIFO. If the FIFO is not enabled, it is read from a one byte buffer register containing

the last byte received by the UART. If it is enabled, data received and error status is automatically

pushed onto the RX FIFO. The RX FIFO is 10-bits wide by 16 deep.

NOTE: These registers should be accessed as words.

Bit

Description

8

FRMERR: UART framing error. This bit is set if the UART detected a framing error while receiv-

ing the associated data byte. Framing errors are caused by non-matching word lengths or bit

rates.

9

PARERR: UART parity error. This bit is set if the UART detected a parity error while receiving the

data byte.

10

OVERR: UART over-run error. This bit is set if more data is received by the UART and the FIFO

is full. The overrun error bit is not associated with any single character, and so is not stored in the

FIFO, if this bit is set the entire contents of the FIFO is invalid and should be cleared. This error

bit is cleared by reading the UARTDR register.

Table 43. UARTDR1-2 UART1-2

74

DS453PP2

EP7209

5.9.2

UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers

ADDRESS: 0x8000.04C0 and 0x8000.14C0

31:19

18:17

16

15

14

13

12

11:0

WRDLEN

FIFOEN

XSTOP

EVENPRT

PRTEN

BREAK

Bit rate divisor

The bit rate divisor and line control register is a 19-bit read / write register. Writing to these registers

sets the bit rate and mode of operation for the internal UARTs.

Bit

Description

0:11

Bit rate divisor: This 12-bit field sets the bit rate. If the system is operating from the PLL clock,

then the bit rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided

internally by 16 to give the bit rate. The formula to give the divisor value for any bit rate when

operating from the PLL clock is: Divisor = (230400/bit rate divisor) – 1. A value of zero in this field

is illegal when running from the PLL clock. The tables below show some example bit rates with

the corresponding divisor value. In 13 MHz mode, the clock frequency fed to the UART is

1.8571 MHz. In this mode, zero is a legal divisor value, and will generate the maximum possible

bit rate. The tables below show the bit rates available for both 18.432 MHz and 13 MHz opera-

tion.

Divisor Value

Bit Rate Running

From the Pll Clock

Divisor

Value

Bit Rate at

13 Mhz

Error on

13 MHz

Value

0

1

—

0

1

116071

58036

38690

19345

14509

9673

0.75%

0.42%

0.28%

0.18%

115200

76800

57600

38400

19200

14400

9600

2

3

5

7

11

15

23

95

191

2094

11

47

96

1054

2418

1196

2400

110.02

1200

110

12

13

14

BREAK: Setting this bit will drive the TX output active (high) to generate a break.

PRTEN: Parity enable bit. Setting this bit enables parity detection and generation

EVENPRT: Even parity bit. Setting this bit sets parity generation and checking to even parity,

clearing it sets odd parity. This bit has no effect if the PRTEN bit is clear.

15

XSTOP: Extra stop bit. Setting this bit will cause the UART to transmit two stop bits after each

data byte, clearing it will transmit one stop bit after each data byte.

Table 44. UBRLCR1-2 UART1-2

DS453PP2

75

EP7209

Bit

Description

16

FIFOEN: Set to enable FIFO buffering of RX and TX data. Clear to disable the FIFO (i.e., set its

depth to one byte).

17:18

WRDLEN: This two bit field selects the word length according to the table below.

WRDLEN

Word Length

5 bits

00

01

10

11

6 bits

7 bits

8 bits

Table 44. UBRLCR1-2 UART1-2 (cont.)

76

DS453PP2

EP7209

5.10 LCD Registers

5.10.1 LCDCON — The LCD Control Register

ADDRESS: 0x8000.02C0

31

30

29:25

24:19

18:13

12:0

Video buffer size

GSMD

GSEN

AC prescale

Pixel prescale

Line length

The LCD control register is a 32-bit read/write register that controls the size of the LCD screen and

the operating mode of the LCD controller. Refer to the system description of the LCD controller for

more information on video buffer mapping.

The LCDCON register should only be reprogrammed when the LCD controller is disabled.

Bit

Description

0:12

Video buffer size: The video buffer size field is a 13-bit field that sets the total number of bits x

128 (quad words) in the video display buffer. This is calculated from the formula:

Video buffer size = (Total bits in video buffer / 128) – 1

i.e., for a 640 x 240 LCD and 4-bits per pixel, the size of the video buffer is equal to

614400 bits.

Video buffer = 640 x 240 x 4=614400 bits

Video buffer size field = (614400 / 128) – 1 = 4799 or 0x12BF hex.

The minimum value allowed is 3 for this bit field.

13:18

19:24

Line length: The line length field is a 6-bit field that sets the number of pixels in one complete

line. This field is calculated from the formula:

line length = (Number of pixels in line / 16) – 1

i.e., for 640 x 240 LCD Line length = (640 / 16) – 1 = 39 or 0x27 hex.

The minimum value that can be programmed into this register is a 1 (i.e., 0 is not a legal value).

Pixel prescale: The pixel prescale field is a 6-bit field that sets the pixel rate prescale. The pixel

rate is always derived from a 36.864 MHz clock when in PLL mode, and is calculated from the

formula:

Pixel rate (MHz) = 36.864 / (Pixel prescale + 1)

When the EP7209 is operating at 13 MHz, pixel rate is given by the formula:

Pixel rate (MHz) = 13 / (Pixel prescale + 1)

The pixel prescale value can be expressed in terms of the LCD size by the formula:

When the EP7209 is operating @ 18.432 MHz:

Pixel prescale = (36864000 / (Refresh Rate x Total pixels in display)) – 1

When the EP7209 is operating @ 13 MHz:

Pixel prescale = (13000000 / (Refresh Rate x Total pixels in display)) – 1

Refresh Rate is the screen refresh frequency (70 Hz to avoid flicker)

The value should be rounded down to the nearest whole number and zero is illegal and will result

in no pixel clock.

EXAMPLE: For a system being operated in the 18.432–73.728 MHz mode, with a 640 x 240

screen size, and 70 Hz screen refresh rate desired, the LCD Pixel prescale equals

36.864E6/(70 x 640x240) – 1 = 2.428

Rounding 2.428 down to the nearest whole number equals 2.

This gives an actual pixel rate of 36.864E6 / (2+1) = 12.288 MHz

Which gives an actual refresh frequency of 12.288E6/(640x240) = 80 Hz.

NOTE:

As the CL[2] low pulse time is doubled after every CL[1] high pulse this refresh fre-

quency is only an approximation, the accurate formula is 12.288E6/((640x240)+120) =

79.937 Hz.

Table 45. LCDCON

DS453PP2

77

EP7209

Bit

Description

25:29

AC prescale: The AC prescale field is a 5-bit number that sets the LCD AC bias frequency. This

frequency is the required AC bias frequency for a given manufacturer’s LCD plate. This fre-

quency is derived from the frequency of the line clock (CL[1]). The LCD M signal will toggle after

n+1 counts of the line clock (CL[1]) where n is the number programmed into the AC prescale

field. This number must be chosen to match the manufacturer’s recommendation. This is nor-

mally 13, but must not be exactly divisible by the number of lines in the display.

30

31

GSEN: Gray scale enable bit. Setting this bit enables gray scale output to the LCD. When this bit

is cleared each bit in the video map directly corresponds to a pixel in the display.

GSMD: Gray scale mode bit. Clearing this bit sets the controller to 2-bits per pixel (4 gray scales),

setting it sets it to 4 bits per pixel (16 gray scales). This bit has no effect if GSEN is cleared.

Table 45. LCDCON (cont.)

5.10.2 PALLSW Least Significant Word — LCD Palette Register

ADDRESS: 0x8000.0580

31:28

27:24

23:20

19:16

15:12

11:8

7:4

3:0

Gray scale

value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel

value 7 value 6 value 5 value 4 value 3 value 2 value 1 value 0

The least and most significant word LCD palette registers make up a 64-bit read/write register which

maps the logical pixel value to a physical gray scale level. The 64-bit register is made up of 16 x 4-bit

nibbles, each nibble defines the gray scale level associated with the appropriate pixel value. If the

LCD controller is operating in two bits per pixel, only the lower 4 nibbles are valid (D[15:0] in the least

significant word). Similarly, one bit per pixel means only the lower 2 nibbles are valid (D[7:0]) in the

least significant word.

5.10.3 PALMSW Most Significant Word — LCD Palette Register

ADDRESS: 0x8000.0540

31:28

27:24

23:20

19:16

15:12

11:8

7:4

3:0

Gray scale

value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel value for pixel

value 15 value 14 value 13 value 12 value 11 value 10 value 9 value 8

The pixel to gray scale level assignments and the actual physical color and pixel duty ratio for the gray

scale values are shown in Table 46. Note that colors 8–15 are the inverse of colors 7–0 respectively.

This means that colors 7 and 8 are identical. Therefore, in reality only 15 gray scales available, not

16. The steps in the gray scale are non-linear, but have been chosen to give a close approximation

to perceived linear gray scales. The is due to the eye being more sensitive to changes in gray level

close to 50% gray (See PALLSW description).

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Gray Scale Value

Duty Cycle

% Pixels Lit

0 %

% Step Change

11.1 %

8.9 %

0

1

0

1/9

1/5

4/15

3/9

2/5

4/9

1/2

5/9

3/5

6/9

11/15

4/5

8/9

1

11.1 %

20.0 %

26.7 %

33.3 %

40.0 %

44.4 %

50.0 %

55.6 %

60.0 %

66.7 %

73.3 %

80.0 %

88.9 %

100 %

2

6.7 %

3

6.6 %

4

6.7 %

5

5.4 %

6

5.6 %

7

0.0 %

8

5.6 %

9

5.4 %

10

11

12

13

14

15

6.7 %

6.6 %

6.7 %

8.9 %

11.1 %

Table 46. Gray Scale Value to Color Mapping

5.10.4 FBADDR LCD Frame Buffer Start Address

ADDRESS: 0x8000.1000

This register contains the start address for the LCD Frame Buffer. It is assumed that the frame buffer

starts at location 0x0000000 within each chip select memory region. Therefore, the value stored with-

in the FBADDR register is only the value of the chip select where the frame buffer is located. On reset,

this will be set to 0xC. The register is 4 bits wide (bits [3:0]). This register must only be reprogrammed

when the LCD is disabled (i.e., setting the LCDEN bit within SYSCON2 low).

5.11 SSI Register

5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register

ADDRESS: a0x8000.0500

In the default mode, the bits in SYNCIO have the following meaning:

31:15

14

13

12:8

7:0

Reserved

TXFRMEN

SMCKEN

Frame length

ADC Configuration Byte

Whereas in extended mode, the following applies:

15

14

13

12:7

6:0

Reserved

TXFRMEN

SMCKEN

Frame length

ADC Configuration Length

ADC Configuration Extension

NOTE:

The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read bits

(= 33 cycles).

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SYNCIO is a 32-bit read/write register. The data written to the SYNCIO register configures the master

only SSI. In default mode, the least significant byte is serialized and transmitted out of the synchro-

nous serial interface1 (i.e., SSI1) to configure an external ADC, MSB first. In extended mode, a vari-

able number of bits are sent from SYNCIO[16:31] as determined by the ADC Configuration Length.

The transfer clock will automatically be started at the programmed frequency and a synchronization

pulse will be issued. The ADCIN pin is sampled on every positive going clock edge (or the falling clock

edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to the SYNCIO read register.

During data transfer, the SSIBUSY bit is set high; at the end of a transfer the SSEOTI interrupt will be

asserted. In order to clear the interrupt the SYNCIO register must be read. The data read from the

SYNCIO register is the last sixteen bits shifted out of the ADC.

The length of the data frame can be programmed by writing to the SYNCIO register. This allows many

different ADCs to be accommodated. The device is SPI/Microwire compatible (transfers are in multi-

ples of 8 bits). However, to be compatible with some non-SPI/Microwire devices, the data written to

the ADC device can be anything between 8 to 16 bits. This is user-definable as defined in the ADC

Configuration Extension section of the SYNCIO register.

Bit

Description

0:7 or 0:6

ADC Configuration Byte: When the ADCCON control bit in the SYSCON3 register = 0, this is

the 8-bit configuration data to be sent to the ADC. When the ADCCON control bit in the

SYSCON3 register = 1, this field determines the length of the ADC configuration data held in the

ADC Configuration Extension field for sending to the ADC.

8:12 or 7:12

Frame length: The Frame Length Field is the total number of shift clocks required to complete a

data transfer.

In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit

+ 16 bits result).

In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).

13

14

SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC

clock frequency to be output on the SMPLCK pin.

TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC

configuration field will be shifted out to the ADC and depending on the frame length programmed,

a number of bits will be captured from the ADC. If the SYNCIO register is written to with the

TXFRMEN bit low, no ADC transfer will take place, but the Frame length and SMCKEN bits will

be affected.

16:31

ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0

this field is ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the

SYSCON3 register = 1, this field is the configuration data to be sent to the ADC. The ADC Con-

figuration Extension field length is determined by the value held in the ADC Configuration Length

field (SYNCIO[6:0]).

Table 47. SYNCIO

5.12 STFCLR Clear all ‘Start Up Reason’ flags location

ADDRESS: 0x8000.05C0

A write to this location will clear all the ‘Start Up Reason’ flags in the system flags status register SYS-

FLG. The ‘Start Up Reason’ flags should first read to determine the reason why the chip was started

(i.e., a new battery was installed). Any value may be written to this location.

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5.13 ‘End Of Interrupt’ Locations

These locations are written to after the appropriate interrupt has been serviced. The write is per-

formed to clear the interrupt status bit, so that other interrupts can be serviced. Any value may be writ-

ten to these locations.

5.13.1 BLEOI Battery Low End of Interrupt

ADDRESS: 0x8000.0600

A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK with

nEXTPWR high).

5.13.2 MCEOI Media Changed End of Interrupt

ADDRESS: 0x8000.0640

A write to this location will clear the interrupt generated by a falling edge of the nMEDCHG input pin.

5.13.3 TEOI Tick End of Interrupt Location

ADDRESS: 0x8000.0680

A write to this location will clear the current pending tick interrupt and tick watch dog interrupt.

5.13.4 TC1EOI TC1 End of Interrupt Location

ADDRESS: 0x8000.06C0

A write to this location will clear the under flow interrupt generated by TC1.

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5.13.5 TC2EOI TC2 End of Interrupt Location

ADDRESS: 0x8000.0700

A write to this location will clear the under flow interrupt generated by TC2.

5.13.6 RTCEOI RTC Match End of Interrupt

ADDRESS: 0x8000.0740

A write to this location will clear the RTC match interrupt

5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt

ADDRESS: 0x8000.0780

A write to this location will clear the modem status changed interrupt.

5.13.8 COEOI Codec End of Interrupt Location

ADDRESS: 0x8000.07C0

A write to this location clears the sound interrupt (CSINT).

5.13.9 KBDEOI Keyboard End of Interrupt Location

ADDRESS: 0x8000.1700

A write to this location clears the KBDINT keyboard interrupt.

5.13.10 SRXEOF End of Interrupt Location

ADDRESS: 0x8000.1600

A write to this location clears the SSI2 RX FIFO overflow status bit.

5.14 State Control Registers

5.14.1 STDBY Enter the Standby State Location

ADDRESS: 0x8000.0840

A write to this location will put the system into the Standby State by halting the main oscillator. A write

to this location while there is an active interrupt will have no effect.

NOTES: 1) Before entering the Standby State, the LCD Controller should be disabled. The LCD

controller should be enabled on exit from the Standby State.

2) If the EP7209 is attempting to get into the Standby State when there is a pending

interrupt request, it will not enter into the low power mode. The instruction will get

executed, but the processor will ignore the command.

5.14.2 HALT Enter the Idle State Location

ADDRESS: 0x8000.0800

A write to this location will put the system into the Idle State by halting the clock to the processor until

an interrupt is generated. A write to this location while there is an active interrupt will have no effect.

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5.15 SS2 Registers

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register

ADDRESS: 0x8000.1500

This is the 16-bit wide data register for the full-duplex master/slave SSI2 synchronous serial interface.

Writing data to this register will initiate a transfer. Writes need to be word writes and the bottom 16

bits are transferred to the TX FIFO. Reads will be 32 bits as well; the low 16 bits contain RX data and

the upper 16-bits should be ignored. Although the interface is byte-oriented, data is written in two

bytes at a time to allow higher bandwidth transfer. It is up to the software to assemble the bytes for

the data stream in an appropriate manner.

All reads/writes to this register must be word reads/writes.

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte

ADDRESS: 0x8000.16C0

This is a write-only location which will cause the contents of the RX shift register to be popped into

the RX FIFO, thus enabling a residual byte to be read. The data value written to this register is ig-

nored. This location should be used in conjunction with the RESVAL and RESFRM bits in the

SYSFLG2 register.

5.16 DAI Register Definitions

There are five registers within the DAI Interface, one control register, three data registers, and one

status register. The control register is used to mask or unmask interrupt requests to service the DAI’s

FIFOs, and to select whether an on-chip or off-chip clock is used to drive the bit rate, and to en-

able/disable operation. The first pair of data register addresses the top of the right channel transmit

FIFO and the bottom of the right channel receive FIFO. A read accesses the receive FIFOs, and a

write the transmit FIFOs. Note that these are four physically separate FIFOs to allow full-duplex trans-

mission. The status register contains bits which signal FIFO overrun and underrun errors and transmit

and receive FIFO service requests. Each of these status conditions signal an interrupt request to the

interrupt controller. The status register also flags when the transmit FIFOs are not full when the re-

ceive FIFOs are not empty.

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5.16.1 DAI Control Register

ADDRESS: 0x8000.2000

31:24

23

22

21

20

19

18

17

16

15:0

Reserved

LBM

RCRM

RCTM

LCRM

LCTM

Reserved

ECS

DAIEN

Reserved

The DAI control register (DAIR) contains eight different bit fields that control various functions within

the DAI interface.

Bit

Description

Reserved

Must be set to 0x0404

0:15

7

Reserved

15

DAIEN: DAI Interface Enable

0 — DAI operation disabled, control of the SDIN, SDOUT, SCLKLRCK, and LRCK pins given to

the SSI2/codec/DAI pin mulitiplexing logic to assign I/O pins 60-64 to another block.

1 — DAI operation enabled

16

Note that by default, the SSI/CODEC have precedence over the DAI interface in regard to the

use of the I/O pins. Nevertheless, when Bit 3 (MCPSEL) of register SYSCON3 is set to 1, then

the above mentioned DAI ports are connected to I/O pins 60–64.

17

18

ECS: External Clock Select selects external MCLK when = 1.

Reserved

Must be 0.

LCTM: Left Channel Transmit FIFO Interrupt Mask

0 — Left Channel transmit FIFO half-full or less condition does not generate an interrupt (LCTS

bit ignored).

1 — Left Channel transmit FIFO half-full or less condition generates an interrupt (state of LCTS

sent to interrupt controller).

19

20

21

22

LCRM: Left Channel Receive FIFO Interrupt Mask

0 — Left Channel receive FIFO half-full or more condition does not generate an interrupt (LCRS

bit ignored).

1 — Left Channel receive FIFO half-full or more condition generates an interrupt (state of LCRS

sent to interrupt controller).

RCTM: Right Channel Transmit FIFO Interrupt Mask

0 — Right channel transmit FIFO half-full or less condition does not generate an interrupt (RCTS

bit ignored).

1 — Right channel transmit FIFO half-full or less condition generates an interrupt (state of RCTS

sent to interrupt controller).

RCRM: Right Channel Receive FIFO Interrupt Mask

0 — Right Channel receive FIFO half-full or more condition does not generate an interrupt

(RCRS bit ignored).

1 — Right Channel receive FIFO half-full or more condition generates an interrupt (state of RCRS

sent to interrupt controller).

Table 48. DAI Control Register

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Bit

23

Description

LBM: Loop Back Mode

0 — Normal serial port operation enabled

1 — Output of serial shifter is connected to input of serial shifter internally and control of SDIN,

SDOUT, SCLK, and LRCK pins is given to the PPC unit.

24:31

Reserved

Table 48. DAI Control Register (cont.)

5.16.1.1 DAI Enable (DAIEN)

The DAI enable (DAIEN) bit is used to enable and disable all DAI operation.

When the DAI is disabled, all of its clocks are powered down to minimize power consumption. Note

that DAIEN is the only control bit within the DAI interface that is reset to a known state. It is cleared

to zero to ensure the DAI timing is disabled following a reset of the device.

When the DAI timing is enabled, SCLK begins to transition and the start of the first frame is signaled

by driving the LRCK pin low. The rising and falling-edge of LRCK coincides with the rising and falling-

edge of SCLK. As long as the DAIEN bit is set, the DAI interface operates continuously, transmitting

and receiving 128 bit data frames. When the DAIEN bit is cleared, the DAI interface is disabled im-

mediately, causing the current frame which is being transmitted to be terminated. Clearing DAIEN re-

sets the DAI’s interface FIFOs. However DAI data register 3, the control register and the status

register are not reset. Therefore, the user must ensure these registers are properly reconfigured be-

fore re-enabling the DAI interface.

5.16.1.2 DAI Interrupt Generation

The DAI interface can generate four maskable interrupts and four non-maskable interrupts, as de-

scribed in the sections below. Only one interrupt line is wired into the interrupt controller for the whole

DAI interface. This interrupt is the wired OR of all eight interrupts (after masking where appropriate).

The software servicing the interrupts must read the status register in the DAI to determine which

source(s) caused the interrupt. It is possible to prevent any DAI sources causing an interrupt by mask-

ing the DAI interrupt in the interrupt controller register.

5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM)

The left channel sample transmit FIFO interrupt mask (LCTM) bit is used to mask or enable the left

channel sample transmit FIFO service request interrupt. When LATM = 0, the interrupt is masked and

the state of the left channel transmit FIFO service request (LCTS) bit within the DAI status register is

ignored by the interrupt controller. When LCTM = 1, the interrupt is enabled and whenever LCTS is

set (one) an interrupt request is made to the interrupt controller. Note that programming LCTM = 0

does not affect the current state of LCTS or the left channel transmit FIFO logic’s ability to set and

clear LCTS; it only blocks the generation of the interrupt request.

5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM)

The left channel sample receive FIFO interrupt mask (LCRM) bit is used to mask or enable the left

channel receive FIFO service request interrupt. When LCRM = 0, the interrupt is masked and the

state of the left channel sample receive FIFO service request (LCRS) bit within the DAI status register

is ignored by the interrupt controller. When LCRM = 1, the interrupt is enabled and whenever LCRS

is set (one) an interrupt request is made to the interrupt controller. Note that programming LCRM = 0

does not affect the current state of LCRS or the left channel receive FIFO logic’s ability to set and

clear LCRS, it only blocks the generation of the interrupt request.

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5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM)

The right channel transmit FIFO interrupt mask (RCTM) bit is used to mask or enable the right channel

transmit FIFO service request interrupt. When RCTM = 0, the interrupt is masked and the state of the

right channel transmit FIFO service request (RCTS) bit within the DAI status register is ignored by the

interrupt controller. When RCTM = 1, the interrupt is enabled and whenever RCTS is set (one) an in-

terrupt request is made to the interrupt controller. Note that programming RCTM = 0 does not affect

the current state of RCTS or the right channel transmit FIFO logic’s ability to set and clear RCTS; it

only blocks the generation of the interrupt request.

5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM)

The right channel receive FIFO interrupt mask (RCRM) bit is used to mask or enable the right channel

receive FIFO service request interrupt. When RCRM = 0, the interrupt is masked and the state of the

right channel receive FIFO service request (RCRS) bit within the DAI status register is ignored by the

interrupt controller. When RCRM = 1, the interrupt is enabled and whenever RCRS is set (one) an

interrupt request is made to the interrupt controller. Note that programming RCRM = 0 does not affect

the current state of RCRS or the right channel receive FIFO logic’s ability to set and clear RCRS; it

only blocks the generation of the interrupt request.

5.16.1.7 Loop Back Mode (LBM)

The loop back mode (LBM) bit is used to enable and disable the ability of the DAI’s transmit and re-

ceive logic to communicate. When LBM = 0, the DAI operates normally. The transmit and receive data

paths are independent and communicate via their respective pins. When LBM = 1, the output of the

serial shifter (MSB) is directly connected to the input of the serial shifter (LSB) internally and control

of the SDOUT, SDIN, SCLK, and LRCK pins are given to the peripheral pin control (PPC) unit.

Table 48 shows the bit locations corresponding to the ten different control bit fields within the DAI con-

trol register. Note that the DAIEN bit is the only control bit which is reset to a known state to ensure

the DAI is disabled following a reset of the device. The reset state of all other control bits is unknown

and must be initialized before enabling the DAI. Writes to reserved bits are ignored and reads return

zeros.

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5.16.2 DAI Data Registers

The DAI contains three data registers: DAIDR0 addresses the top entry of the right channel transmit FIFO

and bottom entry of the right channel receive FIFO; DAIDR1 addresses the top and bottom entry of the

left channel transmit and receive FIFOs, respectively; and DAIDR2 is used to perform enable and disable

the DAI FIFOs.

5.16.2.1 DAI Data Register 0

ADDRESS: 0x8000.2040

31:16

15:0

Reserved

Bottom of Right Channel Receive FIFO

Read Access

31:16

15:0

Reserved

Top of Right Channel Transmit FIFO

Write Access

When DAI Data Register 0 (DAIDR0) is read, the bottom entry of the right channel receive FIFO is

accessed. As data is removed by the DAI’s receive logic from the incoming data frame, it is placed

into the top entry of the right channel receive FIFO and is transferred down an entry at a time until it

reaches the last empty location within the FIFO. Data is removed by reading DAIDR0, which accesses

the bottom entry of the right channel FIFO. After DAIDR0 is read, the bottom entry is invalidated, and

all remaining values within the FIFO automatically transfer down one location.

When DAIDR0 is written, the top-most entry of the right channel transmit FIFO is accessed. After a

write, data is automatically transferred down to the lowest location within the transmit FIFO which

does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time

by the transmit logic, loaded into the correct position within the 64-bit transmit serial shifter, then se-

rially shifted out onto the SDOUT pin.

Table 49 shows DAIDR0. Note that the transmit and receive right channel FIFOs are cleared when

the device is reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved

bits are ignored and reads return zeros.

Bit

0:15

Description

RIGHT CHANNEL DATA: Transmit/Receive right channel FIFO Data

Read — Bottom of Right Channel Receive FIFO data

Write — Top of Right Channel Transmit FIFO data

16:31

Reserved

Table 49. DAI Data Register 0

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5.16.2.2 DAI Data Register 1

ADDRESS: 0x8000.2080

31:16

15:0

Reserved

Bottom of Left Channel Receive FIFO

Read Access

31:16

15:0

Reserved

Top of Left Channel Transmit FIFO

Write Access

When DAI Data Register 1 (DAIDR1) is read, the bottom entry of the left channel receive FIFO is ac-

cessed. As data is removed by the DAI’s receive logic from the incoming data frame, it is placed into

the top entry of the left channel receive FIFO and is transferred down an entry at a time until it reaches

the last empty location within the FIFO. Data is removed by reading DAIDR1, which accesses the bot-

tom entry of the left channel FIFO. After DAIDR1 is read, the bottom entry is invalidated, and all re-

maining values within the FIFO automatically transfer down one location.

When DAIDR1 is written, the top-most entry of the left channel transmit FIFO is accessed. After a

write, data is automatically transferred down to the lowest location within the transmit FIFO which

does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time

by the transmit logic. It is then loaded into the correct position within the 64-bit transmit serial shifter

then serially shifted out onto the SDOUT pin.

Table 50 shows DAIDR1. Note that the transmit and receive left channel FIFOs are cleared when the

device is reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved bits

are ignored and reads return zeros.

Bit

0:15

Description

LEFT CHANNEL DATA: Transmit/Receive left channel FIFO Data

Read — Bottom of Left Channel Receive FIFO data

Write — Top of Left Channel Transmit FIFO data

16:31

Reserved

Table 50. DAI Data Register 1

5.16.2.3 DAI Data Register 2

ADDRESS: 0x8000.20C0

DAIDR2 contains 21 bits and is used to enable and disable the FIFOs for the left and right channels

of the DAI data stream. The left channel FIFO is enabled by writing 0x000D.C000 and disabled by

writing 0x000D.0000. The right channel FIFO is enabled by writing 0x0011.C000 and disabled by writ-

ing 0x0011.0000. After writing a value to this register, wait until the FIFO operation complete bit

(FIFO) is set in the DAI status register before writing another value to this register.

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5.16.3 DAI Status Register

ADDRESS: 0x8000.2100

The DAI Status Register (DAISR) contains bits which signal FIFO overrun and underrun errors and

FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.

The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty,

when a FIFO operation is complete, and when the right channel or left channel portion of the codec

is enabled (no interrupt generated).

Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is

cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags.

Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ-

ing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set and

cleared by hardware, and writes have no effect. Additionally some bits which cause interrupts have

corresponding mask bits in the control register and are indicated in the section headings below. Note

that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con-

troller mask register INTMR3.

5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS)

The right channel transmit FIFO service request flag (RCTS) is a read-only bit which is set when the

right channel transmit FIFO is nearly empty and requires service to prevent an underrun. RCTS is set

any time the right channel transmit FIFO has four or fewer entries of valid data (half full or less), and

is cleared when it has five or more entries of valid data. When the RCTS bit is set, an interrupt request

is made unless the right channel transmit FIFO interrupt request mask (RCTM) bit is cleared. After

the CPU fills the FIFO such that four or more locations are filled within the right channel transmit FIFO,

the RCTS flag (and the service request and/or interrupt) is automatically cleared.

5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS)

The right channel receive FIFO service request flag (RCRS) is a read-only bit which is set when the

right channel receive FIFO is nearly filled and requires service to prevent an overrun. RCRS is set

any time the right channel receive FIFO has six or more entries of valid data (half full or more), and

cleared when it has five or fewer (less than half full) entries of data. When the RCRS bit is set, an

interrupt request is made unless the right channel receive FIFO interrupt request mask (RCRM) bit is

cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the service

request and/or interrupt) is automatically cleared.

5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS)

The left channel transmit FIFO service request flag (LCTS) is a read-only bit which is set when the

left channel transmit FIFO is nearly empty and requires service to prevent an underrun. LCTS is set

any time the left channel transmit FIFO has four or fewer entries of valid data (half full or less), and is

cleared when it has five or more entries of valid data. When the LCTS bit is set, an interrupt request

is made unless the left channel transmit FIFO interrupt request mask (LCTM) bit is cleared. After the

CPU fills the FIFO such that four or more locations are filled within the left channel transmit FIFO, the

LCTS flag (and the service request and/or interrupt) is automatically cleared.

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5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS)

The left channel receive FIFO service request flag (LCRS) is a read-only bit which is set when the left

channel receive FIFO is nearly filled and requires service to prevent an overrun. LCRS is set any time

the left channel receive FIFO has six or more entries of valid data (half full or more), and cleared when

it has five or fewer (less than half full) entries of data. When the LCRS bit is set, an interrupt request

is made unless the left channel receive FIFO interrupt request mask (LCRM) bit is cleared. After six

or more entries are removed from the receive FIFO, the LCRS flag (and the service request and/or

interrupt) is automatically cleared.

5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU)

The right channel transmit FIFO underrun status bit (RCTU) is set when the right channel transmit

logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun

occurs, the right channel transmit logic continuously transmits the last valid right channel value which

was transmitted before the underrun occurred. Once data is placed in the FIFO and it is transferred

down to the bottom, the right channel transmit logic uses the new value within the FIFO for transmis-

sion. When the RCTU bit is set, an interrupt request is made.

5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO)

The right channel receive FIFO overrun status bit (RCRO) is set when the right channel receive logic

attempts to place data into the right channel receive FIFO after it has been completely filled. Each

time a new piece of data is received, the set signal to the RCRO status bit is asserted, and the newly

received data is discarded. This process is repeated for each new sample received until at least one

empty FIFO entry exists. When the RCRO bit is set, an interrupt request is made.

5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU)

The left channel transmit FIFO underrun status bit (LCTU) is set when the left channel transmit logic

attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs,

the left channel transmit logic continuously transmits the last valid left channel value which was trans-

mitted before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the

bottom, the left channel transmit logic uses the new value within the FIFO for transmission. When the

LCTU bit is set, an interrupt request is made.

5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO)

The left channel receive FIFO overrun status bit (LCRO) is set when the left channel receive logic

places data into the left channel receive FIFO after it has been completely filled. Each time a new

piece of data is received, the set signal to the LCRO status bit is asserted, and the newly received

sample is discarded. This process is repeated for each new piece of data received until at least one

empty FIFO entry exists. When the LCRO bit is set, an interrupt request is made.

5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF)

The right channel transmit FIFO not full flag (RCNF) is a read-only bit which is set whenever the right

channel transmit FIFO contains one or more entries which do not contain valid data and is cleared

when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the right

channel transmit FIFO. This bit does not request an interrupt.

5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE)

The right channel receive FIFO not empty flag (RCNELCNF) is a read-only bit which is set when ever

the right channel receive FIFO contains one or more entries of valid data and is cleared when it no

longer contains any valid data. This bit can be polled when using programmed I/O to remove remain-

ing data from the receive FIFO. This bit does not request an interrupt.

90

DS453PP2

EP7209

5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF)

The left channel transmit FIFO not full flag (LCNF) is a read-only bit which is set when ever the left

channel transmit FIFO contains one or more entries which do not contain valid data. It is cleared when

the FIFO is completely full. This bit can be polled when using programmed I/O to fill the left channel

transmit FIFO. This bit does not request an interrupt.

5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE)

The left channel receive FIFO not empty flag (LCNE) is a read-only bit which is set when ever the left

channel receive FIFO contains one or more entries of valid data and is cleared when it no longer con-

tains any valid data. This bit can be polled when using programmed I/O to remove remaining data

from the receive FIFO. This bit does not request an interrupt.

5.16.3.13 FIFO Operation Completed Flag (FIFO)

The FIFO operation completed (FIFO) flag is set after the FIFO operation requested by writing to

DAIDR2 as completed.

FIFO is automatically cleared when DAIDR2 is read or written. This bit does not request an interrupt.

31:13

Reserved

6

12

FIFO

11

LCNE

10

LCNF

3

9

8

RCNF

1

7

RCNE

2

RCCELCRO

0

5

4

RCNFLCTU

LCRORCRO

LCTURCTU

LCRS

LCTS

LCRSRCRS

LCTSRCTS

Bit

Description

RCTS: Right Channel Transmit FIFO Service Request Flag (read-only)

0 — right channel transmit FIFO is more than half full (five or more entries filled) or DAI disabled

1 — right channel transmit FIFO is half full or less (four or fewer entries filled) and DAI operation

is enabled, interrupt request signaled if not masked

0

(if RCTM = 1)

RCRS: Right Channel Receive FIFO Service Request (read-only)

0 — right channel receive FIFO is less than half full (five or fewer entries filled) or DAI disabled

1 — right channel receive FIFO is half full or more (six or more entries filled) and DAI operation

is enabled, interrupt request signaled if not masked (if RCRM = 1)

1

2

3

LCTS: Left Channel Transmit FIFO Service Request Flag (read-only)

0 — Left Channel transmit FIFO is more than half full or less (four or fewer entries filled) or DAI

disabled.

1 — Left Channel transmit FIFO is half full or less (four or fewer entries filled) and DAI operation

is enabled, interrupt request signaled if not masked

(if LCTM = 1)

LCRS: 0 — Left Channel receive FIFO is less than half full (five or fewer entries filled) or DAI

disabled.

1 — Left Channel receive FIFO is half full or more (six or more entries filled) and DAI operation

is enabled, interrupt request signalled if not masked (if LCRM = 1)

Table 51. DAI Control, Data and Status Register Locations

DS453PP2

91

EP7209

Bit

Description

Right Channel Transmit FIFO Underrun

0 — Right Channel transmit FIFO has not experienced an underrun

1 — Right Channel transmit logic attempted to fetch data from transmit FIFO while it was empty,

4

request interrupt

RCRO: Right Channel Receive FIFO Overrun

0 — Right Channel receive FIFO has not experienced an overrun

1 — Right Channel receive logic attempted to place data into receive FIFO while it was full,

request interrupt

5

6

7

LCTU: Left Channel Transmit FIFO Underrun

0 — Left Channel transmit FIFO has not experienced an underrun

1 — Left Channel transmit logic attempted to fetch data from transmit FIFO while it was empty,

request interrupt

LCRO: Left Channel Receive FIFO Overrun

0 — Left Channel receive FIFO has not experienced an overrun

1 — Left Channel receive logic attempted to place data into receive FIFO while it was full,

request interrupt

RCNF: Right Channel Transmit FIFO Not Full (read-only)

0 — Right Channel transmit FIFO is full

8

1 — Right Channel transmit FIFO is not full

RCNE: Right Channel Receive FIFO Not Empty (read-only)

0 — Right Channel receive FIFO is empty

9

1 — Right Channel receive FIFO is not empty

LCNF: LCNETelecom Transmit FIFO Not Full (read-only)

0 — Left Channel transmit FIFO is full

1 — Left Channel transmit FIFO is not full

10

11

12

LCNE: Left Channel Receive FIFO Not Empty (read-only)

0 — Left Channel receive FIFO is empty

1 — Left Channel receive FIFO is not empty

FIFO: FIFO Operation Completed (read-only)

0 — A FIFO Operation has not completed since the last time this bit was cleared

1 — THe FIFO Operation was completed

13

14

Reserved

15

16:31

Table 51. DAI Control, Data and Status Register Locations (cont.)

92

DS453PP2

EP7209

6. ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

DC Core, PLL, and RTC Supply Voltage

DC I/O Supply Voltage (Pad Ring)

DC Pad Input Current

2.9 V

3.6 V

±10 mA/pin; ±100 mA cumulative

–40°C to +125°C

Storage Temperature, No Power

Table 52. absolute Maximum Ratings

6.2

RecommendedOperatingConditions

DC core, PLL, and RTC Supply Voltage

DC I/O Supply Voltage (Pad Ring)

DC Input/Output Voltage

2.5 V ± 0.2 V

2.3V - 3.6V

O–I/O supply voltage

0°C to +70°C

Operating Temperature

Table 53. Recommended Operating Conditions

6.3

DC Characteristics

All characteristics are specified at V = 2.5 volts and V = 0 volts over an operating temperature of 0°C

DD

SS

to +70°C for all frequencies of operation. The current consumption figures relate to typical conditions at

2.5 V, 18.432 MHz operation with the PLL switched ‘on.’

Symbol

VIH

Parameter

Min

1.7

Max

Unit

V

Conditions

V_DD= 2.5 V

CMOS input high voltage

V_DD+ 0.3

VIL

-0.3

0.8

2.0

V

CMOS input low voltage

Schmitt trigger positive going

threshold

VT+

1.6 (Typ)

0.8

V

Schmitt trigger negative going

threshold

VT-

1.2 (Typ)

0.4

V

Vhst

0.1

Schmitt trigger hysteresis

VIL to VIH

CMOS output high voltage

Output drive 1

Output drive 2

V_DD– 0.2

IOH = 0.1 mA

OH = 4 mA

OH = 12 mA

V

VOH

VOL

2.5

CMOS output low voltage

Output drive 1

Output drive 2

IOL = –0.1 mA

OL = –4 mA

OL = –12 mA

0.3

0.5

V

Input leakage current

VIN = V_DDor GND

IIN

IOZ

CIN

1

µA

pF

Output tri-state leakage cur-

rent*

VOUT = V_DDor GND

25

8

100

10

Input capacitance

Table 54. DC Characteristics

DS453PP2

93

EP7209

Symbol

COUT

CI/O

Parameter

Min

8

Max

10

Unit

pF

Conditions

Output capacitance

Transceiver capacitance

Startup current consumption

8

10

pF

Initial 100 ms from power up,

32 kHz oscillator not stable,

POR signal at VIL, all other

I/O static, VIH = V_DD± 0.1 V,

IDD_startup

µA

VIL = GND ± 0.1 V

Standby current consumption

Just 32 kHz oscillator running,

all other I/O static, VIH = V_DD

IDD_standby

4

µA

± 0.1 V, VIL = GND ± 0.1 V

Idle current consumption

At 13 MHz

At 18 MHz

Both oscillators running, CPU

static, LCD refresh active, VIH

= V_DD± 0.1 V, VIL = GND ±

4.2

6

IDD_idle

mA

12

At 36 MHz

0.1 V

Operating current consump-

tion

All system active, running typ-

ical program

At 13 MHz

At 18 MHz

At 36 MHz

At 49 MHz

14

20

40

50

68

IDD_operating

mA

At 74 MHz

Standby supply voltage

Minimum standby voltage for

state retention and RTC oper-

ation only

V_DDstandby

TBD

V

NOTE:

All power dissipation values can be derived from taking the particular IDD current and multiplying by

2.5 V.

The RTC of the EP7209 should be brought up at room temperature. This is required because the RTC

OSC will NOT function properly if it is brought up at –40°C. Once operational, it will continue to operate

down to –40°C.

A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This

is to allow the I/O to be compatible with 3.3 V powered external logic (i.e., 3.3 V DRAMs).

Pull-up current = 50 µA typical at V_DD= 3.3 volts.

Table 54. DC Characteristics (cont.)

94

DS453PP2

EP7209

6.4

AC Characteristics

All characteristics are specified at V = 2.3 to 2.7 volts and V = 0 volts over an operating temperature

DD

SS

of 0°C to +70°C. Those characteristics marked with a # will be significantly different for 13 MHz mode

because the EXPCLK is provided as an input rather than generated internally. These timings are estimated

at present. The timing values are referenced to 1/2 V

.

DD

Symbol

Parameter

13 MHz

Max

18/36 MHz

Units

Min

0

Min

Max

25

t1

Falling CS to data bus Hi-Z

35

45

0

ns

kHz

ns

t2

Address change to valid write data

DATA in to falling EXPCLK setup time

DATA in to falling EXPCLK hold time

EXPRDY to falling EXPCLK setup time

Falling EXPCLK to EXPRDY hold time

Rising nMWE to data invalid hold time

Sequential data valid to falling NMWE setup time

LCD CL2 low time

0

35

t3

0 #

10 #

0 #

10 #

10

—

18

0

—

t4

—

t5

—

18

0

—

t6

50

t7

—

5

—

t8

–10

80

10

–10

80

0

10

t15

t16

t17

t18

t19

t20

t21

t22

t23

t24

t25

t31

t32

t33

t34

t35

t36

t37

t38

t39

t40

3,475

25

3,475

25

LCD CL2 high time

80

LCD falling CL[2] to rising CL[1] delay

LCD falling CL[1] to rising CL[2]

LCD CL[1] high time

0

80

3,475

6,950

10,425

20

80

200

300

–10

—

3,475

6,950

10,425

20

80

LCD falling CL[1] to falling CL[2]

LCD falling CL[1] to FRM toggle

LCD falling CL[1] to M toggle

200

300

–10

—

LCD rising CL[2] to display data change

Falling EXPCLK to address valid

20

33 #

—

5

Data valid to falling nMWE for non sequential access only

SSICLK period (slave mode)

SSICLK high

5

—

0

512

1025

7

0

512

1025

7

925

SSICLK low

SSICLK rise/fall time

SSICLK rising to RX and/or TX frame sync

SSICLK rising edge to frame sync low

SSICLK rising edge to TX data valid

SSIRXDA data set-up time

528

448

80

528

448

80

30

40

30

40

SSIRXDA data hold time

SSITXFR and/or SSIRXFR period

750

The values for 36 MHz include 1 wait state, the 18 MHz values have 0 wait states.

Table 55. AC Timing Characteristics

DS453PP2

95

EP7209

Symbol

Characteristics

13 MHz

Min Max

18 MHz

Min Max

36 MHz

Min Max

Units

Negative strobe (nCS[0:5]) zero

wait state read access time

t_nCSRD

t_nCSWR

t_EXBST

120

55

70

35

ns

Negative strobe (nCS[0:5]) zero

wait state write access time

Sequential expansion burst mode

read access time

The values for 36 MHz include 1 wait state, the 18 MHz values have 0 waits

tates.

Table 56. Timing Characteristics

96

DS453PP2

EP7209

eXPCLK

nCS[5:0]

tNCSRD

nMOE

A[27:0]

WORD

t1

tADRD

tPCSRD

t3

t4

t3

t4

D[31:0]

Bus held

Data in

t5

t6

eXPRDY

NOTES:

1) tnCSRD = 50 ns at 36.864 MHz

70 ns at 18.432 MHz

120 ns at 13.0 MHz

Maximum values for minimum wait states. This time can be extended by integer multiples of the

clock period (27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 1 MHz), by either driving

EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling

edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock

period where EXPRDY is sampled again. EXPCLK need not be referenced when driving

EXPRDY, but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential

access wait state field is used to determine the number of wait states, and no idle cycles are

inserted between successive non-sequential ROM/expansion cycles. This improves perfor-

mance so the SQAEN bit should always be set where possible.

3) tnCSRD = tADRD = tPCSRD

Figure 13. Consecutive Memory Read Cycles with Minimum Wait States

DS453PP2

97

EP7209

EXPCLK

nCS[5:0]

nMOE

A[27:4]

tEXBST

4

tEXBST

0

8

WORD

D[31:0]

t1

tEXRD

t5

t3

Data in

t4

t3

Data in

t3

Data in

t4

Bus held

t6

EXPRDY

NOTES:

1) tEXBST = 35 ns at 36.864 MHz

35 ns at 18.432 MHz

55 ns at 13.0 MHz

(Value for 36.864 MHz assumes 1 wait state.)

Maximum values for minimum wait states. This time can be extended by integer multiples of the

clock period (27 nsec at 36 MHz, 54 nsec at 18.432 MHz and 77 ns at 13 MHz), by either driving

EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling

edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock

period where EXPRDY is sampled again. EXPCLK need not be referenced when driving

EXPRDY, but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential

access wait state field is used to determine the number of wait states, and no idle cycles are

inserted between successive non-sequential ROM/expansion cycles. This improves perfor-

mance so the SQAEN bit should always be set where possible.

Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States

98

DS453PP2

EP7209

eXPCLK

nCS[5:0]

tnCSWR

t8

tADWR

nMWE

A[27:0]

WORD

t2

t7

t2

D[31:0]

Bus held

Write data

t5

t6

EXPRDY

NOTES:

1) tnCSWR = 35 nsec at 36.864 MHz

70 ns at 18.432 MHz

120 ns at 13.0 MHz

Maximum values for minimum wait states. This time can be extended by integer multiples of the

clock period (27 nsec at 36 MHz, 54 nsec at 18.432 MHz, and 77 nsec at 13 MHz), by either

driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on

the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed

by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when

driving EXPRDY, but is shown for clarity.

2) Consecutive reads with sequential access enabled are identical except that the sequential

access wait state field is used to determine the number of wait states, and no idle cycles are

inserted between successive non-sequential ROM/expansion cycles. This improves perfor-

mance so the SQAEN bit should always be set where possible.

3) Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin,

as this cannot be driven with valid timing under zero wait state conditions.

Figure 15. Consecutive Memory Write Cycles with Minimum Wait States

DS453PP2

99

EP7209

t20

t15

t16

CL[2]

t17

t19

t18

t22

t21

CL[1]

FRM

M

t23

DD[3:0]

NOTES:

1) The figure shows the end of a line.

2) If FRM is high during the CL[1] pulse, this marks the first line in the display.

3) CL[2] low time is doubled during the CL[1] high pulse

Figure 16. LCD Controller Timings

4

8

10

9

1

3

5

7

11 12

23

22

6

13

15

14

2

ADCCLK

(SCLK)

nADCCS

(nRFS/TFS)

DI9

DI8

DI7

DI6

ADCIN

(Din)

DI5 DI4

DI3 DI2

DI1

DI0

ADCOUT

(Dout)

DO9 DO8

DO1 DO0

Figure 17. SSI Interface for AD7811/2

100

DS453PP2

EP7209

13

14

15

24 25

1

2

3

4

5

6

7

8

9

10

11

12

ADCCLK

(SCLK)

nADCCS

(nCS)

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

ADCIN

(Din)

ADCOUT

(Dout)

DO15 DO14 DO13 DO12

DO11 DO10

DO1 DO0

Figure 18. SSI Timing Interface for MAX148/9

t33 t32

t31

SSICLK

t40

t35

SSI RX/TXFR

t36

t37

SSITXDA

SSIRXDA

D7

t39

D7

D2

D1

D0

t38

D0

Figure 19. SSI2 Interface Timings

DS453PP2

101

EP7209

Table 57 defines the I/O buffer output characteris-

tics which will apply across the full range of tem-

perature and voltage (i.e., these values are for 3.3

V, +70°C).

6.5

I/O Buffer Characteristics

All I/O buffers on the EP7209 are CMOS threshold

input bidirectional buffers except the oscillator and

power pads. For signals that are nominally inputs,

the output buffer is only enabled during pin test

mode. All output buffers are tristated during system

(hi-Z) test mode. All buffers have a standard

CMOS threshold input stage (apart from the

Schmitt triggered inputs) and CMOS slew rate con-

trolled output stages to reduce system noise.

All propagation delays are specified at 50% V to

DD

50% V , all rise times are specified as 10% V

DD

to 90% V and all fall times are specified as 90%

DD

V

to 10% V

.

DD

Buffer Type

Drive Current

Propagation

Delay (Max)

Rise Time

(Max)

Fall Time

(Max)

Load

I/O strength 1

I/O strength 2

±4 mA

7

5

14

6

14

6

50 pF

±12 mA

Table 57. I/O Buffer Output Characteristics

6.6

JTAG Bandary Scan Signal Ordering

No.

Signal

Type

Strength Reset

State

No.

Signal

Type

Strength Reset

State

1

nCS[5]

VDDIO

VSSIO

EXPCLK

WORD

WRITE

RUN/CLKEN

EXPRDY

TXD[2]

RXD[2]

TDI

Out

Pad Pwr

Pad Gnd

I/O

1

High

PB[1]/

PRDY2

19

20

I/O

1

Input

2

PB[0]/

PRDY1

3

4

1

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

VDDIO

TDO

Pad Pwr

Out

I/O

5

Out

Low

1

Tristate

Input

Low

6

Out

PA[7]

7

I/O

PA[6]

I/O

8

In

PA[5]

I/O

9

Out

High

PA[4]

I/O

10

11

12

13

14

15

16

17

18

In

PA[3]

I/O

In

with p/u*

PA[2]

I/O

VSSIO

PB[7]

Pad Gnd

I/O

PA[1]

I/O

1

Input

PA[0]

I/O

PB[6]

I/O

LEDDRV

TXD[1]

VSSIO

PHDIN

CTS

Out

Pad Gnd

In

PB[5]

I/O

High

PB[4]

I/O

PB[3]

I/O

PB[2]

I/O

In

RXD[1]

In

Table 58. 208-Pin LQFP Numeric Pin Listing

Table 58. 208-Pin LQFP Numeric Pin Listing (cont.)

102

DS453PP2

EP7209

No.

Signal

Type

Strength Reset

State

No.

Signal

Type

Strength Reset

State

37

38

39

40

41

42

43

44

DCD

In

Core

Gnd

71

VSSCORE

DSR

72

73

74

VDDCORE

VSSIO

Core Pwr

Pad Gnd

Pad Pwr

nTEST[1]

nTEST[0]

EINT[3]

nEINT[2]

nEINT[1]

nEXTFIQ

With p/u*

VDDIO

High/

Low

75

76

DRIVE[1]

DRIVE[0]

I/O

1

High/

Low

1

PE[2]/

CLKSEL

77

78

ADCCLK

ADCOUT

SMPCLK

FB[1]

Out

1

Low

45

46

47

I/O

1

Input

PE[1]/

BOOTSEL[1]

79

Out

80

In

PE[0]/

BOOTSEL[0]

81

VSSIO

FB[0]

Pad Gnd

In

48

49

50

VSSRTC

RTCOUT

RTCIN

RTC Gnd

Out

82

83

COL[7]

COL[6]

COL[5]

COL[4]

COL[3]

COL[2]

VDDIO

TCLK

Out

1

High

In

84

Out

RTC

power

85

Out

51

VSSRTC

86

Out

52

53

54

55

56

57

58

59

60

61

N/C

PD[7]

PD[6]

PD[5]

PD[4]

VDDIO

TMS

87

Out

I/O

1

Low

88

Out

89

Pad Pwr

In

I/O

90

I/O

91

COL[1]

COL[0]

BUZ

Out

1

High

Low

Pad Pwr

In

92

Out

with p/u*

93

Out

PD[3]

PD[2]

PD[1]

I/O

1

Low

94

D[31]

I/O

95

D[30]

I/O

96

D[29]

I/O

PD[0]/

LEDFLSH

97

D[28]

I/O

62

I/O

1

Low

98

VSSIO

A[27]

Pad Gnd

Out

63

64

65

66

67

68

69

70

SSICLK

VSSIO

I/O

Pad Gnd

I/O

Input

99

2

1

2

1

2

1

Low

—

100

101

102

103

104

105

106

107

D[27]

I/O

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

ADCIN

1

Low

A[26]

Out

D[26]

I/O

In

A[25]

Out

I/O

Input

High

D[25]

I/O

In

HALFWORD

A[24]

Out

nADCCS

Out

1

Out

Table 58. 208-Pin LQFP Numeric Pin Listing (cont.)

VDDIO

Pad Pwr

Table 58. 208-Pin LQFP Numeric Pin Listing (cont.)

DS453PP2

103

EP7209

No.

Signal

Type

Strength Reset

State

No.

Signal

Type

Strength Reset

State

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

VSSIO

D[24]

A[23]

D[23]

A[22]

D[22]

A[21]

D[21]

VSSIO

A[20]

D[20]

A[19]

D[19]

A[18]

D[18]

VDDIO

VSSIO

nTRST

A[17]

D[17]

A[16]

D[16]

A[15]]

D[15]

A[14]

D[14]

A[13]

D[13]

A[12]

D[12]

A[11]

VDDIO

VSSIO

D[11]

A[10]

D[10]

A[9]

Pad Gnd

I/O

—

147

148

149

150

151

152

153

154

D[8]

A[7]

I/O

1

Low

1

Low

Out

VSSIO

D[7]

Pad Gnd

I/O

In

1

Low

Out

nBATCHG

nEXTPWR

BATOK

nPOR

I/O

In

Out

In

I/O

In

Schmitt

Pad Gnd

Out

nMEDCHG/

nBROM

155

In

1

Low

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

nURESET

VDDOSC

MOSCIN

MOSCOUT

VSSOSC

WAKEUP

nPWRFL

A[6]

In

Osc Pwr

Osc

I/O

Out

I/O

Osc

Out

Osc Gnd

In

I/O

Schmitt

Pad Pwr

Pad Gnd

In

Out

1

Low

D[6]

I/O

Out

1

Low

A[5]

Out

I/O

D[5]

I/O

Out

VDDIO

VSSIO

A[4]

Pad Pwr

Pad Gnd

Out

I/O

Out

1

2

1

2

Low

I/O

D[4]

I/O

Out

A[3]

Out

I/O

D[3]

I/O

Out

A[2]

Out

I/O

VSSIO

D[2]

Pad Gnd

I/O

Out

1

Low

I/O

A[1]

Out

D[1]

I/O

Pad Pwr

Pad Gnd

I/O

A[0]

Out

D[0]

I/O

1

Low

VSS CORE

VDD CORE

VSSIO

VDDIO

CL[2]

Core Gnd

Core Pwr

Pad Gnd

Pad Pwr

Out

I/O

Out

D[9]

I/O

1

Low

A[8]

Out

Table 58. 208-Pin LQFP Numeric Pin Listing (cont.)

104

DS453PP2

EP7209

No.

Signal

Type

Strength Reset

State

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

CL[1]

FRM

Out

1

Low

M

Out

DD[3]

DD[2]

VSSIO

DD[1]

DD[0]

N/C

I/O

Pad Gnd

I/O

1

Low

I/O

N/C

VDDIO

VSSIO

N/C

Pad Pwr

Pad Gnd

N/C

nMWE

nMOE

VSSIO

nCS[0]

nCS[1]

nCS[2]

nCS[3]

nCS[4]

Out

1

High

Pad Gnd

Out

1

High

Out

NOTE:

‘With p/u’ means with internal pull-up on

the pin.

Table 58. 208-Pin LQFP Numeric Pin Listing (cont.)

DS453PP2

105

EP7209

7. TEST MODES

7.2

Oscillator and PLL Test Mode

The EP7209 supports a number of hardware acti-

vated test modes, these are activated by the pin

combinations shown in Table 59. All latched sig-

nals will only alter test modes while NPOR is low,

their state is latched on the rising edge of NPOR.

This allows these signals to be used normally dur-

ing various test modes.

This mode is selected by nTEST[0] = 0,

nTEST[1] = 1, Latched nURESET = 0

This test mode will enable the main oscillator and

it will output various buffered clock and test signals

derived from the main oscillator, PLL, and 32-kHz

oscillator. All internal logic in the EP7209 will be

static and isolated from the oscillators, with the ex-

Within each test mode, a selection of pins is used as ception of the 6-bit ripple counter used to generate

multiplexed outputs or inputs to provide/monitor 576 kHz and the Real Time Clock divide chain.

the test signals unique to that mode.

Port A is used to drive the inputs of the PLL direct-

ly, and the various clock and PLL outputs are mon-

itored on the COL pins. Table 60 defines the

EP7209 signal pins used in this test mode. This

mode is only intended to allow test of the oscilla-

tors and PLL. Note that these inputs are inverted

before being passed to the PLL to ensure that the

default state of the port (all zero) maps onto the cor-

rect default state of the PLL (TSEL = 1, XTALON

= 1, PLLON = 1, D0 = 0, D1 = 1, PLLBP = 0). This

state will produce the correct frequencies as shown

in Table 60. Any other combinations are for testing

the oscillator and PLL and should not be used in-

circuit.

7.1 Oscillator and PLL Bypass Mode

This mode is selected by nTEST[0] = 1,

nTEST[1] = 0.

In this mode all the internal oscillators and PLL are

disabled and the appropriate crystal oscillator pins

become the direct external oscillator inputs bypass-

ing the oscillator and PLL. MOSCIN must be driv-

en by a 36.864 MHz clock source and RTCIN by a

32.768 kHz source.

Test Mode

Latched

nMEDCHG

Latched

PE[0]

Latched

PE[1]

Latched

nURESET

nTEST[0]

nTEST[1]

Normal operation

(32-bit boot)

1

0

1

0

1

X

1

Normal operation

(8-bit boot)

Normal operation

(16-bit boot)

Alternative test ROM

boot

0

X

0

1

0

1

0

1

Oscillator / PLL bypass

Oscillator / PLL test

mode

ICE Mode

X

1

0

System test (all HiZ)

Table 59. EP7209 Hardware Test Modes

106

DS453PP2

EP7209

Signal

TSEL *

XTLON *

PLLON *

PLLBP

I/O

I

PA5

Function

PLL test mode

I

PA4

Enable to oscillator circuit

Enable to PLL circuit

Bypasses PLL

I

PA3

I

PA0

RTCCLK

CLK1

O

COL0

COL1

COL2

COL4

COL6

Output of RTC oscillator

1 Hz clock from RTC divider chain

36 MHz divided PLL main clock

576 KHz divided from above

Test clock output for PLL

OSC36

CLK576K

VREF

Table 60. Oscillator and PLL Test Mode Signals

range for nCS[5]. Additionally, in this mode, the

internal signals shown in Table 61 are multiplexed

out of the device on port pins.

7.3

Debug/ICE Test Mode

This mode is selected by nTEST0 = 0, nTEST1 =

0, Latched nURESET = 1.

Selection of this mode enables the debug mode of

the ARM720T. By default, this is disabled which

saves approximately 3% on power.

Signal

CLK

I/O

O

PE0

PE1

PE2

Function

Waited clock to CPU

nFIQ interrupt to CPU

nIRQ interrupt to CPU

nFIQ

O

7.4

Hi-Z (System) Test Mode

nIRQ

O

This mode selected by nTEST0 = 0, nTEST1 = 0,

Latched nURESET = 0.

Table 61. Software Selectable Test Functionality

This test mode asynchronously disables all output

buffers on the EP7209. This has the effect of re-

moving the EP7209 from the PCB so that other de-

vices on the PCB can be in-circuit tested. The

internal state of the EP7209 is not altered directly

by this test mode.

This test is not intended to be used when LCD

DMA accesses are enabled. This is due to the fact

that it is possible to have internal peripheral bus ac-

tivity simultaneously with a DMA transfer. This

would cause bus contention to occur on the external

bus.

7.5

Software Selectable Test

Functionality

The ‘Waited clock to CPU’ is an internally ANDed

source that generates the actual CPU clock. Thus, it

is possible to know exactly when the CPU is being

clocked by viewing this pin. The signals nFIQ and

nIRQ are the two output signals from the internal

interrupt controller. They are input directly into the

ARM720T processor.

When bit 11 of the SYSCON register is set high, in-

ternal peripheral bus register accesses are output on

the main address and data buses as though they

were external accesses to the address space ad-

dressed by nCS[5]. Hence, nCS[5] takes on a dual

role, it will be active as the strobe for internal ac-

cesses and for any accesses to the standard address

DS453PP2

107

EP7209

8. PIN INFORMATION

8.1 208-Pin LQFP Pin Diagram

D[25]

A[25]

D[26]

A[26]

D[27]

A[27]

VSSIO

D[28]

D[29]

D[30]

D[31]

BUZ

COL[0]

COL[1]

TCLK

VDDIO

COL[2]

COL[3]

COL[4]

COL[5]

COL[6]

COL[7]

FB[0]

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

VDDOSC

MOSCIN

MOSCOUT

VSSOSC

WAKEUP

NPWRFL

A[6]

D[6]

A[5]

D[5]

VDDIO

VSSIO

A[4]

D[4]

A[3]

D[3]

A[2]

VSSIO

D[2]

A[1]

D[1]

A[0]

D[0]

VSSIO

FB[1]

EP7209

208-Pin LQFP

VSSCORE

VDDCORE

VSSIO

VDDIO

CL[2]

SMPCLK

ADCOUT

ADCCLK

DRIVE[0]

DRIVE[1]

VDDIO

VSSIO

VDDCORE

VSSCORE

NADCCS

ADCIN

SSIRXFR

SSIRXDA

SSITXDA

SSITXFR

VSSIO

SSICLK

PD[0]/LEDFLSH

PD[1]

PD[2]

PD[3]

TMS

VDDIO

PD[4]

PD[5]

PD[6]

PD[7]

CL[1]

FRM

M

DD[3]

DD[2]

VSSIO

DD[1]

DD[0]

N/C

VDDIO

VSSIO

N/C

(Top View)

N/C

NMWE

NMOE

VSSIO

NCS[0]

NCS[1]

NCS[2]

NCS[3]

NCS[4]

Notes:

1) For package specifications, please see 208--Pin LQFP Package Outline Drawing on page 117

2) N/C should not be grounded but left as no connects

Figure 20. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

108

DS453PP2

EP7209

8.2

208-Pin LQFP Numeric Pin Listing

No.

Signal

Type

Strength Reset

State

No.

Signal

Type

Strength Reset

State

36

37

38

39

40

41

42

43

44

RXD[1]

DCD

In

1

nCS[5]

VDDIO

VSSIO

EXPCLK

WORD

WRITE

RUN/CLKEN

EXPRDY

TXD[2]

RXD[2]

TDI

Out

Pad Pwr

Pad Gnd

I/O

1

High

DSR

2

nTEST[1]

nTEST[0]

EINT[3]

nEINT[2]

nEINT[1]

nEXTFIQ

With p/u*

3

4

1

5

Out

Low

6

Out

7

I/O

8

In

PE[2]/

CLKSEL

9

Out

High

45

46

47

I/O

1

Input

10

11

12

13

14

15

16

17

18

In

PE[1]/

BOOTSEL[1]

In

with p/u*

VSSIO

PB[7]

Pad Gnd

I/O

PE[0]/

BOOTSEL[0]

1

Input

PB[6]

I/O

48

49

50

VSSRTC

RTCOUT

RTCIN

RTC Gnd

Out

PB[5]

I/O

PB[4]

I/O

In

PB[3]

I/O

RTC

power

51

VSSRTC

PB[2]

I/O

52

53

54

55

56

57

58

59

60

61

N/C

PD[7]

PD[6]

PD[5]

PD[4]

VDDIO

TMS

PB[1]/

PRDY2

19

20

I/O

1

Input

I/O

1

Low

PB[0]/

PRDY1

I/O

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

VDDIO

TDO

Pad Pwr

Out

I/O

1

Tristate

Input

Low

Pad Pwr

In

PA[7]

with p/u*

PA[6]

I/O

PD[3]

PD[2]

PD[1]

I/O

1

Low

PA[5]

I/O

PA[4]

I/O

PA[3]

I/O

PD[0]/

LEDFLSH

62

I/O

1

Low

PA[2]

I/O

PA[1]

I/O

63

64

65

66

67

68

69

SSICLK

VSSIO

I/O

Pad Gnd

I/O

Input

PA[0]

I/O

LEDDRV

TXD[1]

VSSIO

PHDIN

CTS

Out

Pad Gnd

In

SSITXFR

SSITXDA

SSIRXDA

SSIRXFR

ADCIN

1

Low

High

Out

In

I/O

Input

In

Table 62. 208-Pin LQFP Numeric Pin Listing

Table 62. 208-Pin LQFP Numeric Pin Listing (cont.)

DS453PP2

109

EP7209

No.

Signal

Type

Strength Reset

State

No.

Signal

Type

Strength Reset

State

70

nADCCS

Out

1

High

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

VDDIO

VSSIO

D[24]

A[23]

D[23]

A[22]

D[22]

A[21]

D[21]

VSSIO

A[20]

D[20]

A[19]

D[19]

A[18]

D[18]

VDDIO

VSSIO

nTRST

A[17]

D[17]

A[16]

D[16]

A[15]]

D[15]

A[14]

D[14]

A[13]

D[13]

A[12]

D[12]

A[11]

Pad Pwr

Pad Gnd

I/O

—

Core

Gnd

71

VSSCORE

1

Low

72

73

74

VDDCORE

VSSIO

Core Pwr

Pad Gnd

Pad Pwr

Out

I/O

VDDIO

Out

High/

Low

I/O

75

76

DRIVE[1]

DRIVE[0]

I/O

2

Out

High/

Low

I/O

Pad Gnd

Out

77

78

ADCCLK

ADCOUT

SMPCLK

FB[1]

Out

In

1

Low

1

Low

I/O

79

Out

80

I/O

81

VSSIO

FB[0]

Pad Gnd

In

Out

82

I/O

83

COL[7]

COL[6]

COL[5]

COL[4]

COL[3]

COL[2]

VDDIO

TCLK

Out

Pad Pwr

In

1

High

Pad Pwr

Pad Gnd

In

84

85

86

Out

1

Low

87

I/O

88

Out

89

I/O

90

Out

91

COL[1]

COL[0]

BUZ

Out

I/O

1

High

Low

I/O

92

Out

93

I/O

94

D[31]

Out

95

D[30]

I/O

96

D[29]

I/O

Out

97

D[28]

I/O

98

VSSIO

A[27]

Pad Gnd

Out

I/O

Out

99

2

1

2

1

2

1

Low

VDDIO

VSSIO

D[11]

A[10]

D[10]

A[9]

Pad Pwr

Pad Gnd

I/O

100

101

102

103

104

105

106

D[27]

A[26]

Out

I/O

1

Low

D[26]

Out

A[25]

Out

I/O

D[25]

Out

HALFWORD

A[24]

Out

D[9]

I/O

Table 62. 208-Pin LQFP Numeric Pin Listing (cont.)

110

DS453PP2

EP7209

No.

Signal

Type

Strength Reset

State

No.

Signal

Type

Strength Reset

State

146

147

148

149

150

151

152

153

154

A[8]

D[8]

Out

I/O

1

Low

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

CL[2]

CL[1]

FRM

Out

1

Low

A[7]

Out

Pad Gnd

I/O

Out

VSSIO

D[7]

M

Out

1

Low

DD[3]

DD[2]

VSSIO

DD[1]

DD[0]

N/C

I/O

nBATCHG

nEXTPWR

BATOK

nPOR

In

I/O

In

Pad Gnd

I/O

In

1

Low

In

Schmitt

I/O

nMEDCHG/

nBROM

155

In

N/C

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

nURESET

VDDOSC

MOSCIN

MOSCOUT

VSSOSC

WAKEUP

nPWRFL

A[6]

In

Osc Pwr

Osc

N/C

VDDIO

VSSIO

N/C

Pad Pwr

Pad Gnd

Osc

Osc Gnd

In

Schmitt

N/C

In

nMWE

nMOE

VSSIO

nCS[0]

nCS[1]

nCS[2]

nCS[3]

nCS[4]

Out

1

High

Out

1

Low

D[6]

I/O

Pad Gnd

Out

A[5]

Out

1

High

D[5]

I/O

Out

VDDIO

VSSIO

A[4]

Pad Pwr

Pad Gnd

Out

1

2

1

2

Low

Out

D[4]

I/O

A[3]

Out

NOTE:

‘With p/u’ means with internal pull-up on

the pin.

D[3]

I/O

A[2]

Out

Table 62. 208-Pin LQFP Numeric Pin Listing (cont.)

VSSIO

D[2]

Pad Gnd

I/O

1

2

1

2

1

Low

A[1]

Out

D[1]

I/O

A[0]

Out

D[0]

I/O

VSS CORE

VDD CORE

VSSIO

VDDIO

Core Gnd

Core Pwr

Pad Gnd

Pad Pwr

Table 62. 208-Pin LQFP Numeric Pin Listing (cont.)

DS453PP2

111

EP7209

8.3

256-Pin PBGA Pin Diagram

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

256-Ball PBGA

(Bottom View)

NOTE:

For package specifications, please see 256-Ball PBGA Dimensions page 118

112

DS453PP2

EP7209

8.4

256-Ball PBGA Ball Listing

Ball

Name

Type

Location

Ball

Location

Name

Type

C5

C6

VSSIO

VDDIO

VSSIO

VDDIO

VSSIO

nPOR

nEXTPWR

WRITE

EXPRDY

VSSIO

VDDIO

nCS[2]

nMWE

N/C

Pad ground

A1

A2

VDDIO

nCS[4]

nCS[1]

NC

Pad power

C7

Pad ground

O

C8

Pad power

A3

O

C9

Pad ground

A4

No Connect

C10

C11

C12

C13

C14

C15

C16

D1

Pad ground

A5

NC

No Connect

Pad ground

A6

DD[1]

O

Pad power

A7

M

O

Pad ground

A8

VDDIO

D[0]

Pad power

Pad ground

A9

I/O

I

A10

A11

A12

A13

A14

A15

A16

B1

D[2]

I/O

I

A[3]

O

VDDIO

A[6]

Pad power

D2

I

O

D3

Pad ground

MOSCOUT

VDDOSC

VSSIO

nCS[5]

VDDIO

nCS[3]

nMOE

VDDIO

N/C

O

D4

Pad power

Oscillator power

D5

O

Pad ground

D6

O

D7

No Connect

B2

Pad power

D8

CL[2]

O

B3

O

D9

VSSRTC

D[4]

Core ground

B4

O

D10

D11

D12

D13

D14

D15

D16

E1

I/O

B5

Pad power

nPWRFL

MOSCIN

VDDIO

VSSIO

D[7]

I

B6

No Connect

I

B7

DD[2]

O

Pad power

B8

CL[1]

O

Pad ground

B9

VDDCORE

D[1]

Core power

I/O

B10

B11

B12

B13

B14

B15

B16

C1

I/O

D[8]

I/O

A[2]

O

RXD[2]

PB[7]

I

A[4]

O

E2

I

A[5]

O

E3

TDI

I

WAKEUP

VDDIO

nURESET

VDDIO

EXPCLK

VSSIO

VDDIO

I

E4

WORD

VSSIO

nCS[0]

NC

O

Pad power

I

E5

Pad ground

E6

O

Pad power

I

E7

No Connect

C2

E8

FRM

O

C3

Pad ground

Pad power

E9

A[0]

C4

Table 63. 256-Ball PBGA Ball Listing (cont.)

Table 63. 256-Ball PBGA Ball Listing

DS453PP2

113

EP7209

Ball

Name

Type

Ball

Name

Type

Location

E10

E11

E12

E13

E14

E15

E16

F1

D[5]

VSSOSC

VSSIO

nMEDCHG/nBROM

VDDIO

D[9]

I/O

H1

H2

H3

H4

H5

H6

H7

H8

H9

H10

H11

H12

H13

H14

H15

H16

J1

PA[7]

PA[5]

I

Oscillator ground

I

Pad ground

VSSIO

PA[4]

Pad ground

I

Pad power

PA[6]

I

I/O

PB[0]/PRDY[1]

PB[2]

I

D[10]

I/O

I

PB[5]

I

VSSRTC

A[10]

RTC ground

F2

PB[3]

I

RTC ground

F3

VSSIO

TXD[2]

RUN/CLKEN

VSSIO

NC

Pad ground

O

F4

O

A[11]

O

F5

O

A[12]

O

F6

Pad ground

A[13]

O

F7

No Connect

VSSIO

D[14]

Pad ground

F8

DD[3]

O

I/O

F9

A[1]

O

D[15]

I/O

F10

F11

F12

F13

F14

F15

F16

G1

D[6]

I/O

PA[3]

I

VSSRTC

BATOK

nBATCHG

VSSIO

D[11]

RTC ground

J2

PA[1]

I

J3

VSSIO

PA[2]

Pad ground

I

J4

I

Pad ground

J5

PA[0]

I

I/O

J6

TXD[1]

CTS

O

VDDIO

PB[1]/PRDY[2]

VDDIO

TDO

Pad power

J7

I

J8

VSSRTC

A[17]

RTC ground

G2

Pad power

J9

RTC ground

G3

O

J10

J11

J12

J13

J14

J15

J16

K1

O

G4

PB[4]

I

A[16]

O

G5

PB[6]

I

A[15]

O

G6

VSSRTC

DD[0]

Core ground

A[14]

O

G7

RTC ground

nTRST

D[16]

I

G8

O

I/O

G9

D[3]

I/O

D[17]

I/O

G10

G11

G12

G13

G14

G15

G16

VSSRTC

A[7]

RTC ground

LEDDRV

PHDIN

VSSIO

DCD

O

K2

I

A[8]

O

K3

Pad ground

A[9]

O

Pad ground

I/O

K4

I

VSSIO

D[12]

K5

nTEST[1]

EINT[3]

VSSRTC

I

K6

I

D[13]

I/O

K7

RTC ground

Table 63. 256-Ball PBGA Ball Listing (cont.)

114

DS453PP2

EP7209

Ball

Name

Type

Ball

Name

Type

Location

K8

K9

ADCIN

COL[4]

TCLK

I

M15

M16

N1

A[20]

D[21]

O

I/O

K10

K11

K12

K13

K14

K15

K16

L1

I

nEXTFIQ

PE[1]/BOOTSEL[1]

VSSIO

I

D[20]

I/O

N2

D[19]

I/O

N3

Pad ground

Pad power

I/O

D[18]

I/O

N4

VDDIO

PD[5]

VSSIO

Pad ground

N5

VDDIO

RXD[1]

DSR

Pad power

N6

PD[2]

I/O

Pad power

N7

SSIRXDA

ADCCLK

SMPCLK

COL[2]

D[29]

I/O

I

N8

O

L2

I

N9

O

L3

VDDIO

nEINT[1]

PE[2]/CLKSEL

VSSRTC

PD[0]/LEDFLSH

VSSRTC

COL[6]

D[31]

Pad power

N10

N11

N12

N13

N14

N15

N16

P1

O

L4

I

I/O

L5

I

D[26]

I/O

L6

RTC ground

HALFWORD

VSSIO

O

L7

I/O

Pad ground

I/O

L8

Core ground

D[22]

L9

O

D[23]

I/O

L10

L11

L12

L13

L14

L15

L16

M1

M2

M3

M4

M5

M6

M7

M8

M9

M10

M11

M12

M13

M14

I/O

VSSRTC

RTCOUT

VSSIO

RTC ground

O

VSSRTC

A[22]

RTC ground

P2

O

P3

Pad ground

Pad power

Pad ground

Pad power

Pad ground

Pad power

Pad ground

Pad power

Pad ground

I/O

A[21]

O

P4

VSSIO

Pad ground

P5

VDDIO

VSSIO

A[18]

O

P6

A[19]

O

P7

VSSIO

nTEST[0]

nEINT[2]

VDDIO

PE[0]/BOOTSEL[0]

TMS

I

P8

VDDIO

VSSIO

I

P9

Pad power

P10

P11

P12

P13

P14

P15

P16

R1

VDDIO

VSSIO

I

VSSIO

VDDIO

SSITXFR

DRIVE[1]

FB[0]

Pad power

VDDIO

VSSIO

I/O

D[24]

I

VDDIO

RTCIN

Pad power

I/O

COL[0]

D[27]

O

I/O

R2

VDDIO

PD[4]

Pad power

I/O

VSSIO

Pad ground

O

R3

A[23]

R4

PD[1]

I/O

VDDIO

Pad power

R5

SSITXDA

O

Table 63. 256-Ball PBGA Ball Listing (cont.)

DS453PP2

115

EP7209

Ball

Name

Type

Ball

Name

Type

Location

R6

R7

nADCCS

VDDIO

ADCOUT

COL[7]

COL[3]

COL[1]

D[30]

O

T12

T13

T14

T15

T16

BUZ

D[28]

A[26]

O

Pad power

I/O

R8

O

I/O

R9

O

D[25]

VSSIO

R10

R11

R12

R13

R14

R15

R16

T1

O

Pad ground

O

Table 63. 256-Ball PBGA Ball Listing (cont.)

I/O

A[27]

O

8.4.1

PBGA Ground Connections

A[25]

O

Table 64 lists the balls on the PBGA package that

must be connected to ground. These extra leads are

not used on the PBGA package.

VDDIO

A[24]

Pad power

O

VDDRTC

PD[7]

RTC power

T2

I/O

A16

E5 E11 E12

J3 J8 J9

N3 N14

T3

PD[6]

I/O

P1 P3 P4 P6

P7 P9 P11

P12 P14

F3 F6 F11

F14

T4

PD[3]

I/O

K3 K7 K14

T5

SSICLK

SSIRXFR

VDDCORE

DRIVE[0]

FB[1]

I/O

C3 C5 C6 C7

C9 C10 C11

C13 C14

T6

–

G6 G7 G10

G14

L6 L8 L11 L14

M12

T16

T7

Core power

T8

I/O

H3 H8 H9

H14

D3 D9 D14

T9

I

O

T10

T11

COL[5]

VDDIO

Table 64. PBGA Balls to Connect to Ground (V_SS)

Pad power

Table 63. 256-Ball PBGA Ball Listing (cont.)

116

DS453PP2

EP7209

9. PACKAGE SPECIFICATIONS

9.1 208-Pin LQFP Package Outline Drawing

29.60 (1.165)

30.40 (1.197)

27.80 (1.094)

28.20 (1.110)

0.17 (0.007)

0.27 (0.011)

27.80 (1.094)

28.20 (1.110)

29.60 (1.165)

30.40 (1.197)

EP7209

208-Pin LQFP

0.50

(0.0197)

BSC

Pin 1 Indicator

Pin 208

Pin 1

1.35 (0.053)

1.45 (0.057)

1.00 (0.039) BSC

0.45 (0.018)

0.75 (0.030)

0.09 (0.004)

0.20 (0.008)

0° MIN

7° MAX

0.05 (0.002)

0.15 (0.006)

1.40 (0.055)

1.60 (0.063)

NOTES:

1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.

2) Drawing above does not reflect exact package pin count.

3) Before beginning any new design with this device, please contact Cirrus Logic for

the latest package information.

4) For pin description, please see 208-Pin LQFP Pin Diagram page 12

DS453PP2

117

EP7209

9.2

EP7209 256-Ball PBGA (17 × 17 × 1.53-mm Body) Dimensions

0.80 (0.032)

±0.05 (.002)

17.00 (0.669)

0.40 (0.016)

±0.10 (.004)

Pin 1 Corner

+0.70 (.027)

-0.00

(0.590)

15.00

30° TYP

Pin 1 Indicator

17.00 (0.669)

15.00 (0.590)

+0.70 (.027)

-0.00

4 Layer

0.56 (0.022)

±0.06 (0.002)

2 Layer

0.36 (0.022)

+0.04 (0.001)

–0.06 (0.002)

TOP VIEW

SIDE VIEW

Pin 1 Corner

17.00 (0.669)

1.00 (0.040)

REF

16 15 14 13 12 11 109 8 7 6 5 4 3 21

1.00 (0.040)

REF

A

B

C

D

E

F

G

H

J

K

L

1.00 (0.040)

17.00 (0.669)

M

N

P

R

T

0.50

R

BOTTOM VIEW

3 Places

NOTE:

118

For pin description, please see 256-Ball PBGA Pin Diagram page 112

DS453PP2

EP7209

10. ORDERING INFORMATION

The order number for the device is:

EP7209 — CV — A

Revision †

Package Type:

V = Low Profile Quad Flat Pack

B = Plastic Ball Grid Array (17 mm x 17 mm)

Temperature Range:

C = Commercial

Part Number

Product Line:

Embedded Processor

NOTE:

† Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site

at http://cirrus.com/corporate/contacts to find contact information for your local sales representa-

tive.

DS453PP2

119

EP7209

11. APPENDIX A: BOOT CODE

;

TTL

CL-EP7209 Sample program

version 1.0 (initial version) ;ks

boot from uart1

;

AREA

|C$$code|,CODE,READONLY

ENTRY

;

System constants

HwBaseAddress

EQU

0x80000000

;

HwControl

HwControl2

EQU

0x00000100

0x00001100

0x00000100

HwControlUartEnable

;

EQU

HwStatus

EQU

0x00000140

0x000001140

0x00400000

HwStatus2

HwStatusUartRxFifoEmpty

;

HwUartData

EQU

0x00000480

0x00001480

0x0100

HwUartData2

HwUartDataFrameErr

HwUartDataParityErr

HwUartDataOverrunErr

HwUartControl

0x0200

0x0400

0x000004C0

0x000014C0

0x00000FFF

0x001

HwUartControl2

HwUartControlRate

HwUartControlRate115200

HwUartControlRate76800

HwUartControlRate57600

HwUartControlRate38400

0x002

0x003

0x005

120

DS453PP2

EP7209

HwUartControlRate19200

HwUartControlRate14400

HwUartControlRate9600

HwUartControlRate4800

HwUartControlRate2400

HwUartControlRate1200

HwUartControlRate600

EQU

0x00B

0x00F

0x017

0x02F

0x05F

0x0BF

0x17F

HwUartControlRate300

0x2FF

HwUartControlRate150

0x5FF

HwUartControlRate110

0x82E

HwUartControlRate115200_13

HwUartControlRate57600_13

HwUartControlRate38400_13

HwUartControlRate19200_13

HwUartControlRate14400_13

HwUartControlRate9600_13

HwUartControlRate4800_13

HwUartControlRate2400_13

HwUartControlRate1200_13

HwUartControlRate600_13

HwUartControlRate300_13

HwUartControlRate150_13

HwUartControlRate110_13

HwUartControlBreak

0x000

0x001

0x002

0x005

0x007

0x00b

0x017

0x02F

0x060

0x0c0

0x182

0x305

0x41E

0x00001000

0x00002000

0x00004000

0x00008000

0x00010000

0x00060000

0x00000000

0x00020000

0x00040000

0x00060000

HwUartControlParityEnable

HwUartControlPartiyEvenOrOdd

HwUartControlTwoStopBits

HwUartControlFifoEnable

HwUartControlDataLength

HwUartControlDataLength5

HwUartControlDataLength6

HwUartControlDataLength7

HwUartControlDataLength8

;

9600baud, 8bits/ch no parity, 1 stop bit

UartValue

EQU

HwUartControlRate9600+HwUartControlDataLength8

HwUartControlRate9600_13+HwUartControlDataLength8

UartValue_13

BufferAddress

codeexeaddr

count

0x10000000

0x00000800

;start address sram snooze buffer

;

;2k bytes

DS453PP2

121

EP7209

startflag

endflag

CLKMOD

EQU

’<’

’>’

0x40

;clock mode 1 = 13 MHz

;

ARM Processor constants

ArmIrqDisable

ArmFiqDisable

EQU

0x00000080

0x00000040

; 26bit mode is not supported

;

ArmUserMode

ArmFIQMode

ArmIRQMode

ArmSVCMode

ArmAbortMode

ArmUndefMode

ArmMaskMode

;

EQU

0x10

0x11

0x12

0x13

0x17

0x1B

0x1F

ArmMmuCP

CP

CN

0xF

;

ArmMmuId

0x00

0x01

;

ArmMmuControl

ArmMmuControlMmuEnable

EQU

0x00000001

ArmMmuControlAlignFaultEnable

ArmMmuControlCacheEnable

0x00000002

0x00000004

0x00000008

0x00000010

0x00000020

0x00000040

0x00000080

0x00000100

0x00000200

ArmMmuControlWriteBufferEnable EQU

ArmMmuControl32BitCodeEnable

ArmMmuControl32BitDataEnable

ArmMmuControlMandatory

ArmMmuControlBigEndianEnable

ArmMmuControlSystemEnable

ArmMmuControlRomEnable

;

EQU

ArmMmuPageTableBase

CN

0x02

0x03

0x05

;

ArmMmuDomainAccess

;

ArmMmuFlushTlb

122

DS453PP2

EP7209

;

ArmMmuPurgeTlb

;

CN

0x06

0x07

ArmMmuFlushIdc

;InitialMmuConfig

+ArmMmuControl32BitDataEnable

+ArmMmuControlBigEndianEnable

EQU

ArmMmuControl32BitCodeEnable

+ArmMmuControlMandatory

InitialMmuConfig

EQU

ArmMmuControl32BitCodeEnable

+ArmMmuControl32BitDataEnable +ArmMmuControlMandatory

11/6/96 ks

;leave as little endian

;==============================================================================

======

;

REAL CODE START

;

set little endian, 32bit code, 32bit data by writing to CP15’s control

register

LDR

MCR

r0, =InitialMmuConfig

ArmMmuCP, 0, r0, ArmMmuControl, c0

;

set the cpu to SVC32 mode

MRS

BIC

r0, CPSR

;read psr

r0, r0, #ArmMaskMode

r0, r0, #ArmSVCMode

CPSR, r0

;remove the mode bits

ORR

;set to supervisor 32 bit mode

; Now set the CPU into the new mode

MSR

;

initialize HW control

UARTEnable

LDR

r12,=HwBaseAddress

r0,#HwControlUartEnable

r0,[r12,#HwControl]

r1,=HwStatus2

r1,r1,r12

MOV

;Enable UART

STR

LDR

ADD

LDR

r2,[r1]

;read system flag2

TST

r2,#CLKMOD

LDREQ

LDRNE

r0,=UartValue

r0,=UartValue_13

;load 18 mhz value if bit not set

;load 13 mhz value if bit set

DS453PP2

123

EP7209

STR

r0,[r12,#HwUartControl]

;initialise Uart

; send ready

;

Send ready signal

LDR

r0,=startflag

STRB

r0,[r12,#HwUartData]

receive the data

LDR

r3,=count

r2,=BufferAddress

01

;

wait for byte available

r1,[r12,#HwStatus]

r1,#HwStatusUartRxFifoEmpty

%b01

LDR

TST

BNE

; spin, if Rx FIFO is empty

;

read the data ,store it and accumulate checksum

LDRB

STRB

SUBS

BNE

r0,[r12,#HwUartData]

r0,[r2],#1

r3,r3,#1

; read data

; save it in memory

; decrement count

%b01

; do more if count has not expired

all received, send end flag

r0,=endflag

LDR

STRB

LDR

r0,[r12,#HwUartData]

r15,=codeexeaddr

; send reply

;jump to execution address

LTORG

END

124

DS453PP2

EP7209

F

12. INDEX

functional block diagram 19

functional description 18

Symbols

/ BOOTSEL0 15

/ BOOTSEL1 15

/ CLKSEL 15

/ LEDFLSH 15

/PRDY1 15

I

idle state 28

iInternal UARTs 34

in-circuit emulation 48

interrupt Ccontroller 23

Numerics

L

pin information

PB 15

LCD controller 43

PD 15

PE 15

DRIVE 15

FB 15

M

memory and I/O expansion interface 30

CL-EP7211 boot ROM 29

NTEST 16

A 13

NCS 13

pin information

DD 15

O

operating state 28

P

NCS 13

D 13

COL 15

PA 15

PD 15

PB 15

PADDR Port A Data Direction Register 54

PADR Port A Data Register 54

PBDR Port B Data Register 54

PBGA ground connections 116

PDDDR Port D Data Direction Register 55

PDDR Port D Data Register 54

PE 15

PEDDR Port E Data Direction Register 55

NEINT 14

RXD 15

TXD 15

PE 15

pin descriptions, external signal functions 13

pin diagram 12, 108

pin information

ADCCLK 15

ADCIN 15

/PRDY2 PB 15

pin information

NCS 13

ADCOUT 15

BATOK 14

BUZ 15

CL1 15

CL2 15

B

boundary scan 47

CTS 15

DCD 15

DSR 15

EINT3 14

EXPCLK 13

EXPRDY 13

FRM 15

LEDDRV 15

M 15

C

clocks 23

external clock input (13 MHz) 24

on-chip PLL 23

CPU core 19

D

dedicated LED flasher 47

MOSCIN 16

MOSCOUT 16

NADCCS 15

NBATCHG 14

E

endianness 33

DS453PP2

125

EP7209

NEXTFIQ 14

NEXTPWR 14

NMEDCHG/ BROM 14

NMOE 13

NMWE 13

NPOR 14

NPWRFL 14

NURESET 14

PHDIN 15

S

serial interface

ADC iInterface 39

clock polarity 43

continuous data transfer 43

discontinuous clock 43

error conditions 43

MCP interface 37

MCP operation 38

RTCIN 16

readback of residual data 42

support for asymmetric traffic 42

serial interfaces 34

codec sound interface 36

SIR encoder 34

standby state 28

state control 20

SYSFLG, The System Status Flags Register 62

RTCOUT 16

RUN/CLKEN 14

SMPCLK 15

SSICLK 14

SSIRXDA 14

SSIRXFR 14

SSITXDA 14

SSITXFR 14

TCLK 16

TDI 16

TDO 16

TMS 16

TNRST 16

T

timer counters 45

free running mode 46

prescale mode 46

WAKEUP 14

WRITE 13

PWM interface 47

U

UART 19

R

realtime clock 46

resets 23

126

DS453PP2


型号：	EP7209
厂家：	CIRRUS LOGIC
描述：	Ultra-Low-Power Audio Decoder System-on-Chip 超低功耗音频解码器系统级芯片解码器
文件：	总128页 (文件大小：1385K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EP7209 [CIRRUS]

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