CS7808_技术文档

CS7808

Multi-Purpose Audio/Video Embedded Processor

Features

Description

The CS7808 processor is a single chip solution that pro-

vides all of the processing functions you need for a broad

range of audio and video applications including thin me-

dia clients, CD recorders, advanced set-top boxes,

interactive TV and much more. It supports all CD for-

mats, disk control, video decoding and up to eight

channels of output. Achieve new levels of performance

with 240 highly configurable MIPS of processing power.

Its flexible set of design features maximizes perfor-

mance, reduces system complexity, and minimizes

system cost. CS7808 is the perfect choice.

! Dual 32-bit RISC processors (81 MIPS each)

! 32-bit DSP (81 MIPS)

! Digital video input for Picture-in-Picture (PIP)

! On-screen display generator

! 8-bit graphic engine with advanced vertical flicker filter

! Programmable audio decoder

! MPEG1 & MPEG2 video decoder

! System interface supports ATAPI CD loaders and

hard disk drives

! Host interface supports peripherals such as 10/100

Ethernet controllers, DSPs, etc.

! V.90 soft-modem support

! AC'97 link support

! 2 channels of audio input

! 8 channels of audio output

! 2 channel IEC60958 transmitter

! Remote control input support

! Large number of GPIO increases design flexibility

! On-chip PLLs generate system clocks from 27 MHz

! SDRAM, SGRAM, and Flash memory support

! Available in a 208 pin MQFP

Working on your next consumer entertainment product

design? Combine CS7808 with other Cirrus mixed-sig-

nal converters, DSP chips, and factory firmware for a

highly integrated platform crucial for Video-on-demand,

set-top boxes, and other similar platforms. CS7808 is a

Total-E™ (Total Entertainment) IC solution specifically

designed for consumer entertainment electronics.

ORDERING INFORMATION

CS7808-CM

0° to 70° C

208-pin MQFP

RISC-1

RISC-2

Memory Controller

32-Bit DSP

I-Cache

MMU

I-Cache

MMU

D-Cache

MAC

D-Cache

MAC

SDRAM Control

I-Cache

X,Y Data

Memory

Flash Control

Video Input

Filter

Clock Manager

CPU / MAC

Subpicture Decode

Scaler

MPEG Decoder

VLC Parser IDCT

RAM

Dataflow Engine

Audio/IO

DMA / BitBlit

PCM Out

System Controls

MoCo

SRAM Buffer

PCM In

STC

Video Processor

On-Screen Display

Picture-in-Picture

XMT958

Interupts

Registers

External I/Os

Remote Input

GPIOs

Host

Interface

Video/Graphics Display

SDRAM

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

Copyright  Cirrus Logic, Inc. 2002

MAR ‘02

DS554PP1

1

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

CS7808

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

1.1 AC and DC Parametric Specifications ............................................................................... 5

1.1.1 Absolute Maximum Rating .................................................................................... 5

1.1.2 Recommended Operating Conditions ................................................................... 5

1.1.3 Electrical Characteristics ...................................................................................... 6

1.2 DC Characteristics ............................................................................................................. 7

1.2.1 Host Interface ........................................................................................................ 7

1.2.2 SDRAM Interface .................................................................................................. 8

1.2.3 ROM/NVRAM Interface ...................................................................................... 10

1.2.4 Video Output Interface ........................................................................................ 11

1.2.5 Video Input Interface ........................................................................................... 12

1.2.6 Audio Input Interface ........................................................................................... 13

1.2.7 Audio Output Interface ........................................................................................ 14

1.2.8 AC97/CODEC Interface ...................................................................................... 15

1.2.9 Miscellaneous Interface Timing ........................................................................... 16

2. TYPICAL APPLICATION ........................................................................................................ 17

3. FUNCTIONAL DESCRIPTION ............................................................................................... 18

3.1 Block Diagram .................................................................................................................. 18

3.2 CS7808 Device Details .................................................................................................... 18

3.2.1 RISC-32 Processors ........................................................................................... 18

3.2.2 Powerful 32-Bit DSP ........................................................................................... 18

3.2.3 System Controls .................................................................................................. 18

3.2.4 Memory Controller ............................................................................................... 19

3.2.5 Data Flow Engine ................................................................................................ 19

3.2.6 Audio Interface .................................................................................................... 19

3.2.7 Video Input .......................................................................................................... 19

3.2.8 External Interface ................................................................................................ 19

3.2.9 Video Processor .................................................................................................. 19

3.2.10 Cursor ............................................................................................................... 19

3.2.11 System Functions .............................................................................................. 20

3.3 RISC Processor ............................................................................................................... 20

3.4 DSP Processor ................................................................................................................ 20

3.5 Memory Control ............................................................................................................... 20

3.6 Dataflow Control (DMA) ................................................................................................... 20

3.7 System Control Functions ................................................................................................ 20

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information de-

scribes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this

document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).

Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All prod-

ucts are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and

limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale

of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus

Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus

Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization

with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic web site

or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The

names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which

may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com

.

Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those

components in a standard I2C system.

2

CS7808

3.8 Host Interface .................................................................................................................. 21

3.9 MPEG Video Decoding .................................................................................................... 21

3.10 Audio Processing ........................................................................................................... 21

3.11 Soft Modem ................................................................................................................... 21

3.12 Video ............................................................................................................................. 21

4. MEMORY MAP ....................................................................................................................... 23

4.1 Processor Memory Map .................................................................................................. 23

4.2 Host Port Memory Map .................................................................................................... 23

4.3 Internal I/O Space Map .................................................................................................... 23

5. REGISTER DESCRIPTION .................................................................................................... 24

5.1 CS7808 Register Space .................................................................................................. 24

6. PIN DESCRIPTION ................................................................................................................. 33

6.1 Pin Assignments .............................................................................................................. 34

6.2 Miscellaneous Interface Pins ........................................................................................... 40

6.3 SDRAM Interface ............................................................................................................. 41

6.4 ROM/NVRAM Interface ................................................................................................... 42

6.5 Video Output Interface ..................................................................................................... 43

6.6 Video Input Interface ....................................................................................................... 44

6.7 Audio Output/Input Interface ............................................................................................ 45

6.8 AC97/CODEC Interface ................................................................................................... 46

6.9 Host Master/ATAPI Interface ........................................................................................... 47

6.10 General Purpose Input/Output (GPIO) .......................................................................... 48

6.11 Power and Ground ........................................................................................................ 49

7. PACKAGE SPECIFICATIONS ............................................................................................... 50

LIST OF FIGURES

Figure 1. Host Timing Diagram.................................................................................................... 7

Figure 2. SDRAM Refresh Transaction ....................................................................................... 8

Figure 3. SDRAM Burst Write Transaction .................................................................................. 8

Figure 4. SDRAM Burst Read Transaction.................................................................................. 9

Figure 5. SDRAM Timing............................................................................................................. 9

Figure 6. ROM/RVRAM Timing.................................................................................................. 10

Figure 7. Video Output Timing.................................................................................................. 11

Figure 8. Video Input Timing...................................................................................................... 12

Figure 9. Audio Input Timings.................................................................................................... 13

Figure 10. Audio Output Timing................................................................................................. 14

Figure 11. CODEC Timing......................................................................................................... 15

Figure 12. Miscellaneous Timing ............................................................................................... 16

Figure 13. CS7808 Typical Application...................................................................................... 17

Figure 14. CS7808 Block Diagram ............................................................................................ 18

Figure 15. CS7808 Pinouts........................................................................................................ 33

Figure 16. 208-Pin Package Drawing ........................................................................................ 50

LIST OF TABLES

Table 1. Host Interface Symbols / Characterization Data............................................................ 7

Table 2. SDRAM Interface Symbols and Characterization Data ................................................. 8

Table 3. ROM/NVRAM Interface Symbols and Characterization Data...................................... 10

Table 4. Video Output Interface Symbols and Characterization Data ....................................... 11

Table 5. Video Input Interface Symbols and Characterization Data .......................................... 12

Table 6. Audio Input Interface Symbols and Characterization Data .......................................... 13

Table 8. AC97/CODEC Interface Symbols and Characterization Data ..................................... 15

3

CS7808

Table 9. Miscellaneous Interface Symbols and Characterization Data...................................... 16

Table 10. Memory Map-RISC0 Processor ................................................................................. 23

Table 11. Host Port Memory Map .............................................................................................. 23

Table 12. Internal I/O Space Map .............................................................................................. 23

Table 13. CS7808 Register Map and Blocks ............................................................................. 24

Table 14. CS7808 Registers...................................................................................................... 24

Table 15. Pin Type Legend........................................................................................................ 33

Table 16. 208-Pin Package Assignments .................................................................................. 34

Table 17. Miscellaneous Interface Pins ..................................................................................... 40

Table 18. SDRAM Interface ....................................................................................................... 41

Table 19. ROM/NVRAM Interface.............................................................................................. 42

Table 20. Video Output Interface ............................................................................................... 43

Table 21. Video Input Interface.................................................................................................. 44

Table 22. Audio Input/Output Interface ...................................................................................... 45

Table 23. AC97/CODEC Interface ............................................................................................. 46

Table 24. Host Master/ATAPI Interface ..................................................................................... 47

Table 25. General Purpose I/O Interface ................................................................................... 48

Table 26. Power and Ground.................................................................................................... 49

4

CS7808

1. CHARACTERISTICS AND SPECIFICATIONS

1.1

AC AND DC PARAMETRIC SPECIFICATIONS

(AGND, DGND=0V, all voltages with respect to 0V)

1.1.1

ABSOLUTE MAXIMUM RATING

Symbol Description

Min

Max

Unit

VDD_IO

VDD_CORE

V_I

Power Supply Voltage on I/O ring

Power Supply Voltage on core logic and PLL

Digital Input Applied Voltage (power applied)

Digital Input Forced Current

-0,5

4.6

Volts

-0.5

-10

-50

-

3.6

5.5

10

Volts

mA

^oC

I_I

I_O

Digital Output Forced Current

50

T_SOL

T_VSOL

T_STOR

T_AMB

P_total

Lead Soldering Temperature

260

220

125

70

Vapor Phase Soldering Temperature

Storage Temperature (no power applied)

Ambient Temperature (power applied)

Total Power consumption

-

-40

0

^oC

-

2.5

W

CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to

the device. Cirrus Logic recommends that CS7808 devices operate at the settings described in the next ta-

ble.

1.1.2

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

3.0

2.25

0

Typ

3.3

2.5

25

Max

3.6

Units

Volts

^oC

Supply Voltage, IO

V_DD

Supply Voltage, core and PLL

2.75

70

Ambient Temperature (power applied)

T_AMB

5

CS7808

1.1.3

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

I_DD

Conditions

Min

Typ

Max

-

Units

mA

Supply Current, IO

Supply Current, core and PLL

Input Voltage, High

Input Voltage, Low

Input Current

Normal Operating

-

45

I_DD

550

-

mA

V_IH

2.0

-

5.0

0.8

+1

-

Volts

µA

V_IL

I_IN

V_IN= V_DDor V_SS

-1

-

Input Pull up/down resistor

Output Voltage, High

Output Voltage, Low

High-Z Leakage

R_I

75

-

KΩ

V_OH

V_OL

I_OZ

@ buffer rating

2.4

-

Volts

µA

-

0.4

+10

-

V_OUT= V_SSor V_DD

-10

-

Input Capacitance

C_IN

3

pF

6

CS7808

1.2

DC CHARACTERISTICS

(T = 25°C; VDD_PLL=VDD_CORE=2.5V±10%, VDD_IO=3.3V±10%)

A

1.2.1

Host Interface

CS7808 can interface with a ATAPI-type slave loader gluelessly. Figure 1 illustrates a read ATAPI trans-

action and a write ATAPI transaction. PIO mode 4 is implemented to enable a sufficient data transfer rate

between ATAPI device and CS7808.

Symbol

^tacyc

^taavr

Description

Min

Typ

Max

Unit

Cycle Time¹

98

ns

Address Valid to HMRD-/HMWR- Setup

Address Hold from HMRD-/HMWR- Setup

H_RD-/H_WR- Pulse Width

H_RD-/H_WR- Recovery Time

H_WR- Data Setup

10

72

22

20

10

20

0

ns

^tah

^tarww

^tarec

^tawsu

^tawh

H_WR- Data Hold

^tardsu

^tarddh

^tarsu

^tarh

H_RD- Data Setup

H_RD- Data hold

H_RD- Data High-Z

0

10

12

H_RDY Setup Time

ns

H_RDY Hold Time¹

0

Table 1. Host Interface Characteristics

1.Values are guaranteed by design only.

tacyc

H_A[2:0] ,

H_CS[3:0]

t aavr

tarww

t ah

H_RD/H_WR

tarec

H_D[15:0](WRITE)

H_D[15:0](READ)

tawsu

tawh

tarsu

tarddh

tardsu

tardts

H_RDY(deasserted

before tarsu)

t arh

H_RDY(asserted

before tarsu)

Figure 1. Host Timing Diagram

7

CS7808

1.2.2

SDRAM Interface

CS7808 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure 2 shows the

refresh cycle performed by CS7808. Figure 3 shows a burst write (length = 8) transaction. Figure 4 on

page 9 shows a burst read (length = 8) transaction, while Figure 5 on page 9 shows detailed SDRAM in-

terface timing. In both Figure 3 and Figure 4, CAS latency is programmed to 3.

Symbol

Description

Min

Typ

Max

Unit

t_msur

t_mhr

M_D[31:0] setup to M_CKO

3

ns

M_D[31:0] hold time after M_CKO

0

ns

t_mco

M_CKO active edge to Output transition

7

M_CKO Period¹

t_mper

t_mhw

t_mdow

10.5

5

12.2

M_D[31:0] valid time after M_CKO

M_D[31:0] delay from M_CKO rising edge

5

Table 2. SDRAM Interface Characteristics

1.Values are guaranteed by design only.

M_CKE

M_A_[11:0]

M_BS_N

M_RAS_N

M_CAS_N

M_WE_N

MD[31:0]

M_DQM_[3:0]

M_AP

Figure 2. SDRAM Refresh Transaction

M_CKO

M_A_[11:0]

M_BS_N

R0

C0

C1 C2 C3

C4 C5 C6

C7

M_RAS_N

M_CAS_N

M_WE_N

M_D_[31:0]

M_DQM_[3:0]

M_AP

D0 D1

D2

D3

D4 D5 D6

D7

Figure 3. SDRAM Burst Write Transaction

8

CS7808

M_CKO

M_A_[11:0]

M_BS_N

R0

C0

C1 C2 C3 C4 C5 C6 C7

M_RAS_N

M_CAS_N

M_WE_N

M_D_[31:0]

M_DQM_[3:0]

M_AP

D0 D1 D2 D3 D4 D5 D6 D7

Figure 4. SDRAM Burst Read Transaction

tmco

tmper

M_CKO

M_RAS_N,M_CAS_N

M_WE_N,M_AP,M_DQM[3:0],

M_CKE,M_A[11:0]

tmdow

tmhw

M_D[31:0](WRITE)

M_D[31:0](READ)

t^msur

tmhr

Figure 5. SDRAM Timing

9

CS7808

1.2.3

ROM/NVRAM Interface

Symbol

Description

Min

Typ

Max

Unit

^tmper

^tnco

^tnwdo

^tnsur

^tnhw

^tnhr

M_CKO period¹

10.5

12.2

ns

M_CKO to WE or OE out

M_CKO to write data out

Data setup to M_CKO

5

ns

10

5

0

Data hold from WE inactive

Data hold from OE inactive

Table 3. ROM/NVRAM Interface Characteristics

1.Values are guaranteed by design only.

t mper

tnco

M_CKO

NVM_OE_L,

NVM_WE_L

tnhr

tnsur

M_D0:15 (READ)

t nwdo

tnhw

M_D0:15(WRITE)

Figure 6. ROM/RVRAM Timing

10

CS7808

1.2.4

Video Output Interface

Symbol

Description

Min

Typ

Max

Unit

t_suvo

Vsync/Hsync input setup to CLK27_O

VDAT[7:0] delay from CLK27_O transition

Vsync/Hsync delay from CLK27_O transition

5

ns

t_covo1

t_covo2

t_vocper

10

ns

CLK27_O High Time¹

37.037

Table 4. Video Output Interface Characteristics

1.Values are guaranteed by design only

Tvocper

CLK27_O

(Output)

Tcovo1

Tcovo2

VDAT[7:0]

(Output)

VSYNC/HSYNC (Output)

VSYNC/HSYNC (Input)

Tsuvo

Figure 7. Video Output Timing

11

CS7808

1.2.5

Symbol

t_suvi

t_hvi

Video Input Interface

Description

Min

Typ

Max

Unit

VIN_D[7:0] set up to VIN_CLK

5

ns

VIN_D[7:0] hold time after VIN_CLK rising edge

2

ns

VIN_CLK High Time¹

t_vicper

37.087

Table 5. Video Input Interface Characteristics

1.Active clock edge is programmable. Timing is referenced from active edge

.

t vicper

VIN_CLK

t^suvi

thvi

VIN_D[7-0]

VIN_HSNC,VIN_VSNC,

VIN_FLD

Figure 8. Video Input Timing

12

CS7808

1.2.6

Symbol

t_aicl

Audio Input Interface

Description

Min

Typ

Max

Units

AIN_BCK Low Time^{1, 2}

AIN_BCK High Time^{1, 2}

AIN_BCK period^{1, 2}

40

50

%

t_aich

t_aiper

t_stlr

40

216

5

50

%

ns

Time form AIN_LRCK transition to AIN_BCK active edge

AIN_DATA setup to AIN_BCK transition

-

t_lrts

2

t_sdsus

t_sdhs

5

AIN_DATA hold time after AIN_BCK transition

2

Table 6. Audio Input Interface Characteristics

1.Values are guaranteed by design only

2.Active clock edge is programmable. Timing is referenced from active edge

t _aiper

t_aich

t_aicl

AIN_BCK (Input)

t_lrts

t_stlr

AIN_LRCK (Input)

t_sdsus

t_sdhs

AIN_DATA (Input)

Figure 9. Audio Input Timings

13

CS7808

1.2.7

Audio Output Interface

Description

Symbol

t_axch

t_axcl

Min

Typ

Max

Units

AUD_XCLK High Time (AUD_XCLK is Input/Output)^{1, 2}

AUD_XCLK Low Time (AUD_XCLK is Input/Output)^{1, 2}

AUD_XCLK period (Input/Output)^{1, 2}

40

50

-

%

40

27

216

-

50

-

%

t_axper

t_aoper

t_sdm

t_lrds

ns

AUD_BCK period (Output)^{1, 2}

AUD_BCK delay from AUD_XCLK transition

5

3

AUD_BCK delay from AUD_XCLK transition

AUD_LRCK delay from AUD_BCK transition

-

Table 7: Audio Output Interface Characteristics

1.Values are guaranteed by design only

2.Active clock edge is programmable. Timing is referenced from active edge

t

axper

AUD_XCLK(Input/Output)

t

axcl

axch

AUD_BCK(Output)

t

sdm

t _aoperl

AUD_BCK(Output)

t _lrds

AUD_LRCK(Output)

t _adsm

AUD_DO[3:0] (Output)

Figure 10. Audio Output Timing

14

CS7808

1.2.8

AC97/CODEC Interface

Description

Symbol

t_suc

t_hc

Min

Typ

Max

Units

Data set up to CDC_CK

5

ns

Data hold time after CDC_CK

0

ns

%

t_coc

t_cch

t_ccl

Time from active edge of CDC_CK to Data transition

10

CDC_CK High Time^{1, 2}

CDC_CK Low Time^{1, 2}

CDC_CK period^{1, 2}

40

50

%

t_ccper

216

ns

Table 8. AC97/CODEC Interface Characteristics

1.Values are guaranteed by design only

2.Active clock edge is programmable. Timing is referenced from active edge

tccper

tcch

tccl

CDC_CK

(Intput)

tcoc

CDC_DO,

CDC_SY, CDC_Rst

(Output)

t^suc

thc

CDC_DI, CDC_SY

(Input)

Figure 11. CODEC Timing

15

CS7808

1.2.9

Miscellaneous Interface Timing

Symbol Description

Min

Typ

Max

Units

XTLCLOCK period¹

t_xccper

t_rstl

37.037

ns

RESET_N Pulse Width

1000

50

ns

t_gpl

GPIO PW Low

GPIO PW High

t_gpl

50

Table 9. Miscellaneous Interface Characteristics

1.XTLCLOCK must meet the requirement of external the video encoder for correct chroma (27 MHz ± 1 KHz).

xccper

t

XTLCLOCK

trstl

RESET-N

tgpl

tgph

GPIO

Figure 12. Miscellaneous Timing

16

CS7808

2. TYPICAL APPLICATION

The Figure 13 shows a typical example of a complete Set-Top Box solution using the CS7808.

To Phone

DAA

Line

LAN

Controller

CODEC

Ethernet

Infrared

Remote

Keyboard

CS7808

To Parallel Port

Audio

Interface

RISC-1

RISC-2

External

Interface

MPEG

Decoder

DSP

Audio

DAC

To Audio (R)

To Audio (L)

To LED

Video

Input

Memory

Controller

Video

Processor

To RF Modulator

To S-Video

To Composite

Video

Source

& Tuner

Video

Decoder

Video

Encoder

FLASH

SDRAM

8 MB

(up to 32 MB)

.5-2 MB

(up to 32

MB)

Power

Reg.

To Switch

To Power

Figure 13. CS7808 Typical Application

17

CS7808

3.2.2

Powerful 32-Bit DSP

3. FUNCTIONAL DESCRIPTION

3.1 Block Diagram

The CS7808 block diagram is shown in Figure 14.

•

Powerful 32/24-bit DSP processor

24-bit fixed point logic, with 54-bit accumulator

Single-cycle throughput, 2-cycle latency multiply

accumulate, 34-bit simple integer logic

3.2

CS7808 Device Details

•

8-Kbyte instruction cache, 8-Kbyte program visible

local memory

3.2.1

RISC-32 Processors

•

Two Powerful 32-bit RISC processors (RISC0 and

RISC1)

•

Single cycle instructions, runs at 81 Mhz

3.2.3

System Controls

•

Virtual memory support

•

Includes several hardware lockable semaphore

registers

Optimizing C compiler

Big or little endian data formats support

MAC multiply/accumulate in 2 cycles with C support

4 Kbyte instruction cache, 2 Kbyte data cache

Single cycle instructions, runs at 81 Mhz

General-purpose register for inter-processor com-

munication

32-bit timers for I/O and other uses, with program-

mable interval rates

Both hardware and software interrupts on data or

debug

RISC1

(Application)

RISC0

(Navigation &

Control)

MPEG2 Video

Decoder

SubPicture

Decoder

PLL (Main,

Audio, SDRAM)

AC '97

CODEC

Interface

2/4/8 Bit OSD

Video Processor

(I/O, Scale, PIP, Mix)

PCM, SPDIF

Interface

Host Interface

(ATAPI,AV,ISA)

AUDIO DSP

External IO

(GPIO, IR)

DMA Control

(BitBlt, CSS)

I2C

(Debug Port)

Registers

Mem Control

(SDRAM,ROM)

Figure 14. CS7808 Block Diagram

18

CS7808

•

Built in PLLs generate all required clocks from

27 Mhz input clock

•

Programmable parallel host master and slave inter-

face supports many formats including ATAPI, ISA,

and more

3.2.4

Memory Controller

Serial interface supports AC-97 and other standard

MODEM CODEC protocols

•

Supports SDRAM, and SGRAM, from 2 Mbytes to

32 Mbytes

3.2.9

Video Processor

Supports multiple banks of FLASH and ROM up to

16 Mbytes

•

Supports 24-bit 4:2:0 and 4:2:2 video modes and

16-bit true color graphics modes.

32-bit data bus for DRAM, 8 or 16-bit data bus for

ROM

•

On screen display module supports 2-bit, 4-bit, or 8-

bit pixel modes, while supporting 3 separate regions

and 16 transparency overlay levels

3.2.5

Data Flow Engine

•

2432 bytes of internal memory

•

Picture-in-picture module includes horizontal and

vertical downscaling with programmable output siz-

es, positions, and borders

DMA to/from main RAM into local SRAM

Supports endian conversion and byte, short, long

data formats on DMA

•

Overlay mixer with RGB to YUV conversion and

output formatting

•

Supports block transfers for graphics bit blits

Supports 4:2:0, 4:2:2, YUV655, RGB565 and

RGB555 frame buffer inputs

3.2.6

Audio Interface

Supports PCM, I²S and IEC-958 outputs at up to

96 KHz output rate

•

Outputs 4:2:2 video in CCIR-601 or CCIR-656 for-

mat

•

8 output channels, 2 input channels

High quality scaling using a vertical and a horizontal

16 taps polyphase programmable filter and sup-

ports any size image up to 768x576

3.2.7

Video Input

•

NTSC/PAL video decoder input interface

•

Programmable sharpening and de-blocking filters

Built in variable down scaling, handles CCIR 601 to

QCIF input formats

5 taps programmable adaptive anti-flicker filtering

for graphics source

•

Video input image can be displayed in small win-

dow, or as main picture

•

Master or Slave video sync configuration

Multiple video plains overlay (main video / video in-

put / picture_in_picture / picture/on_screen / dis-

play/cursor)

3.2.8

External Interface

®

•

Serial I²C master and slave port

29 independent fully programmable bi-directional

I/O pins

•

Gamma correction

3.2.10

Cursor

•

8 edge or level detection interrupt pins

•

4-bit color

Hardware assisted support for infrared remote de-

vices, such as remote control, infrared keyboard,

mouse, printer, and more

16-level alpha blending

19

CS7808

3.2.11

System Functions

typical application, the CS7808 requires 8 Mbytes

memory space.

•

208-pin PQFP packages

All I/O pins are 3 V with 5 V tolerance

Advanced 0.25 micron CMOS technology

Internal processors run at 81 MHz

Supports Low Power modes and clock shutoff

Sharing the same interface, CS7808 also supports

FLASH ROM, OTP, or mask ROM interface. Code

is stored in ROM. After the system is booted, the

code is shadowed inside SDRAM for execution.

The FLASH ROM interface is provided so that the

code can be upgraded in the field once the commu-

nications channel is established (via modem port,

CD-R, or serial port). Utility software will be pro-

vided to debug and upgrade code for the system

manufacturer.

3.3

RISC Processor

The CS7808 includes two powerful, proprietary

32-bit RISC processors, RISC0 and RISC1, with

optimizing C compiler support and source level de-

bugger. The RISC processors fully support many

Real Time Operation Systems (RTOS).

In addition to being compatible with the standard

3.6

Dataflow Control (DMA)

®

MIPS R3000 instruction set, the RISC proces-

sors also have a MAC engine, which performs mul-

tiply/accumulate in 2 cycles in a pipelined fashion

with C support, effectively achieving single cycle

throughout.

The DMA controller moves data between the exter-

nal memory and internal memory. The external

memory address can be specified using a register,

or in FIFO mode, using start and end address regis-

ters. Separate start/end address registers are used

for DMA read and write operations. The DMA in-

terface also has a block transfer function, which al-

lows for the transfer of one block of data from one

external memory location to another external mem-

ory location. In effect, this feature combines a

DMA read and write into one operation. In addi-

tion, the DMA write operation allows for byte,

short, word, and other types of masking.

3.4

DSP Processor

The CS7808 contains a proprietary digital signal

processor (DSP), which is optimized for audio ap-

plications. The DSP performs 32-bit simple integer

operations, and has a 24-bit fixed point logic unit,

with a 54-bit accumulator. There are 32 general-

purpose registers, and eight independent address

generation registers, featuring: linear and circular

buffer operations, and dual operand read from

memory. The multiply-accumulator has single-cy-

cle throughput, with two cycle latency. The DSP is

optimized for bit packing and unpacking opera-

tions. The interface to main memory is designed for

handling flexible block sizes and skip counts.

3.7

System Control Functions

The system control functions are used to coordinate

the activities of the multiple processors, and to pro-

vide the supporting system operations. Four 32-bit

communication registers are available for inter-

processor communication, and eight semaphore

registers are used for resource locking. Timers are

available for general-purpose functions, as well as

more specialized functions such as watchdog tim-

ers and performance monitoring.

3.5

Memory Control

The DRAM Interface performs the SDRAM con-

trol and arbitration functions for all the other mod-

ules in the CS7808. The DRAM interface services

and arbitrates a number of clients and stores their

code and/or data within the local memory. This ar-

bitration and scheduling guarantees the allocation

of sufficient bandwidth to the various clients. The

DRAM Interface supports up to 32 Mbytes. For a

The large number of general purpose I/Os offers

flexibility in system configurations. An I C master

allows for control of other I C devices, such as a

video encoder. An I C slave port shares the same

2

pins, and can be used for debug functions. Inter-

20

CS7808

rupts can be generated on specific or generic

events. Infrared inputs can be filtered to make them

enough reserve bandwidth to handle the Karaoke

echo-mix and pitch shift, and AC-3 down-mix

free of glitches or stored unfiltered into memory. functions.

Control of all the internal clocks is also possible.

The audio output data is written into a DRAM

Internal PLLs are used to generate the internal sys-

tem and memory clocks and audio clocks of any

widely used frequency.

FIFO in 16-, 18-, 20- or 24-bit PCM format. A flex-

ible audio output stage can simultaneously output 8

channels of PCM data to audio DACs, or 6 chan-

nels of audio data plus an IEC-958 encoded output,

at up to 96 KHz. The audio interface also includes

a flexible PCM input interface, which can input a

wide range of protocols from an audio ADC or an

IEC-958 receiver.

3.8

Host Interface

The CS7808 has a programmable interface port

which can be configured to connect to industry-

standard ATAPI interfaces without external glue

logic.

3.11 Soft Modem

The Host interface can be set up in ATAPI mode,

to connect directly to any ATAPI hard-disk drive

(using two chip selects).

The soft modem processing is handled by one of

the RISC processors, which is typically dedicated

for that function. Data rates up to 56 Kbits (V.90

protocol) are supported. The CS7808 interfaces to

a simple external CODEC/DAA circuit using a

flexible serial interface. The serial interface is a ful-

ly programmable, bi-directional interface and can

be used either as a PCM interface or as an AC97 in-

terface. In PCM mode, the sample size could be ad-

justed to 20, 18 or 16 bits to match common DAC

and ADC formats, or any other specific size. In

AC97 mode, any slot can be used to interface either

a modem CODEC or an audio CODEC.

3.9

MPEG Video Decoding

Compressed MPEG data is read from Internet

through Ethernet controller(Host I/F) or soft mo-

dem(CODEC I/F) into an input FIFO in DRAM.

The data flow (DMA) controller moves Video

packets from the input FIFO into the MPEG decod-

er’s input FIFO (also in DRAM). The DMA con-

troller can also perform advanced functions such as

start code search, relieving the RISC processors.

The System Synchronization function is used to

control the timing of MPEG picture decoding. The

MPEG Video decoder processes I, B, and P frames,

and writes to video frame buffers in DRAM for

output to the display. Special anti-tearing logic en-

sures that currently displayed frame buffers are not

overwritten.

3.12 Video

The Digital Video Interface provides flexible and

powerful means of outputting digital video data to

external devices in CCIR601/3 and CCIR656 for-

mats. The interface directly supports NTSC/PAL

video encoding, in both master and slave synchro-

nization configurations. The internal frame buffer

format could be 4:2:0, 4:2:2, YUV655, RGB565

and RGB555. Cirrus Logic provides some easy-to-

use utilities in order to get the best advantage of the

powerful video filtering capabilities of the CS7808.

The CS7808 also features an NTSC/PAL video de-

coder input interface. The interface accepts

CCIR601, CIF, and QCIF formats, out of many TV

decoders on the market. The video processor also

3.10 Audio Processing

Compressed Audio data is decompressed, then

written to a PCM output FIFO, also in DRAM The

DMA and decompression stages of audio process-

ing can be done with a combination of the DMA

unit, DSP, and RISC processors. The DSP is opti-

mized for audio processing, so most common for-

mats can be handled by the DSP alone, including

AC-3, DTS, MPEG2 audio, and MP3. The DSP has

21

CS7808

allows overlay of multiple video planes (main vid-

eo / video input / picture_in_picture / on_screen

display / cursor). CS7808 has been proven to work

with many TV encoders on the market with brands

such as: Crystal, Brooktree, ADI, and AVS.

laid anywhere on the screen into a ½ or ¼-screen

sized window by the Picture in Picture (PIP) mod-

ule.

An alternate method of using the Video Input func-

tion is to input a full sized picture and present it on

the screen full size (bypass mode). An internal

glitch-free mux can switch the video processor

The Video Input Scaler (VIS) module inputs 8-bit

digital video data from a camera or PAL/NTSC de-

coder, optionally down-scales to SIF or QSIF, and clock source from the internal clock to the Video

stores the data in one to three DRAM frame buff- Input clock, allowing the PIP mode to switch back

ers. The scaled image, with a border, can be over-

and forth on the fly, with no dropout.

22

CS7808

4. MEMORY MAP

4.1

Processor Memory Map

The CS7808 externally supports up to 32 Mbytes 4.2

Host Port Memory Map

DRAM and 16 Mbytes ROM/NVRAM. Table 10,

Table 11 and Table 12 on the next page list the

memory map as viewed by the RISC processors,

and identifies whether each segment is mapped or

cacheable.

Table 11 on page 23 lists the memory map as

viewed by host slave port.

4.3

Internal I/O Space Map

Table 10, Table 11, and Table 12 show how the In-

ternal I/O space is mapped between general regis-

ters, internal SRAM ports, and the RISC

processors’ debug port.

For detailed information on programming CS7808

memory, see CS7808 Memory Interface User’s

Manual (DS525UMD1).

Processor Byte Address

Description

DRAM (mapped)

DRAM (32 Mbytes)

Cacheable

0000_0000 – 07FF_FFFF

8000_0000 - 81FF_FFFF

9400_0000 – 9CFF_FFFF

9C00_0000 – 9CFF_FFFF

9D00_0000 – 9DFF_FFFF

A000_0000 – A1FF_FFFF

B000_0000 – B003_FFFF

B400_0000 – BCFF_FFFF

BC00_0000 – BCFF_FFFF

BD00_0000 – BDFF_FFFF

C000_0000 – FFFF_FFFF

Y

N

Y

N

Y

16-bit NVRAM write (16 Mbytes)

16-bit NVRAM/ROM (16 Mbytes)

8-bit NVRAM/ROM (16 Mbytes)

DRAM (32 Mbytes)

Internal I/O (256 Kbytes)

16-bit NVRAM write (16 Mbytes)

16-bit NVRAM/ROM (16 Mbytes)

8-bit NVRAM/ROM (16 Mbytes)

DRAM (mapped)

Table 10. Memory Map-RISC0 Processor

Host Byte Address

Description

0000 0000 – 003F FFFF

1000 0000 – 13FF FFFF

1400 0000 – 17FF FFFF

Internal I/O Space

DRAM space (16 Mbytes)

NVRAM space (16 Mbytes)

Table 11. Host Port Memory Map

Byte Address Offset

Description

0_0000 – 0_2FFF

0_3000 – 1_FFFF

2_0000 – 2_FFFF

3_0000 – 3_FFFF

General registers

General Internal SRAM

RISC_0 Internal SRAM/Registers

RISC_1 Internal SRAM/Registers

Table 12. Internal I/O Space Map

23

CS7808

5. REGISTER DESCRIPTION

5.1 CS7808 Register Space

Table 13 lists the register groups, and how they are split among the main CS7808 functional blocks.

Table 14 lists all the registers for the CS7808 and their addresses, and indicates whether the registers are

read/write (R/W), read only (RO), or write only (WO).

CS7808 Register

000xx, 010xx

Block

General

Host

001xx

002xx

003xx

005xx

006xx

007xx

008xx

009xx

00Axx

00Bxx

00Cxx

00Dxx

00Exx

02xxxx

03xxxx

DRC

DMA

Serial Interface

DSP

Synchronization Control

MPEG Video Decoder

Video Input Scaler

Picture-in-picture

Video Processor

Subpicture Display

On-screen Display

PCM In/Out

RISC_0

RISC_1

Table 13. CS7808 Register Map and Blocks

Address

Type

R/W

Function Register Name

000

010

014

018

10C

020

024

028

02C

030

034

038

General

Command

R/W

InterProc_Comm_Register_0

InterProc_Comm_Register_1

InterProc_Comm_Register_2

InterProc_Comm_Register_3

Semaphore_Register_0

Semaphore_Register_1

Semaphore_Register_2

Semaphore_Register_3

Semaphore_Register_4

Semaphore_Register_5

Semaphore_Register_6

Table 14. CS7808 Registers

24

CS7808

Address

Type

R/W

Function

Register Name

Semiphore_Register_7

03C

040

044

048

04C

050

054

058

05C

060

064

1040

1044

1048

General

RO

GenIO_Read_Data

R/W

RO

GenIO_Write_Data

GenIO_Three_State_Enable

GenIO_Positive_Edge

GenIO_Negative_Edge

GenIO_Interrupt_Status

GenIO_Positive_Edge_Mask

GenIO_Negative_Edge_Mask

GenIO_Level_Mask

GenIO_Mode Register

GenIOMIS_Read_Data

GenIOMIS_Write_Data

R/W

RO

GenIOMIS_Three_State_Enable

GenIOMIS_Positive_Edge

GenIOMIS_Negative_Edge

GenIOMIS_Interrupt_Status

GenIOMIS_Positive_Edge_Mask

GenIOMIS_Negative_Edge_Mask

GenIOMIS_Level_Mask

GenIOMIS_Mode Register

GenIOD_Read_Data

104C

1050

1054

1058

105C

1060

1064

1068

106C

1070

1074

1078

107C

068

R/W

RO

GenIOD_Write_Data

GenIOD_HiZ_State_Enable

GenIOHST_Read_Data

GenIOHST_Write_Data

GenIOHST_HiZ_State_Enable

I²C_Mstr_Read_Comand

I²C_Mstr_Write_1Byte

I²C_Mstr_Write_2Bytes

I²C_Mstr_Control

R/W

06C

070

074

078

07C

R/W

RO

General

I²C_Mstr_Status

I²C_Mstr_Read_Data

RSK0_Interrupt_Mask

RSK0_Interrupt_Set

RSK0_Interrupt_Status

RSK0_Interrupt_Cause

DSP_Interrupt_Mask

DSP_Interrupt_Set

RO

080

084

088

08C

090

094

R/W

WO

R/W

RO

General

R/W

WO

Table 14. CS7808 Registers (Continued)

25

CS7808

Address

Type

R/W

Function

Register Name

DSP_Interrupt_Status

098

General

Host

09C

0A0

0A4

0A8

0AC

1080

1084

1088

RO

DSP_Interrupt_Cause

RSK0_Interrupt_Mask2

RSK0_Interrupt_Set2

RSK0_Interrupt2_Status

RSK0_Interrupt_Cause2

RSK1_Interrupt_Mask

RSK1_Interrupt_Set

RSK1_Interrupt_Status

RSK1_Interrupt_Cause

RSK1_Interrupt_Mask2

RSK1_Interrupt_Set2

RSK1_Interrupt2_Status

RSK1_Interrupt_Cause2

DSP_Interrupt_Mask2

DSP_Interrupt_Set2

DSP_Interrupt2_Status

DSP_Interrupt_Cause2

Timer_0

R/W

WO

R/W

RO

R/W

WO

R/W

RO

108C

10A0

10A4

10A8

10AC

0B0

0B4

0B8

0BC

0C0

0C4

0C8

0CC

0D0

0D4

0D8

0E0

0E4

0E8

0EC

0F0

R/W

WO

R/W

RO

R/W

WO

R/W

RO

R/W

RO

Timer_1

Timer_2

Timer_3

Timer_Control

Performance_Monitor_Count

Timer_M_Over_N

R/W

RO

IR_Control

IR_Dram_Start_Address

IR_Dram_End_Address

IR_Dram_Write_Address

PLL_Control_Register1

Low_Power_Clock_Control

PLL_Control_Register2

PLL_Control_Register3

PLL_Turn_Off

R/W

10F0

0F4

10F4

0F8

0FC

100

PLL_Clock_Divider

Device_1_Control

104

Host

Device_2_Control

108

Host

Device_3_Control

10C

110

Host

Device_4_Control

Host

Write_Data_Port

Table 14. CS7808 Registers (Continued)

26

CS7808

Address

Type

Function

Register Name

114

120

124

128

12C

13C

200

204

208

20C

210

214

218

21C

220

224

300

304

308

30C

310

314

318

31C

328

32C

330

334

338

33C

540

544

548

54C

550

554

558

55C

560

564

RO

Host

Read_Data_Port

R/W

RO

Host_Start_Address

DRAM Start Address

Stream_Transfer_Size

DRAM_Burst_Threshold

Host_Master_Control

DRAM controller

DMA

DRAM_Controller_Priority0

DRAM_Controller_Priority1

DRAM_Controller_Priority2

DRAM_Controller_Priority3

DRAM_Controller_Priority4

DRAM_Controller_Setup

DRAM_Command

DRAM_Controller_Mb_Width

DRAM_Controller_Debug_Control

DRAM_Debug_Status

DMA_Enable

WO

R/W

RO

DMA

DMA_Control

DMA

DMA_Status

R/W

RO

DMA

Xfer_Byte_Cnt

DMA

Dram_Byte_Start_Addr

Sram_Byte_Start_Addr

Fifo_Start_Rd_Addr

DMA

Fifo_Start_Wr_Addr

DMA

Search_Control

DMA

Search_Status

R/W

RO

DMA

Fifo_End_Rd_Addr

DMA

Fifo_End_Wr_Addr

DMA

Lines_and_Skip

DMA

Byte_Mask_Pattern

SER/DCI

Serial_Frame_Sync_Control

Serial_Output_Input_Control

AC97_Codec_Control

AC97_Codec_Command

Serial_Output_Fifo_Start_Address

Serial_Output_Fifo_End_Address

Serial_Input_Fifo_Start_Address

Serial_Input_Fifo_End_Address

Serial_Output_Fifo_Read_Address

Serial_Input_Fifo_Write_Address

RO

Table 14. CS7808 Registers (Continued)

27

CS7808

Address

Type

R/W

Function

Register Name

Serial_Clock_Synthesis_Parameters

Codec_Register_Status

Slot5_Register_Data

568

56C

570

574

578

57C

580

584

588

600

604

6XX

700

704

708

70C

710

714

718

71C

720

724

728

72C

730

734

738

73C

740

744

748

74C

750

754

758

75C

760

764

768

76C

SER/DCI

DSP

RO

R/W

WO

RO

Slot10_Register_Data

Slot11_Register_Data

Slot12_Register_Data

Out_fifo_int

In_fifo_int

Rate_Control

DSP_Boot_Code_Start_Address

DSP_Run_Enable

DSP

DSP_Program_CntRun_Status

Audio_Sync_Control

R/W

RO

Synchronization Control

Video_Sync_Control

Video_Sync_Status

R/W

RO

Wait_Line

Frame_Period

STC_Interval

System_Time_Clock

Top_Bits

Video_PTS_FIFO_Start_Address

Video_PTS_FIFO_End_Address

Video_PTS_FIFO_Write_Address

Video_PTS_FIFO_Read_Address

Subpicture_PTS_FIFO_Start_Address

Subpicture_PTS_FIFO_End_Address

Subpicture_PTS_FIFO_Write_Address

Subpicture_PTS_FIFO_Read_Address

Highlight_Start_PTS

R/W

RO

R/W

RW

Highlight_End_PTS

Button_End_PTS

Highlight_Control_Information_Address

Video_PTS

R/W

RO

Audio_PTS

Subpicture_PTS

RO

Audio_Time

RO

Video_Sync_Debug

SP_DRC_VPTS_Debug

Frame_Count_Interrupt

Video_DTS

R/W

Table 14. CS7808 Registers (Continued)

28

CS7808

Address

Type

Function

Synchronization Control

MPEG Video Decoder

Video Input Scaler

Register Name

Sync_Interrupt_Status

770

774

778

77C

800

804

808

80C

810

814

818

81C

820

824

828

82C

830

834

83C

840

844

848

84C

854

858

900

904

908

90C

910

914

918

91C

920

A00

A04

A08

A0C

A10

A14

RO

R/W

WO

R/W

RO

Sync_Interrupt_Control

Sync_Interrupt_Set

Sync_Interrupt_Clear

MPEG_Video_Control

MPEG_Video_Setup

MPEG_Video_FIFO_Start_Address

MPEG_Video_FIFO_End_Address

MPEG_Video_FIFO_Current_Address

MPEG_Video_Horiz_Pan_Vector

MPEG_Video_FIFO_Add_Bytes

MPEG_Video_FIFO_Curr_Bytes

MPEG_Video_FIFO_Interrupt_Bytes

MPEG_Video_FIFO_Total_Bytes

MPEG_Video_Status

Macroblock Width_Height

MPEG_Video_Debug

MPEG_U_Offset

RO

WO

RO

R/W

RO

R/W

RO

R/W

RO

MPEG_I_Base_Register

MPEG_P_Base_Register

MPEG_Dest_Control

MPEG_Software_Flags

MPEG_V_Offset

R/W

MPEG_AntiTearWindow

MPEG_Error_Pos

VIS_Control

Video Input Scaler

VIS_StartX

Video Input Scaler

VIS_EndX

Video Input Scaler

VIS_StartY

Video Input Scaler

VIS_EndY

Video Input Scaler

VIS_Frame_Base

Video Input Scaler

VIS_U_Offset

Video Input Scaler

VIS_V_Offset

Video Input Scaler

VIS_Frame_Size

Picture-in-Picture

PIP_Control

Picture-in-Picture

PIP_VidBrdStartX

Picture-in-Picture

PIP_VidBrdEndX

Picture-in-Picture

PIP_VidBrdStartY

Picture-in-Picture

PIP_VidBrdEndY

Picture-in-Picture

PIP_BorderClr

Table 14. CS7808 Registers (Continued)

29

CS7808

Address

Type

R/W

Function

Picture-in-Picture

Video Processor

Register Name

A18

A1C

A20

A24

A28

A2C

A30

A34

B00

B04

B08

B0C

B10

B14

B18

B1C

B20

B24

B28

B2C

B30

B34

B38

B3C

B40

B44

B48

B4C

B50

B54

B58

B5c

B60

B64

B68

B6C

B70

B74

B78

B7C

PIP_Vscale

R/W

WO

R/W

PIP_Line_Offnum_Bot

PIP_FrBaseY

PIP_FrBaseU

PIP_FrBaseV

PIP_Line_Width

PIP_ Line_Offnum_Top

PIP_Frame_Size

Video_Processor_Control

Video_DRAM_Line_Length

Display_ActiveX

Display_ActiveY

Blank_Color

Internal_Hsync_Count

Internal_Vsync_Count

Horizontal_Y_Offset

Horizontal_UV_Offset

Vertical_Offset

Video_Line_Size

Frame_Buffer_Base

Video_Line_Mode_Buffer

Horizontal_Vertical_Filter

Source_X_Offset

Horizontal_Video_Scaling

Frame_V_Buffer_Compressed_Offset

Mb_Width

Anti-Flicker

Gamma Control

Vid_Sync Adjust

Table 14. CS7808 Registers (Continued)

30

CS7808

Address

Type

R/W

Function

Subpicture

Register Name

Subpicture_Color0

C00

C04

C08

C0C

C10

C14

C18

C1C

C20

C24

C28

C2C

C30

C34

C38

C3C

C40

C44

C50

C54

C58

D00

D04

D08

D0C

D10

D14

D18

D1C

D20

D24

D28

D2C

D30

D34

D38

D3C

D40

D44

D48

R/W

RO

Subpicture

Subpicture_Color1

Subpicture_Color2

Subpicture_Color3

Subpicture_Color4

Subpicture_Color5

Subpicture_Color6

Subpicture_Color7

Subpicture_Color8

Subpicture_Color9

Subpicture_Color10

Subpicture_Color11

Subpicture_Color12

Subpicture_Color13

Subpicture_Color14

Subpicture_Color15

Subpicture_DCI_Address

Subpicture_HLI_Address

Subpicture_Control

Subpicture_Display_Offset

Subpicture_Display_Scale

OSD_Status

Subpicture

On Screen Display

R/W

OSD_Control

OSD_Color_Number

OSD_Color_Data

OSD_Region1_Control

OSD_Region1_Hlimits

OSD_Region1_Vlimits

OSD_Region1_DramBase

OSD_Region2_Control

OSD_Region2_Hlimits

OSD_Region2_Vlimits

OSD_Region2_DramBase

OSD_Region3_Control

OSD_Region3_Hlimits

OSD_Region3_Vlimits

OSD_Region3_DramBase

OSD_Blend

OSD_Debug1

OSD_Debug2

Table 14. CS7808 Registers (Continued)

31

CS7808

Address

Type

R/W

Function

Register Name

E00

E04

E08

E0C

E10

E14

E18

E20

E24

E28

E2C

E30

E34

E38

E3C

E40

E44

E48

E4C

E50

PCM

RISC0

RISC1

PCM_Run_Clear

R/W

RO

PCM_Output_Control

PCM_Out_FIFO_Start_Address

PCM_Out_FIFO_End_Address

PCM_Out_FIFO_Interrupt_Address

PCM_Out_FIFO_Current_Address

SPDIF_Channel_Status

R/W

RO

PCM_Input_Control

PCM_In_FIFO_Start_Address

PCM_In_FIFO_End_Address

PCM_In_FIFO_Interrupt_Address

PCM_Out_FIFO_Interrupt_Address2

PCM_Out_FIFO_Interrupt_Address3

PCM_In_FIFO_Current_Address

SPDIF_Output_Control

RW

RO

SPDIF_Output_FIFO_Start_Address

SPDIF_Output _FIFO_End_Address

SPDIF_Output _FIFO_Current_Address

SPDIF_Output _FIFO_Interrupt_Address

SPDIF_Output_Add_Block

RW

R/W

2XXXX

3XXXX

RISC 0 Processor registers

RISC 1 Processor registers

Table 14. CS7808 Registers (Continued)

32

CS7808

6. PIN DESCRIPTION

H_D[15:0]

H_CS[3:0]

H_A[4:0]

H_ALE

M_A[11:0]

M_BS_N

M_D[31:0]

M_DQM_[3:0]

M_RAS_N

H_RD

Host Interface

Memory IF

(57)

(30)

H_WR

H_CKO

M_CAS_N

M_WE_N

M_AP

H_RDY

M_CKE

M_CKO

VIN_ D[7:0]

NVR_OE_N

NVR_WR_N

VIN_HSNC

VIN_VSNC

Video In

(12)

VIN_CLK

VIN_FLD

CS7808

HSYNC

VSYNC

CLK27_O

Video out

(11)

CDC_DI

CDC_DO

CDC_RST

CDC_CK

VDAT[7:0]

CODEC IF

(5)

AUD_BCK

DAC Out

(7)

AUD_LRCK

AUD_DO[3:0]

CDC_SY

SPDIF_O

XTLCLOCK

RST_N

AIN_BCK

AIN_LRCK

MISC.

(41)

ADC In

(3)

IR_IN

MFG_TST

AIN_DATA

D[20-0]

GPIO

GP_IO

H[16-14]

GPIO_V10

GPIO_[15-10, 8-7, 4-2, 0]

_

SCL

SDA

Figure 15. CS7808 Pinouts

Table 15 lists the conventions used to identify the pin type and direction.

Pin Type

Direction

I

Input

IS

Input, with schmitt trigger

ID

IU

Input, with pull down resistor

Input, with pull up resistor

Output

O

O4

Output – 4 mA drive

O8

Output – 8 mA drive

T4

High-Z Output – 4mA drive

Bi-direction

B

B4

Bi-direction – 4 mA drive

Bi-direction – 4 mA drive, with pull-up

Bi-direction – 8 mA drive, with pull-up

Bi-direction – 4 mA drive, with schmitt trigger

B4U

B8U

B4S

B4SU

Pwr

Gnd

Name_N

Bi-direction – 4 mA drive, with pull-up and Schmitt trigger

+2.5 V or +3.3 V power supply voltage

Power supply ground

Low active

Table 15. Pin Type Legend

33

CS7808

6.1

Pin Assignments

Table 16 lists the pin number, pin name, and pin type for the 208 pin CS7808 package. The primary func-

tion and pin direction is shown for all signal pins. For some signal pins, a secondary function and direction

are also shown. For pins having more than one function, the primary function is chosen when the chip is

reset.

1

Name

VDD_PLL

M_A_11

M_A_10

GPIO_D18

M_A_9

Type

Pwr

O8

Primary Function

PLL Power 2.5V

SDRAM Address[11]

SDRAM Address[10]

GenIOD[18]

Dir

I

Secondary Function

Dir Note

2

O

B

O

B

O

B

O

B

I

ROM/NVRAM Address[11]

ROM/NVRAM Address[10]

System Clock PLL Bypass

ROM/NVRAM Address[9]

ROM/NVRAM Address8]

ROM/NVRAM Address[7]

O

I

3

O8

4

B4U

O8

5

SDRAM Address[9]

SDRAM Address[8]

SDRAM Address[7]

GenIOD[16]

O

6

M_A_8

O8

7

M_A_7

O8

8

GPIO_D16

M_A_6

B4SU

O8

9

SDRAM Address[6]

SDRAM Address[5]

SDRAM Address[4]

GenIOD[17]

ROM/NVRAM Address[6]

ROM/NVRAM Address[5]

ROM/NVRAM Address[4]

O

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

M_A_5

O8

M_A_4

O8

GPIO_D17

M_A_3

B4U

O8

SDRAM Address[3]

SDRAM Address[2]

SDRAM Address[1]

SDRAM Address[0]

GenIOD[19]

ROM/NVRAM Address[3]

ROM/NVRAM Address[2]

ROM/NVRAM Address[1]

ROM/NVRAM Address[0]

Memory Clock PLL Bypass

O

I

M_A_2

O8

M_A_1

O8

M_A_0

O8

GPIO_D19

VSS_IO

M_CKO

B4U

Gnd

O8

I/O Ground

SDRAM Clock

O

I

VDD_IO

M_BS_N

M_CKE

Pwr

O8

I/O Power 3.3V

SDRAM Bank Select

SDRAM Clock Enable

SDRAM Auto Pre-charge

SDRAM Row Strobe

SDRAM Column Strobe

GenIOD[20]

O

B

O

B

O

B

B8

GenioMis(7)

B

3

M_AP

O8

M_RAS_N

M_CAS_N

GPIO_D20

M_WE_N

M_DQM_0

M_DQM_1

GPIO_D0

M_DQM_2

M_DQM_3

M_D_8

O8

B4U

O8

SDRAM Write Enable

SDRAM DQM[0]

SDRAM DQM[1]

GenIOD[0]

O8

B4U

O8

SDRAM DQM[2]

SDRAM DQM[3]

SDRAM Data[8]

GenIOD[1]

O8

B8U

B4U

ROM/NVRAM Data[8]

B

GPIO_D1

Table 16. 208-Pin Package Assignments

34

CS7808

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

Name

VSS_IO

Type

Gnd

B8U

Pwr

Primary Function

I/O Ground

Dir

I

Secondary Function

Dir Note

VSS_CORE

M_D_7

Core Ground

I

SDRAM Data[7]

I/O Power 3.3V

GenIOD[2]

B

I

ROM/NVRAM Data[7]

B

VDD_IO

GPIO_D2

M_D_9

B4U

B8U

Pwr

B

I

SDRAM Data[9]

Core Power 2.5V

SDRAM Data[6]

GenIOD[3]

ROM/NVRAM Data[9]

ROM/NVRAM Data[6]

B

VDD_CORE

M_D_6

B8U

B4U

B8U

B4U

B8U

B4U

B8U

B

GPIO_D3

M_D_10

M_D_5

SDRAM Data[10]

SDRAM Data[5]

SDRAM Data[11]

GenIOD[4]

ROM/NVRAM Data[10]

ROM/NVRAM Data[5]

ROM/NVRAM Data[11]

B

M_D_11

GPIO_D4

M_D_4

SDRAM Data[4]

SDRAM Data[12]

GenIOD[5]

ROM/NVRAM Data[4]

ROM/NVRAM Data[12]

B

M_D_12

GPIO_D5

M_D_3

SDRAM Data[3]

may leave unconnected

SDRAM Data[13]

SDRAM Data[2]

SDRAM Data[14]

GenIOD[6]

ROM/NVRAM Data[3]

B

UNUSED

M_D_13

M_D_2

B8U

B4U

Gnd

B8U

B4U

B8U

Gnd

B8U

B4U

Pwr

B

I

ROM/NVRAM Data[13]

ROM/NVRAM Data[2]

ROM/NVRAM Data[14]

B

M_D_14

GPIO_D6

VSS_IO

I/O Ground

M_D_1

SDRAM Data[1]

SDRAM Data[15]

GenIOD[7]

B

I

ROM/NVRAM Data[1]

ROM/NVRAM Data[15]

B

M_D_15

GPIO_D7

M_D_0

SDRAM Data[0]

Core Ground

B

I

ROM/NVRAM Data[0]

VSS_CORE

M_D_24

GPIO_D11

VDD_CORE

M_D_23

M_D_25

GPIO_D10

M_D_22

M_D_26

M_D_21

GPIO_D9

M_D_27

SDRAM Data[24]

GenIOD[11]

B

I

ROM/NVRAM Address[20]

O

2

Core Power 2.5V

SDRAM Data[23]

GenIOD[10]

B8U

B4U

B8U

B4U

B8U

B

ROM/NVRAM Address[19]

ROM/NVRAM Address[21]

O

2

SDRAM Data[22]

SDRAM Data[26]

SDRAM Data[21]

GenIOD[9]

ROM/NVRAM Address[18]

ROM/NVRAM Address[22]

ROM/NVRAM Address[17]

O

2

SDRAM Data[27]

ROM/NVRAM Address[23]

O

2

Table 16. 208-Pin Package Assignments (Continued)

35

CS7808

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

Name

M_D_20

Type

B8U

B4U

B8U

B4U

Gnd

B8U

Pwr

Primary Function

SDRAM Data[20]

SDRAM Data[28]

GenIOD[8]

Dir

B

O

I

Secondary Function

Dir Note

ROM/NVRAM Address[16]

O

2

M_D_28

GPIO_D8

M_D_19

SDRAM Data[19]

SDRAM Data[29]

SDRAM Data[18]

NVRAM Write Enable

Core Ground

ROM/NVRAM Address[15]

O

2

M_D_29

M_D_18

ROM/NVRAM Address[14]

GenioMis[8]

O

B

NV_WE_N

VSS_CORE

M_D_30

SDRAM Data[30]

Core Power 2.5V

Host Address Latch

SDRAM Data[18]

SDRAM Data[31]

SDRAM Data[16]

GenioHst[14]

B

I

ROM/NVRAM Decode Low

O

2

VDD_CORE

H_ALE

B4U

B8U

B4U

O4

O

B

O

GenioHst[13]

B

O

M_D_17

ROM/NVRAM Address[13]

ROM/NVRAM Decode High

ROM/NVRAM Address[12]

2

M_D_31

M_D_16

GPIO_H14

NV_OE_N

ROM/NVRAM Output

Enable

91

92

VDD_IO

H_RD

Pwr

B4S

B4

I/O Power 3.3V

Host Read Strobe

Host Write Strobe

GenioHst[15]

I

O

B

I

93

H_WR

94

GPIO_H15

H_RDY

B4U

B4

95

Host Ready

O

B

96

VSS_IO

H_A_2

Gnd

B4

I/O Ground

I

97

Host Address[2]

GenioHst[16]

O

B

O

I

GenioHst[10]

98

GPIO_H16

H_A_1

B4U

B4

99

Host Address[1]

Host Address[0]

Host Chip Select [1]

Host Address[4]

Core Ground

GenioHst[9]

GenioHst[8]

B

I

100

101

102

103

104

105

106

107

108

109

110

111

112

113

H_A_0

B4

H_CS_1

H_A_4

B4

GenioHst[12]

B

VSS_CORE

VSS_PLL

VDD_PLL

H_CS_0

H_A_3

Gnd

Pwr

B4

PLL Ground

I

PLL Power 2.5V

Host Chip Select[0]

Host Address[3]

Core Power 2.5V

Host Data[15]

I

O

I

B4

GenioHst[11]

GenioHst[18]

B

VDD_CORE

H_D_15

H_D_14

H_CS_3

H_D_13

H_D_12

Pwr

B4

B

O

B

I

1

B4

Host Data[14]

B4

Host Chip Select[3]

Host Data[13]

B

I

B4S

B4

1

Host Data[12]

I

Table 16. 208-Pin Package Assignments (Continued)

36

CS7808

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

Name

H_D_11

Type

B4

Primary Function

Host Data[11]

Dir

B

O

B

I

Secondary Function

Dir Note

I

2

H_CS_2

B4

Host Chip Select[2]

Host Data[10]

GenioHst[17]

B

O

I

H_D_10

B4

2

H_D_9

B4

Host Data[9]

H_D_8

B4

Host Data[8]

O

VSS_IO

Gnd

B4

I/O Ground

H_CKO

Host Clock

O

B

O

B

I

GenioHst[19]

GenioMis[3]

B

I

H_D_7

B4

Host Data[7]

H_D_6

B4

Host Data[6]

I

H_D_5

B4

Host Data[5]

I

AUD_BCK

H_D_4

B4

Audio Out Bit Clock

Host Data[4]

B

I

3

B4

VSS_CORE

H_D_3

Gnd

B4

Core Ground

Host Data[3]

B

O

I

AUD_LRCK

VDD_CORE

H_D_2

O4

Audio Out LR Clock

Core Power 2.5V

Host Data[2]

Pwr

B4

B

I

VDD_IO

Pwr

B4

I/O Power 3.3V

Host Data[1]

H_D_1

B

O

B

O

I

B

I

AUD_DO_2

H_D_0

B4

Audio Out Data[2]

Host Data[0]

GenioMis[2]

GenioMis[1]

3

B4

AUD_DO_0

AUD_DO_1

AIN_BCK

VSS_CORE

AIN_LRCK

AIN_DATA

VDD_CORE

CDC_DI

O4

Audio Out Data[0]

Audio Out Data[1]

Audio In Bit Clock

Core Ground

B4

B

IU

Gnd

IU

I

Audio In LR Clock

Audio In Data

I

B4U

Pwr

IU

I

GenioMis[0]

B

3

Core Power 2.5V

Serial CODEC Data In

I/O Ground

I

VSS_IO

Gnd

T4

I

CDC_DO

VIN_CLK

CDC_RST

CDC_CK

CDC_SY

GPIO_V10

GPIO_D15

GPIO_D14

GPIO_D13

VIN_VSNC

Serial CODEC Data Out

Video Input Clock

Serial CODEC Reset

Serial CODEC Bit Clock

Serial CODEC Sync

GenioMis[26]

O

I

IU

T4

O

I

IU

B4U

B4SU

B4U

B

I

GenIOD[15]

GenIOD[14]

GenIOD[13]

Video Input Vsync

GenioMis[25]

B

Table 16. 208-Pin Package Assignments (Continued)

37

CS7808

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

Name

CLK27_O

GPIO_D12

VDD_PLL

VSS_PLL

VSS_CORE

HSYNC

Type

B4U

Pwr

Gnd

B4U

Pwr

B4U

O4

Primary Function

Video Output Clock

GenIOD[12]

Dir

O

B

I

Secondary Function

Dir Note

GenioMis[6]

B

PLL Power 2.5V

PLL Ground

I

Core Ground

I

Video Output Hsync

Video Input Hsync

Core Power 2.5V

Video Output Vsync

Video Output Data[0]

Video Input Data[0]

Video Output Data[1]

Video Output Data[2]

Video Output Data[3]

Video Input Data[1]

Video Output Data[4]

Video Output Data[5]

may leave unconnected

Video Output Data[6]

Video Output Data[7]

General Purpose IO[0]

Video Input Data[2]

Core Ground

O

I

GenioMis[4]

B

VIN_HSYNC

VDD_CORE

VSYNC

GenioMis[24]

I

O

I

GenioMis[5]

B

VDAT_0

VIN_D0

B4U

O4

GenioMis[16]

VDAT_1

VDAT_2

VDAT_3

VIN_D1

O

I

O4

B4U

O4

GenioMis[17]

B

VDAT_4

VDAT_5

UNUSED

VDAT_6

VDAT_7

GPIO_0

O

O4

O

B

I

O4

B4U

Gnd

B4U

Pwr

B4U

Pwr

B4U

Gnd

B4U

Audio PLL Input Bypass

GenioMis[18]

I

VIN_D2

B

VSS_CORE

AUD_DO_3

VDD_CORE

VIN_D3

I

Audio Out Data[3]

Core Power 2.5V

Video Input Data[3]

I/O Power 3.3V

O

I

General Purpose IO[1]

GenioMis[19]

B

I

VDD_IO

GPIO_2

I

General Purpose IO[2]

I/O Ground

B

I

VSS_IO

GPIO_3

General Purpose IO[3]

Video Input Data[4]

General Purpose IO[4]

I²C Clock

B

I

VIN_D4

GenioMis[20]

B

GPIO_4

B

I

SCL

General Purpose IO[5]

General Purpose IO[6]

B

SDA

I²C Data

GPIO_7

General Purpose IO[7]

Video Input Data[5]

General Purpose IO[8]

Audio 256x/384x Clock

General Purpose IO[10]

Video Input Data[6]

VIN_D5

GenioMis[21]

General Purpose IO[9]

GenioMis[22]

B

GPIO_8

B

I

AUD_XCLK

GPIO_10

VIN_D6

Table 16. 208-Pin Package Assignments (Continued)

38

CS7808

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

Name

GPIO_11

GPIO_12

GPIO_13

GPIO_14

VIN_D7

Type

B4U

Gnd

IS

Primary Function

General Purpose IO[11]

General Purpose IO[12]

General Purpose IO[13]

General Purpose IO[14]

Video Input Data[7]

General Purpose IO[15]

Core Ground

Dir

B

I

Secondary Function

Dir Note

GenioMis[23]

B

GPIO_15

VSS_CORE

IR_IN

B

I

Infrared input

I

XTLCLOCK

VDD_CORE

SPDIF_O

RESET_N

MFG_TEST

VIN_FLD

VSS_PLL

I

27 MHz Clock In

Core Power 2.5V

S/PDIF Out

I

Pwr

O4

I

O

I

IS

Reset In

I

(Tie to ground)

I

ID

Video Input Field

PLL Ground

I

Gnd

I

Table 16. 208-Pin Package Assignments (Continued)

Notes: 1. M_D[31:16] are driving when CS7808 is reading ROM/NVRAM on M_D[15:0], which occurs

immediately after reset.

2. H_D(15:8) pins may be reassigned as GenIOHst(7:0)

3. Pin can receive level or edge signals which generate an internal interrupt if pin is used as GPIO

39

CS7808

6.2

Miscellaneous Interface Pins

2

These pins are used for used for basic functions such as clock and reset input. See Table 17. The I C pins

are used for both master and slave mode (8-bit slave address is 0x30 for write, and 0x31 for read).

Signal Name

Type

Description

I²C Clock

I²C Data

186

187

SCL

B

SDA

B

201

202

205

206

IR_IN

I

Infrared Input, from IR receiver.

27 MHz Clock Input.

XTLCLOCK

RESET_N

MFG_TEST

Reset Input, active low.

Manufacturing test pin, should always connect to ground.

Table 17. Miscellaneous Interface Pins

40

CS7808

6.3

SDRAM Interface

These pins are used to interface the CS7808 with some external SDRAM. The CS7808 can interface with

SDRAM of various sizes. Both 16 and 32-bit data width is supported, but best performance is achieved

with 32 bits. Follow the instructions in Table 18 on how to interface with any particular configuration of

SDRAM.

Signal Name

Type

Description

87, 83, 79, 76,

74, 71, 68, 64,

67, 70, 72, 75,

78, 80, 86, 88,

60, 56, 54, 49,

46, 44, 40, 33,

37, 42, 45, 48,

51, 55, 59. 62

M_D[31..0]

B

Memory Data Bus. CS7808 can use all 32 bits or can use only

M_D[15..0], in which case M_D[31..16] can be left un-con-

nected.

2, 3, 5, 6, 7, 9,

10, 11, 13, 14,

15, 16

M_A[11..0]

O

Memory Address Bus. Connect in order starting with M_A[0] to

all RAM address pins not already connected to M_BS_L or

M_AP. Unused upper M_A pins unconnected.

19

M_CKO

M_CKE

O

Memory Clock

22

Memory Clock Enable

21

M_BS_N

M_AP

Bank Selection. Always connect to RAM BS or BS0 pin.

Memory Auto Pre-charge. Always connect to RAM AP pin.

Memory Row Address Strobe

23

24

M_RAS_N

M_CAS_N

M_WE_N

M_DQM[3..0]

25

Memory Column Address Strobe

Memory Write Enable

27

32, 31, 29, 28

IO Mask of Data Bus M_DQM[3] -> M_D[31:24]

Table 18. SDRAM Interface

41

CS7808

6.4

ROM/NVRAM Interface

This is the interface to the non-volatile memory that contains the firmware. See Table 19. It could be either

ROM, NVRAM – FLASH, or EEPROM, or any combination of these types of memory. This interface can

also connect to SRAM that would emulate a ROM on a development system. The bus width is 8 or 16 bits.

Except for the NVM_WE_N and NVM_OE_N pins, all these pins are shared with the DRAM interface,

which operates simultaneously with the ROM/NVRAM interface.

Signal Name

Type

Description

60, 56, 54, 49,

46, 44, 40, 33,

37, 42, 45, 48,

51, 55, 59. 62

M_D[15..0]

B

Memory Data Bus. Use M_D[7:0] for 8-bit interface

2, 3, 5, 6, 7, 9,

10, 11, 13, 14,

15, 16

M_A[11..0]

O

Memory Address Bus[11..0]

74, 71, 68, 64,

67, 70, 72, 75,

78, 80, 86, 88

M_D[27..16]

Memory Address Bus[23..12]

16-bit data mode, M_D[26:16] is upper word address.

For 8-bit data mode, M_D[27:16] is upper byte address.

For

83

87

60

62

M_D[30]

M_D[31]

O

Address decode low. Copy of address MSB.

Address decode high. Compliment of address MSB.

NVRAM Write Enable.

NVM_WE_N

NVM_OE_N

ROM/NVRAM Output Enable.

Table 19. ROM/NVRAM Interface

42

CS7808

6.5

Video Output Interface

This is the interface to a video encoder chip that will send the CS7808 video signals to a TV. See Figure 20.

The output format is either CCIR-601 or CCIR-656. The CS7808 supports both master and slave config-

uration. For CCIR-656 mode, the CS7808 must be the sync master. In this case, the HSYNC and VSYNC

pins can be redefined as GPIOs.

Signal Name

CLK27_O

HSYNC

Type

O

Description

154

159

27 Mhz Clock Output.

B

Horizontal Sync. Output when the CS7808 is the video

master, input when the video encoder is master.

162

VSYNC

B

Vertical Sync. Output when the CS7808 is the video mas-

ter, input when the video encoder is master.

173, 172, 170,

169, 167, 166,

165, 163

VDAT[7..0]

O

Video Data Output[7..0] in Cb,Y,Cr,Y format.

Table 20. Video Output Interface

.

43

CS7808

6.6

Video Input Interface

The CS7808 supports CCIR-601, CIF, and QCIF video input format thought this interface. See Table 21.

Signal Name

VIN_CLK

Type

Description

145

153

160

207

I

Video Input Clock.

VIN_VSNC

VIN_HSNC

VIN_FLD

Video Input Vertical Sync.

Video Input Horizontal Sync.

Video Input Field.

198, 193, 189,

184, 179, 175,

168, 164

VIN_D [7..0]

Video Data Input[7..0] in Cb,Y,Cr,Y format.

Table 21. Video Input Interface

44

CS7808

6.7

Audio Output/Input Interface

This is the audio PCM interface that connects to an audio CODEC. See Table 22. The sample rate and the

size of the samples are programmable for both input and output direction.

Signal Name

Type

Description

191

AUD_XCLK

B

Audio 256x/384x Clock input or output to Serial DAC. When

output, is generated from CS7808 internal PLL.

124

128

135

136

133

177

204

137

AUD_BCK

AUD_LRCK

AUD_DO_0

AUD_DO_1

AUD_DO_2

AUD_DO_3

SPDIF_O

O

I

Audio Bit Clock output to serial DAC.

Audio Out Left/Right Clock to serial DAC.

Audio Serial Data Out[0].

Audio Serial Data Out[1].

Audio Serial Data Out[2].

Audio Serial Data Out[3].

S/PDIF Output

AIN_BCK

Audio Input Bit Clock. The CS7808 can be programmed to

use the Audio Output function’s internally generated bit

clock, in which case this pin is not required.

139

140

AIN_LRCK

AIN_DATA

I

Audio Input Left/Right Clock. The CS7808 can be pro-

grammed to use the Audio Output function’s internally gen-

erated LR clock, in which case this pin is not required.

Audio Input Data from Serial ADC.

Table 22. Audio Input/Output Interface

45

CS7808

6.8

AC97/CODEC Interface

This serial interface could be used either as a second PCM CODEC interface or as an AC97 serial link to

an AC97 compliant CODEC. This interface could control a modem, or a second set of audio channels.

Table 23 describes the pin to signal assignments for the AC97/CODEC Interface.

Signal Name

CDC_DI

Type

Description

Serial Data Input from Modem CODEC

Serial Data Output to Modem CODEC

Reset Output to Modem CODEC

142

144

146

147

148

I

CDC_DO

CDC_RST

CDC_CK

CDC_SY

O

I

Serial Bit Clock input from Modem CODEC

B

Frame Sync, output when CS7808 is master, input when

CODEC is master.

Table 23. AC97/CODEC Interface

46

CS7808

6.9

Host Master/ATAPI Interface

This 16-bit parallel host interface allows the CS7808 to be a host master, controlling other devices that

would be used on the same system. See Table 24. The interface supports programmable protocols and

speeds, including multiplexed and non-multiplexed addressing. Slaves with different protocols can be con-

nected at the same time, controlled by different chip selects.

Signal Name

Type

Description

111, 115, 101,

106

H_CS[3..0]

O

Host Chip Select[3..0]. The host master can be pro-

grammed to use a different protocol for each of the 4 chip

selects

85

H_ALE

O

Host address latch enable. Used for modes which multiplex

upper address information onto the data lines

92

93

95

H_RD

H_WR

H_RDY

O

I

Host Read Request.

Host Write Request.

Host Ready. Connect to pull-up or pull-down if host is not

used.

120

H_CKO

O

Host clock out, required for some synchronous slaves

Host Address[4..0].

102, 107, 97, 99,

100

H_A[4..0]

109, 110, 112,

113, 114, 116,

117, 118, 121,

122, 123, 125,

127, 130, 132,

134

H_D[15..0]

B

Host Data Bus[15..0]. These pins can also output Host

Address during the address phase for multiplexed

address/data mode. Tie together to pull-up or pull-down if

host is not used.

Table 24. Host Master/ATAPI Interface

47

CS7808

6.10 General Purpose Input/Output (GPIO)

The CS7808 provides 37 GPIO pins, each with individual output High-Z controls. High-Z means that the

output driver is turned off or placed in the high-impedance state. Table 25 describes the General Purpose

I/O Interface. Additional pins may also be re-defined as GPIO’s.

Signal Name

Type

Description

21 General purpose I/O’s

26,17,4,12,8,

150, 151, 152,

155, 65, 69, 73,

77, 61, 57, 50,

47, 43, 39, 34,

30

GPIO_D[20:0]

B

98, 94, 89

149

GPIO_H[16:14]

GPIO_V10

B

3 General purpose I/O’s

General purpose I/O

199, 197, 196,

195, 194, 192

GPIO_[15:10]

6 General purpose I/O’s

190, 188

195, 183, 181

174

GPIO_[8:7]

GPIO_[4:2]

GPIO_0

B

2 General purpose I/O’s

3 General purpose I/O’s

General purpose I/O

Table 25. General Purpose I/O Interface

48

CS7808

6.11 Power and Ground

The CS7808 requires 3 different types of power supplies – PLLs, internal logic and IO pins -. The PLLs

and internal logic use 2.5 V power supply, The IO pins use 3.3 V power supply, and are 5 V input tolerant.

(See Table 26.)

Signal Name

VDD_PLL

Type

Description

1, 105, 158

I

2.5 V for internal PLLs

41, 66, 84, 108,

129, 141, 161,

178, 203

VDD_CORE

2.5 V for internal core logic

20, 38, 91, 131,

180

VDD_IO

I

3.3 V for I/O’s

104, 157, 208

VSS_PLL

I

Ground for internal PLLs

36, 63, 82, 103,

126, 138, 158,

176, 200

VSS_CORE

Ground for internal core logic

18, 35, 58, 96,

119, 143, 182

VSS_IO

I

Ground for I/Os

Table 26. Power and Ground

49

CS7808

7. PACKAGE SPECIFICATIONS

30.6 ±0.2

28.00 ±0.05

3.80(MAX)

3.35 ±0.05

0.35 ±0.1

157

208

156

1

52

105

53

104

Detail A

0.50±0.05

0.22

±0.05

15°

0°(MIN)

R0.15

0.2

(MIN)

R0.20

10°

WITH PLATING

BASE METAL

0.50±0.1

1.3±0.1

5°

0.20

DETAIL A

Figure 16. 208-Pin Package Drawing

50


型号：	CS7808
厂家：	CIRRUS LOGIC
描述：	MULTI PURPOSE AUDIO/VIDEO EMBEDDED PROCESSOR 多用途AUDIO / VIDEO嵌入式处理器
文件：	总52页 (文件大小：933K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CS7808 [CIRRUS]

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