CS1600_1007 [CIRRUS]

LOW-cost PFC Controller for Electronic Ballasts; 低成本的PFC控制器,用于电子镇流器
CS1600_1007
型号: CS1600_1007
厂家: CIRRUS LOGIC    CIRRUS LOGIC
描述:

LOW-cost PFC Controller for Electronic Ballasts
低成本的PFC控制器,用于电子镇流器

功率因数校正 电子 控制器
文件: 总18页 (文件大小:194K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CS1600  
Low-cost PFC Controller for Electronic Ballasts  
Features & Description  
Lowest PFC System Cost for Electronic Ballasts  
Description  
CS1600 is a high-performance Variable Frequency Discontinu-  
ous Conduction Mode (VF - DCM), active Power Factor  
Correction (PFC) controller, optimized to deliver the lowest PFC  
system cost for electronic ballast applications.  
Variable Frequency Discontinuous Conduction Mode  
Improved Efficiency Due to Variable Switching Frequency  
EMI Signature Reduction from Digital Noise Shaping  
Integrated Feedback Compensation  
A variable ON time / variable frequency algorithm is used to  
achieve near unity power factor. This algorithm spreads the EMI  
frequency spectrum, which reduces the conducted EMI filtering  
requirements. The feedback loop is closed through an integrated  
compensation network within the IC, eliminating the need for  
additional external components. Protection features such as  
overvoltage, overcurrent, overpower, open- and short-circuit pro-  
tection, overtemperature, and brownout help protect the device  
during abnormal transient conditions.  
Overvoltage Protection with Hysteresis  
Overpower Protection with Shutdown  
UVLO with Wide Hysteresis  
Thermal Shutdown with Hysteresis  
Pin Assignments  
NC  
STBY  
IAC  
1
2
3
4
8
7
6
5
NC  
VDD  
GD  
FB  
GND  
8-lead SOIC  
D5  
L1  
D6  
RAC  
RFB  
R1a  
R2a  
R2b  
R2c  
BR1  
BR1  
R1b  
R1c  
CS1600  
Clink  
1
3
7
8
2
4
6
5
C3a  
NC  
STBY  
FB  
C1  
AC  
Mains  
IAC  
VDD  
NC  
C3b  
+12V  
Q1  
R3  
GD  
C2  
BR1  
BR1  
GND  
This document contains information for a product under development.  
Cirrus Logic reserves the right to modify this product without notice.  
Advance Product Information  
Cirrus Logic, Inc.  
http://www.cirrus.com  
Copyright Cirrus Logic, Inc. 2010  
JUL ‘10  
DS904A7  
(All Rights Reserved)  
CS1600  
1. PIN DESCRIPTIONS  
NC  
STBY  
IAC  
1
2
3
4
8
7
6
5
NC  
VDD  
GD  
FB  
GND  
Table 1. Pin Descriptions  
Pin Name  
NC  
Pin #  
I/O  
Description  
No Connect — Connect these pins to VDD to prevent any leakage path that could  
1, 8  
-
arise from leaving them unterminated.  
Standby — This is an active-low pin. Shorting this pin to GND disables PFC switch-  
ing. The input has a pull-up resistor and should be driven with an open-collector  
device. Leave this pin unterminated when not in use.  
STBY  
IAC  
2
3
IN  
IN  
Rectified Line Voltage Sense — The IAC pin is used to sense the rectified line volt-  
age. This signal, in conjunction with the signal on the FB pin, is used in the Power  
Factor Correction (PFC) algorithm  
A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide  
noise immunity.  
Feedback Voltage Sense — The FB pin is used to sense the output voltage of the  
PFC stage. This signal, in conjunction with the signal on the IAC pin, is used in the  
Power Factor Correction (PFC) algorithm.  
FB  
4
IN  
A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide  
noise immunity.  
Ground — GND is a common reference for all the functional blocks in this device.  
GND  
GD  
5
6
Gate Drive — GD is the output of the device with a source capability of 0.5 A and a  
current sink capacity of 1 A.  
OUT  
IC Supply Voltage — VDD is the input used to provide bias to the device. This pin  
has an internal shunt to ground. An external bias needs to be applied for steady-  
state operation. A low-ESR ceramic decoupling capacitor at this pin is recommended  
for reliable operation of this device.  
VDD  
7
IN  
2
DS904A7  
CS1600  
2. CHARACTERISTICS AND SPECIFICATIONS  
2.1  
Absolute Maximum Ratings  
Pin  
Symbol  
VDD  
VIN  
Parameter  
Value  
Unit  
IC Supply Voltage1  
Input Voltage  
7
Vz  
V
2,3,4  
3,4  
6
-0.5 to VDD  
50  
V
mA  
V
IIN  
Input Current  
VGD  
IGD  
Gate Drive Voltage  
Gate Drive Current  
Human Body Model  
Machine Model  
-0.3 to VDD  
-1.0 / +0.5  
2000  
6
A
1,2,3,4,5,6,8  
1,2,3,4,5,6,8  
1,2,3,4,5,6,8  
-
ESD  
ESD  
ESD  
PD  
V
200  
V
Charged Device Model  
500  
V
Total Power Dissipation at 50° C2  
Junction Temperature Operating Range  
Storage Temperature Range  
600  
mW  
-
-
TJ  
-40 to +125  
-65 to +150  
ºC  
ºC  
TStg  
Notes: 1. The CS1600 has an internal shunt regulator that controls the nominal operating voltage on the VDD pin.  
2. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power  
dissipation at the rate of 50 mW / ºC for variation over temperature.  
2.2  
Electrical Characteristics  
Recommended operating conditions (unless otherwise specified): TA = TJ = -40º to +125º C, VDD = 10 to 15 V, GND = 0 V.  
Typical values are at TA = 25º C.  
Parameter  
VDD Supply Voltage  
Condition  
Symbol  
Min  
Typ  
Max  
Unit  
VDD Turn-on Threshold Voltage  
VDD Turn-off Threshold Voltage  
UVLO Hysteresis  
V
DD increasing  
Vth(St)  
Vth(Stp)  
VHys  
8.4  
7.1  
-
8.8  
7.4  
9.3  
7.9  
-
V
V
V
V
VDD decreasing  
1.3  
IDD = 20 mA  
VZ  
17.0  
17.9  
18.5  
Zener Voltage  
Supply Current Section  
Start-up Supply Current  
Standby Supply Current  
Operating Supply Current  
PFC Gate Drive Section  
VDD < Vth(St)  
STBY < 0.8V  
IST  
ISB  
IDD  
-
-
-
68  
80  
80  
112  
1.9  
μA  
μA  
CL = 1nF, fsw(max) = 70 kHz  
1.7  
mA  
Maximum Operating Frequency3,4  
Normal mode, VDD = 13 V  
Normal mode, VDD = 13 V  
fSW(max)  
62  
66  
70  
kHz  
Minimum Operating Frequency3,4  
Minimum Duty Cycle  
fSW(min)  
tDC_min  
Dmax  
ton_min  
ROH  
20  
22  
-
23  
0
kHz  
%
VDD = 13 V, STBY < 0.8 V  
-
Maximum Duty Cycle3,4  
Minimum On Time  
VDD = 13 V  
64  
66  
0.5  
9
68  
0.55  
-
%
VDD = 13 V  
0.45  
μs  
Ω
Output Source Resistance  
Output Sink Resistance  
Rise Time  
IGD = 100 mA, VDD = 13 V  
IGD = -200 mA, VDD = 13 V  
CL = 1 nF, VDD = 13 V  
-
-
-
ROL  
6
-
Ω
tr  
32  
60  
ns  
DS904A7  
3
CS1600  
Parameter  
Condition  
Symbol  
tf  
Min  
Typ  
15  
Max  
30  
1.3  
-
Unit  
ns  
v
Fall Time  
CL = 1 nF, VDD = 13 V  
-
-
Output Voltage Low  
Output Voltage High  
IGD = -200 mA,VDD = 13 V  
IGD = 100 mA,VDD = 13 V  
VOL  
0.9  
VOH  
11.3  
11.8  
v
Feedback and Protection 3, 7  
25º C  
-40º to +125º C  
25º C  
125  
120  
104  
101  
98  
129  
-
135  
136  
111  
113  
105  
105  
87  
Reference Current  
Iref  
μA  
%
%
108  
-
Overvoltage Protection Threshold  
Recovery from Overvoltage Protection  
-40º to +125º C  
25º C  
101  
-
-40º to +125º C  
25º C  
94  
Start-up Mode Start Threshold  
Normal Mode Start Threshold  
Recovery from Undervoltage  
83  
85  
99  
10  
125  
%
25º C  
97  
101  
-
25º C  
-
%
%
Overpower Protection Threshold 4  
Overpower Protection Hysteresis 4  
Input Brownout Protection Threshold  
123  
127  
GDRV turns off, 25º C  
% of full load as defined by Eq. 3  
-
5
-
%
Vout = 460V, GDRV turns off, 25º C VBP(th)  
79  
91  
85  
97  
93  
Vrms  
Vrms  
Vout = 460V, GDRV turns on, 25º C  
VBR  
104  
Input Brownout Recovery Threshold  
Thermal Protection  
Thermal Shutdown Threshold 3  
Thermal Shutdown Hysteresis  
STBY Input  
TSD  
130  
-
143  
9
155  
-
ºC  
ºC  
TSD(Hy)  
Logic Threshold 5  
Low  
-
-
-
0.8  
-
V
VDD – 0.8  
High  
2.3  
Thermal Characteristics  
Symbol  
Parameter  
Value  
Unit  
Thermal Resistance (Junction to Ambient)6.  
Thermal Resistance (Junction to Case)6.  
RθJA  
RθJC  
159  
39  
ºC / W  
ºC / W  
3. Specifications guaranteed by design & characterization.  
4. Specifications measured as an instantaneous quantity NOT as a time-averaged quantity.  
5. STBY is designed to be driven by an open-collector device. The input is internally pulled up with a 600 kΩ resistor.  
6. The package thermal impedance is calculated in accordance with JESD 51.  
7. Based upon input voltage 120 to 277 VAC and an output voltage (Vout) of 460 V, with boost inductance of 380 μH,  
output capacitance of 23.5 μF, and VDD of 13 V.  
4
DS904A7  
CS1600  
3. TYPICAL ELECTRICAL PERFORMANCE  
3.5  
13  
12  
11  
10  
9
CL = 1 nF  
SW(max) = 70 kHz  
TA = 25 °C  
3
f
2.5  
2
1.5  
1
Startup  
UVLO  
8
0.5  
0
Rising  
18  
Falling  
7
-50  
0
50  
100  
150  
0
2
4
6
8
10  
12  
14  
16  
20  
o
TEMP ( C)  
V
(V)  
DD  
Figure 1. UVLO Characteristics  
Figure 2. Start-up & UVLO vs. Temperature  
19  
2
1.5  
1
IDD = 20 mA  
18.5  
18  
0.5  
0
17.5  
17  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
o
TEMP ( C)  
o
TEMP ( C)  
Figure 3. UVLO Hysteresis vs. Temperature  
Figure 4. VDD Zener Voltage vs. Temperature  
DS904A7  
5
CS1600  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
14  
12  
10  
8
Operating  
VDD = 13 V  
CL = 1 nF  
fSW(max) = 70 kHz  
Source  
6
VDD = 13 V  
Isource = 100 mA  
sink = 200 mA  
Sink  
4
I
2
Start-up  
Standby  
Standby  
Start-up  
0
-60  
-40  
-20  
0
20  
40  
60  
80  
100 120 140  
-50  
0
50  
100  
150  
o
o
Gate Resistor (ROH, ROL) Temp ( C)  
TEMP ( C)  
Figure 5. Supply Current (ISB, IST, IDD) vs. Temperature  
Figure 6. Gate Resistance (ROH, ROL) vs. Temperature  
6
DS904A7  
CS1600  
4. INTRODUCTION  
The CS1600 is a digitally controlled Power Factor Correction  
(PFC) controller that operates in the Variable Frequency  
Discontinuous Conduction Mode (VF - DCM). The CS1600  
uses a proprietary digital algorithm to optimize control of the  
power switch to deliver highly efficient performance for  
electronic ballast applications. With this control scheme, the  
total number of external components needed is minimized in  
comparison to conventional control techniques, thus reducing  
the overall system cost.  
Figure 7 below.  
120  
Switching Frequency (% of Max)  
100  
80  
60  
40  
20  
0
Line Voltage (% of Max)  
Digital control is achieved by constantly monitoring two voltages  
– the PFC output voltage (Vlink) at pin FB and the rectified AC line  
voltage (Vrect) at pin IAC. This is done by measuring the currents  
that flow into the respective pins. These currents are then fed to  
the inputs of two analog-to-digital converters (ADCs) and are  
compared against an internal target current, Iref.  
0
45  
90  
135  
180  
Rectified Line Voltage Phase (Deg.)  
Figure 7. Switching Frequency vs. Phase Angle  
The digital outputs of the two ADCs are then processed in a  
control algorithm which determines the behavior of the  
CS1600 during start-up, normal operation, and under fault  
conditions such as brownout, overvoltage, overcurrent,  
overpower, and over-temperature. Details of operation during  
these conditions are discussed in later sections of this  
document.  
Maximum power transfer occurs at the peak of the AC line  
voltage, at which time, the frequency reaches its maxi-  
mum value. Switching losses are minimized during peri-  
ods of low power transfer by switching at lower  
frequencies near the zero-crossing of the AC line.  
This switching frequency profile helps reduce total BOM  
cost through savings in the size of the boost inductor and  
the EMI filter components, while at the same time, im-  
proving overall system efficiency.  
Some of the key features of the CS1600 are as follows:  
• Discontinuous Conduction Mode with Continuously  
Variable Switching Frequency  
• Integrated Feedback Control  
The PFC switching frequency is varied every switching  
cycle. This allows for a spread spectrum which minimizes  
the conducted EMI peaks at any given frequency, thereby  
minimizing the size and cost of the EMI filter required at  
the front-end.  
No external feedback compensation components are re-  
quired for the CS1600. The internal digital control engine  
self-compensates the feedback error signal using an  
adaptive control algorithm.  
• Protection Features  
During start-up, the control algorithm limits the maximum  
ON time and adjusts the frequency to avoid inductor sat-  
uration and provides a near-trapezoidal envelope for the  
input current during every half cycle. During normal oper-  
ation, as the line voltage changes over half of a line cycle,  
the frequency varies approximately 2:1 as shown in  
The CS1600 provides various protection features such as  
undervoltage, overcurrent, overpower, open and short  
circuit protection and brownout. It also provides the user  
with the option of using the STBY pin to disable switching  
of the device.  
DS904A7  
7
CS1600  
CRM mode near the peaks of the input line, in order to enable  
maximum power delivery, as illustrated in Figure 10 below.  
4.1  
PFC Implementation  
The PFC switching frequency profile over the line period has  
been discussed in detail in Section 4. In addition, the digital  
control algorithm tracks changes the AC input and operates in  
different frequency bands at different line voltages as  
illustrated in Figure 8 and Figure 9 below.  
Quasi  
CRM  
Quasi  
CRM  
DCM  
DCM  
DCM  
ILB  
fSW  
[kHz]  
100  
Burst Mode  
Max fSW  
Figure 10. DCM and quasi-CRM Operation with CS1600  
70  
4.1.1 Start-up Mode vs. Normal Mode  
CS1600 operates in two discrete states:  
35  
Min fSW  
Start-up mode:  
When the output voltage of the PFC stage, Vlink, is <90% of its  
nominal value, the device operates in the start-up mode. It  
continues operating in this mode till the nominal Vlink voltage  
is reached. The start-up algorithm provides an ON time which  
is varied in proportion to the sensed rectified voltage, while  
changing the switching frequency to provide maximum power.  
5%  
50%  
100%  
PO [W]  
Figure 8. Switching Frequency vs. Output Power  
Vin < 165 VAC  
During this start-up phase of operation, the switching  
frequency could be significantly lower than the normal  
operating frequency, and the input current waveform is forced  
into following a trapezoidal envelope in phase with the line  
voltage, to maximize energy transfer. The ON time and the  
switching frequency of the IC ensure that peak currents are  
kept controlled to prevent saturation of the boost inductor  
during this period.  
fSW  
[kHz]  
Burst Mode  
60  
Max fSW  
48  
Normal mode:  
24  
Min fSW  
Once Vlink reaches its nominal value, the chip operates in the  
normal mode. Here, the frequency follows the profile shown in  
Figure 7, and the ON time is varied to achieve PFC. Any drop  
in Vlink to below its undervoltage threshold, as defined in  
Section 2.2. Electrical Characteristics re-triggers the start-up  
mode of operation. A simplified illustration of operation in  
these two modes is shown below in Figure 11.  
5%  
50%  
100%  
PO [W]  
Figure 9. Switching Frequency vs. Output Power  
Vin > 165 VAC  
The CS1600 primarily operates in the DCM mode with a  
properly sized inductor. However, it will move into a quasi-  
100%  
90%  
Normal Mode  
Normal Mode  
t [ms]  
Figure 11. Start-up and Normal Modes  
8
DS904A7  
CS1600  
I
ref = Target Reference current used for feedback  
4.1.2 Burst Mode  
In addition to the start-up mode and normal mode of operation,  
the controller enters the burst mode of operation when the  
estimated output power (PO) is < 5% of its nominal value.  
During this stage, the PFC driver is disabled intermittently over  
a full line cycle period, as shown in Figure 12. The period of  
time for which the PFC drive is disabled depends on the level  
of loading present..  
Vlink  
RFB  
IFB  
VDD  
7
RIFB  
15k  
PO  
[W]  
ADC  
FB  
4
5%  
Burst Mode  
Active  
Figure 13. Output Feedback  
Vlink  
t [ms]  
Vin  
[V]  
PFC  
Disable  
Vin  
RFB  
IFB  
FET Vgs  
VDD  
7
RIFB  
15k  
ADC  
t [ms]  
FB  
4
Figure 12. Burst Mode of Operation  
4.2  
Input Feedforward and Output  
Regulation  
Figure 14. Input Feedforward  
4.3  
Protection Features  
The CS1600 continuously monitors the rectified AC line and  
the PFC output voltage through sense resistors tied to the IAC  
and the FB pins to monitor the voltages, scaled as currents.  
The rectified AC line sense resistor RAC needs to be the same  
size of the resistor RFB used for current feedback from the  
PFC output voltage. These currents are effectively compared  
against an internal reference current to provide adaptive PFC  
control. The resistor values are calculated as follows:  
4.3.1 Overvoltage Protection  
If the PFC output voltage, Vlink, exceeds the overvoltage  
threshold, as scaled by the current monitored by the sense  
resistors, the CS1600 provides protection by disabling the  
gate drive. A nominal hysteresis is provided to allow the  
system to recover from the fault condition, before switching is  
resumed.  
V
link VDD  
-----------------------------  
=
4.3.2 Overcurrent Protection  
RFB  
[Eq.1]  
[Eq.2]  
Iref  
The CS1600’s digital controller algorithm limits the ON  
time of the Power MOSFET by the following equation:  
RAC = RFB  
0.001126  
Vrect  
------------------------  
Ton  
where  
Where Ton is the max time that the power MOSFET is  
turned on and Vrect is the rectified line voltage. In the  
event of a sudden line surge or sporadic, high dv/dt line  
voltages, this equation may not limit the ON time appro-  
priately. For this type of line disturbance, additional pro-  
tection mechanisms, such as fusible resistors, fast-blow  
fuses, or other current-limiting devices, are recommend-  
ed.  
RFB = Feedback resistor used to sense the PFC output  
voltage  
RAC = Feedforward resistor used to sense the rectified line  
voltage  
V
link= PFC Output Voltage  
DD = IC Supply Voltage  
V
DS904A7  
9
CS1600  
for the output voltage, drops to 49% of its nominal value.  
Detection of brownout for a period of 56 ms disables the gate  
drive. The device continues to monitor the input voltage while  
in this condition. The CS1600 exits the brownout mode when  
the input current scales up to, and stays above 56.4% of its  
nominal value for a period of 56 ms.  
4.3.3 Overpower Protection  
The nominal output power is estimated internally by the  
CS1600 from the following equation  
V
V
link (  
× 2)  
in(min)  
2
V
---------------------------------------------------------  
= α × η × ( in(min)) ×  
[Eq.3]  
P
o
2 × fmax × LB× Vlink  
To minimize false detects, the brownout detection circuit  
increases the brownout detection time by a factor of 1.6 mS/V  
for every volt differential between the minimum operating  
voltage and the brownout threshold, following half of a line  
cycle of exceeding the brownout threshold. The following  
diagram illustrates the brownout sequence whereby the  
CS1600 enters standby, and upon recovery from brownout,  
enters normal operation..  
where  
Po = rated output power of the system  
η = efficiency of the boost converter = estimated as 100% by  
the internal PFC algorithm  
V
in(min) = minimum RMS line voltage for operation  
Vlink = PFC output voltage  
max = maximum switching frequency  
TBrownout  
56 ms  
56 ms  
f
Brownout  
Thresholds  
LB = boost inductor used in the application  
Upper  
Lower  
Vlink  
-------------  
× 90V × 2  
Vlink  
Start  
Timer  
Vlink  
400V  
90V  
in(min)  
2  
------------- --------------------  
---------------------------------------------------------------------  
α =  
×
×
V
400V  
V
Vlink  
× 2  
in(min)  
Enter Standby  
Exit Standby  
Start Timer  
Operation estimated to be at power levels higher than that  
calculated by Eq. 3 above is tracked by the IC as an  
overpower condition. During this phase, the PFC output  
voltage, Vlink, is reduced and will continue to decrease as the  
power draw increases. When Vlink reaches its undervoltage  
threshold, it goes into the start-up mode as explained in  
section 4.1.1.  
Figure 15. Brownout  
4.3.6 Over-temperature Protection  
Over-temperature protection is activated and PFC switching is  
disabled when the die temperature of the device exceeds  
125°C. There is a hysteresis of about 30°C before resumption  
of normal operation.  
At this point, the overpower protection timer is activated. If this  
condition continues to exist for 112 ms, the gate drive is  
disabled for a period of about 3 seconds. This “hiccup” mode  
of operation continues until the fault is removed.  
4.4  
Standby (STBY) Function  
The standby (STBY) pin may be used as a means to force the  
CS1600 into a non-operating, low-power state. The STBY  
input should be driven by an open-collector/open-drain  
device. Internal to the pin, there is a pull-up resistor connected  
to the VDD pin as shown in Figure 16. A filter capacitance of  
about 1000 pF is recommended while this pin is being used.  
If a value of the boost inductor other than that obtained from  
Eq. 3 above is used, the total output power capability as well  
as the thresholds for the different operating conditions will  
scale accordingly.  
4.3.4 Open/short circuit protection  
CAP  
The CS1600 protects the system in case the feedforward  
resistor tied to the IAC pin or the feedback resistor tied to the  
FB pin is open or shorted to ground.  
600 kΩ  
STBY  
A fault seen on the resistor going into the FB pin would imply  
no current being fed into the pin, which would trigger the Vlink  
undervoltage algorithm as described in Section 4.3.1.  
CS1600  
<1 nF  
See Text  
A fault detected on the IAC pin would trigger the brownout  
condition discussed in Section 4.3.5 below.  
GND  
4.3.5 Brownout Protection  
Brownout occurs when the current representing the rectified  
input voltage, nominally 100% of the reference current used  
Figure 16. STBY Pin Connection  
10  
DS904A7  
CS1600  
5. FLUORESCENT BALLAST APPLICATION EXAMPLE  
The following section gives an example for a front-end PFC stage design for an electronic ballast application. The equations that  
follow may be used as guidelines for any other requirements using the CS1600.  
D5  
L1  
D6  
RAC  
RFB  
R1a  
R1b  
R1c  
R2a  
R2b  
R2c  
BR1  
BR1  
CS1600  
Clink  
1
3
7
8
2
4
6
5
C3a  
C3b  
NC  
STBY  
C1  
AC  
Mains  
IAC  
VDD  
NC  
FB  
GD  
+12V  
Q1  
R3  
C2  
BR1  
BR1  
GND  
Figure 17. CS1600 Basic Application Circuit  
5.1  
Component Selection Guidelines  
[Eq.5]  
The following design example is for a wide-input-voltage  
fluorescent ballast application using 2 T5 lamps in series for a  
total nominal power of 108W.The target specifications for the  
PFC portion of the design, assuming a 94% efficient second  
stage, are as follows:  
RAC = RFB  
RAC = 3.45MΩ  
where  
V
V
108 VAC  
305 VAC  
460 V  
in(min)  
RFB = Feedback resistor used to reflect the PFC output  
voltage  
in(max)  
RAC = Feedforward resistor used to reflect the rectified line  
voltage  
V
link  
P
115 W  
95%  
o
Vlink= PFC Output Voltage  
η
V
DD = IC Supply Voltage  
I
ref = Target reference current used for feedback  
5.1.1 IAC and IFB Sense Resistors  
1% or lower tolerance resistors are recommended to  
maximize the tightly toleranced system behavior provided by  
the unique digital controller in the CS1600. Resistors may be  
separated into two or more series elements if voltage  
breakdown and/or regulatory compliance is of concern.  
The rectified line voltage, VAC, and the output voltage of the  
PFC boost converter, Vlink, are scaled as currents by using  
sense resistors, whose values are estimated based on the  
equations below:  
V
link Vdd  
5.1.2 PFC Input Filter Capacitor  
---------------------------  
[Eq.4]  
RFB  
RFB  
=
=
Iref  
For a typical 115 W PFC output stage required to power up a  
108 W fluorescent ballast, an input filter capacitance of  
0.33 μF is recommended. Capacitor tolerances and the value  
of the EMI filter capacitor need to be considered when  
selecting the value of the capacitor to be used in this  
application.  
460 12  
---------------------------  
130 × 106  
RFB = 3.45MΩ  
DS904A7  
11  
CS1600  
The minimum RMS current rating, IFET(rms), required for the  
FET is calculated as follows:  
5.1.3 PFC Boost Inductor  
Equation 3 can be rewritten to calculate the PFC boost  
PO  
Inductor, LB, as follows:  
Vlink  
[Eq.9]  
-----------------------------  
IFET(rms)  
ILB(rms)  
=
=
V
in(min) × η  
-------------  
× 90V × 2  
Vlink  
2  
115  
Vlink  
400V  
90V  
in(min)  
------------- --------------------  
---------------------------------------------------------------------  
[Eq.6]  
α =  
×
×
---------------------------  
V
400V  
V
108 × 0.95  
Vlink  
×
2
in(min)  
Vlink  
ILB(rms) = 1.12A  
× 90V × 2  
-------------  
Vlink  
2  
Vlink  
400V  
90V  
in(min)  
------------- --------------------  
---------------------------------------------------------------------  
α =  
×
×
=0.937  
V
400V  
V
Vlink  
×
2
in(min)  
5.1.5 PFC Diode  
The PFC diode peak current is equal to the inductor peak  
current:  
V
V
link (  
×
2)  
in(min)  
2
V
---------------------------------------------------------  
[Eq.6]  
LB = α × η × ( in(min)) ×  
ID(pk) = ILB(pk)  
ID(pk) = 3.17 A  
[Eq.10]  
2 × fmax × PO × Vlink  
2
(460 108 × 2)  
----------------------------------------------------------------  
LB = 0.937 × 0.95× 108 ×  
= 431μH  
2 × 70 × 103 × 115 × 460  
The PFC diode average current is calculated as follows:  
PO  
The RMS current rating for the inductor can be estimated as  
follows:  
-----------  
ID(avg)  
=
[Eq.11]  
Vlink  
PO  
115  
460  
---------  
ID(avg)  
=
-----------------------------  
ILB(rms)  
ILB(rms)  
=
=
V
in(min) × η  
[Eq.7]  
115  
ID(avg) = 0.25 A  
---------------------------  
108 × 0.95  
5.1.6 PFC Output Capacitor  
ILB(rms) = 1.12A  
The output capacitor needs to be designed to meet the voltage  
ripple and hold-up time requirements. In the case of a cost-  
sensitive ballast application, the hold-up requirement is not a  
key requirement.  
The peak inductor current, ILB(pk), may be estimated using the  
following equation:  
4 × PO  
The CS1600 has been designed to operate with a low output  
capacitance of approximately 0.2 μF per watt of output power.  
-------------------------------------------  
ILB(pk)  
=
η × Vin(min)  
×
2
[Eq.8]  
For this specific application:  
4 × 115  
0.95 × 108 ×  
-----------------------------------------  
ILB(pk)  
=
2
0.2μF  
---------------  
× 115W = 23μF  
Cout  
=
W
ILB(pk) = 3.17 A  
The 120 Hz ripple on the output capacitor may be estimated  
using the following equation:  
Inductor tolerances should be considered when estimating the  
peak currents present in the application.  
PO  
------------------------------------------------------------------------  
The internal control algorithm of the controller dictates that the  
peak inductor current seen in the application could be as high  
as a pre-defined threshold of 0.001984 times the inverse of  
the inductor, which in this example amounts to 4.72 A. Care  
needs to be taken to ensure that the saturation current rating  
of the PFC boost inductor factors in this threshold used for the  
protection schemes.  
[Eq.12]  
ΔVlink(rip)  
=
=
2π × fline(min) × Vlink × Cout  
115  
------------------------------------------------  
2π × 45 × 460 × 23  
= 40.2V  
where  
out = Output Capacitance value  
Po = Output Power  
line(min) = Minimum Line Frequency  
link = PFC Output Voltage  
ΔVlink = Peak-Peak Voltage Ripple on the PFC Output  
5.1.4 PFC MOSFET  
C
The peak voltage stress on the PFC MOSFET is a diode drop  
above the output voltage. Accounting for leakage spikes, for  
the 460 V output application, a 600 V FET is recommended.  
f
V
The FET should be able to handle the same peak current as  
that seen through the inductor. This would amount to 3.17 A.  
12  
DS904A7  
CS1600  
The voltage rating on the capacitor needs to account for the  
operation of the device before it hits the overvoltage protection  
threshold. This is typically 105% of nominal value, which is  
483 V. With the ripple voltage factored in, 22 μF of  
capacitance rated at 500 V would suffice for this application.  
DS904A7  
13  
CS1600  
5.2  
Bill of Materials (for Application Example shown in Figure 17)  
Designator  
R1a  
R1b  
R1c  
R2a  
R2b  
R2c  
R3  
Value  
1.5 MΩ  
1.5 MΩ  
1.5 MΩ  
1.5 MΩ  
1.5 MΩ  
1.5 MΩ  
24.9Ω  
Description/Part Number  
C1  
0.47μF  
4.7μF  
C2  
C3a  
C3b  
BR1  
D5  
23.5μF  
2 47μF, 250V caps in series  
4A, 600V  
1 A, 600  
3A, 600V  
Bridge diode - GBU4J-BP  
1N4005  
D6  
MURS360  
Premier Magnetics TSD-2798  
Renco RLCS-1002  
L1  
420μH (max)  
Q1  
9A, 600V  
-
FCP9N60N  
CS1600  
CS1600-FSZ  
14  
DS904A7  
CS1600  
5.3  
Summary of Equations  
Eq. #  
Equation  
V
link VDD  
1, 4  
2, 5  
3, 6  
-----------------------------  
RFB  
=
Iref  
RAC = RFB  
V
V
link (  
× 2)  
in(min)  
2
V
---------------------------------------------------------  
PO = α × η × ( in(min)) ×  
2 × fmax × LB× Vlink  
PO  
7
-----------------------------  
=
ILB(rms)  
V
in(min) × η  
4 × PO  
-------------------------------------------  
ILB(pk)  
=
8
9
η × Vin(min)  
×
2
PO  
-----------------------------  
=
IFET(rms)  
V
in(min) × η  
10  
11  
ID(pk) = ILB(pk)  
PO  
-----------  
=
ID(avg)  
Vlink  
PO  
12  
--------------------------------------------------------------------------------------  
=
Cout  
2π × fline(min) × Vlink × ΔVlink(rip)  
DS904A7  
15  
CS1600  
6. PACKAGE DRAWING  
8L SOIC (150 MIL BODY) PACKAGE DRAWING  
E
H
1
b
c
D
SEATING  
PLANE  
A
L
e
A1  
INCHES  
MILLIMETERS  
MIN  
DIM  
A
MIN  
0.053  
0.004  
0.013  
0.007  
0.189  
0.150  
0.040  
0.228  
0.016  
0°  
MAX  
0.069  
0.010  
0.020  
0.010  
0.197  
0.157  
0.060  
0.244  
0.050  
8°  
MAX  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
1.52  
6.20  
1.27  
8°  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
1.02  
5.80  
0.40  
0°  
A1  
B
C
D
E
e
H
L
JEDEC # : MS-012  
16  
DS904A7  
CS1600  
7. ORDERING INFORMATION  
Part #  
Temperature Range  
Package Description  
8-lead SOIC, Lead (Pb) Free  
CS1600-FSZ  
-40 °C to +125 °C  
8. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION  
a
b
Model Number  
Peak Reflow Temp  
MSL Rating  
Max Floor Life  
CS1600-FSZ  
260 °C  
2
365 Days  
a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.  
b. Stored at 30 °C, 60% relative humidity.  
DS904A7  
17  
CS1600  
9. REVISION HISTORY  
Revision  
A1  
Date  
Changes  
Initial Advance Information release.  
OCT 2009  
MAR 2010  
A2  
Revised feature list, product description and parametric table to reflect  
the C0 version of silicon.  
A3  
A4  
MAR 2010  
APR 2010  
Revised to reflect the update in switching frequency and variation of  
frequency over line.  
Revised parametric table and equations to reflect the C1 version of  
silicon.  
A5  
A6  
A7  
MAY 2010  
JUN 2010  
JUL 2010  
Updated with additional test bench data for EP level.  
Added RθJA and RθJC in electrical specifications section.  
Updated operating supply current, overpower protection recovery, out-  
put capacitance calculation. Added Figure 6.  
Contacting Cirrus Logic Support  
For all product questions and inquiries contact a Cirrus Logic Sales Representative.  
To find one nearest you go to http://www.cirrus.com  
IMPORTANT NOTICE  
“Advance” product information describes products that are in development and subject to development changes.  
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject  
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant  
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale  
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus  
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third  
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,  
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-  
sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent  
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-  
ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE  
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT-  
ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR-  
RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND  
FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM-  
ER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY  
INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT-  
TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.  
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL CORE, and the EXL CORE logo designs are trademarks of Cirrus Logic, Inc. All other brand and product  
names in this document may be trademarks or service marks of their respective owners.  
18  
DS904A7  

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