CL-CD2431-10QC-D [CIRRUS]
Multi Protocol Controller, 4 Channel(s), 0.01640625MBps, MOS, PQFP100, PLASTIC, QFP-100;
| 型号： | CL-CD2431-10QC-D |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | Multi Protocol Controller, 4 Channel(s), 0.01640625MBps, MOS, PQFP100, PLASTIC, QFP-100 通信 时钟 数据传输 外围集成电路 |
| 文件： | 总190页 (文件大小：1592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CL-CD2431
Data Book
FEATURES
■ Four full-duplex multi-protocol channels, each running
up to 134.4 kbits/second (with CLK = 35 MHz)
Advanced Multi-Protocol
Communications Controller
■ Supports async, async-HDLC (high-level data link
control), and HDLC/SDLC (synchronous data link
control; non-multidrop) on all channels
■ 32-bit address, 16-bit data, double-buffered DMA
controller for each transmitter and receiver; two
independent bit-rate generators per channel for
transmit and receive
OVERVIEW
■ On-chip NRZ (nonreturn-to-zero), NRZI (nonreturn-to-
zero inverted), and Manchester data encoding and
decoding
The CL-CD2431 is a 4-channel synchronous/asyn-
chronous communications controller specifically
designed to reduce host-system processing over-
head and increase efficiency in a wide variety of
communications applications. The CL-CD2431 is
packaged in a 100-pin PQFP, and offers eight
clock/modem pins per channel.The device has four
fully independent serial channels that support asyn-
chronous, asynchronous-HDLC, and bit-synchro-
nous (HDLC/SDLC) protocols.
■ DPLL (digital phase locked loop) on each receiver
■ Two independent timers per channel
PPP (Point-to-Point Protocol) Features
■ Supports data link level — RFC-1661
■ Supports dual async control character maps (32
control characters) — RFC-1662
Async-HDLC Features
The CL-CD2431 is based on a proprietary on-chip
RISC processor that performs all time-critical, low-
level tasks that are otherwise performed by the host
system.
■ Compatible with ISO 3309/4335 Addendum 1
■ Automatic insertion and deletion of control/ escape
characters and bit complements
■ Automatic generation and detection of 16-bit FCS
(frame check sequence)
(cont.)
(cont.)
Functional
Block Diagram
4 SERIAL
INTERFACE
MODEM
CHANNELS
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
HOST
BUS
INTERFACE
LOGIC
RAM
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
HOST
INTERFACE
MODEM
RECEIVE/CRC
TRANSMIT/CRC
ON-CHIP
DMA
CONTROLLER
TIMER/BRG/DPLL
PROPRIETARY
RISC
PROCESSOR
AND
FIRMWARE
INTERFACE
ROM
LOGIC
MODEM
RECEIVE/CRC
TRANSMIT/CRC
TIMER/BRG/DPLL
Version 3.0
August 1996
World Wide Web: http://www.cirrus.com ftp: ftp.cirrus.com/~ftp/pub/support/sio
CL-CD2431
Advanced Multi-Protocol Communications Controller
FEATURES (cont.)
— Flow-control transparency, LNext
MNP 4 V.42 Features
■ Programmable timer closely coupled with character
reception, especially for asynchronous receive DMA
operation
■ AppleTalk Remote Access Protocol 1.0/2.0
SLIP Features
■ Supports data link level — RFC-1055
DMA Controller Features
■ DMA or interrupt selectable per channel and per
HDLC/SDLC (Non-multidrop) Features
direction
■ Four 8-bit or two 16-bit frame address matching
■ FCS generation and validation
■ Dual Configuration register sets to reduce realtime
constraints
■ CRC (cyclic redundancy check) optionally readable
■ Programmable leading-pad character transmission
■ Supports shared flags on receive frames
■ Programmable number of leading flags
■ Append and Block mode DMA
■ Chain/unchain of long frames into multiple buffers
■ 32-bit address and 8- or 16-bit data transfer
■ Programmable gap in buffers following a receive
character exception
Asynchronous Features
Other Features
■ User-programmable and automatic flow control modes
— In-band (software) via XON/XOFF
■ Improved interrupt schemes
— Out-of-band (hardware flow control) via RTS/CTS and
DTR/DSR
— Vectored interrupts per channel allow direct jump into
proper service routines
— Line break detection and generation
— Special-character and character-range recognition and
transmission
— Good Data interrupts eliminate need for status checks
■ Easily cascadable for multiple-device configurations
■ 16-byte receive and transmit FIFOs
— Transmit delay
■ Local and remote maintenance loopback modes
■ 5- to 8-bit character plus optional parity
■ Enhanced features for UNIX environment
■ Byte-endian-orientation selection pin allows easy
interface to 80X86 and 680X0 processors
— Character expansion in transmit (for example, sending
<LF> will be expanded to <CR> <LF> automatically)
— Programmable translation of receiving character with
error to different pattern (for example, character with par-
ity error can be translated into FFh, 00h, character on
the system side)
■ Eight clock/modem control signals per channel
(in addition to TxD and RxD)
OVERVIEW (cont.)
The CL-CD2431 boosts system efficiency with on- The CL-CD2431 can be programmed to interrupt
chip DMA, on-chip FIFOs, intelligent vectored inter- the host at the completion of a frame or buffer. In
rupts, and intelligent protocol processing. The on- applications where buffers are of a small, fixed size,
chip DMA controller provides ‘fire-and-forget’ trans- the dual-buffer scheme allows large frames to be
mit support — the host need only inform the
CL-CD2431 of the location of the packet to be sent.
Similarly, on receive, the CL-CD2431 automatically
receives a complete packet with no host intervention
or assistance required.The DMA controller also has
an ‘Append mode’ for use in asynchronous applica-
tions.
divided into multiple buffers.
For applications where a DMA interface is not
desired, the device can be operated as an interrupt-
driven or polled device.This choice is available indi-
vidually for each channel and each direction. For
example, a channel can be programmed for DMA
transmit and interrupt-driven receive.
The DMA controller uses a dual-buffer scheme that
easily implements simple or complex buffer
schemes. Each channel and direction has two
active buffers.
In either case, 16-byte FIFOs on each channel and
in each direction reduce latency time requirements,
making both software and hardware designs less
2
August 1996
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
OVERVIEW (cont.)
time-critical. Threshold levels on FIFOs are user-
programmable.
modem-signal change, with unique user-defined
vectors for each type and channel. This allows very
flexible interfacing and fast, efficient interrupt cod-
ing. For example, the Good Data interrupt allows
the host to vector directly to a routine that transfers
the data — no status or error checking is required.
Efficient vectored interrupts are another way the
CL-CD2431 help system efficiency. Separate inter-
rupts are generated for transmit, receive, and
Benefits
❒ Substantially reduced host CPU overhead means more channels and faster overall throughput.
❒ No time-critical host software enables faster, easier software development.
❒ Smallest possible footprint for multi-channel device.
CL-CD2XXX Family Compatibility
Features
CL-CD2231
CL-CD2401
CL-CD2431
Number of serial channels
Interrupt on-chip DMA mechanism
FIFO depth (per channel and per direction)
Data size (bits)
2
4
✓
16
✓
✓
✓
✓
–
4
✓
16
✓
✓
✓
–
a
✓
16
✓
✓
✓
–
ASYNC
SDLC/HDLC
X.21, BISYNC
Async-HDLC, PPP
SLIP
✓
✓
●
●
b
●
–
●
MNP
4
–
c,d
c
c
Serial data rate (kbits/second)
256/230.4
128/134.4
128/134.4
Number of modem leads
(per channel, including RxD and TxD)
10
10
10
On-chip timers
✓
✓
✓
e
UNIX character processing
✓
✓
✓
●
In-band Rx flow control
Special character Tx and recognition
Package
–
(Revision B)
✓
100-pin PQFP
✓
✓
100-pin PQFP
✓
✓
100-pin PQFP
✓
System interface
Pin compatibility
CL-CD2401/CD2431
CL-CD2431/CD2231 CL-CD2401/CD2231
a
✓indicates identical operation and register setting.
b
c
d
●indicates available in production revision (Revision B) and later.
A clock frequency of 35 MHz is required to obtain maximum bit rates.
134.4 kbps/230.4 kbps in all async modes, 128 kbps/256 kbps in sync modes: applies to Revision M or later CL-CD2401, Revision D and
later CL-CD2431, Revision D or later CL-CD2231.
e
UNIX character processing is available in ASYNC only.
August 1996
3
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Before beginning any new design with this device, please contact Cirrus Logic Inc. for the
latest errata information. See the back cover of this document for sales office locations and
phone numbers.
TABLE OF CONTENTS
3.3.6 Transmit Timer ..............................................37
3.4 DMA Operation ................................................37
3.4.1 Bus Acquisition Cycle...................................38
REVISION HISTORY ............................. 6
CONVENTIONS..................................... 7
1. PIN INFORMATION ............................... 8
1.1 Pin Diagram — CL-CD2431...............................8
1.2 Pin Functions — CL-CD2431 ............................9
1.3 Pin Descriptions...............................................10
3.4.2 DMA Data Transfer .......................................39
3.4.3 Bus Error Handling .......................................40
3.4.4 A and B Buffers and Chaining ......................40
3.4.5 Transmit DMA Transfer .................................41
3.4.6 Synchronous Transmitter Examples .............42
3.4.7 Receive DMA Transfer..................................44
3.4.8 Transmit DMA Transfer .................................47
3.4.9 Receive Buffer Interrupts..............................49
3.5 Bit Rate Generation and Data Encoding..........50
3.5.1 BRG and DPLL Operation............................50
3.6 Hardware Configurations .................................59
3.6.1 Interface to a 32-Bit Data Bus.......................60
3.6.2 DMA Connections for the CL-CD2431..........60
2. REGISTER TABLE............................... 14
2.1 Memory Map....................................................14
2.1.1 Global Registers...........................................14
2.1.2 Option Registers...........................................15
2.1.3 Bit Rate and Clock Option Registers............16
2.1.4 Channel Command and Status Registers ....16
2.1.5 Interrupt Registers........................................16
2.1.6 DMA Registers .............................................18
2.1.7 Timer Registers ............................................19
2.2 Register Definitions..........................................20
2.2.1 Global Registers...........................................20
2.2.2 Option Registers...........................................20
2.2.3 Bit Rate and Clock Option Registers............23
2.2.4 Channel Command and Status Registers ....24
2.2.5 Interrupt Registers........................................25
2.2.6 DMA Registers .............................................28
2.2.7 Timer Registers ............................................30
3.6.3 Recommended CL-CD2431 as a DTE and
DCE Interface ...............................................61
4. PROTOCOL PROCESSING................ 62
4.1 HDLC Processing ............................................62
4.1.1 FCS (Frame Check Sequence).....................62
4.1.2 HDLC Transmit Mode....................................62
4.1.3 HDLC Receive Mode....................................63
4.2 PPP (Point-to-Point Protocol) Mode.................63
4.2.1 Character Format..........................................63
4.2.2 Frame Format...............................................64
4.2.3 FCS (Frame Check Sequence).....................64
4.2.4 Transparency ................................................64
4.2.5 Definition of a Valid Frame............................65
4.2.6 Transmitter....................................................66
4.2.7 Receiver........................................................66
4.3 SLIP Processing ..............................................67
4.3.1 Framing.........................................................67
4.3.2 Debugging Aids ............................................67
4.4 MNP 4/ARAP Protocol Processing................68
4.4.1 Framing.........................................................68
3. FUNCTIONAL DESCRIPTION............ 31
3.1 Host Interface...................................................31
3.1.1 Host Read and Write Cycles ........................31
3.1.2 Byte and Word Transfers...............................32
3.2 Interrupts..........................................................32
3.2.1 Contexts and Channels ................................32
3.2.2 Interrupt Registers........................................33
3.2.3 Groups and Types.........................................34
3.2.4 Hardware Signals and IACK Cycles .............35
3.2.5 Multi–CL-CD2431 Systems ..........................35
3.3 FIFO and Timer Operations.............................36
3.3.1 Receive FIFO Operation...............................36
3.3.2 Transmit FIFO Operation..............................36
3.3.3 Timers...........................................................36
3.3.4 Timers in Synchronous Protocols.................36
3.3.5 Timers in Asynchronous Protocols...............37
4.4.2 MNP 4/ARAP FCS (Frame Check
Sequence) Calculation .................................68
4.5 Async Processing ............................................69
4.5.1 Transmitter In-Band Flow Control .................69
4.5.2 Out-of-Band Flow Control.............................70
4
August 1996
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
4.5.3 Line Break Detection and Generation ..........71
4.5.4 Special Character Transmission ...................72
4.5.5 Special Character Recognition and Special
Character Range ..........................................72
6.2.14 Transmit Special Mapped Characters — PPP
Mode only...................................................106
6.2.15 Transmit Async Control Character Maps —
PPP Mode Only..........................................107
6.2.16 Receive Async Control Character Maps — PPP
Mode Only ..................................................108
6.3 Bit Rate and Clock Option Registers .............109
4.5.6 Special Character Range .............................73
4.5.7 UNIX Support Features ................................73
4.6 Non-8-Bit Data Transfers..................................73
6.3.1 Receive Bit Rate Generator Registers........109
6.3.2 Transmit Bit Rate Generator Registers.......111
6.4 Channel Command and Status Registers......113
6.4.1 Channel Command Register (CCR) ...........113
6.4.2 Special Transmit Command Register
(STCR) .......................................................116
6.4.3 Channel Status Register (CSR)..................119
6.4.4 Modem Signal Value Registers (MSVR).....123
6.5 Interrupt Registers .........................................124
6.5.1 General Interrupt Registers ........................124
6.5.2 Receive Interrupt Registers ........................129
6.5.3 Transmit Interrupt Registers........................140
6.5.4 Modem Interrupt Registers.........................145
6.6 DMA Registers...............................................149
6.6.1 DMA Receive Registers..............................151
6.6.2 DMA Transmit Registers .............................156
6.7 Timer Registers..............................................165
6.7.1 Timer Period Register (TPR) ......................165
5. PROGRAMMING EXAMPLES............ 77
5.1 Global Initialization...........................................78
5.2 Async Interrupt Setup Example .......................79
5.3 HDLC DMA Channel Setup Example ..............79
5.4 Receive DMA Interrupt Service Routine..........80
5.5 Transmit Interrupt Service Routine ..................81
5.6 Support Files....................................................82
5.6.1 The Cirrus Logic FTP Server........................82
5.6.2 Web Access..................................................82
6. DETAILED REGISTER
DESCRIPTIONS .................................. 83
6.1 Global Registers ..............................................83
6.1.1 Global Firmware Revision Code Register
(GFRCR) ......................................................83
6.1.2 Channel Access Register (CAR) ..................84
6.2 Option Registers..............................................85
6.2.1 Channel Mode Register (CMR) ....................85
6.2.2 Channel Option Register 1 (COR1)..............86
6.2.3 Channel Option Register 2 (COR2)..............88
6.2.4 Channel Option Register 3 (COR3)..............91
6.2.5 Channel Option Register 4 (COR4)..............96
6.2.6 Channel Option Register 5 (COR5)..............97
6.2.7 Channel Option Register 6 (COR6) — Async
Mode Only ....................................................98
6.2.8 Channel Option Register 7 (COR7) — Async
Mode Only ....................................................99
6.7.2 Receive Timeout Period Register (RTPR)
Async Mode Only .......................................166
6.7.3 General Timer 1 (GT1) Sync Modes Only ..167
6.7.4 General Timer 2 (GT2) Sync Modes Only ..168
6.7.5 Transmit Timer Register (TTR) Async
Modes Only ................................................168
7. ELECTRICAL SPECIFICATIONS......169
7.1 Absolute Maximum Ratings ...........................169
7.2 DC Electrical Characteristics .........................169
7.3 AC Electrical Characteristics..........................170
6.2.9 Special Character Registers — Async Modes
Only ............................................................100
8. PACKAGE SPECIFICATIONS ...........180
6.2.10 Special Character Range Register — Async
Mode Only ..................................................102
6.2.11 LNext Character (LNXT) — Async Mode Only .
103
9. ORDERING INFORMATION
EXAMPLE...........................................181
INDEX .................................................183
BIT INDEX ..........................................187
6.2.12 Receive Frame Address Registers — HDLC
Sync Mode Only .........................................104
6.2.13 CRC Polynomial Select Register (CPSR)...105
August 1996
5
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
REVISION HISTORY
Major changes between the previous data book (dated March 1995) and this version are listed below.
Section
Revision
2, 6
A new bit has been added to the DMR register.This bit allows optional internal syn-
chronization of the DTACK input to the BUSCLK. This bit must be set if external
logic does not synchronize the DTACK input with BUSCLK before it is applied to
the input pin.
6
The register-description format has been changed to better describe register
options.
7
Timing diagrams and tables that reflect the new maximum clock frequency of 35
MHz (Revision D and later devices only) have been added.
Index
A bit index has been added.
6
August 1996
REVISION HISTORY
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Acronyms
Acronym
CONVENTIONS
Definition
This section lists abbreviations and acronyms
used in this data book.
AC
alternating current
BRG
bisync
CMOS
CRC
DC
bit rate generation
Abbreviations
byte synchronous
complementary metal-oxide semiconductor
cyclic redundancy chack
direct current
Symbol
Units of measure
°C
µF
degree Celsius
microfarad
DCE
DMA
DPLL
DRAM
DTE
data communication equipment
direct-memory access
digital phase-locked loop
dynamic random-access memory
data terminal equipment
frame check sequence
first in/first out
µs
microsecond (1,000 nanoseconds)
hertz (cycle per second)
kilobit (1,024 bits)
Hz
Kbit
kbits/sec.
kbps
kilobit (1,000 bits) per second
Kbyte
kbytes/sec.
kHz
kilobyte (1,024 bytes)
FCS
kilobyte (1,000 bytes) per second
FIFO
HDLC
ISA
kilohertz
high-level data link control
industry standard architecture
least-significant bit
kΩ
kilohm
Mbyte
MHz
mA
megabyte (1,048,576 bytes)
LSB
megahertz (1,000 kilohertz)
MSB
NRZ
NRZI
PPP
most-significant bit
milliampere
nonreturn to zero
ms
millisecond (1,000 microseconds)
nonreturn to zero inverted
point-to-point protocol
plastic quad-flat pack
random-access memory
read/write
ns
nanosecond
picovolt
volt
pV
PQFP
RAM
R/W
V
W
watt
SDLC
SLIP
TTL
synchronous data link control
The use of ‘tbd’ indicates values that are ‘to be
determined’, ‘n/a’ designates ‘not available’, and
‘n/c’ indicates a pin that is a ‘no connect’.
transistor-transistor logic
August 1996
7
DATA BOOK v3.0
CONVENTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
1. PIN INFORMATION
1.1 Pin Diagram — CL-CD2431
RXCIN[3]
51
TXCIN[3]
52
DSR*[0]
53
CTS*[0]
54
AEN*
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
ADLD*
DATEN*
DATDIR*
RESET*
RXCOUT[0]
IREQ*[3]
IREQ*[2]
CD*[3]
IREQ*[1]
GND
IACKOUT*
CD*[2]
IACKIN*
DTACK*
DS*
TXCOUT/DTR*[0]
55
RTS*[0]
56
DSR*[1]
57
CTS*[1]
58
TXCOUT/DTR*[1]
59
RTS*[1]
60
DSR*[2]
61
GND
62
CTS*[2]
63
CL-CD2431
TXCOUT/DTR*[2]
64
100-Pin PQFP
RTS*[2]
65
DSR*[3]
66
CTS*[3]
67
AS*
R/W*
TXCOUT/DTR*[3]
68
RTS*[3]
69
GND
70
BGACK*
CD*[1]
BGOUT*
BGIN*
VDD
A[7]
71
A[6]
72
A[5]
73
8
A[4]
74
BR*
7
A[3]
75
A[2]
76
BUSCLK
CLK
6
5
A[1]
77
SIZ[1]
4
A[0]
78
SIZ[0]
3
VDD
79
GND
2
A/D[15]
80
CS
1
8
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PIN INFORMATION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
1.2 Pin Functions — CL-CD2431
A [0-7]
A/D [0-15]
CLK
TXD
RXD
TXCIN
RXCIN
TXCOUT/DTR*
RXCOUT
RTS*
CS*
AS*
DS*
R/W*
DTACK*
SIZ [0-1]
BUSCLK
BERR*
RESET*
TEST
CTS*
DSR*
CD*
7
7
7
ADLD*
AEN*
DATDIR*
DATEN*
BYTESWAP
IACKIN*
IACKOUT*
IREQ*[1-3]
BR*
BGIN*
BGOUT*
BGACK*
6
VDD and GND
August 1996
9
DATA BOOK v3.0
PIN INFORMATION
CL-CD2431
Advanced Multi-Protocol Communications Controller
1.3 Pin Descriptions
The following conventions are used in the pin-description tables:
•
•
•
•
•
•
•
•
(*) after a name indicates that the signal is active-low
‘I’ indicates the pin is input-only
‘O’ indicates the pin is output-only
‘I/O’ indicates the pin is bidirectional
‘OD’ indicates open-drain; OD pins must be terminated to V by a 2-KΩ – 4.7-KΩ resistor
CC
‘TS’ indicates tristate
(–) indicates ascending pin numbers
(:) indicates descending pin numbers
Table 1-1. Pin Descriptions
Pin
Number
Symbol
Type
Description
CHIP SELECT*: When low, the CL-CD2431 registers can be read or written
by the host processor.
CS*
1
I
ADDRESS STROBE*: When the CL-CD2431 is a bus master, this pin is an
output that indicates that R/W*, A[0–7], and the externally latched A[8–31]
are valid.
AS*
DS*
14
15
I/O (TS)
DATA STROBE*: When the CL-CD2431 is not a bus master, this is an input
used to strobe data into registers during write cycles and enable data onto
the bus during read cycles. When the CL-CD2431 is a bus master, DS* is an
output used to control data transfer to and from system memory.
I/O (TS)
I/O (TS)
READ/WRITE*: When the CL-CD2431 is not a bus master, this pin is an
input that determines if a read or write operation is required when the CS*
and DS* signals are active. When the CL-CD2431 is a bus master, R/W* is an
output and indicates whether a read from or a write to system memory is
being performed.
R/W*
13
16
DATA TRANSFER ACKNOWLEDGE*: When the CL-CD2431 is not a bus
master, this is an output and indicates to the host when a read or write to the
CL-CD2431 is complete. When BR* is driven low by the CL-CD2431,
DTACK* is an input that indicates that the system bus is no longer in use.
When the CL-CD2431 is a bus master, DTACK* is an input that indicates
when system memory read and write cycles are complete.
DTACK*
I/O (OD)
10
August 1996
PIN INFORMATION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Pin
Number
Symbol
Type
Description
SIZE [0–1]: When not the active bus master, these are inputs that determine
the size of the operand being read or written by the host.
SIZ[1] SIZ[0]
†
0
1
0
1
1
0
0
1
Byte
16 Bit
32 Bit
3 Bytes
‡
‡
SIZ[0–1]
3, 4
I/O (TS)
When the CL-CD2431 is a bus master, this is an output determining the size
of the operand being transferred to or from system memory.
SIZ[1] SIZ[0]
†
0
1
0
Byte
1
16 Bit
†
See BYTESWAP description.
‡
The CL-CD2431 drives DTACK* even though the device does not
respond to such byte alignment.
INTERRUPT ACKNOWLEDGE IN*: This input qualified with DS*, and
A[0–6], acknowledges CL-CD2431 interrupts.
IACKIN*
17
19
I
INTERRUPT ACKNOWLEDGE OUT*: This output is driven low during inter-
rupt acknowledge cycles for which no internal interrupt is valid.
IACKOUT*
O
INTERRUPT REQUEST* [1–3]: These outputs signal that the CL-CD2431
I/O (OD) has a valid interrupt for modem-lead activity (IREQ*[1]), transmit activity
(IREQ*[2]), or receive activity (IREQ*[3]).
IREQ*[1–3]
21, 23, 24
BUS REQUEST*: This output is used to signal to the (open drain) host pro-
cessor or bus arbiter that bus mastership is required by the CL-CD2431.
BR*
7
9
OD
BUS GRANT IN*: This input indicates that the bus is available after the cur-
rent bus master relinquishes the bus.
BGIN*
I
BUS GRANT OUT*: This output is asserted when BGIN* is low and no inter-
nal Bus Request has been made. A daisy-chain scheme of bus arbitration
BGOUT*
10
O
can be formed by connecting BGOUT* to BGIN* of the next device in the
chain. If a priority scheme is preferred, bus requests must be prioritized exter-
nally and bus grant routed to the BGIN* of the appropriate device
BUS GRANT ACKNOWLEDGE*: As an input, this signal is used to deter-
I/O (OD) mine if another alternate bus master is in control of the bus. As an output, it
signals to other bus masters that this device is in control of the bus.
BGACK*
BERR*
12
BUS ERROR*: If this input becomes active while the CL-CD2431 is a bus
master, the current bus cycle is terminated, the bus relinquished, and an
interrupt generated to indicate the error to the host processor.
100
I
ADDRESS [0–7]: When the CL-CD2431 is not a bus master, these pins are
inputs used to determine which registers are being accessed, or which inter-
rupt is being acknowledged. When ADLD* is low, A[0–7] output address bits
8 through 15 for external latching. When the CL-CD2431 is a bus master,
A[0–7] output the least-significant byte of the transfer address.
A[7:0]
71–78
I/O (TS)
ADDRESS/DATA [0–15]: When the CL-CD2431 is not a bus master, these
pins provide the 16-bit data bus for reading and writing to the CL-CD2431
registers. When ADLD* is low, A/D[0–15] provide the upper address bits for
external latching. When the CL-CD2431 is a bus master, A/D[0–15] provide a
multiplexed address/data bus for reading and writing to system memory.
80, 81, 83,
84, 86–95,
97, 98
A/D[15:0]
I/O (TS)
August 1996
11
DATA BOOK v3.0
PIN INFORMATION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Pin
Number
Symbol
Type
Description
ADDRESS LOAD*: This is a strobe used to externally latch the upper portion
of the system address bus A[8–31]. While ADLD* is low, address bits 16–31
are available on A/D[0–15], and address bits 8 through 15 on A[0–7].
ADLD*
AEN*
29
30
O (TS)
O (TS)
ADDRESS ENABLE*: This output is used to output enable the external
address bus drivers during CL-CD2431 DMA cycles.
DATA ENABLE*: This output is active when either the CL-CD2431 is a bus
master, or the CS* and DS* pins are low. It is used to enable the external data
bus buffers during host register read/write operations or during DMA opera-
tions. For operations on 32-bit buses, this signal needs to be gated with A[1]
to select the correct half of the data bus.
DATEN*
DATDIR*
28
27
O (TS)
O (TS)
DATA DIRECTION*: This output is active when either the CL-CD2431 is a
bus master, or the CS* pin is low. It is used to control the external data buff-
ers; when low, the buffers should be enabled in the CL-CD2431 to system
bus direction.
CLK
5
6
I
CLOCK: System clock.
BUS CLOCK: This is the system clock divided by 2, which is used internally
to control certain bus operations.This pin is driven low during hardware reset.
BUSCLK
O
RESET*:This signal should stay valid for a minimum of 20 ns. The reset state
of the CL-CD2431 is guaranteed at the rising edge of this signal. When
RESET* is removed, the CL-CD2431 also performs a software initialization of
its registers.
RESET*
26
I
I
TEST: In normal operation, this pin should be kept low. For board-level test-
ing purposes, it provides a mechanism for forcing normal output pins to High-
Impedance mode. When the TEST pin is high, the following pins are in High-
Impedance mode: BUSCLK, BGOUT*, IACKOUT*, RXCOUT[0–1],
RTS*[0–1], DTR*[0–1], and TXD[0–1].
TEST
33
To ensure all CL-CD2431 outputs are high-impedance, either of the following
two conditions must be met: the RESET* pin can be driven low, and the TEST
pin driven high; or, the CL-CD2431 is kept in the bus idle state (not accessed
for read/write operations nor DMA active), and the TEST pin is driven high.
56, 60, 65,
69
REQUEST TO SEND* [0–3]: This output can be controlled automatically by
the CL-CD2431 to indicate that data is being sent on the TXD pin.
RTS*[0–3]
O
O
TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0–1]: This output can
be controlled automatically by the CL-CD2431 to indicate a programmable
threshold has been reached in the receive FIFO. It can also be programmed
to output the transmit data clock. Following reset, this pin is high and stays
high in Clock mode until the transmit channel is enabled for the first time;
after which it remains active, independent of the state of the transmit enable.
In all modes, the clock transitions every bit time, even during idle fill in Asyn-
chronous mode. Data transitions are made on the negative-going edge of
TXCOUT.
TXCOUT/DTR*
[0–3]
55, 59, 64,
68
RECEIVE CLOCK OUT [0–1]: This output provides a one-time bit rate clock
for the receive data in all modes, except when an input (RXCIN) one-time
receive clock is used. After reset, this pin is low until the channel is receive
enabled for the first time, after which it remains active, independent of the
state of receive enable. When in Asynchronous mode, the output only transi-
tions while receiving data and not during inter-character fill. The receive data
is sampled on the positive-going edge of this clock.
25, 32, 37,
47
RXCOUT[0–3]
O
12
August 1996
PIN INFORMATION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Pin
Number
Symbol
Type
Description
54, 58, 63,
67
CLEAR TO SEND* [0–1]: This input can be programmed to control the flow
of transmit data, for out-of-band flow control applications.
CTS*[0–3]
CD*[0–3]
I
I
85, 11, 18,
22
CARRIER DETECT* [0–1]: This pin is always visible in the MSVR register.
The CD input can be programmed to validate receive data.
44, 48, 50,
52
TRANSMIT CLOCK [0–1]: This pin inputs the transmit clock to the bit rate
generator.
TXCIN[0–3]
RXCIN[0–3]
DSR*[0–3]
TXD[0–3]
I
43, 46, 49,
51
RECEIVE CLOCK [0–1]: This pin inputs the receive clock to the bit rate gen-
erator.
I
53, 57, 61,
66
DATA SET READY* [0–1]: This pin is always visible in the MSVR register.
The DSR input can be programmed to validate receive data.
I
39, 40, 41,
42
O
I
TRANSMIT DATA [0–1]: Serial data output for each channel.
RECEIVE DATA [0–1]: Serial data input for each channel.
34, 35, 36,
38
RXD[0–3]
BYTESWAP: This pin alters the byte ordering of data during certain 16-bit
transfers and changes the half of the data bus on which byte transfers are
made to comply with Intel or Motorola processor systems. BYTESWAP
does not alter the bus handshake signals. When the BYTESWAP pin is high,
the byte of A/D[0–7] precedes that of A/D[8–15] in a string of transmit or
receive bytes; when BYTESWAP is low, A/D[8–15] precedes A/D[0–7].
BYTESWAP
31
I
When the BYTESWAP pin is high, bytes are transferred on A/D[0–7] when
A[0] is low, and on A/D[8–15] when A[0] is high. When BYTESWAP is low,
bytes are transferred on A/D[8–15] when A[0] is low, and A/D[0–7] when A[0]
is high. A different register map is used, depending on the state of this pin.
Byteswap
Byte Alignment
0
1
Motorola byte alignment
Intel byte alignment
8, 45, 79,
96
V
–
–
POWER
DD
2, 20, 62,
70, 82, 99
GND
GROUND
August 1996
13
DATA BOOK v3.0
PIN INFORMATION
CL-CD2431
Advanced Multi-Protocol Communications Controller
2. REGISTER TABLE
Registers in the CL-CD2431 are either Global or Per-Channel.The column ‘Address mode’in the memory
map on the following pages defines this attribute for each register. Only one set of Global registers exists,
and are accessible by the host at any time.Two sets of Per-Channel registers exist, and the set accessible
at any one time is determined by the currently active channel number.The channel number is selected by
the host in normal (non-interrupt) processing by writing to the Channel Access register.The channel num-
ber in the Channel Access register remains in force until changed by the host. The channel number is
provided automatically by the CL-CD2431 during interrupt service routines and DMA transfers.
In the following list, some register locations appear twice. They have different names and functions for
asynchronous and synchronous protocol operations. See Chapter 6 on page 83 of this data book for
detailed descriptions of all register functions.
2.1 Memory Map
2.1.1 Global Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
GFRCR
CAR
Global Firmware Revision Code Register
Channel Access Register
G
G
82
81
B
B
R/W
R/W
83
84
EC
EE
The following notes are applicable for Section 2.1.1 through Section 2.1.7.
NOTES:
1) Address mode G: Global register — one set is always accessible.
Address mode P: Per-Channel register — two sets, one per channel, accessible by CAR or interrupt context.
2) INT = address for Intel -style processor.
3) MOT = address for Motorola -style processor.
14
August 1996
REGISTER TABLE
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.2 Option Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access
Page
1
CMR
Channel Mode Register
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
18
13
14
15
16
17
1B
04
1C
1D
1E
1F
20
21
2D
1C
1D
1E
1F
D4
1B
04
2D
1C
1D
1E
1F
1B
10
17
16
15
14
18
07
1F
1E
1D
1C
23
22
2E
1F
1E
1D
1C
D6
18
07
2E
1F
1E
1D
1C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
R/W
R/W
85
86
COR1
COR2
COR3
COR4
COR5
COR6
COR7
SCHR1
SCHR2
SCHR3
SCHR4
SCRl
Channel Option Register 1
Channel Option Register 2
Channel Option Register 3
Channel Option Register 4
Channel Option Register 5
Channel Option Register 6
Channel Option Register 7
Special Character Register 1
Special Character Register 2
Special Character Register 3
Special Character Register 4
Special Character Range low
Special Character Range high
LNext Character
R/W
88
R/W
91
R/W
96
R/W
97
R/W
98
R/W
99
R/W Async
R/W Async
R/W Async
R/W Async
R/W Async
R/W Async
R/W Async
R/W Sync
R/W Sync
R/W Sync
R/W Sync
R/W Sync
R/W
100
100
101
101
102
102
103
104
104
104
104
105
106
106
106
107
107
107
107
SCRh
LNXT
RFAR1
RFAR2
RFAR3
RFAR4
CPSR
Receive Frame Address Register 1
Receive Frame Address Register 2
Receive Frame Address Register 3
Receive Frame Address Register 4
CRC Polynomial Select Register
TSPMAP1 Transmit Special Mapped Character 1
TSPMAP2 Transmit Special Mapped Character 2
TSPMAP3 Transmit Special Mapped Character 3
TXACCM0 Transmit Async Control Character Map 0
TXACCM1 Transmit Async Control Character Map 1
TXACCM2 Transmit Async Control Character Map 2
TXACCM3 Transmit Async Control Character Map 3
R/W
R/W
R/W
R/W
R/W
R/W
August 1996
15
DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access
Page
1
RXACCM0 Receive Async Control Character Map 0
RXACCM1 Receive Async Control Character Map 1
RXACCM2 Receive Async Control Character Map 2
RXACCM3 Receive Async Control Character Map 3
P
P
P
P
20
21
22
23
23
22
21
20
B
B
B
B
R/W
R/W
R/W
R/W
108
108
108
108
2.1.3 Bit Rate and Clock Option Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
RBPR
RCOR
TBPR
TCOR
Receive Bit Rate Period Register
Receive Clock Option Register
Transmit Bit Rate Period Register
Transmit Clock Option Register
P
P
P
P
C9
CA
C1
C2
CB
C8
C3
C0
B
B
B
B
R/W
R/W
R/W
R/W
109
110
111
112
2.1.4 Channel Command and Status Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
CCR
STCR
CSR
Channel Command Register
Special Transmit Command Register
Channel Status Register
P
P
P
P
P
10
11
19
13
12
B
B
B
B
B
R/W
R/W
R
113
116
119
123
123
1A
DE
DF
DC
DD
R/W
R/W
MSVR-RTS
MSVR-DTR
Modem Signal Value Registers
16
August 1996
REGISTER TABLE
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.5 Interrupt Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
LIVR
IER
Local Interrupt Vector Register
Interrupt Enable Register
Local Interrupting Channel Register
Stack Register
P
P
P
G
0A
12
25
E0
09
11
26
E2
B
B
B
B
R/W
R/W
R/W
R
124
125
127
128
LICR
STK
2.1.5.1 Receive Interrupt Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
RPILR
RIR
Receive Priority Interrupt Level Register
Receive Interrupt Register
G
G
G
G
G
G
G
G
E3
EF
8A
8A
8B
33
F8
87
E1
ED
88
89
88
30
F8
84
B
B
W
B
B
B
B
B
R/W
R
129
130
131
131
136
137
137
138
RISR
RISRl
RISRh
RFOC
RDR
Receive Interrupt Status Register
Receive Interrupt Status Register low
Receive Interrupt Status Register high
Receive FIFO Output Count
R
R
R
R
Receive Data Register
R
REOIR
Receive End of Interrupt Register
W
2.1.5.2 Transmit Interrupt Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
TPILR
TIR
Transmit Priority Interrupt Level Register
Transmit Interrupt Register
G
G
G
G
G
G
E2
EE
89
83
F8
86
E0
EC
8A
80
F8
85
B
B
B
B
B
B
R/W
R
140
141
142
143
143
144
TISR
TFTC
TDR
Transmit Interrupt Status Register
Transmit FIFO Transfer Count
Transmit Data Register
R
R
W
W
TEOIR
Transmit End of Interrupt Register
August 1996
17
DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.5.3 Modem Interrupt Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
MPILR
MIR
Modem Priority Interrupt Level Register
Modem Interrupt Register
G
G
G
G
E1
ED
88
E3
EF
8B
86
B
B
B
B
R/W
R
145
146
147
148
MISR
MEOIR
Modem (/Timer) Interrupt Status Register
Modem End of Interrupt Register
R
85
W
2.1.6 DMA Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access
Page
1
DMR
DMA Mode Register
Bus Error Retry Count
DMA Buffer Status
G
G
P
F4
8D
1A
F6
8E
19
B
B
B
W
R/W
R
149
149
150
BERCNT
DMABSTS
2.1.6.1 DMA Receive Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
ARBADRL
ARBADRU
BRBADRL
BRBADRU
ARBCNT
BRBCNT
ARBSTS
A Receive Buffer Address Lower
A Receive Buffer Address Upper
B Receive Buffer Address Lower
B Receive Buffer Address Upper
A Receive Buffer Byte Count
B Receive Buffer Byte Count
A Receive Buffer Status
P
P
P
P
P
P
P
P
P
P
40
42
44
46
48
4A
4C
4D
3C
3E
42
40
46
44
4A
48
4F
4E
3E
3C
W
W
W
W
W
W
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
151
151
152
152
153
153
154
154
155
155
BRBSTS
B Receive Buffer Status
B
RCBADRL
RCBADRU
Receive Current Buffer Address Lower
Receive Current Buffer Address Upper
W
W
R
18
August 1996
REGISTER TABLE
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.6.2 DMA Transmit Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
ATBADRL
A Transmit Buffer Address Lower
P
P
P
P
P
P
P
P
P
P
50
52
54
56
58
5A
5C
5D
38
3A
52
50
56
54
5A
58
5F
5E
3A
38
W
W
W
W
W
W
B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
156
156
157
157
158
158
159
159
164
164
ATBADRU A Transmit Buffer Address Upper
BTBADRL B Transmit Buffer Address Lower
BTBADRU B Transmit Buffer Address Upper
ATBCNT
BTBCNT
ATBSTS
BTBSTS
A Transmit Buffer Byte Count
B Transmit Buffer Byte Count
A Transmit Buffer Status
B Transmit Buffer Status
B
TCBADRL Transmit Current Buffer Address Lower
TCBADRU Transmit Current Buffer Address Upper
W
W
R
2.1.7 Timer Registers
Addr.
Mode
2
3
Name
Description
INT
MOT
Size
Access Page
1
TPR
Timer Period Register
G
D8
26
DA
24
B
R/W
165
166
R/W
Async
RTPR
Receive Timeout Period Register
P
P
P
P
P
P
W
R/W
Async
RTPRl
RTPRh
GT1
Receive Timeout Period Register low
Receive Timeout Period Register high
General Timer 1
26
27
28
28
29
25
24
2A
2B
2A
B
B
166
166
167
167
167
R/W
Async
R/W
Sync
W
B
R/W
Sync
GT1l
General Timer 1 low
R/W
Sync
GT1h
General Timer 1 high
B
R/W
Sync
GT2
TTR
General Timer 2
P
P
2A
2A
29
29
B
B
168
168
Transmit Timer Register
R Async
August 1996
19
DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2 Register Definitions
2.2.1 Global Registers
Global Firmware Revision Code Register (GFRCR)
82
81
B
B
R/W
Firmware Revision Code
Channel Access Register (CAR)
EC
EE
R/W
0
0
0
0
0
0
C1
C0
2.2.2 Option Registers
Channel Mode Register (CMR)
18
1B
10
B
R/W
RxMode
TxMode
0
0
0
chmd2
chmd1
chmd0
Channel Option Register 1 (COR1)
HDLC Mode
13
B
R/W
AFLO
ClrDet
AdMde1
AdMde0
Ignore
Flag3
Chl3
Flag2
Chl2
Flag1
Flag0
Asynchronous Mode
Parity
ParM1
ParM0
Chl1
Chl0
Channel Option Register 2 (COR2)
Asynchronous / Async-HDLC / PPP Mode
14
17
B
R/W
IXM
TxlBE
0
0
0
0
CRCNinv
0
RLM
0
RtsAO
RtsAO
RtsAO
CtsAE
DsrAE
HDLC Mode
0
FCSApd
CtsAE
CtsAE
DsrAE
DsrAE
MNP 4/SLIP Mode
0
0
RLM
20
August 1996
REGISTER TABLE
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Channel Option Register 3 (COR3)
Async-HDLC/PPP Mode
15
16
B
R/W
Stop2
FCSApd
FCSApd
Alt1
RxChk
RxChk
FCSPre
FCT
TxGen
TxGen
FCS
npad3
npad3
idle
npad2
npad1
npad0
MNP 4 Mode
Stop2
npad2
npad2
Stop2
npad2
npad1
npad1
Stop1
npad0
npad0
Stop0
HDLC Mode
sndpad
Asynchronous Mode
EDCDE
RngDE
0
SCDE
0
Splstp
npad3
SLIP Mode
Stop2
0
npad1
npad0
Channel Option Register 4 (COR4)
16
17
15
B
R/W
DSRzd
CDzd
CTSzd
0
FIFO Threshold
Channel Option Register 5 (COR5)
14
B
R/W
DSRod
CDod
CTSod
In/Out
Rx Flow Control Threshold
Channel Option Register 6 (COR6)
Asynchronous Mode
1B
18
07
B
R/W
IgnCR
ICRNL
INLCF
IgnBrk
NBrklnt
ParMrk
INPCK
Parlnt
Channel Option Register 7 (COR7)
Asynchronous Mode
04
B
R/W
IStrip
LNE
FCErr
0
0
0
ONLCR
OCRNL
August 1996
21
DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
Special Character Registers
Special Character Register 1 (SCHR1)
1C
1D
1E
1F
1F
1E
1D
1C
B
B
B
B
R/W Async
R/W Async
R/W Async
R/W Async
Special Character Register 2 (SCHR2)
Special Character Register 3 (SCHR3)
Special Character Register 4 (SCHR4)
Special Character Ranges
Special Character Range low (SCRl)
20
21
23
22
B
B
R/W Async
R/W Async
Special Character Range high (SCRh)
LNext Character (LNXT)
2D
2E
B
R/W Async
Receive Frame Address Registers
Receive Frame Address Register 1 (RFAR1)
1C
1D
1E
1F
1F
1E
1D
1C
B
B
B
B
R/W Sync
R/W Sync
R/W Sync
R/W Sync
Receive Frame Address Register 2 (RFAR2)
Receive Frame Address Register 3 (RFAR3)
Receive Frame Address Register 4 (RFAR4)
CRC Polynomial Select Register (CPSR)
D4
D6
B
R/W
0
0
0
0
0
0
0
Poly
Transmit Special Mapped Characters (PPP only)
Transmit Special Mapped Character 1 (TSPMAP1)
Transmit Special Mapped Character 2 (TSPMAP2)
Transmit Special Mapped Character 3 (TSPMAP3)
1B
04
2D
18
07
2E
B
B
B
R/W PPP
R/W PPP
R/W PPP
22
August 1996
REGISTER TABLE
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Transmit Async Control Character Maps (PPP only)
Transmit Async Control Character Map 0 (TXACCM0)
Transmit Async Control Character Map 1 (TXACCM1)
Transmit Async Control Character Map 2 (TXACCM2)
Transmit Async Control Character Map 3 (TXACCM3)
1C
1D
1E
1F
1F
1E
1D
1C
B
B
B
B
R/W PPP
R/W PPP
R/W PPP
R/W PPP
Receive Async Control Character Maps (PPP only)
Receive Async Control Character Map 0 (RXACCM0)
Receive Async Control Character Map 1 (RXACCM1)
Receive Async Control Character Map 2 (RXACCM2)
Receive Async Control Character Map 3 (RXACCM3)
20
21
22
23
23
22
21
20
B
B
B
B
R/W PPP
R/W PPP
R/W PPP
R/W PPP
2.2.3 Bit Rate and Clock Option Registers
Receive Bit Rate Period Register (RBPR)
C9
CB
C8
C3
C0
B
B
R/W
Receive Bit Rate Period (Divisor)
Receive Clock Option Register (RCOR)
CA
R/W
TLVal
0
DpllEn
Dpllmd1
Dpllmd0
ClkSel2
ClkSel1
ClkSel0
Transmit Bit Rate Period Register (TBPR)
C1
C2
B
R/W
Transmit Bit Rate Period (Divisor)
Transmit Clock Option Register (TCOR)
B
R/W
ClkSel2
ClkSel1
ClkSel0
0
Ext-1X
0
LLM
0
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.4 Channel Command and Status Registers
Channel Command Register (CCR)
10
13
12
B
R/W
0
1
ClrCh
ClrT1
InitCh
ClrT2
RstAll
0
EnTx
0
DisTx
EnRx
DisRx
0
0
0
Special Transmit Command Register (STCR)
Async-HDLC/PPP Mode
11
B
R/W
0
Abort
0
0
0
0
sndsp
sndsp
frame
frame
Xon
Xoff
SLIP/MNP 4 Mode
0
Abort
0
0
0
Asynchronous and HDLC Modes
0
AbortTx
AppdCmp
SndSpc
SSPC2
SSPC1
SSPC0
Channel Status Register (CSR)
HDLC Mode
19
1A
B
R
RxEn
RxFlag
RxFrame
RxFlon
RFram
RxMark
0
TxEn
TxEn
TxEn
TxEn
TxFlag
TxFloff
TxFloff
0
TxFrame
TxMark
Asynchronous Mode
RxEn
RxFloff
TxFlon
TFram
TFram
0
Async-HDLC/PPP Mode
RxEn
RxFloff
Rldle
Rldle
TIdle
TIdle
SLIP/MNP 4 Mode
RxEn
0
RFram
Modem Signal Value Registers (MSVR)
R/W
R/W
R/W
Modem Signal Value Register (MSVR-RTS)
Modem Signal Value Register (MSVR-DTR)
DC
DD
DE
DF
B
B
DSR
CD
CTS
DTRop
0
0
DTR
RTS
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.5 Interrupt Registers
Local Interrupt Vector Register (LIVR)
0A
12
09
11
26
E2
B
R/W
X
X
X
X
0
X
RxD
C1
0
X
IT1
IT0
Interrupt Enable Register (IER)
B
R/W
Mdm
0
RET
TIMER
TxMpty
TxD
Local Interrupting Channel Register (LICR)
25
B
R/W
X
X
X
X
C0
X
X
Interrupt Stack Register (STK)
E0
B
R
CLvl [1]
MLvl [1]
TLvl [1]
0
TLvl [0]
MLvl [0]
CLvl [0]
2.2.5.1 Receive Interrupt Registers
Receive Priority Interrupt Level Register (RPILR)
Receive Interrupt Register (RIR)
E3
EF
E1
B
B
R/W
R
ED
Ren
Ract
Reoi
0
Rvct [1]
Rvct [0]
Rcn[1]
Rcn [0]
Receive Interrupt Status Register (RISR)
8A
8A
88
89
W
B
R
R
Receive Interrupt Status Register low (RISRl)
HDLC Mode
0
EOF
RxAbt
CRC
SCdet0
CRC
OE
OE
OE
Reslnd
0
FE
0
ClrDct
Break
Break
Asynchronous Mode
Timeout
SCdet2
SCdet1
PE
FE
Async-HDLC / PPP / MNP 4 Mode
0
EOF
RxAbt
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CL-CD2431
Advanced Multi-Protocol Communications Controller
SLIP Mode
0
EOF
0
0
OE
FE
0
0
Break
Receive Interrupt Status Register high (RISRh)
8B
33
88
30
F8
84
B
B
R
Berr
EOF
EOB
0
BA/BB
0
0
Receive FIFO Output Count (RFOC)
R
0
0
0
RxCt4
RxCt3
RxCt2
RxCt1
RxCt0
Receive Data Register (RDR)
F8
B
R
D7
D6
D5
D4
D3
D2
D1
D0
Receive End of Interrupt Register (REOIR)
Asynchronous and HDLC Modes
87
B
W
TermBuff
DiscExc
SetTm2
SetTm1
NoTrans
NoTrans
Gap2
0
Gap1
Gap0
Async-HDLC / PPP / SLIP / MNP 4 Modes
TermBuff
DiscExc
SetTm2
SetTm1
0
0
26
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.5.2 Transmit Interrupt Registers
Transmit Priority Interrupt Level Register (TPILR)
Transmit Interrupt Register (TIR)
E2
EE
E0
B
B
R/W
R
EC
Ten
Tact
Teoi
0
Tvct [1]
BA/BB
TxCt3
D3
Tvct [0]
Tcn[1]
Tcn [0]
Transmit Interrupt Status Register (TISR)
89
83
8A
80
F8
85
B
R
Berr
EOF
EOE
UE
0
TxEmpty
TxDat
Transmit FIFO Transfer Count (TFTC)
B
R
0
0
0
TxCt4
TxCt2
TxCt1
TxCt0
Transmit Data Register (TDR)
F8
B
W
D7
D6
D5
D4
D2
D1
D0
Transmit End of Interrupt Register (TEOIR)
86
B
W
TermBuff
EOF
SetTm2
SetTm1
NoTrans
0
0
0
2.2.5.3 Modem/Timer Interrupt Registers
Modem Priority Interrupt Level Register (MPILR)
Modem Interrupt Register (MIR)
E1
E3
EF
B
B
R/W
R
ED
Men
Mact
Meo
0
Mvct [1]
Mvct [0]
Mcn[1]
Mcn [0]
Modem (/Timer) Interrupt Status Register (MISR)
88
8B
86
B
R
DSRChg
CDChg
CTSChg
0
0
0
0
0
Timer2
Timer1
Modem End of Interrupt Register (MEOIR)
85
B
W
0
0
SetTm2
SetTm1
0
0
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.6 DMA Registers
DMA Mode Register (DMR)
F4
8D
1A
F6
8E
19
F8
B
W
EnSync
0
0
0
ByteDMA
0
0
0
Bus Error Retry Count (BERCNT)
R/W
Binary Value
DMA Buffer Status (DMABSTS)
B
R
TDAlign
RstApd
CrtBuf
Append
Ntbuf
Tbusy
Nrbuf
Rbusy
2.2.6.1 DMA Receive Registers
A Receive Buffer Address Lower (ARBADRL)
A Receive Buffer Address Upper (ARBADRU)
B Receive Buffer Address Lower (BRBADRL)
B Receive Buffer Address Upper (BRBADRU)
40
42
40
46
44
W
R/W
R/W
R/W
R/W
42
44
46
W
W
W
A Buffer Receive Byte Count (ARBCNT)
B Buffer Receive Byte Count (BRBCNT)
48
4A
48
W
W
R
R
4A
A Receive Buffer Status (ARBSTS)
B Receive Buffer Status (BRBSTS)
4C
4D
4F
4E
B
B
R/W
R/W
Berr
EOF
EOB
0
0
0
0
2431own
Receive Current Buffer Address Lower (RCBADRL)
Receive Current Buffer Address Upper (RCBADRU)
3C
3E
3E
3C
W
W
R
R
28
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.6.2 DMA Transmit Registers
A Transmit Buffer Address Lower (ATBADRL)
A Transmit Buffer Address Upper (ATBADRU)
B Transmit Buffer Address Lower (BTBADRL)
B Transmit Buffer Address Upper (BTBADRU)
50
52
54
56
52
50
56
54
W
W
W
W
R/W
R/W
R/W
R/W
A Buffer Transmit Byte Count (ATBCNT)
B Buffer Transmit Byte Count (BTBCNT)
58
5A
58
W
W
R/W
R/W
5A
A Transmit Buffer Status (ATBSTS)
B Transmit Buffer Status (BTBSTS)
Async-HDLC/PPP Mode
5C
5D
5F
5E
B
B
R/W
R/W
Berr
EOF
EOB
0
0
0
0
map32
INTR
2431own
2431own
2431own
SLIP/MNP 4 Mode
Berr
EOF
EOB
0
0
INTR
INTR
Asynchronous and HDLC Mode
Berr
EOF
EOB
UE
Append
Transmit Current Buffer Address Lower (TCBADRL)
Transmit Current Buffer Address Upper (TCBADRU)
38
3A
38
W
R
R
3A
W
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DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.7 Timer Registers
Timer Period Register (TPR)
D8
26
DA
24
B
R/W
Binary Value
Binary Value
Receive Time-Out Period Register (RTPR)
W
R/W Async
Receive Time-Out Period Register low (RTPRl)
26
27
25
24
B
B
R/W Async
R/W Async
Binary Value, bits 7:0
Receive Time-Out Period Register high (RTPRh)
Binary Value, bits 15:8
General Timer 1 (GT1)
28
28
29
2A
2A
2B
2A
29
W
B
B
B
R/W Sync
R/W Sync
R/W Sync
R/W Sync
General Timer 1 low (GT1l)
General Timer 1 high (GT1h)
General Timer 2 (GT2)
Transmit Timer Register (TTR)
2A
29
B
R Async
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
word transfers are supported in each of the Bus
Slave and DMA Bus Master modes. Figure 3-1 and
Figure 3-2 show the signals involved in these trans-
fers.
3. FUNCTIONAL
DESCRIPTION
3.1 Host Interface
3.1.1 Host Read and Write Cycles
The CL-CD2431 is a synchronous device with an
asynchronous bus interface. A stable input clock is
required on the CLK pin — nominally 33 MHz. The
CLK is divided by two (2) internally, and the resulting
signal is an output on the BUSCLK pin. The baud-
rate generators and timers are also related to CLK.
The “AC Electrical Characteristics” in Section 7
shows that many input signal setup and output sig-
nal transitions are related to the edges of the CLK
and BUSCLK signals. It is possible, however, to use
the CL-CD2431 in a purely asynchronous bus envi-
ronment.
The host read and write cycles begin with the activa-
tion of the CS* (chip select) and DS* (data strobe)
signals.The DATADIR* (data direction) and DATEN*
(data enable) signals are used to control external
data buffers. The falling edge of the DTACK* (data
transfer acknowledge) signal indicates that the
transfer is complete. DTACK* is released when DS*
is deasserted. At that time CS* should also be deas-
serted.The AS* (address strobe) is not used during
slave cycles; it is an output during DMA transfers.
Note that the following open-drain and tristate out-
puts should have pull-up resistors attached: AEN*,
AS*, DATADIR*, DATEN*, and DTACK*.
The CL-CD2431 can act either as a bus master, dur-
ing DMA transfers, or as a bus slave device, during
normal host read and write transfers. Both byte and
CS*
DS*
R/W*
A/D[15:0]
DOUT
A[7:0], SIZ[1:0]
DTACK*
DATEN*
DATDIR*
Figure 3-1. Host Read Cycle
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
CS*
DS*
R/W*
A/D[15:0]
DIN
A[7:0], SIZ[1:0]
DTACK*
DATEN*
DATDIR*
Figure 3-2. Host Write Cycle
3.1.2 Byte and Word Transfers
3.2 Interrupts
Data can be moved to and from the CL-CD2431 in
either byte or word transfers. To accommodate vari-
ous families of host processors, the BYTESWAP
input pin is set to indicate the system byte-ordering
scheme.The SIZ pins (SIZ[1:0]) are used to indicate
whether the transfer is 1 or 2 bytes wide.
The CL-CD2431 uses interrupt requests to alert the
host that certain events have occurred. Interrupt
operations on the CL-CD2431 are tightly coupled
with several registers described later. The concept
of context affects the accessibility of these and other
registers.
In systems where the even addresses represent the
most-significant byte, the BYTESWAP input pin
should be tied low, and byte transfers occur on the
A/D[15:8] pins for even addresses and on the
A/D[7:0] pins for odd addresses. In systems where
the most-significant byte is on the odd address, the
situation is reversed, and BYTESWAP should be
tied high. Byte transfers to even addresses occur on
the A/D[7:0] pins, and to odd addresses on the
A/D[15:8] pins.
3.2.1 Contexts and Channels
The registers in the CL-CD2431 are grouped into
Global, Virtual, and four sets of Per-Channel
registers. The CL-CD2431 is normally in the
background context, where the CAR (Channel
Access register) selects the channel number for the
Per-Channel registers. The interrupt context begins
with the interrupt acknowledge bus cycle, and ends
with a write access to the appropriate End of
Interrupt register. In the interrupt context, only the
Per-Channel registers for the channel number being
serviced are available; the CAR has no effect. Most
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Global registers are available at all times, but some
are shared by the four channels, such as the FIFO
registers. These are called Virtual registers, and
must be accessed only during an interrupt context.
registers. IER contains bits to enable or disable the
various interrupt sources within the CL-CD2431.
The LIVR value is output on the data bus during the
interrupt acknowledge cycle.There are sets of three
Global registers that correspond to the three types
of interrupts: Receive, Transmit, and Modem. The
Priority Interrupt Level registers (RPILR, TPILR, and
MPILR) are programmed to contain the value that is
present on the address bus during the interrupt
acknowledge bus cycle for each type of interrupt.
The Interrupt Status registers (RISR, TISR, or
MISR) are examined during the interrupt service
routine to determine the cause of each type of inter-
rupt.TDR and RDR provide access to the FIFO buff-
ers for each channel. These registers must not be
accessed outside of the proper interrupt context. A
write operation to the End of Interrupt registers —
REOIR, TEOIR, or MEOIR must be the last access
to the CL-CD2431 at the end of this handler routine
to return it to its background context.
Interrupt contexts can be nested so that a higher-pri-
ority interrupt service can preempt a lower priority
interrupt already in progress. The CL-CD2431
pushes the current interrupt context onto the stack,
visible in the STK (Stack register), and enters the
context for the newly acknowledged interrupt. Any
register accesses are in the new interrupt context
until the host performs a write to the appropriate
EOIR for the top-level context.The CL-CD2431 then
pops the top-level context off the stack and returns
to the previous interrupt context.
3.2.2 Interrupt Registers
The IER (Interrupt Enable register) and the LIVR
(Local Interrupt Vector register) are Per-Channel
IREQn*
IACKIN*
1-CLOCK DELAY
CL-CD2431
SAMPLES AD BUS
DS*
R/W*, CS*
A/D[15:0]
VECTOR*
A[7:0]
DTACK*
DEN*
DATDIR*
* INTERRUPT VECTOR IS ALWAYS ON A/D[7:0]
Figure 3-3. Interrupt Acknowledge Cycle
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.2.3 Groups and Types
Group 1 is used only for exceptions. Groups 2 and 3
include both data transfer and exceptions. Table 3-1
shows the possible causes of transmit and receive
interrupt service requests. The cause of an interrupt
request is encoded into the 2 least-significant bits of
the vector presented on the data bus during the
interrupt acknowledge cycle. The most-significant 6
bits of the vector come from the LIVR:
There are two general reasons for the CL-CD2431
to request service from the host processor — data
transfer and exceptional conditions. Furthermore,
interrupts are grouped into three categories, each
with an associated Interrupt Request signal —
IREQ1*, IREQ2*, and IREQ3*.
•
•
•
Group 1 — Modem signal change/timer events
Group 2 — Transmit interrupts
Interrupt Vector LSBs
00
01
10
11
Receive exception
Modem signal change or timer event
Transmit data or exception
Receive Good Data
Group 3 — Receive interrupts
Table 3-1. Transmit and Receive Interrupt Service Requests
Interrupt Cause
ASYNC
HDLC
PPP
SLIP
MNP 4
Comments
Receive Good Data
Break detect
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Not in DMA mode
Framing error
Parity error
Receive timeout, no data
Special character match
Transmitter empty
Tx FIFO threshold
Receive overrun
Clear detect
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Not in DMA mode
CRC error
•
•
Residual bit count
Receive abort
•
•
•
•
•
•
End of frame
Transmit underrun
Bus error
•
•
•
•
•
•
•
•
DMA mode only
DMA mode only
End of buffer
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.2.4 Hardware Signals and IACK Cycles
locations from the CL-CD2431 to produce an
IACKIN* instead of CS*. The PILR registers should
be programmed with the addresses of these three
locations.
The IACK (interrupt acknowledge) bus cycle begins
with the IACKIN* and DS* asserted, and a value
matching the appropriate PILR contents on the
least-significant seven address bus bits, A[6:0]. If
the IACK cycle is valid (that is, the PILR values
match), the corresponding vector from the interrupt-
ing channel LIVR is driven onto the data bus and
DTACK* asserted. DTACK* is released after DS* is
removed.
Alternatively, a single location can be decoded and
the three PILRs given identical values as described
earlier. In either case, the host should read one of
these locations before the first access to the device
in an interrupt service routine. The CL-CD2431
enters its interrupt acknowledge context for the
proper type and channel, and the data returned is
the device interrupt vector from the LIVR.
Figure 3-3 shows the interrupt acknowledge cycle
timing. It is similar to the basic host read cycle,
except that IACKIN* is active and CS* is inactive.
3.2.5 Multi–CL-CD2431 Systems
The three IREQn* pins are open-drain outputs
requiring external pull-up resistors, nominally 4.7
kΩ. The IACKOUT* is used to form a daisy chain in
systems with more than one CL-CD2431.
Multiple CL-CD2431s can be chained for systems
requiring more than four channels. Each group of
interrupt request lines (IREQn*) can be connected
in a parallel wired-OR fashion.The system Interrupt
Acknowledge signal is connected to the IACKIN* pin
of the first device, its IACKOUT* is then connected
to the IACKIN* of the next device, and so on, forming
a chain of CL-CD2431s.
3.2.4.1 Programming the PILR
The three PILRs must be programmed with values
that correspond to the least-significant seven
address bits present on A[6:0] during the interrupt
acknowledge bus cycle. Some CPUs output the pri-
ority level of the interrupts that are being acknowl-
edged on the bus during the IACK cycle. In these
systems the three PILR values are unique. In other
systems that do not use this scheme, the PILR val-
ues can be the same or different depending on the
specific design. When all of the PILRs contain the
same value and multiple IREQn* lines are asserted,
the CL-CD2431 imposes the following priority
scheme to determine which interrupt request are
acknowledged:
3.2.5.1 Keep and Pass Logic
The acceptance of an interrupt acknowledge cycle
by the CL-CD2431 depends on whether the part is
requesting service and whether the least-significant
seven address bits match the contents of the appro-
priate PILR. The following rules apply to the keep-
and-pass logic:
1) If the CL-CD2431 does not have an interrupt
asserted, the interrupt acknowledge is passed
out on IACKOUT*.
2) If the CL-CD2431 is asserting one or more of its
interrupts, but the interrupt priority levels driven
on the address bus by the host do not match the
contents of the appropriate PILR, this interrupt
acknowledge is also passed out on the IACK-
OUT*.
Highest priority: Receive Interrupt register
Transmit Interrupt register
Lowest priority: Modem Interrupt register
3) If the CL-CD2431 is asserting an interrupt and
the interrupt priority level on the address bus
matches the PILR for that interrupt type, the
interrupt acknowledge is accepted by the
CL-CD2431, and the vector from the LIVR is
driven onto the data bus.
3.2.4.2 Systems with Interrupt Controllers
Some systems use an interrupt controller that sup-
plies its own vector during the interrupt acknowl-
edge cycle. To function properly, the CL-CD2431
needs an IACK cycle in response to its interrupt
request . These systems can decode three distinct
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.2.5.2 Fair Share Scheme
3.3.1 Receive FIFO Operation
When multiple CL-CD2431s are chained, the Fair
Share logic in these devices guarantees that the
interrupts from all CL-CD2431s in the system are
presented to the host with equal urgency. There is
no positional hierarchy in the interrupt scheme. For
example, the CL-CD2431 that is farthest from the
host has an equal chance of getting its interrupts
through as the CL-CD2431 that is nearest to the top
of the interrupt chain. The Fair Share scheme is
totally transparent to the user, and no enabling or
disabling is required.
In the Asynchronous mode, a Good Data interrupt is
initiated when the number of characters in the FIFO
is greater than the FIFO threshold. Note that receive
timeout and receive data exception conditions also
cause an interrupt to the host.
In Synchronous mode, an interrupt request for data
transfer is initiated when the number of characters is
greater than the FIFO threshold or an end of frame
is reached.
3.3.2 Transmit FIFO Operation
When an interrupt request line is asserted, the Fair
bit for that type of interrupt on the asserting device is
cleared. The Fair bit remains cleared until the inter-
rupt line returns to a high state. The CL-CD2431
does not assert a new interrupt of that type while the
corresponding Fair bit is cleared. Therefore, when
multiple CL-CD2431s assert interrupts together,
each one is serviced in turn, before they can reas-
sert the same interrupt type.
The TxDat and TxEmpty bits in the IER control the
generation of transmit FIFO interrupts. The
CL-CD2431 initiates an interrupt request for more
data when the number of empty bytes in the FIFO is
greater than the threshold set. During synchronous
operation when the last byte of the frame is trans-
ferred to the FIFO, the CL-CD2431 stops asserting
transmit interrupts until the frame is sent.
3.3.3 Timers
The IREQn* lines are open-drain outputs that can
be tied together in groups of the same type, creating
a Fair Share scheme for each group of interrupts.
Alternatively, all three groups can be tied to a com-
mon request using the CL-CD2431 internal-priority
scheme (see Section 3.2.4.1).
The global TPR (Timer Period register) provides a
timer prescale ‘tick’ as a clock source for the timers.
The TPR counter is clocked by the system clock
(CLK) divided by 2048. To maintain timer accuracy,
the TPR should not be programmed with a value
less than 16 (10 hex) — a‘tick’of about 1 millisecond
when CLK is 33 MHz.
3.3 FIFO and Timer Operations
Each channel in the CL-CD2431 has a 16-byte
receive FIFO and a 16-byte transmit FIFO. The
FIFOs are accessible through the RDR and TDR.
These Virtual registers are shared among the four
channels; therefore, they can not be accessed out-
side an interrupt context.
Each channel has two timers: one 16-bit general
timer 1 (GT1), and one 8-bit general timer 2 (GT2).
Their operation and programming are different in
synchronous and asynchronous protocols.
3.3.4 Timers in Synchronous Protocols
Each channel’s threshold level is common for both
FIFOs. It is set by COR4 (Channel Option Register
4), with a maximum threshold value of 12.The FIFO
threshold is meaningful in both DMA and non-DMA
modes. In DMA mode, the FIFO threshold deter-
mines when transfer bursts should occur. In non-
DMA mode, the threshold level determines when
transfer interrupts are asserted.
In synchronous protocols, the timers have no spe-
cial significance for the CL-CD2431; they are avail-
able to support the protocols. They are started by
host commands or by interrupts generated by the
CL-CD2431. General timers 1 and 2 can be started
in either of two ways:
1) By loading a new value to GT1 or GT2 when the
timer is not running.
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
2) By setting the SetTm1 or SetTm2 bits in the
EOIR when terminating an interrupt service rou-
tine. In this case, the value should be written to
the appropriate Interrupt Status register (RISR,
TISR, or MISR).
A simple Ownership Status bit is used for each
buffer; this ensures that there are no deadlocks
between the host and the CL-CD2431 regarding the
use of a particular buffer.
By using the simple and flexible DMA management
of the CL-CD2431, the user host processor is con-
cerned with transmit/receive data on a block-by-
block basis. The user does not need to be con-
cerned with character-by-character transfers, or
even filling and emptying the FIFOs. DMA controls
are user-selectable per-channel and operate inde-
pendently of one another.
These timers can be disabled by a command
through the CCR (Channel Command register).
3.3.5 Timers in Asynchronous Protocols
The receive timer is restarted from the value pro-
grammed in RTPR every time a character is
received and loaded into the FIFO, or data is read by
the host. For example, receive FIFO threshold is set
to eight, and six characters are stored in the receive
FIFO. If no more characters are received and the
receiver timer times-out, a receive interrupt is
asserted (in DMA mode, DMA transfer occurs).The
host is expected to retrieve all six characters from
the receive FIFO. Assuming the host is still enabling
this feature (that is, IER[5] is still set) and if there is
no character being received and receiver timer
times-out, a receive exception timeout interrupt (a
group 3 interrupt) is asserted. The timer can be dis-
abled if the value in RTPR is set to ‘0’ or the RET bit
(IER[5]) is cleared.
The CL-CD2431 can perform DMA operations in
any of the supported line protocols. A special
Append mode feature can reduce host CPU over-
head for asynchronous datastreams. DMA opera-
tions are channel- and direction-specific. In each
channel, either the transmitter and the receiver, or
both, can be independently programmed for DMA
mode by the CMR (Channel Mode register).
When the CL-CD2431 acquires the bus for a DMA
transfer, only data for one channel and in one direc-
tion is transferred; then, bus ownership is relin-
quished. A maximum of 16 bytes — the depth of the
transmit and receive FIFOs — are transferred dur-
ing any ownership cycle.
3.3.6 Transmit Timer
The TTR (Transmit Timer register) is used only if the
embedded transmit command is enabled in the
COR2. The delay transmit command specifies the
delay period loaded in the TTR; no further transmit
operations are performed until this timer reaches
zero.The current state of the line is held at either ‘0’
for send break or ‘1’ for inter-character fill.
Whenever possible, DMA cycles are 16 bits wide,
and buffers have the proper byte alignment.
Unaligned buffers are sent using only 8-bit-wide
transfers. If the buffer begins on an even address
and contains an odd number of bytes, the
CL-CD2431 uses 16-bit transfers for all the words in
the buffer except the last transfer, which is 8 bits.
If one buffer in a chain ends on an odd address, the
next buffer in the chain should also start on an odd
address to maintain proper alignment for most effi-
cient bus usage. In this case, only the last transfer of
the first buffer and the first transfer of the next buffer
is 8 bits wide; all others are 16 bits.
3.4 DMA Operation
The CL-CD2431 uses a simple, but powerful, dou-
ble-buffering method that is readily compatible with
higher-level buffer control procedures, such as cir-
cular queues, link lists, and buffer pools. Each trans-
mitter and receiver is assigned an ‘A’ and ‘B’ buffer.
When transmitting, the host processor alternately
fills the A and B buffers and commands the
CL-CD2431 to transmit the buffers one at a time.
When receiving, the CL-CD2431 fills the A and B
buffers and informs the host processor when each is
ready.
The CL-CD2431 can be forced to perform only byte-
wide DMA operations by setting the ByteDMA bit
(DMR[3]).
August 1996
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
5) Once the CL-CD2431 senses that BGACK* is
high, the CL-CD2431 waits for the current bus
cycle to terminate (DS* and DTACK* high) and
then asserts BGACK* by driving it low. At that
time, the CL-CD2431 owns the bus. After driving
BGACK* low, the CL-CD2431 drives BR* high.
3.4.1 Bus Acquisition Cycle
1) CL-CD2431 asserts BR* and waits for BGIN*.
2) When BGIN* is detected, the CL-CD2431 can
access the bus after the current bus owner relin-
quishes control of the bus.
In Figure 3-4, the CL-CD2431 was required to wait
to access the bus.
3) If BGACK* is high when BGIN* goes low, then
the bus is free to access. Go to step 5.
4) If BGACK* is low when BGIN* goes low, then the
bus is in use.The CL-CD2431 waits for BGACK*
to go high.
BR*
BGIN*
BGACK*
Another component owns the
bus and gives it up here.
The CL-CD2431 owns the bus at this point.
Figure 3-4. Bus Acquisition Cycle
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.2 DMA Data Transfer
During each DMA read and write cycle, the least-
significant eight memory address bits, MA[0–7]
come from A[0–7].
After the CL-CD2431 acquires the bus, it pulses
ADLD* once.This loads the upper 24 address bits to
the external 24-bit latch.This happens only once per
DMA grant cycle.The AD[15:0] bits are remapped to
memory address (MA) bits MA[31:16] and A[7:0]
are mapped to MA[15:8].If during DMA the upper 24
bits need to change, the CL-CD2431 relinquishes
the bus and then re-acquires the bus.
In Figure 3-5, one DMA access after bus is acquired
is shown.
ADLD*
AEN*
DATDIR*
High for MEM read
Low for MEM write
AS*
R/W*
High for MEM read
Low for MEM write
DS*
DTACK*
Figure 3-5. Data Transfer Timing
August 1996
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.3 Bus Error Handling
CL-CD2431 ‘owns’ the buffer. When 2431own is set
to ‘0’, the host ‘owns’ the buffer. A simple rule pre-
vents confusion in the buffer management — nei-
ther the CL-CD2431 nor the host seizes buffer
ownership. Each always relinquishes ownership to
the other.
When a bus error is detected during a DMA
sequence, the CL-CD2431 terminates the current
bus cycle and relinquishes the bus. Any data trans-
fer in the bus ownership cycle is ignored, and the
original conditions are restored. A subsequent retry
attempt would start again from these original condi-
tions.
The host relinquishes ownership of a receive buffer
to the CL-CD2431 when the receive buffer is ready.
The CL-CD2431 is then free to write received data
into the buffer.The CL-CD2431 returns ownership of
the receive buffer after the receive data is in the
buffer.The host gives ownership of a transmit buffer
to the CL-CD2431 when the transmit buffer is ready
to transmit.The CL-CD2431 then transmits the con-
tents of the buffer. When this is complete, the
CL-CD2431 returns ownership back to the host.
If there is a non-zero value in the BERCNT register,
the register is decremented and the failed transfer is
retried automatically. If the BERCNT is zero, a bus
error interrupt is generated and DMA transfers are
suspended on the failing buffer until the interrupt is
serviced.
3.4.4 A and B Buffers and Chaining
The CL-CD2431 keeps track of which buffer (A or B)
is to be used next in the status bits — Ntbuf for trans-
mit and Nrbuf for receive. The relationship between
the 2431own bit and the ‘next’ bits is shown later.
The receive buffers are handled in the same way
using the Nrbuf (next receive buffer).
The buffer management of the CL-CD2431 uses a
dual-buffer scheme. There is an A and B buffer pair
for each transmitter and each receiver. Each buffer
is controlled by an Ownership Status bit, called
2431own. When 2431own is set to ‘1’, the
Table 3–2. A and B Buffers and Chaining
2431own
Buffer A
2431own
Buffer B
Ntbuf
Transmit Action
0
0
1
1
1
0
0
0
1
1
0
0
0
1
0
0
0
0
1
1
1
Send nothing
Host sets up buffer A
CL-CD2431 accepts buffer A and marks B as next
CL-CD2431 completes A Tx, and passes it to host
Host sets up buffer B
CL-CD2431 accepts B and marks A as next
Host sets up buffer A
CL-CD2431 completes B Tx, passes to host, accepts A
and marks B as next
1
1
1
0
0
0
CL-CD2431 completes A Tx and passes it to host
Chaining is used to break up relatively long frames
into shorter blocks in memory, and is useful where
there are frequent smaller frames and occasional
long frames. Chaining allows more efficient use of
the user RAM.
receive. For transmit, the host determines the EOF
bit; for receive, the CL-CD2431 determines the EOF
bit.
In Transmit DMA when the first buffer is supplied to
the CL-CD2431, it is treated as the start of frame —
the CRC is reset and leading pad/flag/syn charac-
ters are transmitted, followed by the data. If the EOF
The EOF Status bit controls chaining in Synchro-
nous modes. Chaining applies to both transmit and
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
bit is set, the CRC and closing flag/syn is appended,
and the next buffer is again treated as the start of
frame. If the EOF bit is not set, the CL-CD2431
treats the buffer as the first part of a larger frame and
chains into the next buffer (does not reset CRC);this
process continues until a buffer is supplied with the
EOF bit set.
Transmit buffers can be chained to support large
frames.To minimize bus usage, the first buffer of the
chain should begin on an even address in host
memory. The CL-CD2431 begins fetching a frame
from a buffer performing DMA transfer, reading two
bytes at a time.The CL-CD2431 cannot realign data
between external memory and the FIFO. If one
buffer of the chain ends on an odd address, the next
buffer in the chain should begin on an odd address.
Otherwise, only single-byte transfers are made for
the rest of the buffer.
3.4.5 Transmit DMA Transfer
As in receive data transfers, two buffers are avail-
1
able for DMA transmit transfers. The A/BTBADR
and A/BTBCNT (Transmit Buffer Address and
Transmit Buffer Count registers) contain the start
address of and the byte count in the buffers. These
registers are set by the host when initiating a trans-
fer. The CL-CD2431 makes a copy of the registers
to perform the transfer, leaving the originals
unchanged.The transfer of buffers between the host
and the CL-CD2431 is controlled by the A/BTBSTS
(Transmit Buffer Status) registers.
Append Mode Transfer (Buffer A Only)
The Append mode is available for buffer A in Asyn-
chronous mode only. If buffer A is set to Append
mode, the host can enable the CL-CD2431 to trans-
mit data in the buffer before it is completely filled.
The CL-CD2431 starts transmitting new data when
it is appended to the buffer.
This mode is useful for terminal echo routines that
do not wait for a complete block to be formed before
starting transmission. In this mode, transmission is
started when the buffer is made available to the
CL-CD2431 by the host; the ATBADR[3:0] and the
ATBCNT[L, H] are initialized. Subsequent triggering
of DMA transfer occurs by programming the
ATBCNT[L, H] with the accumulated byte count.The
ATBCNT should be written as a 16-bit word in this
case, to avoid confusion between two byte opera-
tions. The ATBADR[3:0] should not be repro-
grammed during the Append mode. If the memory
space has to be moved, the Append mode must first
be disabled. When the final data is added to the
append buffer and ATBCNT has been updated, the
host should set the AppdCmp bit (STCR[5]). When
the CL-CD2431 has completed the final transmis-
sion, it clears the 2431own bit in the ATBSTS regis-
ter, and generates an end-of-buffer interrupt.
Buffers can contain either complete frames or
blocks of data, linked together to form a complete
frame or a block, or used in an Append mode to
transmit data as it arrives from another process.The
first two transfer types are Block mode transfers, the
last is the Append mode, and both are described
later. The management of the buffers reduces the
processor overhead associated with short data
transfers and increases the minimum response time
requirements for frame-based transmissions.
Chain Mode Transfer
In Chain mode, the frame should be complete in
buffers in memory before transmission is started.
The Append Status bit should not be set;the Start of
Frame bit must be set to begin transmission, and the
Last Buffer bit must be set if this buffer is the last in
a chained block or is a complete frame or a block.
When the CRC bit is set, the CL-CD2431 generates
and transmits a cyclic redundancy check word for
the frame using the polynomial selected by the
CPSR (CRC Polynomial Select register).If the Inter-
rupt Required bit is set, a host interrupt is generated
after the buffer is transmitted.
1
A/B is used as a Buffer register abbreviation indicating A
buffer / B buffer followed by the register acronym.
August 1996
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Physical
Memory
CL-CD2431 Transmit
DMA Registers
Starting Address
Transmit
Buffer
A
ATBADR (32)
ATBCNT (16)
Buffer Byte Count
ATBSTS (8)
(Status register)
Current Count
TABADR (32)
(Currently using Buffer A)
Starting Address
Buffer Byte Count
BTBADR (32)
BTBCNT (16)
Transmit
Buffer
B
BTBSTS (8)
(Status register)
NOTE: Number of bits in each register is shown in parentheses ( ).
Buffer A and buffer B do not need to be the same length.
Figure 3-6. Transmitter A and B Buffers
transmission progresses, the current buffer
3.4.6 Synchronous Transmitter Examples
pointer (TCBADR) is updated by the
CL-CD2431. Also, at the start of transmission,
the Ntbuf bit (Next Buffer) is set to ‘1’ to notify the
host that buffer B is next.
In Figure 3-6, buffers A and B are contained in RAM
external to the CL-CD2431. All others (DMABSTS,
ATBADR, TCBADR, ATBCNT, ATBSTS, BTBADR,
BTBCNT, and BTBSTS) are inside the CL-CD2431.
5) The CL-CD2431 completes frame transmission
by adding any necessary CRCs and trailing
frame delimiters.
Example 1
6) When the CL-CD2431 completes the transmis-
sion, it clears the Tbusy bit.Then, it sets the EOB
bit and clears the 2431own bit in the ATBSTS.
This notifies the host that the transmission is
complete, and return ownership of the buffer
back to the host.
Transmit a frame out of channel 1 — no chaining.
1) The host checks the Ntbuf bit in the DMABSTS
register for channel 1 to determine which buffer
is next. In this example, Ntbuf is set to ‘0’ indicat-
ing that buffer A is used next.
2) The host sets up the buffer data, the starting
address — ATBADR, and the buffer byte count
— ATBCNT.
7) The CL-CD2431 optionally interrupts the host,
with EOF and EOB in the TISR both set to indi-
cate that the transmission is complete and there
was no chaining.
3) The host sets up the ATBSTS (A Buffer Status)
register. The EOF bit is set to indicate that there
is no chaining. The 2431own bit is set to give
ownership to the CL-CD2431. By setting
2431own, the host commands the CL-CD2431
to start transmission. Thus, everything must be
ready (starting address, buffer data, and byte
count) prior to setting 2431own.
4) The CL-CD2431 starts frame transmission out of
channel 1. When transmission is started, the
CL-CD2431 sets Tbusy bit in DMABSTS. As
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
8) The CL-CD2431 optionally interrupts the host
with EOF clear and EOB set in the TISR to indi-
cate that the transmission is complete and
chaining occurred.
Example 2
Transmit out of channel 0 and chain three buffers
into one frame.The frame is 240 bytes long, and the
maximum buffer size is 100.
9) The ATBSTS register indicates that the
CL-CD2431 has ownership of buffer A for trans-
mission of the next ‘link’. The EOF is cleared so
that this link is not the last link in the transmitted
chain.
1) The host checks the Ntbuf bit in the DMABSTS
register for channel 0 to determine which buffer
is next. In this example, Ntbuf is set to ‘1’ indicat-
ing that buffer B is used next.
10) The CL-CD2431 continues transmission of the
current frame, but now transmission is from
buffer A. This is the second link, which is 100
bytes long. During this time, the host must set up
a new buffer B for the third and final link. The
BTBCNT for the last link is set to 40 bytes.
2) The host sets up the buffer data, the starting
address (BTBADR), and the buffer byte count
(BTBCNT) for the first ‘link’ of the chain to be
transmitted. For this example, BTBCNT is set to
‘100’.
3) The host sets up the BTBSTS (B Buffer Status)
register. The EOF bit is cleared to indicate that
this buffer is the first link in a chain.The 2431own
bit is set to give ownership to the CL-CD2431. By
setting 2431own, the host commands the
CL-CD2431 to start transmission. Thus, every-
thing must be ready (starting address, buffer,
and data count) prior to setting 2431own.
11) After the CL-CD2431 has completed transmis-
sion of the second link out of buffer A, it sets the
EOB bit and clears the 2431own bit in the
ATBSTS.This notifies the host that the transmis-
sion has completed, and returns ownership of
the buffer back to the host. As with the first link,
the CL-CD2431 does not add CRCs or ending
frame delimiters to this link.
4) At this point, the host has enough time to trans-
mit 100 bytes to set up the next buffer link. If the
host fails to do this in time, there is a transmitter
underrun, and the frame is aborted in HDLC.
12) The CL-CD2431 optionally interrupts the host
with the EOF bit cleared, and the EOB bit set
(TISR[6:5]) to indicate that the transmission is
complete and chaining occurred.
5) The CL-CD2431 starts transmitting buffer B from
channel 0. When this is started, the Ntbuf bit is
cleared to ‘0’ to indicate that buffer A is next.This
helps the host keep track of which buffer is next.
As transmission progresses, the current buffer
pointer, TCBADR, is updated by the
CL-CD2431. During this or prior, the host has
readied buffer A. For buffer A, the EOF bit in the
ATBSTS register is cleared by the host, indicat-
ing that the buffer is not at the end of the chain.
13) By this time, the host has set up a new buffer for
buffer B. The EOF bit in the BTBSTS is set to
indicate that this is the last link in the chain.
14) The CL-CD2431 transmits buffer B in the same
manner as explained earlier. As before, the
CL-CD2431 transmits the number of bytes indi-
cated in the BTBCNT, which is 40 bytes for the
third segment.
15) When the CL-CD2431 completes transmission,
any necessary CRCs and ending frame delimit-
ers are transmitted.
6) At the end of transmission of this buffer, the
CL-CD2431 does not add any CRCs or end of
frame delimiters because there is more data for
the current frame.
16) The CL-CD2431 optionally interrupts the host
with EOF and EOB bits set (TISR[6:5]) to indi-
cate that the transmission has completed, and
that this was the last link in the chain.
7) After the CL-CD2431 has completed transmis-
sion of the first link out of buffer B, the
CL-CD2431 sets the EOB bit and clears the
2431own bit in the BTBSTS. This notifies the
host that the transmission is complete, and
returns ownership of the buffer back to the host.
August 1996
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.7 Receive DMA Transfer
is buffered internally in the FIFO until the host ser-
vices the exception interrupt. The host has the fol-
lowing three options when terminating an exception
interrupt:
In all protocol modes, two host memory buffers can
be made available to each receive channel, by the
A/BRBADR and A/BRBCNT (Receive Buffer
Address and Receive Buffer Count registers) regis-
ters. To make a buffer available, the user must sup-
ply the buffer address in the Receive Buffer Address
registers; the number of free bytes in the buffer must
be written in the Receive Buffer Count registers, and
the buffer status must be updated in the A/BRBSTS
registers. The CL-CD2431 is then free to use the
buffer for receive data, and updates the Buffer Sta-
tus register as appropriate. When the buffer is no
longer in use, the CL-CD2431 writes the number of
bytes stored in the buffer in RBCNT and updates
status in RBSTS. This frees the host to take control
of this buffer and supply a new buffer in its place.The
CL-CD2431 automatically switches to the other
buffer whenever one buffer becomes full, or the end
of a frame has been reached. If the other buffer has
not been allocated, the host still has the time
required to fill the CL-CD2431 16-byte FIFO, to
respond, and to avoid loss of data.
1) The exception character can be discarded.
2) The buffer can be terminated if there is no addi-
tional interrupt to be generated. The transfer
count is not provided in A/BRBCNT, but can be
calculated by RCBADR.
3) A user-defined gap can be left in the buffer.
These selections are communicated to the
CL-CD2431 by the value written by the host to the
REOIR, when the Receive Interrupt service is com-
plete. Leaving an ‘n’ byte gap enables the host to
insert status of its own in the current buffer, while
continuing to receive data in the same buffer. This
eliminates the overhead of allocating a new buffer.
The host must have noted the starting location of the
gap while in the exception interrupt. This is done by
reading the RCBADR.The address in this register is
guaranteed to be stable during the Receive Inter-
rupt, and point to the next free character location in
the current DMA buffer. If the size of the gap sup-
plied by the host is sufficient to fill or complete the
current buffer, the CL-CD2431 automatically
switches to the other buffer and advances the
Receive Current Buffer Address enough to com-
plete the desired gap. The CL-CD2431 readjusts
data alignment in its internal FIFO as needed to
maintain alignment with the external buffer.
Special actions are taken depending on the channel
protocol. In HDLC, PPP, SLIP, and MNP 4 the end-
of-frame/data block boundaries are recognized by
the CL-CD2431. When a data-block boundary is
detected, the current buffer is automatically termi-
nated. If the other buffer is allocated and owned by
the CL-CD2431, it becomes the current buffer. End-
of-frame and block interrupts are also generated to
the host.
Receiver A and B Buffers
In the Figure 3-7, buffers A and B are contained in
RAM external to the CL-CD2431. All others
(DMABSTS, ARBADR, ARBCNT, ARBSTS,
RCBADR, BRBADR, BRBCNT, and BRBSTS) are
inside the CL-CD2431.
In Asynchronous mode, a host interrupt is gener-
ated when there are receive exceptions (framing
error, special character, and so on) but the buffer is
not terminated. The data and exception status are
made available to the host, just as when the Asyn-
chronous mode is purely interrupt-driven. New data
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FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Physical
Memory
CL-CD2431 Transmit
DMA Registers
Starting Address
ARBADR (32)
ARBCNT (16)
Receiver
Buffer
A
Buffer Byte Count
ARBSTS (8)
(Status register)
Current Address
RCBADR (32)
(Currently using Buffer A)
Starting Address
BRBADR (32)
BRBCNT (16)
Receiver
Buffer
B
Buffer Byte Count
BRBSTS (8)
(Status register)
NOTE: Number of bits in each register is shown in parentheses ( ).
Buffer A and buffer B do not need to be the same length.
Figure 3-7. Receiver A and B Buffers
5) At the end of the received frame, the CL-CD2431
Example 1
tests for correct end of frame delimiter and CRC.
When the received frame is complete, the
CL-CD2431 clears the Rbusy bit. In this exam-
ple, there is no receive chaining, so the received
frame byte count is less than or equal to the
buffer size count — ARBCNT. The CL-CD2431
writes the value of the actual received byte count
into the same register — ARBCNT. (Note that
the host has written the maximum buffer size in
ARBCNT when the buffer is given to the
CL-CD2431; however, when the buffer is
returned back to the host, the CL-CD2431 has
written the actual byte count of the received
buffer into ARBCNT.)
Receive a frame from channel 1 — no chaining.
1) The host must first make a receive buffer avail-
able before a frame can be received. Thus, the
host checks the Nrbuf bit (DMABSTS[1]) for
channel 1 to determine which buffer is next. In
this example, Nrbuf is set to ‘0’ indicating that
buffer A is used next.
2) The host sets up the starting address —
ARBADR, and the buffer byte count — ARBCNT.
When the host writes the count — ARBCNT, the
host has defined the size limit for the buffer.
3) The host then gives the buffer to the CL-CD2431
by setting the 2431own bit in the ARBSTS status
register. This notifies the CL-CD2431 that it is
now OK to write received.
6) The CL-CD2431 sets the EOB and EOF bits.
This notifies the host that the end of the buffer
and frame have been reached. The CL-CD2431
also clears the 2431own bit to return the buffer to
the host.
4) The Rbusy bit in the DMABSTS register for
channel 1 is ‘0’ until a frame starts to be
received. When frame data starts coming in, the
CL-CD2431 sets Nrbuf to notify the host that
buffer B is next. As data bytes are written into the
buffer, the current buffer pointer (RCBADR) is
updated by the CL-CD2431.
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
8) The ARBSTS register indicates that the
CL-CD2431 has ownership of buffer A for trans-
mission of the next link.
Example 2
Receive a frame on channel 0, which consists of
three buffers chained together. The frame is 240
bytes long, and the maximum buffer size is 100.
9) As the frame continues to be received, the data
goes into buffer A. This is the second link, which
is 100 bytes long. During this time, the host must
set up a new buffer B for the third and final link.
1) The host checks the Nrbuf bit (DMABSTS[1]) for
channel 0 to determine which buffer is next. In
this example, Nrbuf set to ‘1’ indicates that buffer
B is used next.
10) After the CL-CD2431 has received the second
link into buffer A, the CL-CD2431 sets the EOB
bit and clears the 2431own bit in the ARBSTS.
This returns ownership of the buffer to the host.
2) The host sets up the starting address
(BRBADR). Buffer size is set to ‘100’ in this
example. Thus, the host sets BRBCNT to ‘100’.
As with the first link, the received byte count
(ARBCNT) remains unchanged at 100 since the
received data filled the buffer.
3) The host then sets the 2431own bit to give own-
ership to the CL-CD2431.
4) The host should know the amount of time it takes
to receive 100 bytes, because this is the mini-
mum time the host has to set up the next buffer
link. If the host fails to do this in time, there is a
receiver overrun, and the received frame is lost.
11) The CL-CD2431 optionally interrupts the host
with the EOF bit clear and the EOB bit set in the
RISR to indicate that the received buffer is com-
plete and that there was chaining.
12) By this time the host has set up a new buffer for
5) Suppose that the CL-CD2431 starts receiving
data into buffer B of channel 0. When this is
started, the Nrbuf bit is cleared to ‘0’ by the
CL-CD2431 to help the host keep track of which
buffer is next. (During this time or prior, the host
has made buffer A ready.)
buffer B.
13) The CL-CD2431 receives data into buffer B in
the same manner as previously explained.
14) In this example, the third link does not fill the
buffer. Thus, when the end-of-frame delimiter is
detected by the CL-CD2431, the value of 40 (for
40 received bytes) is written into the received
byte count (BRBCNT).
6) After the CL-CD2431 has received the first link of
the frame into buffer B, it sets the EOB and SOB
bits and clears the EOF bit. This indicates that
the first link in a chain has been received. Also,
the CL-CD2431 clears the 2431own bit, and
returns ownership of the buffer to the host.
15) Next, the CL-CD2431 sets the EOB and EOF
bits to show that the buffer is complete, and that
this is the last link in the chain.
16) The CL-CD2431 optionally interrupts the host
with the EOF and EOB bits set (RISRh[6:5]) to
indicate that the received frame is complete, and
this was the last link in the chain.
For the first received link, the received byte count
(BRBCNT) remains unchanged at 100, since the
received data filled the buffer.
7) The CL-CD2431 optionally interrupts the host
with the EOF bit clear (RISRh[6]) and the EOB
bit set (RISRh[5]) to indicate that the received
buffer is complete, and that there was chaining.
46
August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.8 Transmit DMA Transfer
When theTxMpty interrupt is enabled, interrupts are
generated when there is no transmit data available
to send. For example, the TxMpty interrupt can be
used by the CPU to determine when line turn-
around can occur on half-duplex lines.
The CL-CD2431 contains two DMA descriptors that
can be loaded by the CPU to specify transmit buff-
ers.These descriptors are designated A and B, and
each consists of a 32-bit address (A/BTBADR), a
16-bit count (A/BTBCNT), and an 8-bit status
(A/BTBSTS).
Normally, theTxD interrupt indicates the end of each
transmit buffer. The interrupt is scheduled internally
when the last data is read from the transmit buffer
into the FIFO.
The Status register contains an Ownership Status
bit (2431own). When this bit is set the CL-CD2431
owns the descriptor, and it should not be written to
by the CPU. When this bit is clear, the descriptor is
owned by the CPU.
Because only one interrupt is generated for each
buffer, the TxD bit (IER[0]) can be left permanently
enabled. If interrupts are required selectively for
individual buffers, the INTR bit in the ATBSTS/BTB-
STS registers can selectively enable interrupts.
When DMA is selected and the channel is enabled,
the CL-CD2431 waits for ownership of buffer A.
When ownership of A is given by setting the
2431own bit, the buffer is transmitted and the own-
ership bit is cleared.The CL-CD2431 waits for own-
ership of buffer B; this process continues, toggling
between the two buffer descriptors.
3.4.8.2 Chained Buffers
In Synchronous modes when the frame size
exceeds the maximum buffer size, a frame can be
transmitted from a number of separate buffers. This
is achieved simply by not setting the EOF bit in the
A/BTBSTS registers until the last buffer of the frame.
The CL-CD2431 transmits the buffers as one frame;
it appends the CRC only when all the data is trans-
mitted from the buffer with the EOF flag set.
The DMABSTS register contains a status bit (NtBuf)
that informs the CPU of the next buffer to transmit
and to ensure that the CPU and CL-CD2431 stay in
synchronization. This procedure ensures that a
pipeline of data is available for the CL-CD2431 to
send, maximizing the bandwidth utilization and min-
imizing the possibility of underruns. Figure 3-8 illus-
trates this procedure.
If the above procedure for allocating buffers is used,
the CPU has the transmission time of the last buffer
to allocate the next to avoid possible underrun. The
EOF bit (TISR[6]) is set for the interrupt associated
with the last buffer.
3.4.8.1 Interrupts for Transmit DMA Buffers
Two types of transmit interrupts are available in DMA
mode;they are enabled by the IER and controlled by
the TxD and TxMpty bits.
August 1996
47
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Start
Read
DMABSTS to
Determine Next
Transmit Buffer
(NtBuf)
Next Buffer
2431own Bit
?
0
1
Update
Descriptor and
Set 2431own
No
More Data
to Send
?
Yes
Other Buffer
2431own Bit
?
0
1
Update
Descriptor and
Set 2431own
End
Figure 3-8. DMA Transmit Buffer Selection
48
August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.8.3 Append Mode
able in the TCBADR[0–3] registers, and the bus
error occurred on the last transfer that started at this
address. This means the actual error address can
be up to 16 bytes further in the buffer.
The Append mode reduces the CPU overhead
required to provide asynchronous terminal echoing
functionality; this is also necessary for any similar
application that involves an unpredictable
datastream. The A buffer can be set into Append
mode by the ATBSTS register. This buffer can then
be used for the echoed data, while the B buffer is
used for all other output data. The append buffer
allows data transmission to start from a buffer before
all the data is available for transmission. For
example, terminal echoing requires that each
character is echoed (or translated and echoed)
before the complete line is typed.
Following a bus error condition, the CPU can either
discontinue the current buffer or retry from the start
of the last transfer.To discontinue, the current buffer
and the TermBuff bit should be set when TEOIR is
written to at the end of the interrupt. In Synchronous
mode, the frame is still in progress and needs to be
aborted by the STCR.
To retry the frame, the CPU should set the 2431own
bit in the A/BTBSTS register, and not set the Term-
Buff bit when writing toTEOIR at the end of the inter-
rupt. This causes the last transfer to be retried;
should a bus error occur again, the above procedure
is repeated.The CPU should check to ensure that a
bad location is not continually retried.
To operate in Append mode, the ATBADR and
ATBCNT are set as normal (the ATBCNT can be
zero), and the 2431own and Append bits are set in
the ATBSTS. When any data is available for trans-
mission, it is placed in the RAM buffer by the CPU,
and the total buffer byte count is updated in the
ATBCNT. The CL-CD2431 now scans the ATBCNT
register for any changes; if new data is found, it is
read from the buffer and transmitted.
3.4.9 Receive Buffer Interrupts
When a receive buffer is complete, the CL-CD2431
generates an end-of-frame receive exception inter-
rupt. It provides the CPU with RISR status and infor-
mation on which buffer is complete.
When no more data is found in the append buffer,
the CL-CD2431 scans the B buffer for ownership. If
the B buffer is owned by the CL-CD2431, the data in
that buffer is transmitted uninterrupted; at the end of
the transmission, the A buffer count continues to be
scanned for new data.
When a receive error occurs, the device stops DMA
at the point of error and generates a bus error
receive exception interrupt. RISR indicates the
cause of the exception, and RCBADR provides the
next location in the receive buffer.
For correct operation of this feature, the ATBCNT
register should be updated with a word-write opera-
tion. If only byte access is possible, the value should
not exceed 256 bytes. This mode allows multiple
transfers to be performed through a single buffer; it
saves CPU overhead by either processing multiple
buffers or in handling interrupts with every character.
The CPU has the following five options:
1) Terminate the buffer.
2) Discard the exception.
3) Terminate the buffer and discard the exception.
4) Continue from the current position in the buffer.
5) Leave an ‘n’-byte gap in the buffer and then con-
Line retransmission becomes as simple as‘stepping
back’ in the buffer and resending. To terminate the
Append mode, a command can be given by the
STCR to terminate the A buffer when all current data
has been sent.
tinue.
The required option is written to the REOIR by the
CPU to terminate the interrupt. If the terminate
buffer option is chosen, the 2431own bit in the
A/BRBSTS register should first be cleared by the
CPU, or a new buffer can be supplied by the CPU.
3.4.8.4 Transmit Bus Errors
When a transmit bus error interrupt is generated, the
TISR and A/BTBSTS registers both indicate a bus
error status. The current transfer address is avail-
August 1996
49
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.9.1 Receive Timeout in Asynchronous
DMA Mode
The transfer that failed to the first buffer (due to the
bus error) is still in the receive FIFO and is trans-
ferred to the next buffer following the end of the inter-
rupt.
In Asynchronous DMA mode, the only way that the
CL-CD2431 releases the ownership is by reaching
the end-of-buffer. Receive timeouts or any excep-
tions do not release the ownership if end-of-buffer
condition is not met.The following illustrates recom-
mended procedures to handle a receive timeout in
Asynchronous DMA mode.
To retry the buffer from the failure point, the CPU
should set the 2431own bit in the A/BRBSTS regis-
ter. The CPU should not set the TermBuff bit when
writing to REOIR at the end of the interrupt, this
causes the last transfer to be retried. Should a bus
error occur again, the above procedure is repeated.
The CPU should check to ensure that a bad location
is not continually retried.
Scenario 1: Buffer A is currently selected, receive
timeout occurs, host wants to continue on.
Recommendation: Do nothing in the receive time-
out interrupt service routine.
3.5 Bit Rate Generation and Data
Encoding
Scenario 2: Buffer A is currently selected, receive
timeout occurs, host no longer requires DMA.
Recommendation: Reset ownership bits in
ARBSTS/BRBSTS, and set TermBuff in REOIR in
the receive timeout interrupt service routine.
3.5.1 BRG and DPLL Operation
Data clocks are generated in the CL-CD2431 by
feeding one of a number of clock sources into a pro-
grammable divider.The clock source and divisor are
user-programmable separately for each channel
and direction. Clock options are programmed in the
TCOR and RCOR. The divisors are programmed in
the TBPR and RBPR. The possible clock sources
are as following:
Scenario 3:Buffer A is currently used, a receive tim-
eout occurs, host wants to start DMA in buffer B.
Recommendation: Set TermBuff in REOIR in the
receive timeout interrupt service routine. The
CL-CD2431 switches to buffer B.
NOTE: When a receive timeout occurs in buffer B, the
CL-CD2431 pops back to buffer A, unless the
host clears both Ownership Status bits.
Transmit
1) Clk 0 – CLK input/8
2) Clk 1 – CLK input/32
3) Clk 2 – CLK input/128
4) Clk 3 – CLK input/512
5) Clk 4 – CLK input/2048
6) TXCIN pin
The above scenarios applies if buffer B is selected
first.
3.4.9.2 Receive Bus Errors
When a receive bus error interrupt is generated, the
RISR and A/BRBSTS registers both indicate a bus
error status. The current transfer address is avail-
able in the RCBADR[0–3] registers, the bus error
occurred on the last transfer that started at this
address. This means that the actual error address
can be up to 16 bytes further in the buffer.
7) Receive bit clock
Following a bus-error condition, the CPU can either
discontinue the current buffer or retry from the start
of the last transfer. If the buffer is discontinued, the
number of valid receive bytes can be calculated by
subtracting the starting address A/BRBADR[0–3]
from the current address RCBADR[0–3]. The CPU
should set the TermBuff bit in REOIR to terminate
this buffer and move to the next.
50
August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Receive
In Section 3.2 examples for programming standard
bit rates are provided.The value to be loaded to set
a given bit rate is determined by the following equa-
tion:
1) Clk 0 – CLK input/8
2) Clk 1 – CLK input/32
3) Clk 2 – CLK input/128
4) Clk 3 – CLK input/512
5) Clk 4 – CLK input/2048
6) RXCIN pin
Bit rate divisor =
Equation 3-1
Frequency of chosen clock source
---------------------------------------------------------------– 1
Desired bit rate
In general Equation 3-1 yields a non-integer result.
The nearest integer value, along with the clock
source, is the optimum choice for that bit rate. The
value loaded in the Period register must be that inte-
ger expressed as an 8-bit binary value. The bit-rate
error is the difference between the integer value and
the ideal value, expressed as a percentage.
The CLK input is nominally 33 MHz.
The divisor can be programmed for values from
1–255.To maximize the accuracy of edge detection
in Asynchronous and DPLL (digital phase locked
loop) modes, select the highest frequency clock and
largest divisor combination.
An external clock input can be used and be at a mul-
tiple of the desired bit rate.If so, the appropriate divi-
sor value must be loaded into the Bit Rate Period
register. If the external clock is at the desired bit rate
(1× clock) a value of 01h must be loaded into the
associated Bit Rate Period register.
Example 1
This example illustrates programming the bit rate
generator at 19.2 kbps using the internal clock with
a system clock frequency of 33 MHz.
1
Divisor loaded into R/TBPR = 214 or d6h
Value loaded into R/TCOR = 00h, to select Clk 0
The receive bit rate generator can also be pro-
grammed to act as a DPLL. In that mode, the clock
select and divisor are programmed to be as near as
possible to the nominal receive bit rate. Clock phase
adjustments are made by the DPLL logic to lock to
the incoming datastream.The receive bit clock is an
optional input to the transmitter.This makes it possi-
ble to use the DPLL derived clock to synchronize the
transmit datastream.
Example 2
This example illustrates programming the bit rate
generator at 56,000 bps using the external clock
with a system clock frequency of 33 MHz.
The user provides a 1.25-MHz clock on the RXCIN
or TXCIN pin.
Divisor loaded into R/TBPR = 21 or 15h
Value loaded into RCOR = 06h, to select External
Clock mode
Value loaded into TCOR = C0h, to select External
Clock mode
1
R/T is used as a register abbreviation indicating Receive/
Transmit followed by the register acronym.
August 1996
51
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Period Register
(RBPR or TBPR)
Mux
Adjustments
applied here
(for DPLL only)
System
Clock
Count Register
(RBCR or TBCR)
÷ 8
÷ 32
Clk 0
Clk 1
Clk 2
Clk 3
Clk 4
0
1
2
3
4
5
6
÷ 128
÷ 512
÷ 2048
dec/inc ÷ N
Mux
Zero Detect
RXCIN or TXCIN
RX bit clk
7
(for TX BRG only)
From RCOR/TCOR
Figure 3-9. BRG and DPLL
Receive Clock Option Register (RCOR)
CA
C8
C0
B
R/W
TLVal
res
dpllEn
Dpllmd1
Dpllmd0
Ext-1X
ClkSel2
ClkSel1
ClkSel0
Transmit Clock Option Register (TCOR)
C2
B
R/W
ClkSel2
ClkSel1
ClkSel0
res
res
LLM
res
52
August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-3. Clock Source Select
ClkSel2 ClkSel1 ClkSel0
Select
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
1
Clk 0
Clk 1
Clk 2
Clk 3
Clk 4
Reserved
External clock
Reserved
Receive clock
(RCOR)
(TCOR)
Table 3-4. Bit Rate Constants, CLK = 20 MHz
a
Bit Rate
Divisor
Clock
Error
50
c2
58
40
81
40
81
40
ad
81
56
40
81
40
2c
26
Clk 4
Clk 4
Clk 4
Clk 3
Clk 3
Clk 2
Clk 2
Clk 1
Clk 1
Clk 1
Clk 1
Clk 0
Clk 0
Clk 0
Clk 0
0.16%
0.25%
0.16%
0.16%
0.16%
0.16%
0.16%
0.22%
0.16%
0.22%
0.16%
0.16%
0.16%
0.80%
0.16%
110
150
300
600
1200
2400
3600
4800
7200
9600
19200
38400
56000
64000
a
All divisors are in hexadecimal.
August 1996
53
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-5. Bit Rate Constants, CLK = 25 MHz
a
Bit Rate
Divisor
Clock
Error
50
f3
Clk 4
Clk 4
Clk 4
Clk 3
Clk 3
Clk 2
Clk 2
Clk 1
Clk 1
Clk 1
Clk 1
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
0.06%
0.02%
0.47%
0.15%
0.47%
0.15%
0.47%
0.01%
0.15%
0.45%
0.47%
0.15%
0.47%
0.35%
0.35%
0.76%
110
6e
50
a2
50
a2
50
d8
a2
6c
50
a2
50
37
30
28
150
300
600
1200
2400
3600
4800
7200
9600
19200
38400
56000
64000
76800
a
All divisors are in hexadecimal.
Table 3-6. Bit Rate Constants, CLK = 30 MHz
a
Bit Rate
Divisor
Clock
Error
110
84
61
c2
61
c2
61
40
c2
81
61
c2
Clk 4
Clk 4
Clk 3
Clk 3
Clk 2
Clk 2
Clk 2
Clk 1
Clk 1
Clk 1
Clk 0
0.13%
0.35%
0.16%
0.35%
0.16%
0.35%
0.16%
0.16%
0.16%
0.35%
0.16%
150
300
600
1200
2400
3600
4800
7200
9600
19200
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August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-6. Bit Rate Constants, CLK = 30 MHz (cont.)
a
Bit Rate
Divisor
Clock
Error
38400
56000
64000
76800
115200
61
42
3a
30
20
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
0.35%
0.05%
0.69%
0.35%
1.38%
a
All divisors are in hexadecimal.
Table 3-7. Bit Rate Constants, CLK = 35 MHz
a
Bit Rate
Divisor
Clock
Error
110
9a
71
e3
71
e3
71
4b
e3
97
71
e3
71
4d
43
38
25
21
20
Clk 4
Clk 4
Clk 3
Clk 3
Clk 2
Clk 2
Clk 2
Clk 1
Clk 1
Clk 1
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
Clk 0
0.23%
0.06%
0.06%
0.06%
0.06%
0.06%
0.06%
0.06%
0.06%
0.06%
0.06%
0.06%
0.16%
0.53%
0.06%
0.06%
0.53%
1.38%
150
300
600
1200
2401
3600
4800
7200
9600
19200
38400
56000
64000
76800
115200
12800
134400
a
All divisors are in hexadecimal.
August 1996
55
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Transmit and receive data can be encoded and
decoded in NRZ, NRZI, or Manchester formats. For
NRZI, at the start of transmission, a learning datas-
tream of contiguous zeros achieves bit synchroniza-
tion; for Manchester, an alternating pattern of ones
and zeros is required.
Divisor loaded into RCOR = 38 or 26h
Value loaded into RCOR = 28h, to enable the DPLL,
NRZI framing and select Clk 0
Example 4
This example illustrates programming the DPLL in
the ×1 External Clock mode with Manchester
encoding.
NRZ, NRZI, and Manchester are data encoding
schemes used in various synchronous protocols. In
NRZ, the signal condition represents the data type,
high for logic ‘1’ and low for logic ‘0’. In NRZ and
NRZI encoding, the transitions of the datastream
occur at the beginning of the bit cell. In NRZI encod-
ing, the signal condition switches to the opposite
state to send a binary ‘0’. In Manchester encoding,
the transitions are always in the middle of the bit cell.
A high-to-low transition is made to send a logic ‘1’,
and a low-to-high transition to send a logic ‘0’. The
timing diagrams (Figure 3-10 to Figure 3-12) illus-
trate the encoding method. The data bits are
‘0110010’.
Divisor loaded into RBPR = 01h to enable ×1 exter-
nal clock
Value loaded into RCOR = 36h to enable the DPLL,
select Manchester framing, and external clock
When using an n-times external clock, the highest
possible clock frequency and largest divisor combi-
nation is recommended. The frequency of an exter-
nal clock should be less than the system CLK input
divided by 16, (that is, for 33-MHz operation, the
data clock should be less than 2.0 MHz). Note that
R/TBPR is an 8-bit register; therefore the largest
divisor value is 255.
Example 3
This example illustrates programming the DPLL at
128 kbits/second in NRZI mode, using the internal
clock with a system clock frequency of 33 MHz.
The equation to compute the divisor value is:
Frequency of external clock source
Bit rate divisor =
– 1
Equation 3-2
-----------------------------------------------------------------------------------
Desired bit rate
56
August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
DATA CLOCK
NRZ
NRZI
MANCHESTER
Figure 3-10. Data Encoding
TXCIN
NRZ TxData
NOTE: When using the external receive clock in Receive mode, data is sampled on
the low-to-high going edge of RXCIN.
Figure 3-11. Transmit Data With External Clock In
August 1996
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
TXCOUT
NRZ TxData
Figure 3-12. Transmit Data With External Clock Out
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August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-8. Data Clock Selection Using External Clock
External Clock
Bit Rate
Divisor (hex)
Frequency
CLK = 33 MHz
9.765 kHz
9.765 kHz
9.765 kHz
39.062 kHz
39.062 kHz
156.250 kHz
156.250 kHz
625.00 kHz
625.00 kHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
1.250 MHz
2.00 MHz
50
110
c2
57
40
81
40
81
40
ef
150
300
600
1200
2400
3600
4800
7200
9600
19200
38400
56000
64000
76800
115200
128000
81
ac
81
40
1f
15
12
0f
10
0f
2.00 MHz
implemented by wire OR’ing BR* and BGACK* and
connecting directly to the 680X0. The 680X0 BG*
signal is then connected to the first device in the
chain and daisy-chained to the remaining devices.A
lower-priority bus master can then be connected at
the end of the chain.
3.6 Hardware Configurations
To demultiplex the A/D[15:0] bus into separate
address and data buses, external buffers and
latches are required. To reduce external circuitry,
these external devices can be shared in
multi–CL-CD2431 applications. The common con-
trol lines (ADLD*, AEN*, DATDIR*, DATEN*) to the
external devices are wire-OR’ed together. These
pins are tristate, not open collector, but an external
pull-up resistor (2.2–5.0 kΩ) must be connected to
each line to ensure logic ‘1’ when no CL-CD2431 is
a bus master.
If a higher-priority bus master is present, the BG*
signal must be qualified before being passed into
the highest priority CL-CD2431. If a priority-
encoded scheme is required, the BR* signals must
be prioritized externally and BG* signals routed to
individual devices.
When no higher-priority alternate bus masters are
present, a daisy-chain priority scheme can be
August 1996
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.6.1 Interface to a 32-Bit Data Bus
half of the data bus is in use for a particular bus
cycle.The CL-CD2431 always drives all 16 data bits
during a register-read or DMA-write operation,
regardless of the size of the actual transfer.
To interface to a 32-bit data bus, two 16-bit data buff-
ers must be used to isolate the CL-CD2431
A/D[15:0] pins from either half of the 32-bit bus.The
A[1] address pin determines if the lower or upper
3.6.2 DMA Connections for the CL-CD2431
DATEN* en
16-BIT
DATA
Xcvr
DATDIR* dir
R/W*
DATA[15:0]
DS*
DTACK*
24-BIT
LATCH
A/D [15:0]
ADLD*
[31:16]
STROBE*
[15:8]
[31:8]
32-BIT
ADDRESS
A[7:0]
DRIVER
MA[31:0]
[7:0]
AEN*
AS*
Figure 3-13. DMA Connections for the CL-CD2431
NOTES:
1) The 24-bit latch is required.
2) The 16-bit transceiver is optional depending on application.
3) The 32-bit driver is optional depending on drive requirements.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
3.6.3 Recommended CL-CD2431 as a DTE
and DCE Interface
The following table shows the recommended DCE
(data communications equipment) connections
between the CL-CD2431 and RS-232C standard
interfaces.
The following table shows the recommended DTE
(data terminal equipment) connections between the
CL-CD2431 and RS-232C standard interfaces.
CL-CD2431
RS-232C
CL-CD2431
RS-232C
RXD
TXD
BA
BB
RXD
TXD
BB
BA
RTS*
CB
CTS*
CA
RTS*
CA
DSR*
CD
CTS*
CB
TXCOUT/DTR*
RXCIN
TXCIN
RXCOUT
CD*
DB/CC
–
DSR*
CC
TXCOUT/DTR*
RXCIN
TXCIN
RXCOUT
CD*
–/CD
DD
DA
DD
DB
DA/–
DA
–/CF
Reference: CCITT 1988 Blue Book.
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
4.1.2 HDLC Transmit Mode
4. PROTOCOL PROCESSING
The transmitter can be programmed to idle in either
Flag (01111110) or Mark (continuous 1’s) mode by
the Idle bit (COR3[3]). When idle in Mark mode,
frame transmission can be programmed to be pre-
pended by a programmable number of pad charac-
ters and flags.The pad character can be selected as
either 00 or AA. The pad characters allow the
remote receivers phase locked loop to synchronize
quickly to the data.When NRZI encoding is used for
Manchester encoding, the 00 character guarantees
a transition every bit time, and the AA character
guarantees exactly one transition per bit time.
4.1 HDLC Processing
4.1.1 FCS (Frame Check Sequence)
The FCS is a 16-bit standard computation used in
HDLC, and defined in ISO 3309.This FCS algorithm
is the same that is used with the synchronous HDLC
operation of the CL-CD2431.The basic characteris-
tics of the FCS are the following:
Accumulation: FCS computation starts after the
opening flag and continues to the closing flag.
If the transmitter is idle in Mark mode, frame trans-
mission is started when data is made available to
the transmitter, either by the TDR (Transmit Data
register) or a DMA buffer. First, the programmable
number of pad characters are transmitted, then the
programmable number of flag characters. Data
characters are then transmitted and a CRC value
accumulated using each data character.
Polynomial: The standard polynomial is
5
x16 + x12 + x + 1
.
Pre-load: The FCS 16-bit accumulator is pre-set to
all ‘1’s.
Transmit order:The FCS bits are identified as X15
to X0. The most-significant bit is X15, and is trans-
mitted first.Thus, the first FCS character transmitted
has bits X15–X8 in character positions D1–D8,
respectively. The second FCS character has bits
X7–X0 in character positions D1–D8, respectively.
When end-of-frame status is passed to the
CL-CD2431 by the TEOIR or the A/BTBSTS, and
the remaining data transmitted, the CRC and a clos-
ing flag are appended to the frame. If a new frame is
available immediately, the correct number of open-
ing flags are transmitted and data transmission
starts. If data is not available, the line is returned to
its idle condition.
Transmit polarity: Inverted.
Correct remainder: The receiver calculates the
entire received frame, including the received FCS
field. If the frame is received error-free, then the cor-
rect remainder in the FCS accumulation is ‘F 0 B 8’
(X15 is the leftmost bit).
If data underrun occurs, the CL-CD2431 does not
append a CRC, but aborts the transmission by
sending eight continuous‘1’s, and then reverts to the
idle condition. An underrun interrupt is generated,
and if interrupt transfer is being used, the CPU
should provide an EOF response in TEOIR. If DMA
Transfer mode is being used, the CL-CD2431 dis-
cards DMA buffers until an EOF buffer is found;
transmission then resumes from the next buffer.This
ensures correct operation when a multiple buffer
frame underruns.
The FCS can be individually enabled or disabled for
the transmitter and receiver.
If enabled for the transmitter, the device appends the
FCS on transmitted frames. If disabled, the device
adds no FCS at the end of the frame.
If enabled for the receiver, the device computes the
received FCS and reports the results. If the FCS
append is also enabled, the device includes the 2-
byte FCS in the received data presented to the host.
If disabled, the device does not test the received
FCS.
When programmed in NRZI mode and idle in Mark
mode, after the closing flag and the first eight ‘1’s
are transmitted, the transmit data line is sampled to
determine if it is a logic high or low. If it is low, an
extra ‘0’ is transmitted to force the line to be a logic
high.
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Advanced Multi-Protocol Communications Controller
When idle in Flag mode is selected, the send pad
and opening number of flags have no significance;
transmission is started when data is first made avail-
able in the FIFO. If no data underrun occurs, the
frame is terminated normally with a CRC, and then
continuous flags are generated. If an underrun does
occur, then no CRC is appended, eight ‘1’s are
transmitted, and then continuous flags and an
underrun interrupt are generated.
(end of frame) interrupt is generated. The CRC can
be either validated or ignored. If the CL-CD2431
does not check the CRC, it is passed onto the host.
A validated CRC can be discarded or passed onto
the host for diagnostic purposes.
The next non-flag/abort character restarts the pro-
cess; the current state of the receive process is vis-
ible to the CPU by the CSR register, which indicates
whether data, flag, or mark are currently being
received. To support the data phase of an X.21 con-
nection, a clear detect feature can be enabled by
COR1. When enabled, the receive data and CTS*
pin are monitored for the clear indication (0, off) from
the remote. If detected, the remainder of the current
frame is discarded, and a clear detect indication is
passed to the CPU by the RISR. However, the chan-
nel remains in HDLC mode until modified by the
CPU.
4.1.3 HDLC Receive Mode
When enabled, the receiver enters Flag Hunt mode.
When the first flag is detected, the next non-
flag/abort character is treated as the start of frame.
If no address recognition is enabled, frame recep-
tion then continues; if Address Recognition mode is
enabled, the incoming data is compared with the
receive address registers. The following two modes
of address recognition are available:
4.2 PPP (Point-to-Point Protocol) Mode
4.2.1 Character Format
•
First byte of address field only (four possible
matches available against RFAR1–4).
•
First and second byte address field (two possible
matches available against RFAR1–2, RFAR3–
4).
The PPP mode uses the async-HDLC character for-
mat, which is fixed as one start bit, eight data bits,
and one stop bit. There is no parity bit. The character
format is as shown in Figure 4-1.
For the purposes of address matching, the Address
Extension bit is not interpreted by the device. The
address matching occurs on either the complete
first byte, or the complete first and second byte of
the frame. If no address match is recognized, Flag
Hunt mode is once again entered, thereby discard-
ing the current frame. If a match is found, normal
frame reception continues. When the closing flag of
the frame is detected, the data remaining in the
FIFO is passed to the CPU, either through DMA
transfers or Good Data interrupts, and then an EOF
Using the bit definitions from the standard format
(Figure 4-1), the data bits are identified as D1–D8.
D1 is the LSB. Characters are identified as either
bits (D1–D8) or as hexadecimal values showing the
hex value for bits D5–D8 first, followed by the hex
value for D1–D4. Thus, a flag character is
‘01111110’, and is indicated as a hex 7E. A control-
escape character is ‘10111110’ or 7D.
START
D1
D2
D3
D4
D5
D6
D7
D8
STOP
The line is high prior to the Start
bit. The high value is either due
to a line idle or the Stop bit from
the previous character.
The Start bit of the next character
could begin no earlier than
immediately after the previous
Figure 4-1. Character Format
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Advanced Multi-Protocol Communications Controller
4.2.2 Frame Format
The standard frame format is as follows:
Interframe idle time fill
or next address.
FLAG A-FIELD C-FIELD FRAME DATA CHARACTERS FCS-1
FCS-2
FLAG
The closing flag (7E) of the previous frame can be the same flag
used as the opening of the next frame. This is a shared flag.
Figure 4-2. Point-to-Point Protocol Frame
A and C fields
When the receiver sees the 7D control-escape char-
acter, the 7D is removed and bit 6 of the following
character is inverted. The resultant reconstructed
character is passed on to the host as one received
character.
The device passes the A and C fields to and from the
host. The device does no special processing on
these fields.
4.2.3 FCS (Frame Check Sequence)
4.2.4.1 Mapped Characters from 00–1F
The PPP mode uses the same 16-bit CRC as HDLC
mode (V.41).
When a channel is selected for PPP mode, two
ACCMs are assigned. Each ACCM consists of four
registers (32 bits) to define mapped characters in
the range 00–1F. One ACCM is for the transmitter
(TXACCM), and one for the receiver (RXACCM).
Each bit within the ACCM points to a particular char-
acter within the range.When the bit is set, that char-
acter is a mapped character. When the bit is clear,
that character is not a mapped character.
Everything between the flags is included in the cal-
culation with two exceptions: control-escape (7D)
characters added for transparency, and mapped
characters received without a preceding control-
escape. For characters preceded by a control-
escape, the FCS calculation is made after bit 6 is
inverted.
For example, suppose the TXACCM bit pointing to
the character 12 is set, and that the TXACCM bit
pointing to the character 0B is clear.Then whenever
a 12 is present for transmission, the actual transmis-
sion is 7D–32. Whenever a 0B is present for trans-
mission, the 0B is transmitted without modification.
4.2.4 Transparency
Transparency means that there is a protocol method
to prevent confusion and ambiguity between control
characters and data characters in the frame.
For PPP mode, there is a control-escape mecha-
nism. Specific characters are identified as ‘control
mapped’ characters. The control map is called the
ACCM (async-control-character map). Whenever
there is a mapped character in the data stream, the
transmitter precedes that character with a control-
escape character of 7D. After the control-escape,
the character itself is transmitted with bit 6 inverted.
For example, if the character 13 is a mapped char-
acter, then the transmission of 13 is 7D–33.
Continuing the example, if the receiver ACCM bits
pointing to 12 and 0B are also set and clear, respec-
tively. Then a received 12 (without a preceding 7D)
is discarded, and a received 0B (without a preceding
7D) is passed through to the host unchanged.
4.2.4.2 Mapped Characters from 20 and
Above
Three characters above 20 can be mapped. These
characters are defined in the Channel Specific reg-
isters TSPMAP[1], TSPMAP[2], and TSPMAP[3].
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Advanced Multi-Protocol Communications Controller
4.2.4.3 Characters 7D and 7E asTransmitted
Data
Async-HDLC and PPP protocols have minimum
frame size requirements. However, the CL-CD2431
devices makes no requirement of a minimum frame
size.
Whenever the transmitter sees either 7D or 7E as
data for transmission, the transmitter treats these as
mapped characters. Thus, a 7D as data is transmit-
ted as 7D–5D, and a 7E as data is transmitted as
7D–5E.
The frame opens and ends with a flag (7E). The
device complies with this in transmit, and requires
opening and closing flags on the receiver.The clos-
ing flag from a preceding frame can be the same flag
as the opening flag of the next frame. This is a
shared flag. The device can send and receive both
shared or non-shared flags.
4.2.4.4 Mapped Characters in the FCS Field
Whenever the transmitter sees that the FCS result
to be transmitted contains a mapped character, it
handles that character as any other mapped charac-
ter. See Section 4.2.4.
The frame never ends with a control-escape fol-
lowed by a flag (7D–7E). The device does not send
a 7D–7E at the end of a frame in the normal PPP
mode. The device can be commanded to send an
abort of either a 7D–7E or a character with a bad
stop bit.
For example, if an FCS field is A7–7E, the transmit-
ter would send three characters in the FCS field,
A7–7D–5E.The receiver would convert the received
FCS back to A7–7E before completing the FCS
computation.
If the device receives a frame that ends in a 7D–7E,
that frame is indicated to the host as being in error.
4.2.5 Definition of a Valid Frame
The PPP mode requires transparency as described
in Section 4.2.4. The transparency is always
enabled when the channel is in the PPP mode.
This section discusses valid frames from the view-
point of the CL-CD2431 devices.
All characters are formatted as in the standard
async-HDLC format shown in Section 4.2.1. When
a channel is placed in the PPP mode, that channel
transmits and expects received characters to be as
shown in Section 4.2.1. There is one exception of
an option to transmit a framing error. See
Section 4.2.6.2 and Section 4.2.6.4.
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Advanced Multi-Protocol Communications Controller
4.2.6 Transmitter
4.2.6.2 Transmitter Options
The device transmitter can be control-bit selected
for the following options:
4.2.6.1 Fixed Transmitter Operations
For PPP mode, all transmitted characters are of the
format shown in Section 4.2.1, and the transmitter
always sends an opening flag.
Option
Description
map32
(ATBSTS)
(BTBSTS)
When map32 is set, all the characters in the TXACCM (00–1F) are mapped. All 32 characters are
transmitted with a preceding 7D, and with bit 6 flipped.
When map32 is clear, the normal TXACCM is used.
npad3, 2, 1, 0
(COR3)
The minimum number idle character times between transmitted frames is programmable from
0–15 character times.
If TxGen is set, the device adds the two character FCS at the end of each frame.
If TxGen is clear, the device ends the frame with a closing flag after the last data byte from the
host.
TxGen
(COR3)
frame
(STCR)
When commanded by setting the frame bit in STCR, the device sends one character in the frame
with the Stop bit forced to ‘0’.
4.2.6.3 Transmission of Abort
If the device is not sending a frame when the Com-
mand bit is set, the device clears the STCR and
does not send a framing error character.
When commanded through a bit in the STCR (Spe-
cial Transmit Command register), the device ends
the transmission of the current frame with an abort
sequence of 7D–7E. After executing the abort, the
device clears the STCR. The rules for shared flag
transmission in Section 4.2.6.2 are followed for the
trailing flag (7E) of the abort sequence (7D–7E).
4.2.7 Receiver
4.2.7.1 Fixed Receiver Operations
The receiver accepts a frame or a character when
the received data is brought through the device and
presented to the host.
If the device is not sending a frame when the Com-
mand bit is set, the device clears the STCR and
does not send an abort sequence.
In Async-HDLC mode, the receiver accepts only
characters of the format shown in Section 4.2.1.
4.2.6.4 Transmit Framing Error
The receiver accepts only frames that have an
opening flag; there can be more than one opening
flag.
For test purposes, one character with a framing
error can be transmitted inside a frame. A Com-
mand bit in the STCR notifies the device to transmit
one character with Stop bit forced to ‘0’. If the chan-
nel is transmitting a frame, one framing error charac-
ter is inserted. After transmission, the channel
continues with the frame transmission. After execut-
ing the command, the device clears the STCR.
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Advanced Multi-Protocol Communications Controller
4.2.7.2 Receiver Options
The device receiver can be control-bit selected for the following options:
Option
Description
RxChk
(COR3)
If RxChk is set, the receiver tests the FCS at the end of each frame and reports the result.
If RxChk is clear, the receiver makes no FCS computation.
The RTPR timer is disabled when all bits are zero. RTPR is enabled with a non-zero value.
See Section 4.5.
RTPR
During receipt of a frame, the CL-CD2431 makes
the following substitutions:
4.3 SLIP Processing
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Con-
trol modes are only available on Revision B and
later devices.
•
When an ‘ESC’ character is found in the data
stream, only the ‘ESC_END’ and ‘ESC_ESC’
characters can follow. These two character
sequences are replaced with a single character:
4.3.1 Framing
— The sequence ‘ESC’, ‘ESC_END’ is
replaced with ‘END’.
As defined in the original implementation, SLIP
frames end with an ‘END’ character and have no
beginning character. However, RFC-1055 suggests
that all frames begin and end with ‘END’ characters.
The CL-CD2431 uses the ‘END’ character essen-
tially as opening and closing flags.The defined char-
acters (see table below) are fixed (hardcoded) and
cannot be changed by the user.
— The sequence ‘ESC’, ‘ESC_ESC’ is
replaced with ‘ESC’.
•
Even though the characters ‘ESC_END’ and
‘ESC_ESC’ are the only valid characters follow-
ing ‘ESC’, RFC-1055 suggests that when other
characters are encountered, the ‘ESC’ should be
discarded and the second character should be
kept unmodified. The CL-CD2431 follows this
convention.
Defined Character
Hex Encoding
The SLIP protocol prohibits in-band flow control. As
such, the CL-CD2431 does not respond to XON and
XOFF characters in any special way, they are
treated as normal data.
END
ESC
0xC0
0xDB
0xDC
0xDD
ESC_END
ESC_ESC
4.3.2 Debugging Aids
For debug purposes, the CL-CD2431 can send the
sequence ‘ESC’, ‘END’, by the STCR (Special
Transmit Command register). This is intended as an
abort frame function. The STCR also has a com-
mand for sending a bad (0 value) Stop bit, which
causes a framing error at the receiving end.
The CL-CD2431 uses the following conventions
when transmitting a SLIP frame:
l
When an ‘END’ character is to be sent, it is
replaced by the character sequence ‘ESC’,
‘ESC_END’.
l
When an ‘ESC’ character is to be sent, it is
replaced by the character sequence ‘ESC’,
‘ESC_ESC’.
When the CL-CD2431 receives the sequence
‘ESC’, ‘END’, it is reported as ‘receive abort’ in the
RISR register. A bad Stop bit is reported as a FE
(framing error) in the RISR.
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Advanced Multi-Protocol Communications Controller
4.4 MNP 4 /ARAP Protocol Processing
Table 4-1. Special Character Definition
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Con-
trol modes are only available on Revision B and
later devices.
Special Character
ARAP 1.0 ARAP 2.0
Register 1 and 2
4.4.1 Framing
SCHR1 contains the start
SYN
DLE
SOH
ESC
character
An MNP 4 (V.42) frame consists of a start flag, data
octets, a stop flag, and a 16-bit FCS (frame check
SCHR2 contains the escape
character
sequence). The FCS uses the polynomial
5
(
), preset to all ‘1’s, transmitted, and
x
16 + x12 + x + 1
For both versions of ARAP, frames begin with
SCHR1, SCHR2, STX, and end with SCHR2 and
ETX:
inverted. The character format uses asynchronous
framing with 8 data bits, no parity, and one Stop bit.
In-band flow control (XON/XOFF) is not permitted in
this mode.
•
ARAP 1.0 — SYN, DLE, STX, data, data, data,
... DLE, ETX
The start flag is a three octet sequence consisting of
the start character, escape character, and STX
(0x02). The stop flag is a two octet sequence con-
sisting of the escape character and ETX (0x03).
•
ARAP 2.0 — SOH, ESC, STX, data, data,
data, ... ESC, ETX
Both versions escape the escape character (in
SHCR2) by duplicating it if it appears within the data
stream.
During transmit, if an escape character is encoun-
tered in the data stream, it is duplicated. Conversely,
the receiver discards the second of two sequential
escape characters.
4.4.2 MNP 4/ARAP FCS (Frame Check
Sequence) Calculation
MNP 4 is the data-link layer of ARAP 1.0 (Apple-
Talk Remote Access Protocol). ARAP 2.0 is the
same as MNP 4 except for the two start and escape
characters.
5
16 + x12 + x + 1
Both versions use the (
) polynomial,
x
preset to all ‘1’s, transmitted and inverted with
remainder equal to 0x1D0F. The frame body and
ETX octet of the stop flag are included in the FCS
calculation for both versions. The start flag and all
DLE (ARAP 1.0)/ESC (ARAP 2.0) octets that are
used for transparency are excluded from the FCS
calculation. Figure 4-3 and Figure 4-4 illustrate the
characters used in the FCS calculation. Data used
in FCS calculation is in bold print.
The CL-CD2431 uses two Special Character regis-
ters (SCHR1 and SCHR2) to hold the definition of
the start and escape characters. There is no mode
selection within the CL-CD2431 that allows it to
determine whether it is in an ARAP 1.0 or ARAP 2.0
environment. It builds and detects frames using the
values in the two Special Character registers. The
user must load the two Special Character registers
with the appropriate start and escape characters for
the version in use during channel initialization. The
two special characters for each protocol are shown
in Table 4-1.
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Advanced Multi-Protocol Communications Controller
Start Flag
DLE
T
End Flag
DLE ETX
SYN
SOH
STX
STX
data
data
data
DLE
DLE
data
data
FCS1
FCS1
FCS2
FCS2
Figure 4-3. ARAP 1.0 Frame
Start Flag
ESC
T
End Flag
ESC ETX
data
DLE
DLE
data
data
Figure 4-4. ARAP 2.0 Frame
NOTE: The DLE (ARAP 1.0) and ESC (ARAP 2.0) characters in the middle of the data stream, indicated by the ‘T’
column, are inserted for transparency and thus not included in the FCS calculation.
COR2, has no meaning. The XON and XOFF char-
acters are defined in the Special Character registers
SCHR[1:2].
4.5 Async Processing
Data is transmitted according to the format options
defined in the Channel Option registers. These
options determine the character length, parity, and
Stop bit length.New data sent from the host is trans-
mitted in a continuous stream, unless one of the fol-
lowing occurs:
When in-band flow control is enabled (TxIBE = 1)
and an XOFF character is received, the channel
stops transmission after the current character in the
transmit shift register and the current character in
the transmit holding register are transmitted. When
IXM = 0, transmission restarts after an XON charac-
ter is received.When IXM = 1, transmission restarts
after any character is received.
1) Transmitter disabled — transmission terminated
at the end of the current character until transmit-
ter enabled.
2) XOFF received from line — transmission termi-
nated at end of the current character until XON
received or transmitter enabled.
The FCT (flow control transparency) Mode bit
(COR3[6]) is used to determine if the received flow
control characters are to be passed to the host. If
FCT = 1, the characters are not passed to the host.
If FCT = 0, they are passed to the host as exception
characters. This bit does not affect non-flow control
special characters.
3) Out-of-band flow control — transmission termi-
nated at the end of the current character until
out-of-band flow control removed.
4) In-line command received in data stream from
host — in-line command is executed and trans-
mission resumed.
Additional status information about transmitter in-
band flow control is available in the CSR (Channel
Status register).The TxFloff (Transmit Flow Off) and
TxFlon (Transmit Flow On) bits are used.
5) Send special character command from host —
the current character is completed and the spe-
cial character is transmitted after which normal
transmission is resumed.
TxFloff = 0 is normal. TxFloff = 1 indicates that the
channel has been requested by the remote to stop
transmission.This bit is reset to‘0’when the channel
receives restart, as described earlier. This bit is
reset to ‘0’ when the transmitter is enabled or dis-
abled, or the channel is reset.
4.5.1 Transmitter In-Band Flow Control
For in-band flow control modes to be active, the
Special Character Detect mode must be enabled.
Transmit in-band flow control is enabled when the
TxIBE (Transmit In-Band Enable) bit in COR2 is set
to ‘1’. When TxIBE is set to ‘0’, in-band flow control
is disabled, the IXM (Implied XON Mode) bit, also in
TxFlon = 0 is normal. TxFlon = 1 indicates that the
channel has been requested by the remote to
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Advanced Multi-Protocol Communications Controller
restart transmission. This bit is reset to ‘0’ once the
channel has restarted transmission.This bit is reset
to ‘0’ when the transmitter is enabled or disabled, or
the channel is reset.
ters falls back to equal or below the programmed
value, an XON character (as defined by SCHR1) is
transmitted. The CL-CD2431 keeps track of
XON/XOFF characters that it has sent so that erro-
neous flow control characters are not transmitted.
For example, it does not transmit an XON simply
because the number of characters is below the
threshold; it only does so if it had previously sent
an XOFF due to the threshold being exceeded. For
this reason, the user should not use the Send Spe-
cial Character command in the STCR (Special
Transmit Command register) to send XON/XOFF
characters because the CL-CD2431 does not keep
track of flow control characters that it did not send
automatically.The result could cause confusion on
the other end of the connection due to conflicting
flow control commands.
4.5.1.1 Receiver In-Band Flow Control
The channel can request the remote to stop trans-
mission by sending an XOFF character. Likewise,
the channel can request the remote to restart trans-
mission by sending an XON characters. The
XON/XOFF characters is transmitted by setting the
SndSpc bit (STCR[3]) to ‘1’.
The CSR contains status bits RxFloff (Receive Flow
Off) and RxFlon (Receive Flow On) which are used
for receiver in-band flow control.
RxFloff = 0 is normal.RxFloff = 1 indicates the chan-
nel has requested that the remote stops transmis-
sion. This bit is reset to ‘0’ when the channel
requests that the remote restart its transmission.
This bit is reset to‘0’when the receiver is enabled or
disabled, or the channel is reset.
Automatic in-band flow control is functional only in
standard Async and Async-HDLC/PPP modes;
SLIP and MNP 4 expressly forbid in-band flow con-
trol. See the COR5 description (page 97) for pro-
gramming details.
RxFlon = 0 is normal. RxFlon = 1 indicates that the
channel has requested that the remote restarts
transmission. This bit is reset to ‘0’ when the next
non-flow control character is received. This bit is
reset to ‘0’ when the receiver is enabled or disabled,
or the channel is reset.
4.5.2 Out-of-Band Flow Control
Receive out-of-band flow control is enabled when
the CtsAE bit (COR2[1]) is set to ‘1’. In this mode,
character transmission begins only after the CTS*
pin is active (low). In asynchronous transmission if
CTS* goes inactive (high) after transmission starts,
the channel stops transmission after the current
character in the Transmit Shift register, and the cur-
rent characters in the Transmit Holding register are
transmitted. In Synchronous modes if CTS* goes
inactive, the channel stops transmission after the
current frame. In either case, transmission restarts
after CTS* goes active.
4.5.1.2 Automatic Receive In-Band Flow
Control
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Con-
trol modes are only available on Revision B and
later devices.
The CL-CD2431 can perform automatic in-band
flow control, if desired. Automatic in-band flow con-
trol means that the device sends XON and XOFF
characters based on the level of characters in the
receive FIFO. This function is identical to the auto-
matic out-of-band (hardware) flow control that
uses the DTR bin.
The CL-CD2431 can automatically flow control the
remote device by the DTR* pin. This mode is
selected by setting a non-zero DTR* threshold in
COR5;when the thresholds in COR4 and COR5 are
exceeded, the CL-CD2431 sets the DTR* pin high.
When the data in the FIFO falls below the DTR*
threshold, the DTR* pin is automatically driven low.
As with automatic hardware flow control, when the
number of characters in the FIFO exceeds the
number programmed in COR5 (Channel Option
Register 5), the automatic feature is activated and
the CL-CD2431 transmits an XOFF character (as
defined by SCHR2). When the number of charac-
Each channel of the CL-CD2431 has four pins that
can be used either as a modem control or general-
purpose input/output pins. The modem signal
names assigned to these four pins were selected to
provide an easy reference for system designers. In
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Advanced Multi-Protocol Communications Controller
fact, they are all simply general-purpose inputs and
outputs (if automatic out-of-band flow-control is not
used) that can be individually controlled by the
Modem Signal Value register(s). Since the pins are
general-purpose, system designers can choose to
connect the pins in any way that is appropriate for
the application.
depending on the state of the pin. If automatic
control is used, then DTR goes inactive when the
receive FIFO reached the programmed threshold,
thus causing the modem to drop the connection
(carrier) to the remote; this would not be the correct
function based on the state of the receive FIFO.
4.5.3 Line Break Detection and Generation
However, when the system software design
employs automatic out-of-band flow control with the
pins, the signal naming convention no longer holds
true in some cases, depending on whether the
device is used as DCE or DTE. In this case, it is best
to think of the pins in terms of their actual uses within
the CL-CD2431 and connect them accordingly,
without regard to their names. The RTS* and CTS*
pins are associated with transmitter, and the DTR*
and DSR* pins are associated with the receiver.The
following table shows the recommended signal
hook-up if automatic out-of-band flow control is
desired.
A line break on the receiver occurs when the input at
the RXD (receive data) pin is all zeros (low) for at
least one full character time. This is indicated when
the Break bit (RISRL[0]) is set to ‘1’.
Line break generation out of the transmitter is possi-
ble when the ETC bit (COR2[5]) is set to ‘1’. A line
break is generated when the output at the TXD pin
is all zeroes (low) for at least one full character time.
Line breaks can be transmitted by embedding cer-
tain sequences in the data stream as defined later.
These sequences are valid for transmitting breaks
only if ETC is set to ‘1’. The embedded sequences
to transmit a break are listed in Table 4–3 on
page 72.
Table 4–2. Recommended Signal Connection
CL-CD2431
Pin Name
Out-of-Band
Flow Control
Mode
The ETC mechanism works in ASYNC mode only,
though breaks can be detected in ASYNC, PPP,
SLIP, and MNP 4 modes.
DCE DTE
CTS
DTR
Signal remote to transmit
Not implemented in this
direction
RTS
Request remote permis-
sion to transmit
RTS
CTS
RTS
CTS
Enable transmitter
For example, if the CL-CD2431 is designed to be
DCE and automatic out-of-band flow control is
desired, connect the DTR pin to the remote CTS
input. If the CL-CD2431 is to be used as the DTE
side, then the CL-CD2431 CTS output would be
connected to the remote CTS input.
Note that if automatic out-of-band flow control is
implemented, the activity of the DTR and DSR pins
do not implement the function assigned to those
signal names by the signaling conventions of the
CCITT and other standards organization. These
names would only apply to these pins if they are
under program control and not under automatic
CL-CD2431 control. In fact, the DTR function
enables the modem to go on- and off-line,
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Advanced Multi-Protocol Communications Controller
Table 4–3. BREAK Sequencing
Index
Description
00h–81h
Send BREAK – Send a line break for at least one character time.
Insert delay – To increase the break generation beyond one character time, the insert delay sequence
can be used. The inserted delay is xx, where xx is a binary number. The delay is xx times the ‘tick’ set
by the TPR (Timer Period register). The minimum period of TPR should be 1 millisecond. If the insert
delay sequence is not preceded by a send BREAK sequence, there is an inserted delay of all ‘1’s
(high) on the output for duration xx.
00h–82h-xxh
00h–83h
00h–00h
Stop BREAK – This must follow the send BREAK sequence, or the insert delay sequence.
Send NUL – If the user needs to send a NUL character and ETC = 1, the user can embed 00h–00h to
send one NUL character. If there are less than 8-bits per character, the user can also send a NUL
character by ‘sending’ an 80h.
NOTE: In addition to insert delay, a ‘break’ can also be increased beyond one full character by transmitting more
than one ‘send BREAK’ sequence at a time.
4.5.4 Special Character Transmission
Table 4–4. SSPC[x] Settings
SSPC2 SSPC1 SSCP0
Selected special characters can be sent preemp-
tively by setting the SndSpc bit (STCR[3]). The
CL-CD2431 channel acknowledges the command
by clearing the STCR. Along with the SndSpc bit,
the host needs to set-up the three Special Character
Select bits (STCR[2:0] to select which character is
to be sent.
Function
0
0
0
1
0
1
1
1
0
1
1
0
0
0
1
1
1
0
1
0
0
1
0
1
Send Special Character #1
Send Special Character #2
Send Special Character #3
Send Special Character #4
Reserved
When the host commands a special character trans-
mission, the channel completes transmitting any
characters in the Transmit Shift register and Trans-
mit Holding register, and then transmit the special
character sequence. Any other characters awaiting
transmission in the FIFO or through DMA are trans-
mitted after the special character.
Reserved
Reserved
Reserved
If the transmitter is off due to in-band flow control,
the special characters override and are sent. Spe-
cial characters override out-of-band flow control.
Also if the transmitter is disabled, the special char-
acter send command overrides and the character
are sent.
4.5.5 Special Character Recognition and
Special Character Range
Special character recognition is enabled when the
SCDE bit (COR3[4]) is set to‘1’.The special charac-
ters are programmed in the SCHRs, and are the
same characters used for the transmitter.
If the FCT bit (COR3[5]) is set to‘1’, the channel pro-
cesses the flow control characters and discards
them. Otherwise, if FCT is set to ‘0’, the received
flow control characters is processed and passed
onto the host by an exception interrupt.
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In the event of an error (framing and/or parity) in a
received character sequence, the channel does not
interpret this character as a special character. But, if
an overrun condition occurred after a special char-
acter was detected, the new character is lost and the
overrun status is set. In this condition, the
CL-CD2431 gives both an overrun exception and a
special character recognition status.
required to perform. Separate receive and transmit
bits are provided to perform CR/NL (carriage
return/new line) translations. In transmit, NL can be
converted to CR NL or CR converted to NL. In
receive, CR can be discarded, NL converted to CR,
or CR converted to NL.
In receive processing, separate modes are provided
to handle break conditions and character error con-
ditions. Break conditions can be handled in the nor-
mal way (by a receive status interrupt), the condition
can be discarded, or the break can be translated to
a NULL (00) and passed as normal data to the CPU.
Parity and framing errors can either be handled as
normal (by receive status interrupts), discarded,
translated to a NULL (00) and passed to the CPU as
normal data, or the character can be passed to the
CPU as normal data preceded by the sequence FF
00.
4.5.6 Special Character Range
The Special Character Range low and high (SCRl
and SCRh) registers define an inclusive range for
special character recognition in Asynchronous
mode.This mode can be useful for identifying that a
received character is within a certain range, such as
a control character.To disable this function, if special
character detection is enabled, make both SCRl and
SCRh equal to Special Character #1 (SCHR1).
Special characters and range detection is through
the three Special Character Detect (SCdet0,
SCdet1, SCdet2) bits in the RISR1 register. The
meanings of these bits are listed in the following
table.
The LNext option (COR7[6]) provides a mechanism
to transfer flow control and other special characters
without invoking flow control or special character
interrupts at the receiver. If the LNext option is
enabled when the LNext character is received, the
following character is just passed to the CPU as a
normal character. The LNext character is pro-
grammed by the LNext register. The ‘Strip’ feature
(COR7[7]) strips the eighth bit off each error-free
received character. This has no effect on the trans-
mitted data. The flowchart in Figure 4-5 shows the
exact order of the CL-CD2431 character processing
steps.
Table 4–5. SCdet[x] Settings
SCdet2 SCdet1 SCdet0
Function
No special characters/range
detected
0
0
0
0
0
0
1
1
0
Special character 1 matched
Special character 2 matched
4.6 Non-8-Bit Data Transfers
Special character 3 matched
if character 1 and 3
sequence not enabled
0
1
1
0
1
0
In Asynchronous mode, it is possible to transmit and
receive less than 8 bits per character. There can be
5, 6, 7, or 8 bits per character.
Special character 4 matched
if character 2 and 4
For HDLC mode, there are always 8 bits per charac-
ter transmitted. The CL-CD2431 transmits only
byte-aligned frames. The CL-CD2431 receives
HDLC frames using transfers of 8 bits per character,
except for the last character received before the
FCS. If this last character is not aligned to an 8-bit
boundary, the ResInd (Residual Indication) bit is set,
along with the EOF bit in RISR.
sequence not enabled
The hex value of the receive
character is within the range
SCRl ≤ receive character ≤
SCRh.
1
1
1
4.5.7 UNIX Support Features
The COR6 provides several functions useful for
UNIX TTY drivers, to further reduce the amount of
character-by-character processing that the CPU is
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Advanced Multi-Protocol Communications Controller
Character
Received
N
Error?
Y
Y
ISTRIP
COR7[7]
Y
Zero
Bit 7
FCErr
COR7[5]
N
N
LNE
COR7[6]
Y
Previous
CHAR =
LNXT
Y
N
Y
Y
ISTRIP
COR7[7]
Zero Bit 7
For Special
Char Match
Only
N
SCDE
COR3[4]
N
N
N
Y
CHAR =
Flow Control
Processing
Done
Done
SCHR1/2
Y
ESCDE
COR3[7]
Y
N
B
Exception
Interrupt
CHAR =
SCHR3/4
A
Figure 4-5. CL-CD2431 Receive Character Processing
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Advanced Multi-Protocol Communications Controller
A
N
CHAR =
BREAK
Y
Process Break Options
COR6[4:3]
Action
IgnBrk
NBrkInt
0
1
1
0
0
1
Exception interrupt
Discard character
Replace with 0
Done
Process Parity Options
COR6[2:0]
Action
ParMrk
INPCK
ParInt
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
Exception interrupt
Replace with 0 (null)
Ignore error
Discard character
Replace with FF + 00 + Char
Done
Figure 4-5. CL-CD2431 Receive Character Processing (cont.)
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Advanced Multi-Protocol Communications Controller
B
SCRl<
CHAR<
SCRh
Y
Y
RNGDE
COR3[6]
Exception
Done
Interrupt
N
N
CR/NL
Options
COR6[6]
Y
Y
Y
Discard
Done
Char
CHAR =
CR/NL
N
N
N
Process
Translation
Options
CHAR
to
Done
FIFO
Y
Y
CHAR
= FF
ParMrk
COR6[3][
Add Extra
FF to FIFO
N
N
Char to
FIFO
Done
Figure 4-5. CL-CD2431 Receive Character Processing (cont.)
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Advanced Multi-Protocol Communications Controller
5. PROGRAMMING EXAMPLES
This section provides some examples of the CL-CD2431 programming.Included are examples of global and
++
per-channel initialization, and two interrupt service routines. The code is written in Borland Turbo C . .
POWER UP
‘RESET ALL’
COMMAND
(ANY CCR)
WAIT FOR GFRCR
A HOST COMMAND
TO BE NON-ZERO
DO NOT ISSUE A
‘RESET ALL’ COMMAND
IMMEDIATELY AFTER POWER UP
SETUP GLOBAL
REGISTERS:
TPR AND PILR1–3
DISABLE
RX AND TX
(CAR, CCR)
SETUP CAR CHANNEL-
SPECIFIC REGISTER
FIRST
SINGLE CHANNEL
RECONFIGURATION
SET UP CHANNEL-SPECIFIC
REGISTERS IN ANY ORDER:
CMR, COR1–5,TBPR,TCOR,
RBPR, RCOR, CPSR, LIVR,
GT1–2, RFAR1–4 (SYNC),
SCHR1–4, SCR, RTPR (ASYNC)
LAST STEP IN CHANNEL
CONFIGURATION:
CCR, IER
A CHANNEL IS
CONFIGURED
Figure 5-1. Initialization Sequence for the CL-CD2431
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Advanced Multi-Protocol Communications Controller
5.1 Global Initialization
The following code segment is an example of global initialization.The host waits for a hardware reset, deter-
mined by a non-zero value in the GFRCR. A ‘RESET ALL’ command is sent to the CL-CD2431 by the CCR.
The internal processor puts a non-zero value into the GFRCR when initialization is complete.
It is a good practice to manually clear the GFRCR before issuing the ‘Reset All’command as it takes a small
amount of time for the internal processor to detect the command and clear the register. If the host is suffi-
ciently fast, it might read the GFRCR before the command execution begins and incorrectly assume the com-
mand is complete.
The PILRs should be loaded with the value of the seven address lines (A[6:0]) during interrupt acknowledge
cycles.The TPR loads the dividing counter that inputs each of the other timers in the CL-CD2431.The DMA
Mode register and the Bus Error Count register are used in DMA modes only.After the global portion is done,
the Per-Channel registers need to be initialized. Transfers and interrupts should be enabled after all other
initialization is complete.
// Global Initialization
while( !inportb( GFRCR ) )
; // wait
// wait for hardware reset
// manually clear GFRCR
// Reset command
outportb( GFRCR, 0x00 );
outportb( CCR, RESET_ALL );
while( !inportb( GFRCR ) )
; // wait
// wait for reset command
outportb( PILR1, 0x02 );
outportb( PILR2, 0x04 );
outportb( PILR3, 0x06 );
outportb( TPR, 0x40 );
outportb( BERCNT, 0 );
outportb( DMR, 0 );
// Priority Interrupt
// Level Registers
// Set timer prescale
// Bus error count
// DMA mode — 16-bit
// per-channel initialization
for( i=0; i<2; i++ ) {
outportb( CAR, i );
// set channel number
// initialize channel
init_chan( cor, bpr );
outportb( CCR, INIT_CH | EN_RX | EN_TX );
while( inportb(CCR) )
; // wait
outportb( IER, TX_DATA|RX_DATA );
// enable interrupts
}
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5.2 Async Interrupt Setup Example
This section provides a code example for an asynchronous channel running at 19,200 bps, with 8 bits/char-
acter, 1 Stop bit, and no parity. The sample program enables In-Band Flow Control and Implied Xon mode.
This code assumes that the proper channel is been set by the CAR.
outportb( LIVR, 0x40 );
outportb( RCOR, 0 );
outportb( RBPR, 0x81 );
outportb( TCOR, 0 );
outportb( TBPR, 0x81 );
// Receive clock option
// Baud Rate divisor
// Transmit clock option
// Baud Rate divisor
outportb( CMR, ASYNC );
// Async Mode, interrupt
outportb( COR1, PARIGN | CHAR8 );
outportb( COR2, IXM | TXIBE );
outportb( COR3, STOP1 | FCT );
outportb( COR4, thresh );
// 8 bit chars, no parity
// in-band flow,implied XON
// 1 stop, flow control
// FIFO threshold
outportb( COR5, 0 );
5.3 HDLC DMA Channel Setup Example
This per-channel initialization code example is for the HDLC protocol at 64 kbps (with CLK = 33MHz) with
NRZI encoding. The setup specifies two extra opening flags before frames, no address matching, and that
DMA transfers should be used.
outportb( LIVR, 0x30 );
outportb( RCOR, DPLL_NRZI );
outportb( RBPR, x’3F );
outportb( TCOR, 0 );
// Set interrupt vector
// Receive clock option
// Baud rate divisor
// Transmit clock option
// Baud rate divisor
outportb( TBPR, x’3F );
outportb( CMR, RX_DMA | TX_DMA | HDLC ); // Mode register
outportb( CPSR, CPSR_CRC_V41 );
// CRC polynomial select
outportb( COR1, NO_ADDR | FLAG_2 );
outportb( COR2, CRC_V41 );
outportb( COR3, 0 );
// No address matching,
// 2 opening flags
outportb( COR4, thresh );
outportb( COR5, 0);
// FIFO threshold
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Advanced Multi-Protocol Communications Controller
5.4 Receive DMA Interrupt Service Routine
The following code example shows an interrupt service routine for the CL-CD2431 in DMA mode.The buffer
class array ib[ ] is used for notational convenience, and its exact implementation is user-defined.The upper
( ) and lower ( ) functions should return the upper and lower 16 bits of the DMA address for the current buffer
segment.The nxt_buf() accesses the next segment.
If the system uses separate interrupt handlers for receive, transmit, and modem interrupts, the channel num-
ber can be obtained from the least-significant bit of the Interrupt register (RIR, TIR, or MIR). Otherwise, first
use the LIVR to determine the type of interrupt. Receive Good Data interrupts should not occur during DMA
transfers.The normal exception is when an end-of-frame is received.
The DMABSTS register shows which buffer the CL-CD2431 expects to use next. Fill the descriptor registers
for that buffer, including the 2431own bit and return. The last access to the CL-CD2431 during the service
routine is the REOIR.
int risrl = inportb( RISRL );
int ch = inportb( RIR ) & 0x01;
// low status
// channel number
switch( inport(LIVR) & 0x03 ) {
case LIVR_GOODDATA:
break;
// shouldn't happen in DMA
// EOF is 'normal' exception
case LIVR_EXCEPTION:
if( risrl & RISR_EOF ) {
if( inportb(DMABSTS) & DMABS_NRBUF ) {// buffer B next
outport( BRBADRU, ib[ch].upper() );
outport( BRBADRL, ib[ch].lower() );
outport( BRBCNT, BUF_MAX );
outport( BRBSTS, OWN_2431 );
ib[ch].nxt_buf();
} else {
// get next buffer
// buffer A next
outport( ARBADRU, ib[ch].upper() );
outport( ARBADRL, ib[ch].lower() );
outport( ARBCNT, BUF_MAX );
outport( ARBSTS, OWN_2431 );
ib[ch].nxt_buf();
// get next buffer
}
}
}
outportb( REOIR, ZERO );
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Advanced Multi-Protocol Communications Controller
5.5 Transmit Interrupt Service Routine
The following code example is a transmit interrupt service handler example.When using a synchronous pro-
tocol, transmitters must declare an end of frame if an underrun occurs. If the end of buffer is encountered
before data is transferred by this interrupt service, then the Notrans bit (TEOIR[3]) should be set along with
EOF (TEOIR[6]).TEOIR is always the last access of an interrupt service routine.
int teoir = ZERO;
// default
int tisr = inportb( TISR );
int ch = inportb( TIR ) & 0x01;
// status
// channel number
switch( tisr ) {
case TISR_UE:
teoir = TEOIR_EOF;
break;
// underflow
// FIFO count
case TISR_TXDATA:
tftc = inportb( TFTC );
for( i=0; i<tftc; i++) {
if( ob[ch].is_eob() ) {
ob[ch].nxt_buf();
teoir = TEOIR_EOF;
if( i==0 )
// end of buffer ?
// get next buffer
teoir |= NOTRANS;
break;
}
else outportb( TDR, ob[ch].nxt_char() );//send next character
}
}
outportb( TEOIR, teoir );
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Advanced Multi-Protocol Communications Controller
5.6 Support Files
5.6.1 The Cirrus Logic FTP Server
For additional programming examples, sample register definitions and symbol header files (for C++), con-
nect to the Cirrus Logic ftp server:
ftp.cirrus.com
Login as anonymous and download the files from the support area:
pub/support/sio/cd2431/EvalBdv2
5.6.2 Web Access
To use a web browser to access the above files, go to the Cirrus Logic web site at:
http://www.cirrus.com/prodtech/internetworking/evalkits.html
Or, to directly access the ftp site, type the location:
ftp://ftp.cirrus.com/pub/support/sio/cd2431/EvalBdv2/
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Advanced Multi-Protocol Communications Controller
6. DETAILED REGISTER DESCRIPTIONS
6.1 Global Registers
6.1.1 Global Firmware Revision Code Register (GFRCR)
Register Name: GFRCR
Intel Hex Address: x’82
Register Description: Global Firmware Revision Code
Default Value: x’0D
Motorola Hex Address: x’81
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Firmware revision code
This register serves two functions in providing the host with information about the CL-CD2431. When a
hardware RESET* signal or a software RESET ALL command is issued through either of the two Channel
Command registers, it initializes the CL-CD2431 and zeros this register at the start of the initialization. At
the end of the initialization, the CL-CD2431 writes its firmware revision code to the GFRCR. All valid
CL-CD2431 revision codes are non-zero and the revision code is incremented by one with each new re-
lease (for example, GFRCR for Revision D = 34 hex).
Host software must confirm that the GFRCR contents are non-zero before proceeding to configure the
CL-CD2431 for normal operation.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.1.2 Channel Access Register (CAR)
Register Name: CAR
Intel Hex Address: x’EC
Register Description: Channel Access
Default Value: x’03
Motorola Hex Address: x’EE
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
C1
Bit 0
C0
Reserved
This register contains the channel number for the channel-oriented host read or write operations, when
the host is not in an interrupt service routine. The CL-CD2431 supplies the interrupting channel number
during all interrupt service operations. The Channel Access register contents are not used during an in-
terrupt service. Note that this means that an interrupt service routine is restricted to accessing only the
register set of the Interrupting Channel and Global registers.
Bits 7:2
Bits 1:0
Reserved – must be ‘0’.
Channel number
C1
0
0
C0
0
1
Channel number
Channel 0
Channel 1
1
1
0
1
Channel 2
Channel 3
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2 Option Registers
6.2.1 Channel Mode Register (CMR)
Register Name: CMR
Intel Hex Address: x’18
Register Description: Channel Mode
Default Value: x’02
Motorola Hex Address: x’1B
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
RxMode
TxMode
chmd2
chmd1
chmd0
Bit 7
Receive Transfer mode
0 – Interrupt
1 – DMA
Bit 6
Transmit Transfer mode
0 – Interrupt
1 – DMA
Bits 5:3
Bits 2:0
Reserved – must be ‘0’.
Protocol mode select
If these options are changed, an initialize command must be given to the CL-CD2431
through the Channel Command register.
chmd2
chmd1
chmd0
Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HDLC
Reserved
Async
Reserved
Async–HDLC/PPP
SLIP
MNP 4/ARAP
Reserved
August 1996
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DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.2 Channel Option Register 1 (COR1)
6.2.2.1 COR1 — HDLC Mode
Register Name: COR1
Intel Hex Address: x’13
Register Description: Channel Option 1
Default Value: x’00
Motorola Hex Address: x’10
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AFLO
ClrDet
AdMd1
AdMd0
Flag3
Flag2
Flag1
Flag0
If any options specified in this register are changed, an initialize command must be given to CL-CD2431
through the Channel Command register.
Bit 7
Address field length option
0 = Address field is one octet in length
1 = Address field is two octets in length
Bit 6
Clear detect for X.21 data transfer phase
0 = Clear detect disabled
1 = Clear detect enabled
A ‘clear’ is defined as two consecutive all-zero receive characters with the CTS* pin high.
Bits 5:4
Bits 3:0
Addressing modes
00 = no address recognition
01 = 4 × 1 byte
10 = 2 × 2 byte
If this bit is set, RFAR1, RFAR2, RFAR3, and RFAR4 should contain the address to be
matched. If AFLO (COR1[7]) is set to ‘1’, an address match is made against the RFAR1 and
RFAR2 pair or the RFAR3 and RFAR4 pair.
Inter-frame flag option
Defines the minimum number of flags transmitted before a frame is started.
Flag 3
Flag 2
Flag 1
Flag 0
0
0
0
0
minimum of one opening flag, with shared
closing/opening flags permitted
0
0
0
through
1
1
minimum number of opening flags sent
1
1
1
The minimum number of opening flags always precede a frame when Idle-in Mark mode is
set, or is always separated by two consecutively transmitted frames. No restriction is placed
on the number of flags between received frames.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.2.2 COR1 — Asynchronous Mode
Register Name: COR1
Intel Hex Address: x’13
Register Description: Channel Option 1
Default Value: x’00
Motorola Hex Address: x’10
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Chle
Bit 2
Chl2
Bit 1
Chl1
Bit 0
Chl0
Parity
ParM1
ParM0
Ignore
Bit 7
Parity
1 = odd parity
0 = even parity
Bits 6:5
Parity mode 1 and 0
Defines Parity mode for both transmitter and receiver:
ParM1
ParM0
Parity
0
0
0
1
none
force
(odd = force 1, even = force 0)
1
1
0
1
normal
reserved
Bit 4
Ignore parity
0 = evaluate parity on received characters.
1 = do not evaluate parity on received characters.
Bits 3:0
Character Length
Chl3
Chl2
Chl1 Chl0
Character Length
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
5 bits
6 bits
7 bits
8 bits
NOTE: Not used in PPP, MNP 4, and SLIP modes.
August 1996
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DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.3 Channel Option Register 2 (COR2)
6.2.3.1 COR2 — HDLC Mode
Register Name: COR2
Intel Hex Address: x’14
Register Description: Channel Option 2
Default Value: x’00
Motorola Hex Address: x’17
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
0
FCSApd
CRCNinv
RtsAO
CtsAE
DsrAE
Bit 7
Bit 6
Reserved – must be ‘0’.
FCS append
0 = receive CRC is not passed to the host at end of frame.
1 = receive CRC passes to the host at end of frame.
Bit 5
Bit 4
Reserved – must be ‘0’.
CRCNinv
0 = CRC is transmitted inverted (that is, CRC V.41).
1 = CRC is not transmitted inverted (that is, CRC-16).
Bit 3
Bit 2
Reserved – must be ‘0’.
RTS Automatic Output Enable
When set, if the channel is enabled, the CL-CD2431 automatically asserts the RTS* output
when it has characters to send. When Idle-in Mark mode is selected, RTS* is asserted prior
to opening flags and remains asserted until after a closing flag is transmitted.
Bit 1
Bit 0
CTS Automatic Enable
This enables the CTS* input to be used as the automatic transmitter enable/disable. If
enabled, CTS* is checked before frame transmission starts.
DSR Automatic Enable
This enables the DSR* input as the automatic receiver enable/disable. If enabled, DSR* is
checked at the beginning of each received frame.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.3.2 Asynchronous / Async-HDLC / PPP Mode
Register Name: COR2
Intel Hex Address: x’14
Register Description: Channel Option 2
Default Value: x’00
Motorola Hex Address: x’17
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
ETC
Bit 4
0
Bit 3
RLM
Bit 2
Bit 1
Bit 0
IXM
TxIBE
RtsAO
CtsAE
DsrAE
Bit 7
Implied XON mode
IXM has meaning only if TxIBE is set.
If transmission stops due to a received XOFF character, and:
If IXM = 0, transmission resumes only after the receipt of an XON character or a transmit
enable command by the CCR (Channel Command register).
If IXM = 1, transmission resumes after the receipt of any character or a transmit enable com-
mand by the CCR.
Bit 6
Transmit In-Band Flow Control Enable
If TxIBE is clear, there is no in-band flow control.
If TxIBE is set, transmission stops after the receipt of an XOFF character (cntl-S or hex 13).
Immediately after receiving an XOFF, any character in the Transmit Shift register or Holding
register is transmitted, and then character transmission is halted. Thus, no more than two
characters are sent after receiving an XOFF.
Depending on the state of the IXM bit, either the receipt of an XON (cntl-Q or hex 11) char-
acter or any other character (IXM = 1) restarts the transmission. A transmit enable command
by the CCR also restarts the transmission.
Bits 5:4
Bit 3
Reserved – must be ‘0’.
RLM – Remote loop back
RLM = 1, enables Remote Loopback mode
RLM = 0, disables Remote Loopback mode
Bit 2
Bit 1
RTS* Automatic Output Enable
If RtsAO = 1, the RTS* output pin remains enabled during DMA or character bursts from the
transmit FIFO. If the CTS* input pin goes high, RTS* goes high and transmission stops after
the current burst is complete.
CTS Automatic Enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to the transmission of each character. If CTS*
is asserted low, that character is transmitted completely. If CTS* is high, that character trans-
mission is held until CTS* goes low.
Bit 0
DSR Automatic Enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the DSR* input pin is evaluated at the end of each received character. If DSR* is
asserted low, the receiver input is enabled for the next character. If DSR* is high, the receiver
is disabled until DSR* goes low.
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.3.3 COR2 — MNP 4/SLIP Mode
Register Name: COR2
Intel Hex Address: x’14
Register Description: Channel Option 2
Default Value: x’00
Motorola Hex Address: x’17
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
RLM
Bit 2
Bit 1
Bit 0
0
0
RtsAO
CtsAE
DsrAE
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and later de-
vices.
Bits 7:6
Bits 5:4
Bit 3
Reserved – must be ‘0’. No in-band flow control in MNP 4 mode.
Reserved – must be ‘0’.
Remote Loop Back mode
RLM = ‘1’ enables Remote Loopback mode
RLM = ‘0’ disables Remote Loopback mode
Bit 2
Bit 1
RTS* Automatic Output Enable
If RtsAO = 1, then the RTS* output pin remains enabled during DMA or character bursts from
the transmit FIFO. If the CTS* input pin goes high, then RTS* goes high and transmission
stops after the current burst is completed.
CTS* Automatic Enable
When clear, the transmitter output enable is independent of the CTS* input pin.
When set, the CTS* input pin is evaluated prior to the transmission of each character. If CTS*
is asserted low, that character transmits completely. If CTS* is high, that character transmis-
sion is held until CTS* goes low.
Bit 0
DSR* Automatic Enable
When clear, the receiver input enable is independent of the DSR* input pin.
When set, the DSR* input pin is evaluated at the end of each received character. If DSR* is
asserted low, the receiver input is enabled for the next character. If DSR* is high, the receiver
is disabled until DSR* goes low.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.4 Channel Option Register 3 (COR3)
6.2.4.1 Async-HDLC/PPP Mode
Register Name: COR3
Intel Hex Address: x’15
Register Description: Channel Option 3
Default Value: x’00
Motorola Hex Address: x’16
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Stop2
FCSApd
RxChk
TxGen
npad3
npad2
npad1
npad0
Bit 7
Stop2
0 = 1 Stop bit
1 = 2 Stop bit
Bit 6
Bit 5
FCS append
0 = Receive CRC is not passed to the host at the end of the frame
1 = Receive CRC is passed to the host at the end of the frame
Receive FCS Check Enabled
When clear, the channel does not test the 2-byte FCS field. All frame data characters are
given to the host.
When set, the channel tests the 2-byte FCS field.
Bit 4
Transmit FCS Enabled
When clear, the channel does not add the 2-byte FCS field.
When set, the channel adds the 2-byte FCS field at the end of the frame.
Bits 3:0
Transmit Frame Leading Pads
The number of character times preceding any frame transmission. A character time is 10 bit
times. All zeros in this field disables the leading pads.
npad3 npad2 npad1 npad0 Number of leading pads
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
2
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DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.4.2 MNP 4 Mode
Register Name: COR3
Intel Hex Address: x’15
Register Description: Channel Option 3
Default Value: x’00
Motorola Hex Address: x’16
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Stop2
FCSApd
RxChk
TxGen
npad3
npad2
npad1
npad0
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and later de-
vices.
Bit 7
Bit 6
Bit 5
Stop2
0 = 1 Stop bit
1 = 2 Stop bit
FCS Append
0 = Receive CRC is not passed to the host at the end of the frame
1 = Receive CRC is passed to the host at the end of the frame
Receive FCS Check Enabled
When clear, the channel does not test the 2-byte FCS field. All frame data characters are
given to the host.
When set, the channel tests the 2-byte FCS field.
Bit 4
Transmit FCS Enabled
When clear, the channel does not add the 2-byte FCS field.
When set, the channel adds the 2-byte FCS field at the end of the frame.
Bits 3:0
Transmit Frame Leading Pads[3:0]
The number of character times preceding any frame transmission. A character time is 10 bit
times. All zeros in this field disables the leading pads.
npad3 npad2 npad1 npad0 Number of leading pads
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
2
15
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.4.3 HDLC Mode
Register Name: COR3
Intel Hex Address: x’15
Register Description: Channel Option 3
Default Value: x’00
Motorola Hex Address: x’16
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
FCS
Bit 3
idle
Bit 2
Bit 1
Bit 0
sndpad
Alt1
FCSPre
npad2
npad1
npad0
In Synchronous mode, COR3 specifies the learning pattern (pad character) sent by the CL-CD2431 to
synchronize the DPLL at the remote end. The pad character (00h or AAh) sent depends on the type of
encoding used.
Bit 7
Sends Pad Character(s)
1 = CL-CD2431 sends pad character(s) before sending flag when coming out of the Idle-in
Mark mode.
0 = CL-CD2431 does not send any pad character.
Bit 6
Bit 5
Bit 4
Send Sync Pattern
1 = AAh (Manchester/NRZ encoding) is sent as pad character.
0 = 00h (NRZI encoding) is sent as pad character.
FCS Preset
0 = FCS is preset to all ‘1’s (CRC V.41).
1 = FCS is preset to all ‘0’s (CRC-16).
FCS mode
1 = disables FCS generation and checking. The CL-CD2431 treats the entire frame as data.
0 = normal FCS mode. The CL-CD2431 generates and appends CRC on transmit and vali-
dates CRC on receive using the CRC polynomial selected through the CRC Polynomial
Select register.
Bit 3
Idle mode
0 = Idle-in Flag mode
1 = Idle-in Mark mode
Bits 2:0
Character Count
These bits specify the number of synchronous characters sent.
npad2 npad1 npad0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Reserved
1 pad character sent
2 pad characters sent
3 pad characters sent
4 pad characters sent
101–111 are reserved.
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DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.4.4 SLIP Mode
Register Name: COR3
Intel Hex Address: x’15
Register Description: Channel Option 3
Default Value: x’00
Motorola Hex Address: x’16
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Stop2
0
npad3
.npad2
npad1
npad0
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and later de-
vices.
Bit 7
Stop2
0 = 1 Stop bit
1 = 2 Stop bit
Bits 6:4
Bits 3:0
Reserved – must be ‘0’.
Transmit Frame Leading Pads[3:0]
The number of character times preceding any frame transmission. A character time is 10 bit
times. All zeros in this field disables the leading pads.
npad3 npad2 npad1 npad0 Number of leading pads
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
2
15
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.4.5 Asynchronous Mode
Register Name: COR3
Intel Hex Address: x’15
Register Description: Channel Option 3
Default Value: x’00
Motorola Hex Address: x’16
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
FCT
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ESCDE
RngDE
SCDE
Splstp
Stop2
Stop1
Stop0
Bit 7
Extended Special Character Detect Enable
0 = Special character detect for SCHR3 and SCHR4 is disabled.
1 = Special character detect for SCHR3 and SCHR4 is enabled; a special character interrupt
is generated following the receipt of a character matching SCHR3 or SCHR4.
Bit 6
Bit 5
Range Detect Enable
0 = Range detect disabled.
1 = Characters between SCRl and SCRh (inclusive) generate special character interrupts.
Flow Control Transparency mode
0 = Flow control characters received are passed to the host by receive exception interrupts.
1 = Flow control characters received are not passed to the host.
This bit has no effect unless both TxIBE (COR2[6]) and SCDE (COR3[4]) are set.
Bit 4
Bit 3
Special Character Detection Enable
0 = Special character detect for SCHR1 and 2 is disabled.
1 = Special character detect for SCHR1 and 2 is enabled.
This bit must be set along with TxIBE (COR2[6]) before FCT (COR3[5]) becomes effective.
Special Character I-strip
When set, this bit causes the receive character to be I-Stripped (COR3[7] set to ‘0’) for the
special character matching functions only. The character passed to the host is unaffected.
This function allows special character processing of data without knowing if the data is 8 bit
with no parity or 7 bit with parity.
Bits 2:0
Stop Bit Length[2:0]
These bits specify the length of the Stop bit.
Stop2 Stop1 Stop0 Stop Bit Length
0
0
1
1
1
0
0
1
0
1 stop bit
1.5 stop bits
2 stop bits
000–001 and 110–111 are reserved.
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DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.5 Channel Option Register 4 (COR4)
Register Name: COR4
Intel Hex Address: x’16
Register Description: Channel Option 4
Default Value: x’00
Motorola Hex Address: x’15
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
DSRzd
CDzd
CTSzd
FIFO threshod
(Modem Change Options and FIFO Transfer Threshold)
Bit 7
Bit 6
Bit 5
DSRzd = 1
Detect one-to-zero transition on the DSR* input (zero-to-one transition of DSR (MSVR) bit)
CDzd = 1
Detect one-to-zero transition on the CD* input (zero-to-one transition of CD (MSVR) bit)
CTSzd = 1
Detect one-to-zero transition on the CTS* input (zero-to-one transition of CTS (MSVR) bit)
Bit 4
Reserved – must be ‘0’.
Bits 3:0
FIFO Threshold in characters
Note that the maximum value allowed for this field is 12 (0C hex). This 4-bit binary-encoded
field sets the FIFO transfer threshold for both transmit and receive FIFOs in both Interrupt
and DMA Transfer modes.
In Asynchronous mode, a Good Data transfer is initiated for the number of characters in the
FIFO greater than the specified threshold. Receive timeout and the occurrence of a receive
data exception are also cause to initiate a receive transfer.
In Synchronous modes, data transfer is initiated when the number of characters in the FIFO
is greater than the specified threshold. An EOF also initiates a receive transfer.
For transmit operation, the CL-CD2431 attempts to refill the transmit FIFO when the empty
space in the FIFO is greater than the set threshold. In synchronous frame transmissions, the
CL-CD2431 stops refilling the transmit FIFO once the last character in the frame transfers to
the FIFO.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.6 Channel Option Register 5 (COR5)
Register Name: COR5
Intel Hex Address: x’17
Register Description: Channel Option 5
Default Value: x’00
Motorola Hex Address: x’14
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DSRod
CDod
CTSod
In/Out
Rx flow control threshold
This register defines the current-state change options to be monitored.
Bit 7
Bit 6
Bit 5
Bit 4
DSRod = 1
Detect zero-to-one transition on DSR* input (one-to-zero transition of DSR (MSVR) bit)
CDod = 1
Detect zero-to-one transition on CD* input (one-to-zero transition of CD (MSVR) bit)
CTSod = 1
Detect zero-to-one transition on CTS* input (one-to-zero transition of CTS (MSVR) bit)
In/Out – Automatic Receive Flow Control Select
This bit is ignored when bits 3:0 are all zeros.
0 = Use out-of-band flow control (DTR pin).
1 = Use in-band flow control (automatic transmission of XOFF/XON characters)
Bit 4
Number of characters in FIFO
CL-CD2431 Action
0
0
1
1
Less than or equal to threshold
Greater than threshold
DTR asserted
DTR deasserted
XON transmitted
XOFF transmitted
Less than or equal to threshold
Greater than threshold
NOTE: Do not use the STCR (Special Transmit Command register) to send XON and XOFF charac-
ters while using automatic in-band flow control.
Bits 3:0
Receive Flow Control FIFO Threshold
These four bits define the threshold for automatic flow control activation based on the con-
tents of the receive FIFO. A threshold value of zero disables this function and the setting of
bit 4 is ignored. Bit 4 determines whether the out-of-band (DTR pin) or the in-band
(XOFF/XON characters) is used to stop the flow of incoming data from the remote transmit-
ter.
When the number of characters in the FIFO exceeds this threshold, the DTR pin deasserts
or an XOFF character is transmitted.When the number of characters in the FIFO is less than
or equal to the threshold, the DTR asserts or and XON is transmitted.
August 1996
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.7 Channel Option Register 6 (COR6) — Async Mode Only
Register Name: COR6
Intel Hex Address: x’1B
Register Description: Channel Option 6
Default Value: x’00
Motorola Hex Address: x’18
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IgnCR
ICRNL
INLCF
IgnBrk
NBrkInt
ParMrk
INPCK
ParInt
CR is defined as 0D hex, NL as 0A hex, and NULL as 00 hex.
Bits 7:5
These three bits are used to enable translation of received CR/NL characters as follows:
IgnCr
ICrRNL INLCR
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No special action on CR and NL
NL translated to CR
CR translated to NL
CR translated to NL and NL translated to CR
CR discarded
CR discarded and NL translated to CR
CR discarded
CR discarded and NL translated to CR
Bits 4:3
Bits 2:0
Break Action
These bits determine the action taken after a break condition is received.
IgnBrk
NBrkInt
0
0
1
1
0
1
0
1
Generate an exception interrupt
Translate to a NULL character
Reserved
Discard character
Parity/Framing Error Actions
These bits determine the action taken when a parity or framing error is received.
Following the generation of a BREAK exception interrupt, a receive exception interrupt is
generated with RET bit (RISRl[7]) set, when the end of break is detected. The RET interrupt
must be enabled (IER[5]) to enable this feature.
ParMrk
INPCK ParInt
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Generated an exception interrupt
Translated to a NULL character
Ignore error; character passed on as good data
Discard error character
Reserved
Translate to a sequence of FF NULL and the error
character and pass on as Good Data
Reserved
1
1
1
1
0
1
Reserved
When ParMrk = 1 and ParInt = 1, each occurrence of FF hex in the datastream is preceded
by FF hex to distinguish it from a parity error sequence.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.8 Channel Option Register 7 (COR7) — Async Mode Only
Register Name: COR7
Intel Hex Address: x’04
Register Description: Channel Option 7
Default Value: x’00
Motorola Hex Address: x’07
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
IStrip
LNE
FCErr
ONLCR
OCRNL
CR is defined as 0D hex, NL as 0A hex, and NULL as 00 hex.
Bit 7
IStrip
When this bit is set, the most-significant bit of receive characters is stripped, leaving 7-bit
characters. IStrip is applied after all other character processing, but before special character
processing.
Bit 6
LNext
This bit enables the LNext option
0 = all receive characters are processed for special character detection.
1 = the character following the LNext character is not processed for special character match-
ing or flow control.
This provides a mechanism to transfer flow control and special characters as normal data,
without invoking flow control action in the CL-CD2431, and without generating special inter-
rupts. The LNext character is defined in the LNXT register, and when processed, is always
passed to the host CPU as normal data.
Bit 5
Flow control on error characters
0 = characters received with an error are not processed for special character/flow control
matching.
1 = all receive characters, even those with errors, are processed for special character/flow
control processing.
Bits 4:2
Bits 1:0
Reserved – must be ‘0’.
Transmit processing for CR and NL
These bits define the Translation mode when CR and/or NL are present in the transmit data.
ONLCR
OCRNL
0
0
1
1
0
1
0
1
No special action.
CR translated to NL.
NL translated to the sequence CR NL.
CR translated to NL and NL translated to the sequence CR NL.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.9 Special Character Registers — Async Modes Only
Special Character registers can be used for detecting specific receive characters in the incoming data
stream, and can be used to transmit character (by STCR) preempting any data in the transmit FIFO.
6.2.9.1 Special Character Register 1 (SCHR1)
Register Name: SCHR1
Intel Hex Address: x’1C
Register Description: Special Character 2
Default Value: x’00
Motorola Hex Address: x’1F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined Special Character,
protcol-defined Special Characters (see below).
6.2.9.2 Special Character Register 2 (SCHR2)
Register Name: SCHR2
Intel Hex Address: x’1D
Register Description: Special Character 2
Default Value: x’00
Motorola Hex Address: x’1E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined Special Character,
protcol-defined Special Characters (see below).
Asynchronous Mode
Special characters 1 and 2 are used in conjunction with the SCDE bit (COR3[4]) to detect incoming char-
acters; when both SCDE and TxIBE (COR2[6]) are set, they define the in-band flow control characters
XON and XOFF.
SCHR1 = XON
SCHR2 = XOFF
In addition to the SCDE and TxIBE bits, if the FCT bit (COR3[5]) is set when flow control characters are
received, they are stripped from the data stream.
MNP 4 Mode
SCHR1 holds the start character.
SCHR1 holds the escape character
MNP 4/ARAP 1.0ARAP 2.0
SCHR1SYN 16 hexSOH 01 hex
SCHR2DLE 10 hexESC 1B hex
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.9.3 Special Character Register 3 (SCHR3)
Register Name: SCHR3
Intel Hex Address: x’1E
Register Description: Special Character 3
Default Value: x’00
Motorola Hex Address: x’1D
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined special character
6.2.9.4 Special Character Register 4 (SCHR4)
Register Name: SCHR4
Intel Hex Address: x’1F
Register Description: Special Character 4
Default Value: x’00
Motorola Hex Address: x’1C
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined special character
Special characters 3 and 4 are used in conjunction with the ESCDE bit (COR3[7]) to detect characters in
the receive data stream and to generate receive special character interrupts.
NOTE: Special characters 3 and 4 are not stripped from the data stream if FCT (Flow Control Transparency) mode
is enabled.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.10 Special Character Range Register — Async Mode Only
6.2.10.1 Special Character Range — Low (SCRl)
Register Name: SCRL
Intel Hex Address: x’20
Register Description: Special Character Range, low
Default Value: x’00
Motorola Hex Address: x’23
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined special character detect range, low
6.2.10.2 Special Character Range — High (SCRh)
Register Name: SCRH
Intel Hex Address: x’21
Register Description: Special Character Range, high
Default Value: x’00
Motorola Hex Address: x’22
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined special character detect range, high
These registers define an inclusive range for special character recognition in the Asynchronous mode. It
can be useful for identifying that a received character is within a user defined range and is, for example,
a control character.
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.11 LNext Character (LNXT) — Async Mode Only
Register Name: LNXT
Intel Hex Address: x’2D
Register Description: Literal Next Character
Default Value: x’00
Motorola Hex Address: x’2E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-defined literal next character
This register defines the LNext character. If the LNext function is enabled (COR7[6]), the CL-CD2431 ex-
amines received characters and compare them against this value. If a match occurs, this character and
the next are placed in the FIFO without any special processing. In effect, the LNext function causes the
CL-CD2431 to ignore characters with special meaning, such as flow control characters. There are two
exceptions: a ‘BREAK’ or an ‘ERROR’ character. If the character following the LNext character is either a
‘break’ or an ‘errored’ character, LNext is placed in the FIFO, and the next character is treated as it nor-
mally would be for these error conditions.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.12 Receive Frame Address Registers — HDLC Sync Mode Only
6.2.12.1 Receive Frame Address Register 1 (RFAR1)
Register Name: RFAR1
Intel Hex Address: x’1C
Register Description: Receive Frame Address 1
Default Value: x’00
Motorola Hex Address: x’1F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 0
Frame Qualification Address 1
6.2.12.2 Receive Frame Address Register 2 (RFAR2)
Register Name: RFAR2
Register Description: Receive Frame Address 2
Default Value: x’00
Intel Hex Address: x’1D
Motorola Hex Address: x’1E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Frame Qualification Address 2
6.2.12.3 Receive Frame Address Register 3 (RFAR3)
Register Name: RFAR3
Register Description: Receive Frame Address 3
Default Value: x’00
Intel Hex Address: x’1E
Motorola Hex Address: x’1D
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Frame Qualification Address 3
6.2.12.4 Receive Frame Address Register 4 (RFAR4)
Register Name: RFAR4
Register Description: Receive Frame Address 4
Default Value: x’00
Intel Hex Address: x’1F
Motorola Hex Address: x’1C
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
Frame Qualification Address 4
Reception of an HDLC frame can be qualified with a matched 1- or 2-byte address field either as four 1-
byte alternatives or two 2-byte alternatives. The use of RFAR registers for address recognition is de-
scribed in the Channel Option registers (COR1) on page 86.
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.13 CRC Polynomial Select Register (CPSR)
Register Name: CPSR
Intel Hex Address: x’D4
Register Description: CRC Polynomial Select
Default Value: x’00
Motorola Hex Address: x’D6
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
Poly
0
0
Bits 7:1
Bit 0
Reserved – must be ‘0’.
Polynomial select
0 = CRC V.41 polynomial (normally used for HDLC protocol and preset to 1’s)
x**16 + x**12 + x**5 + 1
1= CRC-16 polynomial (generally used for Bisync but will work in HDLC mode, preset to 0’s)
x**16 + x**15 + x**2 + 1
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.14 Transmit Special Mapped Characters — PPP Mode only
6.2.14.1 Transmit Special Mapped Character 1 (TSPMAP1)
Register Name: TSMAP1
Intel Hex Address: x’1B
Register Description: Special Mapped Transmit Character 1
Default Value: x’00
Motorola Hex Address: x’18
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 2
Bit 2
Bit 1
Bit 0
User-defined mapped transmit character
6.2.14.2 Transmit Special Mapped Character 2 (TSPMAP2)
Register Name: TSMAP2
Register Description: Special Mapped Transmit Character 2
Default Value: x’00
Intel Hex Address: x’04
Motorola Hex Address: x’07
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
User-defined mapped transmit character
6.2.14.3 Transmit Special Mapped Character 3 (TSPMAP3)
Register Name: TSMAP3
Register Description: Special Mapped Transmit Character 3
Default Value: x’00
Intel Hex Address: x’2D
Motorola Hex Address: x’2E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 1
Bit 0
User-defined mapped transmit character
The three TSPMAP registers are used to provide control character escape processing on characters out-
side the 00–1f (hex) range. Each of these three registers are scanned to match the character currently
being transmitted; if a match occurs, that character is ‘escaped’ before transmission. If a zero value is
found in any of them, the scan is terminated. (Zero is already covered in the standard TXACCM.)
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Advanced Multi-Protocol Communications Controller
6.2.15 Transmit Async Control Character Maps — PPP Mode Only
6.2.15.1 Transmit Async Control Character Map 0 (TXACCM0)
Register Name: TXACCM0
Intel Hex Address: x’1C
Register Description: Transmit Async Control Character Map 0
Default Value: x’00
Motorola Hex Address: x’1F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 07
Char. 06
Char. 05
Char. 04
Char. 03
Char. 02
Char. 01
Char. 00
6.2.15.2 Transmit Async Control Character Map 1 (TXACCM1)
Register Name: TXACCM1
Intel Hex Address: x’1D
Register Description: Transmit Async Control Character Map 1
Default Value: x’00
Motorola Hex Address: x’1E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 0F
Char. 0E
Char. 0D
Char. 0C
Char. 0B
Char. 0A
Char. 09
Char. 08
6.2.15.3 Transmit Async Control Character Map 2 (TXACCM2)
Register Name: TXACCM2
Intel Hex Address: x’1E
Register Description: Transmit Async Control Character Map 2
Default Value: x’00
Motorola Hex Address: x’1D
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 17
Char. 16
Char. 15
Char. 14
Char. 13
Char. 12
Char. 11
Char. 10
6.2.15.4 Transmit Async Control Character Map 3 (TXACCM3)
Register Name: TXACCM3
Intel Hex Address: x’1F
Register Description: Transmit Async Control Character Map 3
Default Value: x’00
Motorola Hex Address: x’1C
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 1F
Char. 1E
Char. 1D
Char. 1C
Char. 1B
Char. 1A
Char. 19
Char. 18
The TXACCM registers define transmitted characters in the range 00–1F as mapped (Control bit set) or
not mapped (Control bit clear) as follows:
TXACCM0 bits 0–7 control characters 00–07, respectively.
TXACCM1 bits 0–7 control characters 08–0F, respectively.
TXACCM2 bits 0–7 control characters 10–17, respectively.
TXACCM3 bits 0–7 control characters 18–1F, respectively.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.2.16 Receive Async Control Character Maps — PPP Mode Only
6.2.16.1 Receive Async Control Character Map 0 (RXACCM0)
Register Name: RXACCM0
Intel Hex Address: x’20
Register Description: Receive Async Control Character Map 0
Default Value: x’00
Motorola Hex Address: x’23
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 07
Char. 06
Char. 05
Char. 04
Char. 03
Char. 02
Char. 01
Char. 00
6.2.16.2 Receive Async Control Character Map 1 (RXACCM1)
Register Name: RXACCM1
Intel Hex Address: x’21
Register Description: Receive Async Control Character Map 1
Default Value: x’00
Motorola Hex Address: x’22
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 0F
Char. 0E
Char. 0D
Char. 0C
Char. 0B
Char. 0A
Char. 09
Char. 08
6.2.16.3 Receive Async Control Character Map 2 (RXACCM2)
Register Name: RXACCM2
Intel Hex Address: x’22
Register Description: Receive Async Control Character Map 2
Default Value: x’00
Motorola Hex Address: x’21
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 17
Char. 16
Char. 15
Char. 14
Char. 13
Char. 12
Char. 11
Char. 10
6.2.16.4 Receive Async Control Character Map 3 (RXACCM3)
Register Name: TXACCM3
Intel Hex Address: x’23
Register Description: Transmit Async Control Character Map 3
Default Value: x’00
Motorola Hex Address: x’20
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Char. 1F
Char. 1E
Char. 1D
Char. 1C
Char. 1B
Char. 1A
Char. 19
Char. 18
The RXACCM registers define received characters in the range 00–1F as mapped (Control bit set) or not
mapped (Control bit clear) as follows:
RXACCM0 bits 0–7 control characters 00–07, respectively.
RXACCM1 bits 0–7 control characters 08–0F, respectively.
RXACCM2 bits 0–7 control characters 10–17, respectively.
RXACCM3 bits 0–7 control characters 18–1F, respectively.
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Advanced Multi-Protocol Communications Controller
6.3 Bit Rate and Clock Option Registers
6.3.1 Receive Bit Rate Generator Registers
6.3.1.1 Receive Bit Rate Period Register (RBPR)
Register Name: RBPR
Intel Hex Address: x’C9
Register Description: Receive Bit Rate Period
Default Value: x’81
Motorola Hex Address: x’CB
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Receive Bit Rate Period (Divisor)
This register contains the preload value for the receive baud rate counter. When using an internal clock
option or an n-times external clock, the preload value in conjunction with the receiver clock source chosen,
determines the receive bit rate. If a 1× external clock is used, a value of 01h must be loaded in the RBPR.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.3.1.2 Receive Clock Option Register (RCOR)
Register Name: RCOR
Intel Hex Address: x’CA
Register Description: Receive Clock Option
Default Value: x’00
Motorola Hex Address: x’C8
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TLVal
0
DpllEn
Dpllmd1
Dpllmd0
ClkSel2
ClkSel1
ClkSel0
This register is used to select the DPLL mode and the desired clock source for the receive bit rate gener-
ator.
Bit 7
Transmit Line Value
This bit reflects the logical value of the transmit data pin. It is a read-only bit; writing to this
bit has no effect.
Bit 6
Bit 5
Reserved – must be ‘0’.
DPLL Enable
1 = DPLL is enabled
0 = DPLL is disabled
Bits 4:3
DPLL mode selects the type of data encoding used.
Dpllmd1 Dpllmd0
Encoding
0
0
1
1
0
1
0
1
NRZ
NRZI
Manchester
Reserved
Bits 2:0
These three bits select the clock source for the receive baud rate generator or DPLL.
Clksel2
Clksel1
Clksel0
Clock Source
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Clk 0
Clk 1
Clk 2
Clk 3
Clk 4
Reserved
External clock
Reserved
NOTE: See the description of clock options in Section 3.5.
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Advanced Multi-Protocol Communications Controller
6.3.2 Transmit Bit Rate Generator Registers
6.3.2.1 Transmit Bit Rate Period Register (TBPR)
Register Name: TBPR
Intel Hex Address: x’C1
Register Description: Transmit Bit Rate Period
Default Value: x’81
Motorola Hex Address: x’C3
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit Bit Rate Period (Divisor)
This register contains the preload value for the transmit baud rate count. When using one of the internal
clocks or an n-times external clock, the preload value in conjunction with the transmitter clock source cho-
sen, determines the transmit bit rate. If a 1× external clock or the receive clock is used, a value of 01h
must be loaded in the TBPR.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.3.2.2 Transmit Clock Option Register (TCOR)
Register Name: TCOR
Intel Hex Address: x’C2
Register Description: Transmit Clock Option
Default Value: x’00
Motorola Hex Address: x’C0
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
0
Bit 1
LLM
Bit 0
0
ClkSel2
ClkSel1
ClkSel0
Ext-1X
This register controls the transmit bit rate generator and Local Loopback mode.
Bits 7:5
These bits select the clock source for the transmit bit rate generator.
ClkSel2
ClkSel1
ClkSel0
Select
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Clk 0
Clk 1
Clk 2
Clk 3
Clk 4
Reserved
External clock
Receive clock
NOTE: See the description of clock options in Section 3.5.
Bit 4
Bit 3
Reserved – must be ‘0’.
Times 1 external clock. This bit is set to ‘1’ when the user supplies the data clock on TXCIN
pin where the frequency is equal to the transmit data rate. When using the external 1× clock
or the clock from the receiver’s DPLL, the TBPR must be programmed to 01h.
Bit 2
Bit 1
Reserved – must be ‘0’.
Local Loopback mode
1 = enables the Local Loopback mode
0 = disables the Local Loopback mode
Bit 0
Reserved – must be ‘0’.
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Advanced Multi-Protocol Communications Controller
6.4 Channel Command and Status Registers
6.4.1 Channel Command Register (CCR)
There are two CCR command sets. Mode 1 (if bit 7 is ‘0’) commands affect basic channel control. In Mode
2 (if bit 7 is ‘1’), additional commands that control timer functions are available.
Mode 1
Register Name: CCR
Intel Hex Address: x’10
Register Description: Channel Command, Mode 1
Default Value: x’00
Motorola Hex Address: x’13
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
ClrCh
InitCh
RstAll
EnTx
DisTx
EnRx
DisRx
The various command and control bits in this register perform largely independent functions.The host can
assert multiple command bits to achieve the desired effect.The CL-CD2431 clears the register to ‘0’ after
it accepts and acts on a host command.The host must verify that the contents of this register are ‘0’ prior
to issuing a new command. If the RESET ALL command is issued, all other commands are ignored. All
other combinations are legal, and the order of processing is as follows:
1) Clear channel
2) Initialize channel
3) Enable receive
4) Disable receive
5) Enable transmit
6) Disable transmit
NOTE: Processing CCR commands is a low-priority task for the internal firmware, since they seldom occur. The
user must take care when waiting for command completions at critical times, that is, during interrupt service
routines.
Channel Control Commands (Bit 7 = 0)
Bit 7
Bit 6
Must be ‘0’.
Clear Channel Command
When this command is issued, the CL-CD2431 clears the data FIFOs and current transmit
and receive status of the channel in the CSR. If the channel is currently transmitting a frame
in synchronous protocol, the host should issue the transmit abort special transmit command,
before issuing a Clear command.The channel parameters are not affected by a Clear Chan-
nel command. This command causes both receive and transmit FIFOs to be cleared, the
transmitter and receiver to be disabled, and all DMA Status registers (DMABSTS, A/BRB-
STS and A/BTBSTS) to be cleared.
Bit 5
Initialize Channel
If any change is made to the Protocol Mode Select bits in the CMR (Channel Mode register)
or to the COR1, the channel must be reinitialized by this command. The InitCh command
causes the internal protocol-specific registers to be initialized.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
▲ WARNING: If the Initialize Channel command is issued after a channel is already in operation, then a Clear
Channel command must be issued prior to, or coinciding with the Initialize Channel command.
Failure to observe this requirement will result in unpredictable device behavior.
Bit 4
Reset All
An on-chip firmware initialization of all channels is performed. All channel and global param-
eters are reset to their power-on reset condition.This command is the strongest the host can
issue. None of the other command bits are interpreted if the RESET ALL command is given.
The host must re-initialize the CL-CD2431 following the execution of this command just as
after a hardware power-on reset. When this command is complete, the GFRCR is updated
with the firmware revision code.
Bit 3
Bit 2
Bit 1
Bit 0
Enable Transmitter
Enables the transmitter by setting the TxEn bit (CSR[3]). In Asynchronous mode, this com-
mand also clears the transmit flow control options.
Disable Transmitter
Disables the transmitter by clearing the TxEn bit (CSR[3]). In Asynchronous mode, the Trans-
mit Flow Control bits are cleared.
Enable Receiver
Enables the receiver by setting the RxEn bit (CSR[7]). In Asynchronous mode, the Receive
Flow Control bits are cleared.
Disable Receiver
Disables the receiver by clearing the RxEn bit (CSR[7]). In Asynchronous mode, the Receive
Flow Control bits are cleared.
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Advanced Multi-Protocol Communications Controller
6.4.1.1 CCR Mode 2
Register Name: CCR
Intel Hex Address: x’10
Register Description: Channel Command, Mode 2
Default Value: x’00
Motorola Hex Address: x’13
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
0
1
ClrT1
ClrT2
ClrRcv
ClrTx
Either one or both of the timers can be cleared with a single command. Note that if the running timer value
is 01h at the time this command is issued, there is a small chance that the timer expires and causes a
timer interrupt before the command is processed.
Bit 7
Bit 6
Must be ‘1’.
Clear Timer 1
General timer 1 is cleared.
Bit 5
Bit 4
Clear Timer 2
General timer 2 is cleared.
Clear Receiver Command
This command only affects the receiver. It resets all receiver functions like a combination of
clear channel, initialize channel and enable receiver commands. ClrRcv clears the receive
FIFO and clears receive status in the CSR register, except for the RcvEn bit. ClrRcv clears
the receive DMA buffer status in A/BRBSTS and receive status in DMABSTS. Clearing the
2431own bits in both Receive Buffer Status registers means that DMA buffers must be
returned to the CL-CD2431 before receive transfers can begin again.
For Synchronous modes, this command puts the receiver back into SYN/Flag Hunt mode.
Bit 3
Clear Transmitter Command
This command only affects the transmitter; it is only available on Revision C and later devices
and only effective in asynchronous protocols. It resets all transmitter functions like a combi-
nation of clear channel, initialize channel and transmit commands. ClrTx clears the transmit
FIFO and clears transmit status in the CSR, except for the TxEn bit.
ClrTx clears transmit DMA buffer status in ATBSTS, BTBSTS, and Transmit Status bits in
DMABSTS. Clearing the 2431own bits in both the Transmit Buffer Status registers means
that DMA buffers have to be returned to the CL-CD2431 before transmit transfers begin
again.
Bits 2:0
Reserved – must be ‘0’.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.2 Special Transmit Command Register (STCR)
Async — HDLC/PPP Mode
Register Name: STCR
Intel Hex Address: x’11
Register Description: Special Transmit Command
Default Value: x’00
Motorola Hex Address: x’12
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
Xon
Bit 0
Xoff
0
AbortTx
SndSpc
Frame
Special characters can be transmitted preemptively (ahead of any characters in the transmit FIFO) upon
commands described below. When the special character is transmitted, the STCR is cleared by the de-
vice.
Bit 7
Bit 6
Reserved – must be ‘0’.
Abort
Transmission of the two-character sequence (7D–7E) aborts the current transmit frame. All
data in the FIFO following the abort is discarded. If DMA is used, the remaining data up to
the EOF is discarded.
Bits 5:4
Bit 3
Reserved – must be ‘0’.
Send Special Character Command
When clear, the frame, Xon, and Xoff bits described below have no meaning.
When set, the host should also set one of the following bits: frame, Xon, or Xoff.
Bit 2
Send Framing Error
This bit causes the next character in the transmit stream to be sent with an incorrect Stop bit
(Stop bit is ‘0’).
This bit is intended as a test function. Unlike the Abort bit, this bit does not terminate the
transmission.
Bit 1
Bit 0
Send XON
This bit causes the transmission of an XON (cntl-Q or hex 11).
NOTE: The user should not use the send XON/XOFF commands if automatic in-band flow control is
enabled (Asynchronous modes only) in COR5.
Send XOFF
Causes the transmission of an XOFF (cntl-S or hex 13).
The command structure associated with the sndsp Control bit is:
sndsp
frame
Xon
Xoff
Action
0
1
1
1
X
1
0
0
X
X
1
X
X
X
1
Send Special Disabled
Send one character with FE
Send Xon
0
Send Ooff
NOTE: The user should not use the send XON/XOFF commands if automatic in-band flow control is
enabled (Asynchronous modes only) in COR5.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.2 Special Transmit Command Register (STCR) (cont.)
SLIP/MNP 4 Mode
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and later de-
vices.
Register Name: STCR
Intel Hex Address: x’11
Register Description: Special Transmit Command
Default Value: x’00
Motorola Hex Address: x’12
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
Bit 2
Bit 1
0
Bit 0
0
0
AbortTx
SndSpc
Frame
Special characters can be transmitted preemptively (ahead of any characters in the transmit FIFO) upon
commands described below. When the special character is transmitted, the STCR is cleared by the de-
vice.
Bit 7
Bit 6
Reserved – must be ‘0’.
Abort
Transmission of the two-character sequence (7D–7E) aborts the current transmit frame. All
data in the FIFO following the abort is discarded. If DMA is used, the remaining data up to
the EOF is discarded.
Bits 5:4
Bit 3
Reserved – must be ‘0’.
Send Special Character Command
When clear, the frame, Xon, and Xoff bits described below have no meaning.
When set, the host should also set one of the following bits: frame, Xon, or Xoff.
Bit 2
Send Framing Error
Causes the next character in the transmit stream to be sent with an incorrect stop bit (stop
bit is ‘0’).
This bit is intended as a test function. Unlike the Abort bit, this bit does not terminate the
transmission.
Bits 1:0
Reserved – must be ‘0’.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.2 Special Transmit Command Register (STCR) (cont.)
Async and HDLC Modes
Register Name: STCR
Intel Hex Address: x’11
Register Description: Special Transmit Command
Default Value: x’00
Motorola Hex Address: x’12
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
0
AbortTx
AppdCmp
SndSpc
SSPC2
SSPC1
SSPC0
The CL-CD2431 clears the register to ‘0’ when it accepts a host CPU command.
Bit 7
Bit 6
Reserved – must be ‘0’.
Abort Transmission (HDLC mode)
Terminates the frame currently in transmission with an abort sequence. In DMA mode, all
data up to the next EOF is discarded.
Bit 5
Append Complete (Asynchronous DMA mode)
This bit should be set by the host when the last addition is made to the append buffer.
Bit 4
Bit 3
Reserved – must be ‘0’.
Send Special Character(s) Çcommand
In Asynchronous mode, the sends a user-defined special character or special-character
sequence. The special character is transmitted ahead of any data remaining in the FIFO.
Bits 2:0
Special Character Select
SSPC2
SSCP1
SSPC0 Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Send Special Character 1
Send Special Character 2
Send Special Character 3
Send Special Character 4
Reserved
Reserved
Reserved
NOTE: The user should not use the send XON/XOFF commands if automatic in-band flow control is
enabled (Asynchronous modes only) in COR5.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.3 Channel Status Register (CSR)
This status register stores the current state of the channel. It can be read by the host at any time. The
states of the RxEn and the TxEn bits are controlled by host CPU commands to the CCR.
HDLC Mode
Register Name: CSR
Intel Hex Address: x’19
Register Description: Channel Status
Default Value: x’00
Motorola Hex Address: x’1A
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RxEn
RxFlag
RxFrame
RxMark
TxEn
TxFlag
TxFrame
TxMark
Bit 7
Receiver Enable
0 = Receiver is disabled.
1 = Receiver is enabled.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rx Flag
0 = Currently not receiving flag/SYN
1 = Currently receiving flag/SYN
Rx Frame
0 = Currently not receiving frame.
1 = Currently receiving frame.
Rx Mark
0 = Currently not receiving continuous mark.
1 = Currently receiving continuous mark.
Transmitter Enable
0 = Transmitter is disabled.
1 = Transmitter is enabled.
Tx Flag
0 = Currently not transmitting flag.
1 = Currently transmitting flag.
Tx Frame
0 = Currently not transmitting frame.
1 = Currently transmitting frame.
Tx Mark
0 = Currently not transmitting continuous ones.
1 = Currently transmitting continuous ones.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.3 Channel Status Register (CSR) (cont.)
Asynchronous Mode
Register Name: CSR
Intel Hex Address: x’19
Register Description: Channel Status
Default Value: x’00
Motorola Hex Address: x’1A
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
0
RxEn
RxFloff
RxFlon
TxEn
TxFloff
TxFlon
If the host determines that a flow control state is inappropriate, it can be cleared by enabling or disabling
the transmitter or receiver by a CCR command.
Bit 7
Receiver Enable
0 = receiver disabled.
1 = receiver enabled.
Bit 6
Receive Flow Off
0 = normal
1 = The CL-CD2431 has requested the remote to stop transmission (Send Xoff command
given to the channel). This bit is reset when the CL-CD2431 has requested the remote to
restart transmission, the receiver is enabled or disabled, or the channel is reset.
Bit 5
Receive Flow On
0 = normal
1 = The CL-CD2431 has requested the remote to restart character transmission (Send XON
command has been given to the channel). This bit is reset when the next (non-flow control)
character is received, the receiver is enabled or disabled, or the channel is reset.
Bit 4
Bit 3
Reserved — always returns ‘0’ when read.
Transmitter Enable
0 = transmitter disabled
1 = transmitter enabled
Bit 2
Bit 1
Bit 0
Transmit Flow Off
0 = normal
1 = The CL-CD2431 has been requested by the remote to stop transmission.This bit is reset
when the CL-CD2431 receives a request to resume transmission, the transmitter is enabled
or disabled, or the channel is reset.
Transmit Flow On
0 = normal
1 = The CL-CD2431 has been requested by the remote to resume transmission. This bit is
reset once character transmission is resumed, the transmitter is enabled or disabled, or the
channel is reset.
Reserved — always returns ‘0’ when read.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.3 Channel Status Register (CSR) (cont.)
Async-HDLC/PPP Mode
Register Name: CSR
Intel Hex Address: x’19
Register Description: Channel Status
Default Value: x’00
Motorola Hex Address: x’1A
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Tidle
RxEn
RxFloff
RFram
Ridle
TxEn
TxFloff
TFram
Bit 7
Receiver Enabled Status
When set, the receiver is enabled.
When clear, the receiver is disabled.
Bit 6
Receive Flow Off Status
When set, Xoff has been transmitted as commanded in the STCR. RxFloff indicates that the
remote station has been requested to stop transmission. RxFloff remains set until the host
issues an STCR command to send an Xon, or when the receiver is enabled or disabled, or
the channel is reset.
When clear, the remote station is not requested to stop transmission. RxFloff remains set
until the host issues an STCR command to send an Xon.
Bit 5
Bit 4
Receive Frame Status
When set, a frame is being received.
When clear, no frame is being received.
Receiver Idle Status
When set, the receiver input is idle.
When clear, the receiver input is not idle.
Notice that RFram and RIdle are mutually exclusive.
Bit 3
Bit 2
Transmitter Enabled Status
When set, the transmitter is enabled.
When clear, the transmitter is disabled.
Transmit Flow Off Status
This bit has no meaning unless TxIBE in COR2 is set.
When set, an Xoff has been received, and the transmitter has stopped sending data.
When clear, the transmitter is able to transmit if there are characters to send.
Bit 1
Bit 0
Transmit Frame Status
When set, a frame is being transmitted.
When clear, no frame is being transmitted.
Transmitter Idle Status
When set, the transmitter output is idle.
When clear, the transmitter output is not idle.
Note that TFram and TIdle are mutually exclusive.
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Advanced Multi-Protocol Communications Controller
6.4.3 Channel Status Register (CSR) (cont.)
SLIP/MNP 4 Mode
NOTE: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and later de-
vices.
Register Name: CSR
Intel Hex Address: x’19
Register Description: Channel Status
Default Value: x’00
Motorola Hex Address: x’1A
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
Bit 0
Tidle
RxEn
0
RFram
Ridle
TxEn
TFram
Bit 7
Receiver Enabled Status
When set, the receiver is enabled.
When clear, the receiver is disabled.
Bit 6
Bit 5
Reserved – must be ‘0’.
Receive Frame Status
When set, a frame is being received.
When clear, no frame is being received.
Bit 4
Bit 3
Receiver Idle Status
When set, the receiver input is idle.
When clear, the receiver input is not idle.
Note that RFram and RIdle are mutually exclusive.
Transmitter Enabled Status
When set, the transmitter is enabled.
When clear, the transmitter is disabled.
Bit 2
Bit 1
Reserved – must be ‘0’.
Transmit Frame Status
When set, a frame is being transmitted.
When clear, no frame is being transmitted.
Bit 0
Transmitter Idle Status
When set, the transmitter output is idle.
When clear, the transmitter output is not idle.
Note that TFram and TIdle are mutually exclusive.
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.4.4 Modem Signal Value Registers (MSVR)
6.4.4.1 Modem Signal Value Register (MSVR-RTS)
Register Name: MSVR-RTS
Register Description: Modem Signal Value - RTS
Default Value: x’00
Intel Hex Address: x’DC
Motorola Hex Address: x’DE
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
CTS
Bit 4
Bit 3
0
Bit 2
0
Bit 1
DTR
Bit 0
RTS
DSR
CD
DTRop
6.4.4.2 Modem Signal Value Register (MSVR-DTR)
Register Name: MSVR-DTR
Register Description: Modem Signal Value - DTR
Default Value: x’00
Intel Hex Address: x’DD
Motorola Hex Address: x’DF
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
CTS
Bit 4
Bit 3
0
Bit 2
0
Bit 1
DTR
Bit 0
RTS
DSR
CD
DTRop
Either of these registers is read to determine the current input levels on the input modem pins. Note that
the pin definitions for these signals is negative true while the register values are positive-true. Two regis-
ters are provided for control of the outputs — DTR* and RTS*. Writing to the MSVR-DTR register affects
only the DTR* pin. Writing to the MSVR-RTS register affects only the RTS* pin.
Bit 7
Bit 6
Bit 5
Bit 4
Data Set Ready
This bit reflects the current state of DSR*.
Carrier Detect
This bit reflects the current state of CD*.
Clear To Send
This bit reflects the current state of CTS*.
DTR Option (written by MSVR-DTR register)
0 = value of DTR bit is output on TXCOUT/DTR* pin
1 = Transmit clock is output on TXCOUT/DTR* pin
NOTE: If the transmit clock source is a 1× clock on the TXCIN pin, this signal cannot be driven on
TXCOUT/DTR*.
Bit 3
Bit 2
Bit 1
Reserved – must be ‘0’.
Reserved – returns ‘0’ when read; writing has no effect.
Data Terminal Ready
This bit reflects the current state of DTR*.
Bit 0
Request To Send
This bit reflects the current state of RTS*.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5 Interrupt Registers
6.5.1 General Interrupt Registers
6.5.1.1 Local Interrupt Vector Register (LIVR)
Register Name: LIVR
Intel Hex Address: x’0A
Register Description: Local Interrupt Vector
Default Value: x’00
Motorola Hex Address: x’09
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
‘IT1
Bit 0
IT0
X
X
The host effectively controls bits 7:2; the device provides bits 1:0 within an interrupt acknowledge context.
The CL-CD2431 has one Local Interrupt Vector register per channel, each with six host-defined bits. The
host can opt to embed the channel number and the protocol in use on the channel in the channel vector.
The CL-CD2431 supplies two modified bits signifying the type of interrupt service required.
Bits 7:2
Bits 1:0
User-defined. These six bits can be used as the CL-CD2431 device ID number.
Interrupt type. These two bits indicate the group/type of interrupt occurring.
IT[1:0]
Group/Type
01
10
11
00
Group 1 — modem signal change interrupt/general timer interrupt.
Group 2 — transmit data interrupt.
Group 3 — receive data interrupt.
Group 3 — eceive exception interrupt.
Note that because the CL-CD2431 provides a unique Local Interrupt Vector register for each
channel, the host has the option to include the channel number within the interrupt vector.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.1.2 Interrupt Enable Register (IER), Non-PPP Modes
Register Name: IER
Intel Hex Address: x’12
Register Description: Interrupt Enable
Default Value: x’00
Motorola Hex Address: x’11
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
RET
Bit 4
0
Bit 3
RxD
Bit 2
Bit 1
Bit 0
TxD
Mdm
0
TIMER
TxMpty
Bit 7
Modem Pin Change Detect Enable
This is the aster interrupt enable for modem change detect functions. The host can select
which modem pins are monitored for input change and select either or both directions of
change by programming the change detect option bits in COR4 and COR5. A Group1-type
interrupt (see the LIVR description on the previous page) is generated from this enable.
Bit 6
Bit 5
Reserved – must be ‘0’.
RET (Async)
In Asynchronous mode, this bit enables a group 3 receive exception timeout interrupt when
a receive data timeout occurs with an empty receive FIFO. This provides a mechanism for
the host to manage a partially full receive buffer when receive data stops.
Bit 4
Bit 3
Reserved – must be ‘0’.
Rx data
The receive FIFO threshold has been reached in Interrupt Transfer mode, causing a Group
3 receive data interrupt. Any receive exception causes a Group 3 receive exception interrupt.
Bit 2
Bit 1
General Timer(s) Timeout Enable
In Synchronous mode, this bit enables a Group 1 interrupt when either timer reaches ‘0’.
Tx Mpty
Transmitter empty. If enabled, a Group 2 interrupt is generated when the channel is com-
pletely empty of transmit data.
Bit 0
Tx Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer mode. Group
2 interrupts are generated at the end of transmit DMA buffers or when the FIFO threshold is
reached in Interrupt Transfer mode.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.1.3 Interrupt Enable Register (IER), PPP Mode
Register Name: IER
Intel Hex Address: x’12
Register Description: Interrupt Enable
Default Value: x’00
Motorola Hex Address: x’11
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
RxD
Bit 2
Bit 1
Bit 0
TxD
Mdm
0
TIMER
TxMpty
Bit 7
Modem Pin Change Detect
Master interrupt enable for modem change detect functions. The host can select which
modem pins are watched for input change and select either or both directions of change by
programming the change detect option bits in COR4 and COR5. A group1 type interrupt (see
LIVR description) is generated from this enable.
Bit 6:4
Bit 3
Reserved – must be ‘0’.
Rx data
The receive FIFO threshold has been reached in Interrupt Transfer mode, causing a group 3
receive data interrupt. Any receive exception causes a group 3 receive exception interrupt.
Bit 2
Bit 1
Bit 0
Timer
General timer(s) timeout
In Synchronous mode, this bit enables a group 1 interrupt when either timer reaches ‘0’.
Transmitter empty
If enabled, a group 2 interrupt is generated when the channel is completely empty of transmit
data.
Tx Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer mode. Group
2 interrupts are generated at the end of transmit DMA buffers or when the FIFO threshold is
reached in Interrupt Transfer mode.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.1.4 Local Interrupting Channel Register (LICR)
Register Name: LICR
Intel Hex Address: x’25
Register Description: Local Interrupting Channel
Default Value: C1:C0 contain channel number
Access: Byte Read/Write
Motorola Hex Address: x’26
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
C1
Bit 2
C0
Bit 1
X
Bit 0
X
X
X
X
X
These per-channel registers are initialized with each channel number. The locations are RAM registers
and can be used for any purpose.
Bits 7:4
Bits 3:2
User-defined
Defines the interrupting channel number
C1 C0
Channel Number
0
0
1
1
0
1
0
1
Channel 0
Channel 1
Channel 2
Channel 3
Bits 1:0
User-defined
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.1.5 Interrupt Stack Register (STK)
Register Name: STK
Intel Hex Address: x’E0
Register Description: Interrupt Stack
Default Value: x’00
Motorola Hex Address: x’E2
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
CLvl [1]
MLvl [1]
TLvl [1]
TLvl [0]
MLvl [0]
CLvl [0]
This register is a 4-bit-deep by 2-bit-wide stack that contains the internal interrupt nesting history. The
stack is pushed from bits 7 and 0 toward the center during an interrupt acknowledge cycle, and popped
from the center during a write to an end of interrupt register.
Bits 7, 0
CLvl [1:0]
CLvl [1]
These bits provide the currently active interrupt level.
CLvl [0]
0
0
0
1
No interrupt active; CAR provides the current channel number
Currently in a modem interrupt service, MIR provides the
current channel number.
1
1
0
1
Currently in a transmit interrupt service, TIR provides the
current channel number.
Currently in a receive interrupt service, RIR provides the
current channel number.
Bits 6, 1
Bits 5, 2
MLvl [1:0]
TLvl [1:0]
These bits hold a previously active interrupt now nested.
These bits hold the oldest interrupt now nested 2 bits deep.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2 Receive Interrupt Registers
6.5.2.1 Receive Priority Interrupt Level Register (RPILR)
Register Name: RPILR
Intel Hex Address: x’E3
Register Description: Receive Priority Interrupt Match
Default Value: x’00
Motorola Hex Address: x’E1
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-assigned priority match value
This register must be initialized by the host to contain the codes that are presented on the address bus
by the host system to indicate which of the three CL-CD2431 interrupt types (modem, transmit, or receive)
is being acknowledged when IACKIN* is asserted.The CL-CD2431 compares bits 0–6 in this register with
A[0–6] to determine if the acknowledge level is correct.The value programmed in the MSB of the register
has no effect on the IACK cycle.
RPILR must contain the code used to acknowledge receive interrupts.
NOTE: Bit 7 of this register always reads back as ‘0’. When each of the three Priority Interrupt Level registers is
programmed with the same value, they are internally prioritized, with receive as the highest priority, followed
by transmit and modem.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.2 Receive Interrupt Register (RIR)
Register Name: RIR
Intel Hex Address: x’EF
Register Description: Receive Interrupt
Default Value: x’00
Motorola Hex Address: x’ED
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Reoi
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Ren
Ract
Rvct [1]
Rvct [0]
Rcn [1]
Rcn [0]
Bit 7
Bit 6
Receive Enable
This bit is set by the CL-CD2431 to initiate a receive interrupt request sequence. It is cleared
during a valid receive interrupt acknowledge cycle.
Receive Active
This bit is set automatically when Ren is set, and the Fair Share logic allows the assertion of
a receive interrupt request. It is cleared when the host CPU writes to the Receive End of
Interrupt register.
Bit 5
Receive End of Interrupt
This bit is set automatically when the host CPU writes to the Receive End of Interrupt register
while in a receive interrupt routine.
Ren
Ract
Reoi
Sequence of Events
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
Idle.
Receive interrupt requested, but not asserted.
Receive interrupt asserted.
Receive interrupt acknowledged.
Receive interrupt service routine completed.
Bit 4
Reserved – always returns ‘0’ when read.
Receive Vector [1:0]
Bits 3:2
These bits are set by the CL-CD2431 to provide the lower two bits of the vector supplied to
the host CPU during an interrupt acknowledge cycle.
The receive good data vector is decoded as follows: Rvct [1] = 1, and Rvct [0] = 1. The
receive exception vector is decoded as follows: Rvct [1] = 0, and Rvct [0] = 0.
Bits 1:0
Receive Channel Number [1:0]
These bits are set by the CL-CD2431 to indicate the channel requiring receive interrupt ser-
vice.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.3 Receive Interrupt Status Register (RISR)
Register Name: RISR
Intel Hex Address: x’8A
Register Description: Receive Interrupt Status
Default Value: x’00
Motorola Hex Address: x’88
Access: Word Read only
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
RISR High
Bit 7
Bit 6
Bit 5
Bit 4
RISR Low
This register reports the status of the channel during the receive interrupt service. It is a 16-bit register,
with the lower byte displaying current receive character oriented status while the upper byte displays cur-
rent DMA interrupt status. The upper byte is not used if DMA mode is not active.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.3 Receive Interrupt Status Register (RISR) (cont.)
RISRl — HDLC Mode
Register Name: RISRl
Intel Hex Address: x’8A
Register Description: Receive Interrupt Status — low
Default Value: x’00
Motorola Hex Address: x’89
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
CRC
Bit 3
OE
Bit 2
Bit 1
0
Bit 0
0
EOF
RxAbt
Reslnd
ClrDct
If RxData in IER is set, these interrupts are enabled.
Bit 7
Bit 6
Reserved – always returns ‘0’ when read.
End of Frame
This bit indicates that a valid end of frame was received, and a data frame is essentially
complete.
Bit 5
Receive Abort
This bit indicates that an abort sequence terminating the frame was received.
Bit 4
Bit 3
CRC error on current frame.
Overrun Error
This bit indicates that new data has arrived, but the CL-CD2431 FIFO or holding registers
are full. The new data is lost, and the overrun indication is flagged on the last character
received before the overrun occurred. In HDLC and Bisync modes, the remainder of a frame,
following an overrun, is discarded.
Bit 2
Residual Indication
This bit indicates that the last character of the frame was a partial character.
Bit 1
Bit 0
Reserved – always returns ‘0’ when read.
Clear Detect
This bit indicates an X.21 data transfer phase clear signal has been detected.This is defined
as two consecutive all-zero receive characters with the CTS* pin high. Clear Detect mode is
enabled by COR1.
During an interrupt service routine, the host can use this register to provide a timer value as detailed in
the Receive End of Interrupt register.The host can only load one of the two timers in the interrupt service
routine.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.3 Receive Interrupt Status Register (RISR) (cont.)
RISRl — Asynchronous Mode
Register Name: RISRl
Intel Hex Address: x’8A
Register Description: Receive Interrupt Status — Low
Default Value: x’00
Motorola Hex Address: x’89
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
OE
Bit 2
PE
Bit 1
FE
Bit 0
Timeout
SCdet2
SCdet1
SCdet0
Break
If RxData in IER is set, these interrupts are enabled.
Bit 7
Timeout
This bit indicates that the receive FIFO is empty, and no data has been received within the
receive timeout period. There is no data character associated with this status, and no other
status bits are valid if the timeout bit is set.
Bits 6:4
Special Character Detect
SCdet[2:0] Status
000
001
010
011
100
111
None detected
Special Character 1 matched
Special Character 2 matched
Special Character 3 matched (only if ESCDE is enabled in COR3)
Special Character 4 matched (only if ESCDE is enabled in COR3)
Character is within the inclusive range of the characters in the Special
Character Range low and high registers (only if RngDE is enabled in COR3).
Special character match can be enabled for error characters by COR7.
Bit 3
Overrun Error
This bit iindicates that new data has arrived, but the CL-CD2431 FIFO or holding registers
are full. The new data is lost and the overrun indication is flagged on the last character
received before the overrun occurred.
Bit 2
Bit 1
Bit 0
Parity Error
This bit indicates that a parity error has occurred.
Framing Error
This bit indicates that a bad Stop bit was detected.
Break
This bit iindicates that a break was detected.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.3 Receive Interrupt Status Register (RISR) (cont.)
RISRl — Async-HDLC / PPP / MNP 4 Mode
Register Name: RISRl
Intel Hex Address: x’8A
Register Description: Receive Interrupt Status — Low
Default Value: x’00
Motorola Hex Address: x’89
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
CRC
Bit 3
OE
Bit 2
FE
Bit 1
0
Bit 0
0
EOF
RxAbt
Break
If RxData in IER is set, these interrupts are enabled.
Bit 7
Bit 6
Reserved – always returns ‘0’ when read.
End of Frame
The EOF bit indicates that a valid end of frame (7E) character has been received, and the
7E was not preceded by a 7D.
Bit 5
Bit 4
Receive Abort
The RxAbt bit indicates that an abort sequence (7D–7E) has been received.
Receive CRC Error
(The terms CRC and FCS are used interchangeably in this document.)
The CRC bit indicates that a frame with a valid end of frame has been received, but the FCS
was not correct. CRC is set only if EOF is set.
Bit 3
Bit 2
Overrun Error
The OE bit indicates that the receiver buffer and FIFO have been overrun. At least one new
character has been received, but lost since there was no room available in the receiver buffer
and/or FIFO.
Framing Error
The FE bit indicates that a character has been received with an incorrect Stop bit. The stop
bit was ‘0’; it should have been ‘1’.
Bit 1
Bit 0
Reserved – always returns ‘0’ when read.
BREAK Detection
The Break bit indicates that a break has been received. A break is a continuous sequence
of at least ten ‘0’ bits.
NOTE: 0E, FE, and BREAK are cumulative over the entire packet in PPP mode. This means that the respective
error occurred somewhere in the packet, but did not cause an immediate interrupt.
The table below defines the encoding of RxABT and FE for an aborted receive frame:
RxABT
FE
0
Error
None
0
0
1
1
1
Not used
0
Received aboft sequence: x’7D, x”7E
Framing error caused a frame abort
1
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.3 Receive Interrupt Status Register (RISR) (cont.)
SLIP Mode
Register Name: RISRl
Intel Hex Address: x’8A
Register Description: Receive Interrupt Status — Low
Default Value: x’00
Motorola Hex Address: x’89
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
OE
Bit 2
FE
Bit 1
0
Bit 0
0
EOF
RxAbt
Break
If RxData in IER is set, these interrupts are enabled.
Bit 7
Bit 6
Reserved – always returns ‘0’ when read.
End of Frame
The EOF bit indicates that a valid end of frame (7E) character has been received, and the
7E was not preceded by a 7D.
Bit 5
Receive Abort
The RxAbt bit indicates that an abort sequence (7D–7E) has been received.
Bit 4
Bit 3
Reserved – always returns ‘0’ when read.
Overrun Error
The OE bit indicates that the receiver buffer and FIFO have been overrun. At least one new
character has been received, but lost since there was no room available in the receiver buffer
and/or FIFO.
Bit 2
Framing Error
The FE bit indicates that a character has been received with an incorrect Stop bit. The Stop
bit was ‘0’; it should have been ‘1’.
Bit 1
Bit 0
Reserved – always returns ‘0’ when read.
BREAK Detection
The Break bit indicates that a break has been received. A break is a continuous sequence
of at least ten ‘0’ bits.
NOTE: 0E, FE, and break are cumulative over the entire packet in PPP mode. This means that the respective error
occurred somewhere in the packet, but did not cause an immediate interrupt.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.4 Receive Interrupt Status Register — High (RISRh)
Register Name: RISRh
Intel Hex Address: x’8B
Register Description: Receive Interrupt Status — High
Default Value: x’00
Motorola Hex Address: x’88
Access: Byte Read only
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
Bit 2
0
Bit 1
0
Bit 0
0
Berr
EOF
BA/BB
This register is used in DMA mode only.
Bit 7
Bus Error (written by CL-CD2431)
0 = no bus error
1 = bus error was detected on the last transfer
The actual address at which the error occurred is available in the Receive Current Buffer
Address register. In response to a bus error status, the host has two possible options:
1) Retry from the next position in the buffer.
2) Terminate this buffer by setting TermBuff bit (REOIR[7]) and move onto the next.
Bit 6
Bit 5
End of Frame
Reception of a data frame is complete (Sync DMA mode only).
End of Buffer
The end of a receive buffer was reached (used only for DMA supported transmission). The
end of one of the host-supplied receive buffers was reached.
Bit 4
Bit 3
Reserved – always returns ‘0’ when read.
Status during buffer A or buffer B data transfer.
0 = buffer A
1 = buffer B
Bits 2:0
Reserved – always returns ‘0’ when read.
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.5 Receive FIFO Output Count Register (RFOC)
Register Name: RFOC
Intel Hex Address: x’33
Register Description: Receive FIFO Output Count
Default Value: x’00
Motorola Hex Address: x’30
Access: Byte Read only
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
RxCt4
RxCt3
RxCt2
RxCt1
RxCt0
Bits 7:5
Bits 4:0
Reserved – always returns ‘0’ when read.
Receive Data Count [4:0]
If the receive channel is interrupt driven, a non-zero value in this bit field is the number of
data characters available for transfer within the current receive interrupt.
6.5.2.6 Receive Data Register (RDR)
Register Name: RDR
Intel Hex Address: x’F8
Register Description: Receive Data
Default Value: x’00
Motorola Hex Address: x’F8
Access: Byte Read only
Bit 7
Bit 6
Bit 5
D5
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
D7
D6
This Virtual register accesses the receive data FIFO of a channel interrupting for receive data transfer.
This register address is used for all channels to transfer receive FIFO data to the host (if programmed in
Interrupt Transfer mode). Data must be read as bytes, and follows the rules listed in Section 6.3 for the
positioning of valid data on the bus. If the BYTESWAP pin is high, data is valid on A/D[7:0], if BYTESWAP
is low, data is valid on A/D[15:8]. This is true because the RDR is on an even address.
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.7 Receive End of Interrupt Register (REOIR)
Asynchronous and HDLC Modes
Register Name: REOIR
Intel Hex Address: x’87
Register Description: Receive End of Interrupt
Default Value: x’00
Motorola Hex Address: x’84
Access: Byte Write only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TermBuff
DiscExc
SetTm2
SetTm1
NoTrans
Gap2
Gap1
Gap0
The CL-CD2431 interprets values written to this register at the completion of all receive interrupts.
Bit 7
Terminate Current DMA Buffer
If this bit is set, the current receive buffer is terminated and data transfer is switched to the
other buffer. This bit should only be set in response to an Async Exception interrupt. If the
buffer is terminated in response to an exception character (that is, parity error) interrupt and
the discard exception character bit is not set, the exception character is written at the start of
the next buffer.
Before writing the terminate buffer command to REOIR, a new buffer descriptor can be
written to the current buffer.
Bit 6
Bit 5
Bit 4
Discard Exception Character (DMA mode only)
When this bit is set in response to an async exception interrupt, the exception character is
not transferred to memory.
Set General Timer 2 in Synchronous modes
0 = do not set general timer
1 = load the value, to general timer 2, provided in RISRl.
Set General Timer 1 in Synchronous modes
0 = do not set general timer 1
1 = load the value provided in RISRl to the high byte of general timer 1.
At the end of an interrupt service routine, the user can set a timer by setting a timer value in
the Receive Interrupt Status register. When the timer reaches ‘0’, the CL-CD2431 generates
a modem/timer group interrupt to the host.
Bit 3
No Transfer of Data
This bit must be set by the host, if no data is transferred from the receive FIFO during a
receive interrupt.
Bits 2:0
Gap2, Gap1, Gap0
These bits set the size of the optional gaps to be left in DMA buffer (starting at the current
location) before resuming data transfer. The CL-CD2431 moves forward its buffer address
pointer to the selected number of bytes. It does not write to any location ‘in the gap’. If the
gap is large enough to complete, or extend beyond the end of the current buffer, it is com-
plete, and the gap continues in the other receive buffer. If the discard exception character is
not selected, the character where the exception occurred is written to the buffer following the
gap.
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.2.7 Receive End of Interrupt Register (REOIR) (cont.)
Async-HDLC / PPP / SLIP / MNP 4 Mode
Register Name: REOIR
Intel Hex Address: x’87
Register Description: Receive End of Interrupt
Default Value: x’00
Motorola Hex Address: x’84
Access: Byte Write only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
0
TermBuff
DiscExc
SetTm2
SetTm1
NoTrans
The CL-CD2431 interprets values written to this register at the completion of all receive interrupts.
Bit 7
Terminate Current DMA Buffer
If this bit is set, the current receive buffer is terminated and data transfer is switched to the
other buffer. This bit should only be set in response to an async exception interrupt. If the
buffer is terminated in response to an exception character (that is, parity error) interrupt and
the discard exception character bit is not set, the exception character is written at the start of
the next buffer.
Before writing the terminate buffer command to REOIR, a new buffer descriptor can be writ-
ten to the current buffer.
Bit 6
Bit 5
Bit 4
Discard Exception Character (DMA mode only)
When this bit is set in response to an async exception interrupt, the exception character is
not transferred to memory.
Set General Timer 2 in Synchronous modes
0 = do not set general timer
1 = load the value, to general timer 2, provided in RISRl.
Set General Timer 1 in Synchronous modes
0 = do not set general timer 1
1 = load the value, to the high byte of general timer 1, provided in RISRl.
At the end of an interrupt service routine, the user can set a timer by setting a timer value in
the Receive Interrupt Status register. When the timer reaches ‘0’, the CL-CD2431 generates
a modem/timer group interrupt to the host.
Bit 3
No Transfer of Data
This bit must be set by the host, if no data is transferred from the receive FIFO during a
receive interrupt.
Bits 2:0
Reserved – always returns ‘0’ when read.
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.3 Transmit Interrupt Registers
6.5.3.1 Transmit Priority Interrupt Level Register (TPILR)
Register Name: TPILR
Intel Hex Address: x’E2
Register Description: Transmit Priority Interrupt Match
Default Value: x’00
Motorola Hex Address: x’E0
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-assigned priority match value
This register must be initialized by the host to contain the codes that are presented on the address bus
by the host system to indicate which of the three CL-CD2431 interrupt types (modem, transmit, or receive)
is being acknowledged when IACKIN* is asserted.The CL-CD2431 compares bits 0–6 in this register with
A[0–6] to determine if the acknowledge level is correct.The value programmed in the MSB of this register
has no effect on the IACK cycle.
The TPILR must contain the code used to acknowledge transmit interrupts.
NOTE: Bit 7 of this register is always read back as ‘0’. When each of the three Priority Interrupt Level registers are
programmed with the same value, they are internally prioritized, with receive as the highest priority, followed
by transmit and modem.
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.3.2 Transmit Interrupt Register (TIR)
Register Name: TIR
Intel Hex Address: x’EE
Register Description: Transmit Interrupt
Default Value: None, value varies
Access: Byte Read only
Motorola Hex Address: x’EC
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Ten
Tact
Teoi
Tvct [1]
Tvct [0]
Tcn [1]
Tcn [0]
Bit 7
Bit 6
Transmit Enable
This bit is set by the CL-CD2431 to initiate a transmit interrupt request sequence. It is cleared
during a valid transmit interrupt acknowledge cycle.
Transmit Active
This bit is set automatically when Ten is set, and the Fair Share logic allows the assertion of
a transmit interrupt request. It is cleared when the host CPU writes to the Transmit End of
Interrupt register.
Bit 5
Transmit End of Interrupt
This bit is set automatically when the host CPU writes to theTransmit End of Interrupt register
while in a transmit interrupt routine.
Ten
Tact
Teoi
Sequence of Events
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
Idle
Transmit interrupt requested, but not asserted
Transmit interrupt asserted
Transmit interrupt acknowledged
Transmit interrupt service routine completed
Bit 4
Reserved – always returns ‘0’ when read.
Transmit Vector [1:0]
Bits 3:2
These bits are set by the CL-CD2431 to provide the lower two bits of the vector supplied to
the host CPU during an interrupt acknowledge cycle. Transmit vector is decoded as follows:
Tvct [1] = 1, and Tvct [0] = 0.
Bit 1:0
Transmit Channel Number [1:0]
These bits are set by the CL-CD2431 to indicate the channel requiring transmit interrupt
service.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.3.3 Transmit Interrupt Status Register (TISR)
Register Name: TISR
Intel Hex Address: x’89
Register Description: Transmit Interrupt Status
Default Value: x’00
Motorola Hex Address: x’8A
Access: Byte Read only
Bit 7
Bit 6
Bit 5
EOB
Bit 4
UE
Bit 3
Bit 2
0
Bit 1
Bit 0
Berr
EOF
BA/BB
TxEmpty
TxDat
When the host receives a transmit interrupt, the following status is provided in this register:
Bit 7
Bus Error (written by the CL-CD2431)
0 = no bus error
1 = bus error detected on the last transfer
Bit 6
Transmit End of Frame Indication in DMA mode
This interrupt occurs when the final data character of a transmit frame is transferred to the
transmit FIFO.
Bit 5
Bit 4
Bit 3
Transmit End of Buffer Indication in DMA mode
Transmit underrun error (HDLC only), otherwise ‘0’ (Async, PPP, SLIP, and MNP 4).
BA/BB – Applicable buffer for the register interrupt
0 = transmit buffer A
1 = transmit buffer B
Bit 2
Bit 1
Reserved – always returns ‘0’ when read.
Transmitter Empty
All characters were completely transmitted, and the serial output is idle.
Bit 0
Transmit Data
This bit indicates that the number of characters in the FIFO is below the threshold.
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DATA BOOK v3.0
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Advanced Multi-Protocol Communications Controller
6.5.3.4 Transmit FIFO Transfer Count Register (TFTC)
Register Name: TFTC
Intel Hex Address: x’83
Register Description: Transmit FIFO Transfer Count
Default Value: x’00
Motorola Hex Address: x’80
Access: Byte Read only
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
TxCt4
TxCt3
TxCt2
TxCt1
TxCt0
Bits 7:5
Bits 4:0
Reserved – always returns ‘0’ when read.
Transmit Data Count [4:0]
If the Transmit channel is interrupt driven, a non-zero value is a request for data. These bits
give the number of spaces available in the transmit FIFO.
6.5.3.5 Transmit Data Register (TDR)
Register Name: TDR
Intel Hex Address: x’F8
Register Description: Transmit Data
Default Value: x’00
Motorola Hex Address: x’F8
Access: Byte Write only
Bit 7
Bit 6
Bit 5
D5
Bit 4
D4
Bit 3
D3
Bit 2
D2
Bit 1
D1
Bit 0
D0
D7
D6
This register accesses the transmit data FIFO of a channel, interrupting for transmit data transfer. This
register address is used for all channels to transfer transmit FIFO data to the host, if programmed in In-
terrupt Transfer mode. Data must be written as bytes, and follows the rules listed in Section 5.4 for posi-
tioning valid data on the bus. If the BYTESWAP pin is high, data must be valid on A/D[7:0]; if BYTESWAP
is low, data must be valid on A/D[15:8] because the TDR is on an even address.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.3.6 Transmit End of Interrupt Register (TEOIR)
Register Name: TEOIR
Intel Hex Address: x’86
Register Description: Transmit End of Interrupt
Default Value: x’00
Motorola Hex Address: x’85
Access: Byte Write only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0
Bit 1
0
Bit 0
0
TermBuff
EOF
SetTm2
SetTm1
Notrans
The Transmit End of Interrupt register must be written to by the corresponding host interrupt service rou-
tine to signal to the CL-CD2431 that the current interrupt service is concluded. This must be the last ac-
cess to the CL-CD2431 during an interrupt service routine. Writing to this register generates an internal
end of interrupt signal which pops the CL-CD2431 interrupt context stack.
Depending on the circumstances of an individual interrupt service, the host can be required to pass a pa-
rameter to the CL-CD2431 through these registers.
Bit 7
1 = Terminate buffer in DMA mode forces the current buffer to be discarded.
NOTE: If current interrupt is a transmit end-of-buffer interrupt, setting this bit at the end of the service
routine causes the next buffer to be terminated also.
Bit 6
Bit 5
Bit 4
End of Frame in Synchronous modes using interrupt-driven data transfer
0 = this data transfer does not complete the frame/block.
1 = this data transfer does complete the frame/block.
Set General Timer 2 in Synchronous modes
0 = do not set general timer 2.
1 = load the value, provided in TISR, to general timer 2.
Set general timer 1 in Synchronous modes
0 = do not set general timer 1.
1 = load the value, provided in TISR, to the high byte of general timer 1.
At the end of an interrupt service routine, the user can set a timer by setting a timer value in
the Transmit Interrupt Status register.When the timer reaches ‘0’, the CL-CD2431 generates
a modem/timer group interrupt to the host.
Bit 3
No Transfer of Data
This bit must be set by the host if no data is transferred to the transmit FIFO during a data
transfer interrupt.
Bits 2:0
Reserved – must be ‘0’.
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DATA BOOK v3.0
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Advanced Multi-Protocol Communications Controller
6.5.4 Modem Interrupt Registers
6.5.4.1 Modem Priority Interrupt Level Register (MPILR)
Register Name: MPILR
Intel Hex Address: x’E1
Register Description: Modem Priority Interrupt Match
Default Value: x’00
Motorola Hex Address: x’E3
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
User-assigned priority match value
This register must be initialized by the host to contain the codes that are presented on the address bus
by the host system to indicate which of the three CL-CD2431 interrupt types (modem, transmit, or receive)
is being acknowledged when IACKIN* is asserted.The CL-CD2431 compares bits 0–6 in this register with
A[6:0] to determine if the acknowledge level is correct. The value programmed in the MSB of the register
has no effect on the IACK cycle.
The MPILR must contain the code used to acknowledge modem/timer interrupts.
NOTE: Bit 7 of this register always reads back as ‘0’. When each of the three Priority Interrupt Level registers is
programmed with the same value, they are internally prioritized, with receive as the highest priority, followed
by transmit and modem.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.4.2 Modem Interrupt Register (MIR)
Register Name: MIR
Intel Hex Address: x’ED
Register Description: Modem Interrupt
Default Value: x’00
Motorola Hex Address: x’EF
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Meo
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
Men
Mact
Mvct [1]
Mvct [0]
Mcn [1]
Mcn [0]
Bit 7
Bit 6
Modem Enable
This bit is set by the CL-CD2431 to initiate a modem interrupt request sequence. It is cleared
during a valid modem interrupt acknowledge cycle.
Modem Active
This bit is set automatically when Mer is set, and the Fair Share logic allows the assertion of
a modem interrupt request. This bit is cleared when the host CPU writes to the Modem End
of Interrupt register.
Bit 5
Modem End of Interrupt
This bit is set automatically when the host CPU writes to the Modem End of Interrupt register
while in a modem interrupt routine.
Mer
Mact
Meo
Sequence of Events
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
Idle
Modem interrupt requested, but not asserted
Modem interrupt asserted
Modem interrupt acknowledged
Modem interrupt service routine completed
Bit 4
Reserved – always returns ‘0’ when read.
Modem Vector [1:0]
Bits 3:2
These bits are set by the CL-CD2431 to provide the lower two bits of the vector supplied to
the host CPU during an interrupt acknowledge cycle. Modem vector is decoded as follows:
Mvct [1] = 0, and Mvct [0] = 1.
Bit 1:0
Modem Channel Number [1:0]
These bits are set by the CL-CD2431 to indicate the channel requiring modem interrupt
service.
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Advanced Multi-Protocol Communications Controller
6.5.4.3 Modem (/Timer) Interrupt Status Register (MISR)
Register Name: MISR
Intel Hex Address: x’88
Register Description: Modem Interrupt Status
Default Value: x’00
Motorola Hex Address: x’8B
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
DSRChg
CDChg
CTSChg
Timer2
Timer1
When the host receives a modem interrupt, the following status is provided in this register:
Bit 7
Bit 6
Bit 5
DSR Changed
1 = a change was detected on the DSR* input. The change detect is programmed in COR4
and COR5.
CD Changed
1 = a change was detected on the CD* input. The change detect is programmed in COR4
and COR5.
CTS Changed
1 = a change was detected on the CTS* input. The change detect is programmed in COR4
and COR5.
Bits 4:2
Bit 1
Unused; returns ‘0’ when read.
General Timer 2 Timed Out
The count reached ‘0’ before being reset or disabled.
Bit 0
General Timer 1 Timed Out
The count reached ‘0’ before being reset or disabled.
During an interrupt service routine, the host can use this register to provide a binary timer value to one of
the timers (Sync modes only), as detailed in the Modem End of Interrupt register. The host can only load
one of the two timers in each interrupt service routine.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
6.5.4.4 Modem End of Interrupt Register (MEOIR)
Register Name: MEOIR
Intel Hex Address: x’85
Register Description: Modem End of Interrupt
Default Value: x’00
Motorola Hex Address: x’86
Access: Byte Write only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
0
0
SetTm2
SetTm1
Bits 7:6
Bit 5
Reserved – always returns ‘0’ when read.
Set General Timer 2 (Synchronous modes)
0 = do not set general timer 2.
1 = load the value, provided in MISR, to general timer 2.
Bit 4
Set General Timer 1 (Synchronous modes)
0 = do not set general timer 1.
1 = load the value, provided in MISR, to the high byte of general timer 1.
At the end of an interrupt service routine, the user can set the timer by setting a timer value
in the Modem Interrupt Status register. When the timer reaches ‘0’, the CL-CD2431
generates a modem/timer group interrupt to the host.
Bits 3:0
Reserved – always returns ‘0’ when read.
148
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DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6 DMA Registers
6.6.0.1 DMA Mode Register (DMR)
Register Name: DMR
Intel Hex Address: x’F4
Register Description: DMA Mode
Default Value: x’00
Motorola Hex Address: x’F6
Access: Byte Write only
Bit 7
Bit 6
Bit 5
0
Bit 4
0
Bit 3
Bit 2
0
Bit 1
0
Bit 0
0
EnSync
0
ByteDMA
This register is write only. No misoperation occurs if the register is read, but the read value is not consis-
tent.
Bits 7
Internal DTACK* Synchronization Enable
If external synchronization of DTACK* with BUSCLK is not provided, an internal synchroni-
zation can be enabled by setting this bit (Revision D and later).
Bits 6:4
Bit 3
Reserved – always returns ‘0’ when read.
Byte DMA
0 = The CL-CD2431 attempts to perform 16-bit data transfers whenever possible, and 8-bit
data transfers only when necessary (when only one byte is available or there are odd
address boundaries).
1 = The CL-CD2431 always performs 8-bit DMA transfers, the position of the data on the bus
still follows the normal rules relating to the BYTESWAP pin.
Bits 2:0
Reserved – always returns ‘0’ when read.
6.6.0.2 Bus Error Retry Count (BERCNT)
Register Name: BERCNT
Intel Hex Address: x’8D
Register Description: Bus Error Retry Count
Default Value: x’00
Motorola Hex Address: x’8E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
When this register is programmed to ‘0’, any bus error causes a receive/transmit interrupt to be generated
and DMA operations suspended to the buffer in error, until the interrupt is processed by the host CPU.
When this register contains a non-zero value and a bus error occurs, the CL-CD2431 retries the same
DMA operation and decrements the register value by one. When the value reaches zero, the next bus
error causes an interrupt, at that time a new count can be loaded by the host CPU.
August 1996
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.0.3 DMA Buffer Status Register (DMABSTS)
Register Name: DMABSTS
Register Description: DMA Buffer Status
Default Value: x’00
Intel Hex Address: x’1A
Motorola Hex Address: x’19
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDAlign
RstApd
CrtBuf
Append
Ntbuf
Tbusy
Nrbuf
Rbusy
When the CL-CD2431 requires an external buffer for DMA transfers, it checks Ntbuf/Nrbuf bits to decide
which buffer to use. Once the CL-CD2431 starts using the buffer, it toggles Ntbuf/Nrbuf bits, and sets
Tbusy/Rbusy bits. At system initialization, Ntbuf and Nrbuf bits are set to buffer A.
Bit 7
Transmit Data Align
This status bit is used internally to manage data alignment in the transmit FIFO.
Bit 6
Reset Append Mode
This bit is set after the terminate append buffer command in STCR is recognized, and is
cleared after the remaining data is flushed from the buffer.
Bit 5
Bit 4
Current Transmit Buffer
This bit is used internally to mark the actual buffer in use.
Append (only buffer A can be used as an append buffer)
This bit is the transmit append buffer usage indicator.
0 = append buffer is not in use.
1 = append buffer is in use.
Bit 3
Next Transmit Buffer
0 = buffer A is the next transmit buffer.
1 = buffer B is the next transmit buffer.
This bit is toggled when transmission starts from a buffer (that is, when data is first read from
buffer A). This bit is set to indicate that buffer B is next.
Bit 2
Bit 1
Current Transmit Buffer Busy
0 = No buffer is in use.
1 = Current transmit buffer is in use.
Next Receive Buffer
0 = buffer A is the next receive buffer.
1 = buffer B is the next receive buffer.
This bit is toggled when receive data is first written to a buffer (that is, when data is first writ-
ten to buffer A). This bit is set to indicate that buffer B is next.
Bit 0
Current Receive Buffer Busy
0 = No buffer is in use.
1 = Current receive buffer is in use.
150
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.1 DMA Receive Registers
6.6.1.1 A Receive Buffer Address Lower (ARBADRL)
Register Name: ARBADRL
Intel Hex Address: x’40
Register Description: Receive Buffer ‘A’ 32-bit Address, lower word
Default Value: x’0000
Motorola Hex Address: x’42
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 15:8
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
6.6.1.2 A Receive Buffer Address Upper (ARBADRU)
Register Name: ARBADRU
Intel Hex Address: x’42
Register Description: Receive Buffer ‘A’ 32-bit Address, upper word
Default Value: x’0000
Motorola Hex Address: x’40
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 23:16
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 31:24
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
August 1996
151
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.1.3 B Receive Buffer Address Lower (BRBADRL)
Register Name: BRBADRL
Intel Hex Address: x’44
Register Description: Receive Buffer ‘B’ 32-bit Address, lower word
Default Value: x’0000
Motorola Hex Address: x’46
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 15:8
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
6.6.1.4 B Receive Buffer Address Upper (BRBADRU)
Register Name: BRBADRU
Intel Hex Address: x’46
Register Description: Receive Buffer ‘B’ 32-bit Address, upper word
Default Value: x’0000
Motorola Hex Address: x’44
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 23:16
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 31:24
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
This register contains the start addresses of two external buffers that are used by the CL-CD2431 to store
the next two receive data blocks. This register is written to by the host and copied internally to control the
data transfer to the memory.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.1.5 A Buffer Receive Byte Count Register (ARBCNT)
Register Name: ARBCNT
Intel Hex Address: x’48
Register Description: Receive Buffer ‘A’ Byte Count
Default Value: x’0000
Motorola Hex Address: x’4A
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Binary count value, 16-bit count, bits 15:8
Bit 4 Bit 3
Binary count value, 16-bit count, bits 7:0
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
Bit 5
6.6.1.6 B Buffer Receive Byte Count Register (BRBCNT)
Register Name: BRBCNT
Intel Hex Address: x’4A
Register Description: Receive Buffer ‘B’ Byte Count
Default Value: x’0000
Motorola Hex Address: x’48
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Binary count value, 16-bit count, bits 15:8
Bit 4 Bit 3
Binary count value, 16-bit count, bits 7:0
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
Bit 5
These registers contain the number of bytes stored in the external data buffers by the CL-CD2431. The
count is updated after a block of data is moved to memory and the buffer is terminated. As initially written
by the host, the register contains the number of bytes that the buffer can hold.
August 1996
153
DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.1.7 A Receive Buffer Status Register (ARBSTS)
Register Name: ARBSTS
Intel Hex Address: x’4C
Register Description: Receive Buffer ‘A’ Status
Default Value: x’00
Motorola Hex Address: x’4F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
Berr
EOF
2431own
6.6.1.8 B Receive Buffer Status Register (BRBSTS)
Register Name: BRBSTS
Intel Hex Address: x’4D
Register Description: Receive Buffer ‘B’ Status
Default Value: x’00
Motorola Hex Address: x’4E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
Berr
EOF
2431own
These registers contain the current status of associated receive buffers and enable the buffers to be
passed between the host and CL-CD2431. Status bits are defined as follows:
Bit 7
Bit 6
Bit 5
Bus Error (set by the CL-CD2431 and cleared by the host CPU)
0 = no bus error
1 = bus error occurred on the last transfer; the suspect address is available in RCBADR.
End of Frame (set by the CL-CD2431 and cleared by the host CPU)
0 = this buffer does not terminate a frame.
1 = this buffer terminates a frame.
Buffer Complete (set by the CL-CD2431 and cleared by the host CPU)
0 = buffer not complete.
1 = buffer complete.
Bits 4:1
Bit 0
Reserved – must be ‘0’.
Ownership of the Transfer Buffer (set by the host CPU and cleared by the CL-CD2431)
0 = buffer not free to be used by CL-CD2431.
1 = buffer free to be used by CL-CD2431.
When the Buffer Complete bit is set by the CL-CD2431, the buffer is free for the host to process. (RBCNT
information is updated to the number of bytes available in the buffer, and a new buffer can be allocated.)
154
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.1.9 Receive Current Buffer Address — Lower (RCBADRL)
Register Name: RCBADRL
Intel Hex Address: x’3C
Register Description: Current Receive Buffer Address, lower word
Default Value: x’0000
Motorola Hex Address: x’3E
Access: Word Read Only
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 15:8
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
6.6.1.10 Receive Current Buffer Address — Upper (RCBADRU)
Register Name: RCBADRU
Intel Hex Address: x’3E
Register Description: Current Receive Buffer Address, upper word
Default Value: x’0000
Motorola Hex Address: x’3C
Access: Word Read Only
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 31:24
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 23:16
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
These registers contain the address of the current DMA buffer being used for receive data, updated at the
end of receive data transfers.These registers are only for the CL-CD2431 to use for managing DMA trans-
fers. In Asynchronous mode, the host can read this register during a receive exception interrupt to deter-
mine how much data is in the buffer. The address is the location of the next character to be transferred to
the buffer. The host needs this information to process newly arrived data in the buffer if used in Append
mode, and the data timeout has occurred. The address is also needed if an exception has occurred, and
a gap is to be left in the DMA buffer (see the description of the Gap[x] bits in Section 6.5.2.7 on page 138
for the insertion of status information by the host. For a bus error during receive data transfer, this register
provides the start address of the transfer causing the bus error.
August 1996
155
DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2 DMA Transmit Registers
6.6.2.1 A Transmit Buffer Address Lower (ATBADRL)
Register Name: ATBADRL
Intel Hex Address: x’50
Register Description: Transmit Buffer A 32-bit Address, lower word
Default Value: x’0000
Motorola Hex Address: x’52
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 15:8
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
6.6.2.2 A Transmit Buffer Address Upper (ATBADRU)
Register Name: ATBADRU
Intel Hex Address: x’52
Register Description: Transmit Buffer A 32-bit Address, upper word
Default Value: x’0000
Motorola Hex Address: x’50
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 23:16
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 31:24
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
156
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.3 B Transmit Buffer Address Register — Lower (BTBADRL)
Register Name: BTBADRL
Intel Hex Address: x’54
Register Description: Transmit Buffer B 32-bit Address, lower word
Default Value: x’0000
Motorola Hex Address: x’56
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 15:8
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
6.6.2.4 B Transmit Buffer Address Register — Upper (BTBADRU)
Register Name: BTBADRU
Intel Hex Address: x’56
Register Description: Transmit Buffer B 32-bit Address, upper word
Default Value: x’0000
Motorola Hex Address: x’54
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 23:16
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 31:24
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
This register contains the start addresses of two external buffers that are used by the CL-CD2431 to trans-
mit the next data blocks. This is written to by the host and copied internally to control the data transfer
from the memory to the CL-CD2431 FIFO.
August 1996
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DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.5 A Buffer Transmit Byte Count Register (ATBCNT)
Register Name: ATBCNT
Intel Hex Address: x’58
Register Description: Transmit Buffer A Byte Count
Default Value: x’0000
Motorola Hex Address: x’5A
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Binary count value, 16-bit count, bits 15:8
Bit 4 Bit 3
Binary count value, 16-bit count, bits 7:0
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
Bit 5
6.6.2.6 B Buffer Transmit Byte Count Register (BTBCNT)
Register Name: BTBCNT
Intel Hex Address: x’5A
Register Description: Transmit Buffer B Byte Count
Default Value: x’0000
Motorola Hex Address: x’58
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Binary count value, 16-bit count, bits 15:8
Bit 4 Bit 3
Binary count value, 16-bit count, bits 7:0
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
Bit 5
These registers contain the count of the bytes in the buffers to be transmitted.
158
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.7 A Transmit Buffer Status Register (ATBSTS) — Async-HDLC/PPP Mode
Register Name: ATBSTS
Register Description: Transmit Buffer ‘A’ Status
Default Value: x’00
Intel Hex Address: x’5C
Motorola Hex Address: x’5F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
Berr
EOF
map32
INTR
2431own
B Transmit Buffer Status Register (BTBSTS) — Async-HDLC/PPP Mode
Register Name: BTBSTS
Intel Hex Address: x’5D
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Motorola Hex Address: x’5E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
0
Bit 2
Bit 1
Bit 0
Berr
EOF
map32
INTR
2431own
Bit 7
Bit 6
Bit 5
Bus Error (set by the CL-CD2431, and cleared by the host)
0 = No bus error
1 = Bus error was detected on the last transfer
End of Frame (set and cleared by the host)
0 = This buffer is not the last in frame/block.
1 = This buffer is the last in frame/block.
End of a Transmit Buffer (set by the CL-CD2431, and cleared by the host).
The end of a host supplied transmit buffer has been reached.
Bits 4:3
Bit 2
Reserved – must be ‘0’.
map32 – Map all transmit characters from 00–1F (set and cleared by the host)
0 = Use the normal TXACCM map.
1 = Map all characters in the range from 00–1F.
Bit 1
Bit 0
Interrupt
0 = No interrupt required after the buffer is transmitted.
1 = Interrupt required after the buffer is transmitted.
2431own – Ownership of the transmit buffer (set by the host and cleared by the CL-CD2431)
0 = Buffer is owned by the host, and not ready for use by the CL-CD2431.
1 = Buffer is owned by the CL-CD2431, and is ready for use by the CL-CD2431.
To start transmission of a buffer, the host must set the A/BTBADR (Transmit Buffer Address) and
A/BTBCNT (Transmit Buffer Count) registers, and then set the 2431own bit. If the CL-CD2431 is to
generate and send the CRC for the frame, the FCSApd bit (COR2[6]) must be set. If the buffer contains
the end of a frame, the EOF bit must also be set. When the buffer has been sent, the EOB bit is set by
the CL-CD2431, and 2431OWN is reset, allowing a new buffer to be allocated.
(cont.)
August 1996
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.7 Transmit Buffer Status Register (A/BTBSTS) (cont.)
Setting the Append bit allows data to be added to the buffer after transmission begins. In this mode, the
host sets ATADR and ATCNT as normal, but when new data is appended to the buffer, the A/BTBCNT
(Transmit Buffer Count) can be updated.When the A buffer is used in Append mode, the CL-CD2431 does
not set the EOB bit. When the host completes use of the buffer, it must issue the append complete com-
mand through STCR. The CL-CD2431, upon transmitting the last characters from the buffer, sets EOB,
thus allowing the host to allocate a new transmit buffer.
160
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.8 A Transmit Buffer Status Register (ATBSTS) — SLIP/MNP 4 Mode
Register Name: ATBSTS
Intel Hex Address: x’5C
Register Description: Transmit Buffer ‘A’ Status
Default Value: x’00
Motorola Hex Address: x’5F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
UE
Bit 3
0
Bit 2
0
Bit 1
Bit 0
Berr
EOF
INTR
2431own
6.6.2.9 B Transmit Buffer Status Register (BTBSTS) — SLIP/MNP 4 Mode
Register Name: BTBSTS
Intel Hex Address: x’5D
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Motorola Hex Address: x’5E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
UE
Bit 3
0
Bit 2
0
Bit 1
Bit 0
Berr
EOF
INTR
2431own
Bit 7
Bit 6
Bus Error (set by the CL-CD2431, and cleared by the host)
0 = no bus error.
1 = bus error was detected on the last transfer.
End of Frame (set and cleared by the host)
0 = this buffer is not the last in frame/block.
1 = this buffer is the last in frame/block.
Bit 5
Bit 4
End of a Transmit Buffer (set by the CL-CD2431 and cleared by the host)
The end of a host supplied transmit buffer was reached.
Transmit underrun occurred as the buffer was not available, and it applies to this buffer.
Reserved – must be ‘0’.
Bits 3:2
Bit 1
Interrupt
0 = no interrupt required after the buffer is transmitted.
1 = interrupt required after the buffer is transmitted.
Bit 0
2431own – Ownership of the transmit buffer (set by the host and cleared by the CL-CD2431)
0 = buffer is owned by the host, and not ready for use by the CL-CD2431.
1 = buffer is owned by the CL-CD2431, and is ready for use by the CL-CD2431.
August 1996
161
DATA BOOK v3.0
DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.10 A Transmit Buffer Status Register (ATBSTS) — HDLC Mode
Register Name: ATBSTS
Intel Hex Address: x’5C
Register Description: Transmit Buffer ‘A’ Status
Default Value: x’00
Motorola Hex Address: x’5F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
UE
Bit 3
0
Bit 2
0
Bit 1
Bit 0
Berr
EOF
INTR
2431own
6.6.2.11 B Transmit Buffer Status Register (BTBSTS) — Async and HDLC Mode
Register Name: BTBSTS
Intel Hex Address: x’5D
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Motorola Hex Address: x’5E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
UE
Bit 3
0
Bit 2
0
Bit 1
Bit 0
Berr
EOF
INTR
2431own
This register contains the status of the associated transmit buffer, and it enables successive buffers to be
passed between the host and the CL-CD2431. Status bits within the register are defined as:
Bit 7
Bit 6
Bit 5
Bit 4
Bus Error (set by the CL-CD2431 and cleared by the host CPU)
0 = No bus error.
1 = Bus error occurred on the last transfer; the suspect address is available in TCBADR.
End of Frame (set and cleared by host CPU)
0 = This buffer is not the last in frame/block.
1 = This buffer is the last in frame/block.
End of a Transmit Buffer has been reached.
This bit is used only for DMA supported transfer.The end of one of the host supplied transmit
buffers has been reached. This bit is set by the CL-CD2431 and cleared by the host CPU.
Underrun
Transmit underrun occurred as the buffer was not available, and it applies to this buffer (only
in HDLC mode).
Bits 3:2
Bit 1
Reserved – must be ‘0’.
Interrupt
0 = No interrupt required after the buffer is sent.
1 = Interrupt required after the buffer is sent.
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CL-CD2431)
0 = Buffer not ready to be used by CL-CD2431.
1 = Buffer is ready for CL-CD2431 to transmit.
162
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.12 A Transmit Buffer Status Register (ATBSTS) — Async Mode
Register Name: ATBSTS
Intel Hex Address: x’5C
Register Description: Transmit Buffer ‘A’ Status
Default Value: x’00
Motorola Hex Address: x’5F
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
Bit 2
0
Bit 1
Bit 0
Berr
EOF
Append
INTR
2431own
6.6.2.13 B Transmit Buffer Status Register (BTBSTS) — Async and HDLC Mode
Register Name: BTBSTS
Intel Hex Address: x’5D
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Motorola Hex Address: x’5E
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
EOB
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
Bit 0
Berr
EOF
INTR
2431own
This register contains the status of the associated transmit buffer, and it enables successive buffers to be
passed between the host and the CL-CD2431. Status bits within the register are defined as:
Bit 7
Bit 6
Bit 5
Bus Error (set by the CL-CD2431 and cleared by the host CPU)
0 = no bus error.
1 = bus error occurred on the last transfer; the suspect address is available in TCBADR.
End of Frame (set and cleared by host CPU)
0 = this buffer is not the last in frame/block.
1 = this buffer is the last in frame/block.
End of a Transmit Buffer has been reached.This bit is used only for DMA supported transfer.
The end of one of the host-supplied transmit buffers has been reached. This bit is set by the
CL-CD2431 and cleared by the host CPU.
Bit 4
Bit 3
Reserved – must be ‘0’.
Append (only buffer A)
0 = no data appended to the buffer
1 = data may be appended to the buffer after transfer starts.
Bit 2
Bit 1
Reserved – must be ‘0’.
Interrupt
0 = no interrupt required after the buffer is sent.
1 = interrupt required after the buffer is sent.
Bit 0
Ownership of the transfer buffer (set by the host CPU and cleared by the CL-CD2431)
0 = buffer not ready to be used by CL-CD2431.
1 = buffer is ready for CL-CD2431 to transmit.
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.6.2.14 Transmit Current Buffer Address — Lower (TCBADRL)
Register Name: TCBADRL
Intel Hex Address: x’38
Register Description: Current Transmit Buffer Address, lower word
Default Value: x’0000
Motorola Hex Address: x’3A
Access: Word Read Only
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 15:8
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
6.6.2.15 Transmit Current Buffer Address — Upper (TCBADRU)
Register Name: TCBADRU
Intel Hex Address: x’3A
Register Description: Current Transmit Buffer Address, upper word
Default Value: x’0000
Motorola Hex Address: x’38
Access: Word Read Only
Bit 15
Bit 14
Bit 13
Binary address value, 32-bit address, bits 31:24
Bit 5 Bit 4 Bit 3 Bit 2
Binary address value, 32-bit address, bits 23:16
Bit 12
Bit 11
Bit 10
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
This register contains the address of the current DMA buffer being used for transmit data, updated at the
end of transmit data transfers. For bus errors during transmit data transfers, this register contains the start
address of the transfer causing the bus error.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.7 Timer Registers
6.7.1 Timer Period Register (TPR)
Register Name: TPR
Intel Hex Address: x’D8
Register Description: Timer Period
Default Value: x’FF
Motorola Hex Address: x’DA
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
This register provides the initialization value for the timer prescaler that is itself clocked by a prescaled
clock equal to system clock ÷ 2048. The timer prescaler establishes the clock for the various on-chip tim-
ers (including RTPR, TTR, and the general timers available to the host in the Synchronous modes). The
minimum value loaded in this register to maintain accuracy in the timer is 0A hex.
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.7.2 Receive Timeout Period Register (RTPR) Async Mode Only
Register Name: RTPR
Intel Hex Address: x’26
Register Description: Receive Timeout Period, 16-bit
Default Value: x’0000
Motorola Hex Address: x’24
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Binary value, bits 15:8
Bit 4 Bit 3
Binary value, bits 7:0
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
Bit 5
6.7.2.1 Receive Timeout Period Register — Low (RTPRl) Async Mode Only
Register Name: RTPRl
Intel Hex Address: x’26
Register Description: Receive Timeout Period, low byte
Default Value: x’00
Motorola Hex Address: x’25
Access: Byte Read/Write, ASYNC Mode only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
6.7.2.2 Receive Timeout Period Register — High (RTPRh) Async Mode Only
Register Name: RTPRh
Register Description: Receive Timeout Period, high byte
Default Value: x’00
Intel Hex Address: x’27
Motorola Hex Address: x’24
Access: Byte Read/Write, ASYNC Mode only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
This value sets the receive data timeout period. As each character is moved to the receive FIFO or the
last data is transferred from the FIFO to the host, the receive timer (an internal timer) is reloaded with the
Receive Timeout Period register.The receive timer is decremented on each ‘tick’ of the prescaler counter,
whose period is controlled by TPR. If the receive timer reaches ‘0’, it causes a receive data interrupt.
166
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.7.3 General Timer 1 (GT1) Sync Modes Only
Register Name: GT1
Intel Hex Address: x’28
Register Description: General Timer 1
Default Value: x’00
Motorola Hex Address: x’2A
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 12
Binary value, bits 15:8
Bit 4 Bit 3
Binary value, bits 7:0
Bit 11
Bit 10
Bit 2
Bit 9
Bit 1
Bit 8
Bit 0
Bit 7
Bit 6
Bit 5
6.7.3.1 General Timer 1— Low (GT1l) Sync Modes Only
Register Name: GT1l
Intel Hex Address: x’28
Register Description: General Timer 1, low byte
Default Value: x’00
Motorola Hex Address: x’2B
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
6.7.3.2 General Timer 1— High (GT1h) Sync Modes Only
Register Name: GT1h
Intel Hex Address: x’29
Register Description: General Timer 1, high byte
Default Value: x’00
Motorola Hex Address: x’2A
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
This 16-bit timer can be started by the user whenever it is inactive by writing a 16-bit timeout value to the
register. When non-zero, it decrements on each prescaler clock ‘tick’. When it reaches ‘0’, a modem/timer
group interrupt is generated to the host. The timer can be disabled by the Channel Command register.
During an interrupt, the user can reload a running timer (high byte only) by providing a reload value in the
Interrupt Status register and a reload timer command in the End of Interrupt register for the interrupt being
serviced. Only one general timer can be restarted this way in a single-interrupt routine.
August 1996
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DETAILED REGISTER DESCRIPTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
6.7.4 General Timer 2 (GT2) Sync Modes Only
Register Name: GT2
Intel Hex Address: x’2A
Register Description: General Timer 2
Default Value: x’00
Motorola Hex Address: x’29
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
This 8-bit timer can be started by the user whenever it is inactive by writing an 8-bit timeout value to the
Timer register. When non-zero, it decrements on each prescaler clock ‘tick’. When it reaches ‘0’, a mo-
dem/timer group interrupt is generated to the host. The timer can be disabled by the Channel Command
register if the timer’s current value is greater than ‘1’. In addition, during a receive or transmit interrupt the
user can reload a running timer by providing a reload value in the Interrupt Status register and a reload
timer command in the End of Interrupt register for the interrupt being serviced. In a single-interrupt rou-
tine, only one general timer can be restarted this way.
6.7.5 Transmit Timer Register (TTR) Async Modes Only
Register Name: TTR
Intel Hex Address: x’2A
Register Description: Transmit Timer
Default Value: x’00
Motorola Hex Address: x’29
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Binary value
This Asynchronous mode timer is managed by the CL-CD2431 to implement embedded transmit delays
when that option is used by the host (see description of COR2). This register should not be modified by
the host under any circumstances.
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DETAILED REGISTER DESCRIPTIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Before beginning any new design with this device, please contact Cirrus Logic Inc. for the
latest errata information. See the back cover of this document for sales office locations and
phone numbers.These characteristics and timing specifications apply to Revision D or later
devices.
7. ELECTRICAL SPECIFICATIONS
7.1 Absolute Maximum Ratings
Operating ambient temperature (T ).............................................0°C to 70°C
A
Storage temperature............................................................... −65°C to 150°C
All voltages with respect to ground..................... −0.5 V to V
+0.5 V (volts)
CC
Supply voltage (V )............................................................................ +7.0 V
CC
Power dissipation ...................................................................... 0.25 W (watt)
NOTE: Stresses above those listed under Absolute Maximum Ratings can cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods can affect device reliability.
7.2 DC Electrical Characteristics
(@ V = 5 V ± 5%, T = 0°C to 70°C)
CC
A
Symbol
Parameter
MIN
MAX
Units
Test Conditions
V
V
Input low voltage
−0.5
0.8
V
IL
Input high voltage (all pins except
CLK, RESET*, and BGIN*)
2.0
2.7
0.4
V
V
IH
CC
Input high voltage for CLK,
RESET*, and BGIN*
V
V
V
V
IH
CC
I
= 2.4 mA
(I for OD pins = 10 ma)
OL
V
V
Output low voltage
OL
OL
Output high voltage
2.4
−10
−10
−10
V
I
= −400 µA
OH
OH
I
I
I
I
Input leakage current
Data bus tristate leakage current
Open-drain output leakage
Power supply current
Input capacitance
10
µA
µA
µA
mA
pF
pF
0 < V < V
IN CC
IL
10
10
50
10
10
0 < V
< V
LL
OUT CC
0 < V
< V
CC
OC
CC
OUT
CLK = 35 MHz
C
C
IN
Output capacitance
OUT
NOTE: The maximum CLK of 35 MHz applies to Revision D and later devices only; revisions prior to D remain spec-
ified at 33 MHz maximum. All values in the following tables apply to the 35-MHz specification.
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ELECTRICAL SPECIFICATIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
7.3 AC Electrical Characteristics
Symbol
Parameter
MIN
MAX
t
Period of CLK input (35 MHz maximum)
CLK high to BUSCLK high
28.57
PERIOD
t
t
20
20
1
2
CLK high to BUSCLK low
Bus Arbitration
t
t
t
t
t
t
t
t
t
t
CLK high to BGACK* tristate
25
40
11
12
13
14
15
16
17
18
19
20
a
BGIN* low to address valid
Address hold after CLK high
0
CLK high to address tristate
25
25
20
CLK high to ADLD* low
CLK high to ADLD* high
Address setup to ADLD* high
CLK high to AEN*/DATEN*/DATDIR* high
CLK high to AEN*/DATEN*/DATDIR* tristate
CLK high to AEN*/DATEN*/DATDIR* low
15
25
25
25
DMA Read
t
Data setup to CLK high
10
15
21
t
Data hold after CLK high
CLK high to address valid
CLK low to AS* low
22
t
30
25
20
25
20
23
t
24
t
CLK high to AS* high
25
t
CLK low to DS* low
26
t
CLK high to DS* high
27
t
DTACK* low setup to CLK high
DTACK* high setup to CLK high (to avoid false termination)
10
50
28
t
29
DMA Write
t
CLK high to data valid
Data hold after CLK high
CLK low to DS* low
40
31
t
0
32
t
25
20
33
t
CLK high to DS* high
34
t
DTACK* low setup to CLK high
10
35
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ELECTRICAL SPECIFICATIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Symbol
Parameter
MIN
MAX
t
DTACK* high setup to CLK high (to avoid false termination)
50
36
Host Read/Write
t
DS* and CS* low setup to CLK high
Reserved
7
5
41
t
42
t
Reserved
43
t
R/W* setup to CLK high
44
t
CLK high to data valid
25
45
t
Data setup time to CLK high
Data hold time after CLK high
Address setup time to CLK high
Address hold time after CLK high
CLK high to DTACK* low (read cycle)
CLK high to DTACK* low (write cycle)
(CS* and DS*) low to DATEN*/DATDIR* low
DS* high to DATEN*/DATDIR* tristate
DS* high to data bus tristate
DS* high to DTACK* high-impedance
6
15
5
46
t
47
t
48
t
15
49
t
25
25
28
25
25
25
50
t
51
t
52
t
53
t
54
t
55
Interrupt Acknowledge
t
t
t
t
t
CLK high to IACKIN*, DS* setup
20
61
63
64
65
66
CLK high to data valid
35
Address setup to IACKIN* low
Address hold after IACKIN* high
CLK high to DTACK* low
0
0
25
40
(IACKIN* and DS*) low and BUSCLK high to
DATEN* and DATDIR* low
t
67
a
This timing assumes the following conditions: BGACK* high, DTACK* high, DS* high, and BUSCLK high.
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ELECTRICAL SPECIFICATIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
t
PERIOD
CLK
t
2
t
1
BUSCLK
RESET*
During RESET* active period, BUSCLK is held low. BUSCLK will transition high and begin
running at one/half CLK frequency on the first rising edge of CLK after RESET* is released.
Figure 7-1. CLK / BUSCLK / RESET* TIming Relationship
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ELECTRICAL SPECIFICATIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
t
41
DS*, CS*
t
44
R/W*
t
49
t
48
A[0–7]
t
45
t
t
54
A/D[0–15]
t
50
55
DTACK*
t
52
t
53
DATEN*
/DATDIR*
Figure 7-2. Slave Read Cycle Timing
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ELECTRICAL SPECIFICATIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
t
41
DS*, CS*
t
44
R/W*
t
49
t
48
A[0–7]
t
47
t
46
A/D[0–15]
DTACK*
DATEN*
t
t
55
51
t
52
t
53
Figure 7-3. Slave Write Cycle Timing
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ELECTRICAL SPECIFICATIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
t
61
DS*, CS*
t
44
R/W*
t
64
t
65
A[0–7]
t
63
t
t
54
A/D[0–15]
t
66
55
DTACK*
t
67
t
53
DATEN*
/DATDIR*
Figure 7-4. Interrupt Acknowledge Cycle Timing
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DATA BOOK v3.0
ELECTRICAL SPECIFICATIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
BR*
BGIN*
ADLD*
t
t
15
16
t
17
t
12
t
13
A[0–7]
A[0–7]
A[8–15]
A/D[0–15]
A[16–31]
NOTE
t
24
AS*
t
20
AEN*/DATEN*/
DATDIR*
BGACK*
R/W*
NOTE: In DMA Read cycle, these pins will be tristate;
in DMA Write cycle, these pins will be D[0:15].
Figure 7-5. Bus Arbitration Cycle Timing
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ELECTRICAL SPECIFICATIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
AS*, DS*
t
14
A[0–7]
A/D[0–15]
t
11
BGACK*
R/W*
t
19
t
18
DATEN*, AEN*,
DATDIR*
Figure 7-6. Bus Release Timing
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DATA BOOK v3.0
ELECTRICAL SPECIFICATIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
t
24
t
25
AS*
DS*
t
26
t
27
t
23
A[0–7]
t
22
t
21
A/D[0–15]
t
29
t
28
DTACK*
BERR*
t
t
H
S
BERR* Timing:
t = setup time to CLK rising edge = 10ns
S
t = hold time after CLK rising edge = 20ns
H
Figure 7-7. DMA Read Cycle Timing
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ELECTRICAL SPECIFICATIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
CLK
BUSCLK
t
24
t
25
AS*
DS*
t
33
t
34
t
23
A[0–7]
t
t
32
31
A/D[0–15]
t
36
t
35
DTACK*
BERR*
t
t
H
S
BERR* Timing:
t = setup time to CLK rising edge = 10ns
S
t = hold time after CLK rising edge = 20ns
H
Figure 7-8. DMA Write Cycle Timing
August 1996
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DATA BOOK v3.0
ELECTRICAL SPECIFICATIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
8. PACKAGE SPECIFICATIONS
22.95 (0.904)
23.45 (0.923)
19.90 (0.783)
20.10 (0.791)
0.22 (0.009)
0.38 (0.015)
0.65
(0.0256)
BSC
13.90 (0.547)
14.10 (0.555)
CL-CD2431
100-Pin PQFP (JEDEC)
16.95 (0.667)
17.45 (0.687)
Pin 1 Indicator
Pin 100
Pin 1
2.57 (0.101)
2.87 (0.113)
0.65 (0.026)
0.95 (0.037)
1.60 (0.063) REF
0.13 (0.005)
0.23 (0.009)
0° MIN
7° MAX
0.25
(0.010)
MIN
3.40
(0.134)
MAX
NOTES:
1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
180
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PACKAGE SPECIFICATIONS
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
9. ORDERING INFORMATION EXAMPLE
CL – CD2431 – 10 QC – D
Revision †
Cirrus Logic, Inc.
Temperature Range:
C = Commercial
Communications, Data
Part number
Package Type:
Q = PQFP (plastic quad flat pack)
Internal reference number
†
Contact Cirrus Logic for up-to-date revision information.
August 1996
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DATA BOOK v3.0
ORDERING INFORMATION EXAMPLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
Notes
182
August 1996
ORDERING INFORMATION EXAMPLE
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Index
host read 31
host read and write 31
host write 32
Numerics
32-bit data bus 60
interrupt acknowledge 33
A
A and C fields 64
abbreviations 7
D
data clock selection 59
data encoding 50, 57
DC electrical characteristics 169
DCE (data communications equipment) 61
DMA
data transfer 39
operation 37
DMA connections 60
DMA read 170
DMA write 170
absolute maximum ratings 169
AC electrical characteristics
bus arbitration 170
DMA read 170
DMA write 170
host read/write 171
interrupt acknowledge 171
ACCM (async-control-character map) 64
acronyms 7
Address Recognition mode 63
Addressing mode 86
Append 163
Append mode 41, 49
async interrupt setup example 79
Async-HDLC/PPP mode 91, 116, 121–122
Async-HDLC/PPP/MNP4 mode 134
Asynchronous DMA mode 50
Asynchronous mode 12, 95, 120, 133
Asynchronous/Async-HDLC/PPP mode 89
DPLL mode 110
DPLL operation 50
DTE (data terminal equipment) 61
DTE and DCE interface 61
E
electrical specifications 169
F
Fair Share scheme 36
FCS (frame check sequence) 62
FCS mode 93
FCT (flow control transparency) mode 95, 101
fields, A and C 64
B
bit rate generation 50
BRG operation 50
buffer allocation 47
buffers and chaining 40
bus acquisition cycle 38
bus arbitration 170
bus error handling 40
byte and word transfers 32
FIFO and timer operations 36
Flag Hunt mode 63
Flag mode 62–63
format
character 63
frame 64
frame format 64
FTP server 82
functional description 31
C
Chain mode 41
character format 63
CLK 172
CLK / BUSCLK / RESET* TIming Relationshi 172
Clock mode 12
G
global initialization 78
contexts and channels 32
conventions 7
cycles
H
hardware configurations
32-bit data bus 60
bus acquisition 38
DMA connections 60
DTE and DCE interface 61
hardware signals and IACK 35
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DATA BOOK v3.0
INDEX
CL-CD2431
Advanced Multi-Protocol Communications Controller
hardware signals and IACK cycles 35
HDLC DMA channel setup examples 79
HDLC mode 86, 88, 93, 132
HDLC processing 62
Asynchronous/Async-HDLC/PPP mode 89
Chain mode 41
Clock 12
DPLL mode 110
High-Impedance mode 12
host interface 31
host read and write cycles 31
host read cycle 31
host read/write 171
host write cycle 32
FCS mode 93
FCT (flow control transparency) mode 95, 101
Flag Hunt mode 63
Flag mode 62–63
HDLC mode 86, 88, 93, 132
High-Impedance mode 12
Idle mode 93
I
Idle-in Flag mode 93
Idle-in Mark mode 93
Local Loopback mode 112
Mark mode 62–63
MNP4 mode 92
MNP4/SLIP mode 90
Parity mode 87
Idle mode 93
initialization sequence for the CL-CD2231 77
interrupt acknowledge 171
interrupt service requests 34
interrupts
acknowledge cycle 33
contexts and channels 32
groups and types 34
Protocol mode 85
Receive Transfer mode 85
Remote Loopback mode 89–90
SLIP mode 94, 135
SLIP/MNP4 mode 117, 122
Syn/Flag Hunt mode 115
Synchronous mode 93
Transmit Transfer mode 85
XON mode 89
IACK cycles 35
keep and pass logic 35
multi–CL-CD2430 systems 35
registers 33
systems with interrupt controllers 35
transmit and interrupt service requests 34
K
multi–CL-CD2430 systems 35
keep and pass logic 35
O
L
operations
BGR 50
DMA 37
DPLL 50
Local Loopback mode 112
logic, keep and pass 35
FIFO and timer 36
receive FIFO 36
transmit FIFO 36
ordering information example 181
M
mapped characters
00–1F 64
20 and above 64
7D and 7E 65
FCS field, in the 65
P
package specifications 180
Parity mode 87
pin diagram
CL-CD2431 8
pin functions
Mark mode 62–63
memory map 14
MNP4 mode 92
MNP4/SLIP mode 90
modes
CL-CD2431 9
pin information 8
Address Recognition mode 63
Addressing mode 86
Append mode 41, 49
Async-HDLC/PPP mode 91, 116, 121–122
Async-HDLC/PPP/MNP4 mode 134
Asynchronous DMA mode 50
Asynchronous mode 12, 95, 120, 133
descriptions 10
programming examples 77
programming the PILR registers 35
Protocol mode 85
protocol processing 62
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INDEX
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
TCBADRL 19, 29, 164
TCBADRU 19, 29, 164
R
read cycle, host 31
Global registers
receive buffer interrupts 49
receive bus errors 50
receive DMA interrupt service routine 80
receive DMA transfer 44
receive FIFO operation 36
receive time-out 50
CAR 14, 20, 84
GFRCR 14, 20, 83
Interrupt registers
IER 16, 25, 125–126
LICR 16, 25, 127
LIVR 16, 25, 124
STK 16, 25, 128
Modem Interrupt registers
MEOIR 17, 27, 148
MIR 17, 27, 146
Receive Transfer mode 85
receiver
A and B buffers 44–45
fixed operations 66
options 67
MISR 17, 27, 147
MPILR 17, 27, 145
Option registers
register definitions 20
register descriptions, detailed 83
register table 14
CMR 15, 20, 85
registers
COR1 15, 20, 86
Bit Rate and Clock Option registers
RBPR 16, 23, 109
COR2 15, 20, 88
COR3 15, 21, 91
RCOR 16, 23, 110
COR4 15, 21, 96
TBPR 16, 23, 111
COR5 15, 21, 97
TCOR 16, 23, 112
COR6 15, 21, 98
Channel Command and Status registers
CCR 16, 24, 113
COR7 15, 21, 99
CPSR 15, 22, 105
LNXT 15, 22, 103
RFAR1 15, 22, 104
RFAR2 15, 22, 104
RFAR3 15, 22, 104
RFAR4 15, 22, 104
RXACCM0 15, 23, 108
RXACCM1 15, 23, 108
RXACCM2 15, 23, 108
RXACCM3 16, 23, 108
SCHR1 15, 22, 100
SCHR2 15, 22, 100
SCHR3 15, 22, 101
SCHR4 15, 22, 101
SCRh 15, 22, 102
SCRl 15, 22, 102
CSR 16, 24, 119
MSVR-DTR 16, 24, 123
MSVR-RTS 16, 24, 123
STCR 16, 24, 116
DMA Receive registers
ARBADRL 18, 28, 151
ARBADRU 18, 28, 151
ARBCNT 18, 28, 153
ARBSTS 18, 28, 154
BRBADRL 18, 28, 152
BRBADRU 18, 28, 152
BRBCNT 18, 28, 153
BRBSTS 18, 28, 154
RCBADRL 18, 28, 155
RCBADRU 18, 28, 155
DMA registers
TSPMAP1 15, 22, 106
TSPMAP2 15, 22, 106
TSPMAP3 15, 22, 106
TXACCM0 15, 23, 107
TXACCM1 15, 23, 107
TXACCM2 15, 23, 107
TXACCM3 15, 23, 107
Receive Interrupt registers
RDR 17, 26, 137
BERCNT 18, 28, 149
DMABSTS 18, 28, 150
DMR 18, 28, 149
DMA Transmit registers
ATBADRL 19, 29, 156
ATBADRU 19, 29, 156
ATBCNT 19, 29, 158
ATBSTS 19, 29, 159, 161–163
BTBADRL 19, 29, 157
BTBADRU 19, 29, 157
BTBCNT 19, 29, 158
BTBSTS 19, 29
REOIR 17, 26, 138
RFOC 17, 26, 137
RIR 17, 25, 130
August 1996
185
DATA BOOK v3.0
INDEX
CL-CD2431
Advanced Multi-Protocol Communications Controller
RISR 17, 25, 131
RISRh 17, 26, 136
RISRl 17, 25
bus release 177
DMA read cycle 178
DMA write cycle 179
interrupt acknowledge cycle 175
slave read cycle 173
slave write cycle 174
transfers, byte and word 32
transmit bus errors 49
transmit data
RPILR 17, 25, 129
Timer registers
GT1 19, 30, 167
GT1h 19, 30, 167
GT1l 19, 30, 167
GT2 19, 30, 168
RTPR 19, 30, 166
RTPRh 19, 30, 166
RTPRl 19, 30, 166
TPR 19, 30, 165
external clock in 57
external clock out 58
transmit DMA buffers
chained buffers 47
DMA selection 48
interrupts 47
transmit DMA transfer
Append mode 41
TTR 19, 30, 168
Transmit Interrupt registers
TDR 17, 27, 143
TEOIR 17, 27, 144
TFTC 17, 27, 143
TIR 17, 27, 141
Chain mode 41
transmit FIFO operation 36
transmit interrupt service routine 81
transmit service requests 34
Transmit Transfer mode 85
transmitter
TISR 17, 27, 142
TPILR 17, 27, 140
Remote Loopback mode 89–90
S
fixed operations 66
framing error 66
options 66
service routine
receive DMA interrupt 80
transmit interrupt 81
setup examples
transmission of abort 66
transmitter A and B buffers 42
transparency 64
async interrupt 79
HDLC DMA channel 79
SLIP mode 94, 135
SLIP/MNP4 mode 117, 122
Syn/Flag Hunt mode 115
Synchronous mode 93
synchronous transmitter examples 42
V
valid frame, definition 65
W
word and byte transfers 32
write cycle, host 32
T
X
timers
asynchronous protocols 37
synchronous protocols 36
transmit 37
XON mode 89
timing
bus arbitration cycle 176
186
August 1996
INDEX
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
Bit Index
DisRx 113
DisTx 113
DpllEn 110
Dpllmd[1:0] 110
DSR 123
DsrAE 88–90
DSRChg 147
DSRod 97
DSRzd 96
DTR 123
Numerics
2431own 154, 159–163
A
AbortTx 116–118
AdMd[1:0] 86
AFLO 86
Alt1 93
AppdCmp 118
Append 150
DTRop 123
B
E
BA/BB 136, 142
Berr 136, 142, 154, 159–163
Break 133–135
EnRx 113
EnSync 149
EnTx 113
EOB 136, 142, 154, 159–163
ByteDMA 149
EOF 132, 134–136, 142, 144, 154, 159–163
ESCDE 95
ETC 89
C
C[1:0] 84, 127
CD 123
CDChg 147
CDod 97
Ext-1X 112
F
CDzd 96
FCErr 99
FCS 93
FCSApd 88, 91–92
FCSPre 93
FCT 95
FE 133–135
FIFO threshod 96
Flag[3:0] 86
Frame 116–117
Frame Qualification Address [4:0] 104
Char. 00–1F 107–108
Chl[2:0] 87
Chle 87
chmd[2:0] 85
ClkSel[2:0] 110, 112
ClrCh 113
ClrDct 132
ClrDet 86
ClrRcv 115
ClrT[2:1] 115
ClrTx 115
G
CLvl [1:0] 128
CRC 132, 134
CRCNinv 88
CrtBuf 150
CTS 123
CtsAE 88–90
CTSChg 147
CTSod 97
Gap[2:0] 138
I
ICRNL 98
idle 93
IgnBrk 98
IgnCR 98
Ignore 87
In/Out 97
InitCh 113
INLCF 98
INPCK 98
INTR 159–163
CTSzd 96
D
D[7:0] 137, 143
DiscExc 138–139
August 1996
187
DATA BOOK v3.0
BIT INDEX
CL-CD2431
Advanced Multi-Protocol Communications Controller
IStrip 99
IT[1:0] 124
IXM 89
RFram 121–122
Ridle 121–122
RISR High, Low 131
RLM 89–90
L
RngDE 95
RstAll 113
RstApd 150
RTS 123
LLM 112
LNE 99
M
RtsAO 88–90
Rvct [1:0] 130
Rx flow control threshold 97
RxAbt 132, 134–135
RxChk 91–92
RxCt[4:0] 137
RxD 125–126
RxEn 119–122
RxFlag 119
RxFloff 120–121
RxFlon 120
RxFrame 119
RxMark 119
Mact 146
map32 159
Mcn [1:0] 146
Mdm 125–126
Men 146
Meo 146
MLvl [1:0] 128
Mvct [1:0] 146
N
NBrkInt 98
NoTrans 138–139
Notrans 144
npad[2:0] 91–94
npad[3:0] 91–92
npad3 94
RxMode 85
S
SCDE 95
SCdet[2:0] 133
SetTm[1:0] 138–139, 144, 148
sndpad 93
Nrbuf 150
Ntbuf 150
SndSpc 116–118
Splstp 95
SSPC[2:0] 118
Stop[1:0] 95
O
OCRNL 99
OE 132–135
ONLCR 99
Stop2 91–92, 94–95
P
T
ParInt 98
Parity 87
ParM0 87
ParM1 87
ParMrk 98
PE 133
Tact 141
Tbusy 150
Tcn [1:0] 141
TDAlign 150
Ten 141
Teoi 141
TermBuff 138–139, 144
TFram 121–122
Tidle 121–122
Timeout 133
TIMER 125–126
Timer[2:1] 147
TLVal 110
TLvl [1:0] 128
Transmit Bit Rate Period (Divisor) 111
Tvct [1:0] 141
TxCt[4:0] 143
Poly 105
R
Ract 130
Rbusy 150
Rcn [1:0] 130
Receive Bit Rate Period (Divisor) 109
Ren 130
Reoi 130
Reslnd 132
RET 125
188
August 1996
BIT INDEX
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
TxD 125–126
TxDat 142
U
UE 142, 161, 162
TxEmpty 142
TxEn 119–122
TxFlag 119
TxFloff 120–121
TxFlon 120
TxFrame 119
TxGen 91–92
TxIBE 89
TxMark 119
TxMode 85
User-assigned priority match value 129, 140, 145
User-defined literal next character 103
User-defined mapped transmit character 106
User-defined special character 101
User-defined special character detect range, high 102
User-defined special character detect range, low 102
X
Xoff 116
Xon 116
TxMpty 125–126
August 1996
189
DATA BOOK v3.0
BIT INDEX
CL-CD2431
Data Book v3.0
Direct Sales Offices
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The Company
Headquartered in Fremont, California, Cirrus Logic is a leading manufacturer of advanced integrated circuits for
desktop and portable computing, telecommunications, and consumer electronics. The Company applies its system-
level expertise in analog and digital design to innovate highly integrated, software-rich solutions.
Cirrus Logic has developed a broad portfolio of products and technologies for applications spanning
multimedia, graphics, communications, system logic, mass storage, and data acquisition.
The Cirrus Logic formula combines innovative architectures in silicon with system design expertise. We deliver
complete solutions — chips, software, evaluation boards, and manufacturing kits — on-time, to help you win in the
marketplace.
Cirrus Logic’s manufacturing strategy ensures maximum product quality, availability, and value for our
customers.
Talk to our systems and applications specialists; see how you can benefit from a new kind of semiconductor
company.
Copyright 1996 Cirrus Logic Inc. All rights reserved.
Cirrus Logic Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is
subject to change without notice. No responsibility is assumed by Cirrus Logic Inc. for the use of this information, nor for infringements of patents or other
rights of third parties. This document is the property of Cirrus Logic Inc. and implies no license under patents, copyrights, or trade secrets. No part of this
publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photographic, or
otherwise, or used as the basis for manufacture or sale of any items without the prior written consent of Cirrus Logic Inc. Cirrus Logic, AccuPak,
CompactCard, CompactStor, DIVA, FastPath, FeatureChips, Good Data, Laguna, MediaDAC, MotionVideo, SimulSCAN, S/LA, SofTarget, TextureJet,
TVTap, UXART, VisualMedia, V-Port, and WavePort are trademarks of Cirrus Logic Inc., which may be registered in some jurisdictions. Other trademarks
in this document belong to their respective companies. CRUS and Cirrus Logic International, Ltd. are trade names of Cirrus Logic Inc.
Cirrus Logic Inc.
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World Wide Web: http://www.cirrus.com
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