CH7317B-BF-I [CHRONTEL]
D/A Converter;
| 型号： | CH7317B-BF-I |
| 厂家： | 
CHRONTEL, INC |
| 描述： | D/A Converter 转换器 |
| 文件： | 总21页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CH7317B
CH7317B SDVO◊ / RGB DAC
Chrontel
Features
General Description
The CH7317B is a Display Controller device interfaces
seamlessly to HDTV or PC monitors that is equipped with a
VGA RGB interface display connector. Its input port,
complied with Intel SDVO Specification 1.2, can accept a
digital graphics, high-speed, AC-coupled, serial-
differential RGB input signal, and convert it to analog RGB
signal for driving the display.
•
•
•
Supporting analog RGB outputs for a display
monitor
Supporting maximum pixel rate of 165MP/s or
graphics resolutions up to 1920x1200*
High-speed SDVO◊ (1G~2Gbps) AC-coupled serial
differential RGB inputs
•
•
•
•
•
Supporting monitor connection detection
Programmable power management
Fully programmable through serial port
Configuration through Intel® SDVO Opcode ◊
Offered in 64-pin LQFP package and 64-pin QFN
package
The CH7317B supports maximum pixel rate of 165MP/s and
is capable of displaying up to 1920x1200 resolution with
reduced blanking. The built-in serial port controller will allow
the graphics chipset to obtain the monitor’s EDID information
or communicate with CH7317B internal registers through
SDVO Opcodes. In addition, the transmitter is designed with
a monitor connection detection algorithm that allows the
graphics chipset to read back the connection status through
CH7317B internal registers.
* Reduced Blanking
◊ Intel® Proprietary.
The CH7317B provides the Boundary-scan test to help
system developers to check the interconnection between
chip I/O and the printed circuit board for faults. When
the device is powered down by the graphics chipset, its
current consumption is less than 100uA. The CH7317B is
available in 64-pin LQFP and 64-pin QFN packages.
AS
SPC
Serial
Port
Control
SPD
RESET*
SC_DDC
SD_DDC
SC_PROM
SD_PROM
Clock
Driver
VSYNC,
HSYNC
SDVO_Clk(+,-)
2
2
DAC2
DAC1
DAC0
DAC2
DAC1
DAC0
ISET
SDVO_R(+,-)
SDVO_G(+,-)
SDVO_B(+,-)
Data Latch,
Serial to Parallel
10 bit-8 bit
decoder
6
10 bit DAC
Figure 1: Functional Block Diagram
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CHRONTEL
CH7317B
Table of Contents
1.0 Pin-Out ____________________________________________________________________ 4
1.1
1.2
Package Diagram ___________________________________________________________________4
Pin Description _____________________________________________________________________6
2.0 Functional Description________________________________________________________ 8
2.1
2.2
2.3
Input Interface______________________________________________________________________8
VGA Output Operation_______________________________________________________________8
Command Interface _________________________________________________________________9
3.0 Register Control ____________________________________________________________ 12
4.0 Electrical Specifications______________________________________________________ 13
4.1
4.2
4.3
4.4
4.5
Absolute Maximum Ratings __________________________________________________________13
Recommended Operating Conditions___________________________________________________13
Electrical Characteristics ____________________________________________________________14
DC Specifications __________________________________________________________________14
AC Specifications __________________________________________________________________16
5.0 Package Dimensions_________________________________________________________ 18
6.0 Revision History ____________________________________________________________ 20
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CH7317B
Figures and Tables
List of Figures
Figure 1: Functional Block Diagram ....................................................................................................................................1
Figure 2: 64-Pin LQFP Package...........................................................................................................................................4
Figure 3: 64-Pin QFN Package.............................................................................................................................................5
Figure 4: Control Bus Switch .............................................................................................................................................10
Figure 5: NAND Tree Connection .....................................................................................................................................10
Figure 6: 64 Pin LQFP Package .........................................................................................................................................18
Figure 7: 64 Pin QFN Package (8 X 8 mm)........................................................................................................................19
List of Tables
Table 1: Pin Description.......................................................................................................................................................6
Table 2: CH7317B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns ..........................................8
Table 3: Various VGA resolutions. ......................................................................................................................................9
Table 4: Video DAC Configurations for CH7317B .............................................................................................................9
Table 5: Signal Order in the NAND Tree Testing..............................................................................................................11
Table 6: Signals not Tested in NAND Test besides power pins.........................................................................................11
Table 7: Revisions ..............................................................................................................................................................20
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CHRONTEL
CH7317B
1.0 Pin-Out
1.1 Package Diagram
T1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Reserved
Reserved
Reserved
NC
SD_DDC
2
3
SC_DDC
SD_PROM
SC_PROM
NC
4
5
NC
NC
6
Chrontel
CH7317B
7
RESET*
AS
NC
NC
NC
NC
8
9
NC
10
11
12
13
14
15
16
DGND
SPD
NC
DGND
VSYNC
DVDD
HSYNC
NC
SPC
DVDD
BSCAN
Reserved
VDAC2
Figure 2: 64-Pin LQFP Package
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CH7317B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Reserved
Reserved
Reserved
NC
T1
1
SD_DDC
2
3
SC_DDC
SD_PROM
SC_PROM
NC
4
NC
5
NC
6
Chrontel
CH7317B
NC
NC
7
RESET*
AS
8
NC
NC
9
NC
10
11
12
13
14
15
16
DGND
SPD
NC
DGND
SPC
VSYNC
DVDD
DVDD
BSCAN
Reserved
VDAC2
HSYNC
NC
Figure 3: 64-Pin QFN Package
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CH7317B
1.2 Pin Description
Table 1: Pin Description
Pin #
Type
Symbol
Description
Test
These pins are reserved for factory test and default to high impedance.
1,51
Out
T1, T2
Routed Serial Port Data Output to DDC
2
In/Out
SD_DDC
This pin functions as the bi-directional data pin of the serial port to DDC receiver. This
pin will require a 10KΩ pull-up resistor to the desired high state voltage. Leave open if
unused.
Routed Serial Port Clock Output to DDC
3
4
In/Out
In/Out
SC_DDC
This pin functions as the clock bus of the serial port to DDC receiver. This pin will
require a 10KΩ pull-up resistor to the desired high state voltage. Leave open if unused.
Routed Data Output to PROM
SD_PROM
This pin functions as the bi-directional data pin of the serial port for PROM on ADD2
card. This pin will require a pull-up resistor to the desired high state voltage. Leave
open if unused.
Routed Clock Output to PROM
This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin
will require a pull-up resistor to the desired high state voltage. Leave open if unused.
5
In/Out
In
SC_PROM
RESET*
AS
7
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition. When this pin
is high, reset is controlled through the serial port register. This pin is 3.3V compliant.
8
In
Address Select (Internal pull-up)
This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS
is low the address is 72h, when high the address is 70h.
11
In/Out
SPD
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and operates with
inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external
4KΩ - 9KΩ pull-up resistor to 2.5V.
12
14
15
In/Out
In
SPC
Serial Port Clock Input
This pin functions as the clock input of the serial port and operates with inputs from 0 to
2.5V. This pin requires an external 4KΩ - 9KΩ pull-up resistor to 2.5V.
BSCAN (Internal pull-down)
This pin should be pulled low with a 10K ohm resistor. This pin enables the boundary
scan for in-circuit testing. Voltage level is 0 to DVDD.
BSCAN
In
Reserved
Reserved (Internal pull-down)
This pin should be pulled low with a 10K ohm resistor.
DAC Output A
Video Digital-to-Analog outputs. RGB Bypass outputs. Each output is capable of
driving a 75-ohm doubly terminated load.
20,24,28 Out
DACA[2:0]
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CH7317B
Table 1: Pin Description (contd.)
Pin #
32
Type
In
Symbol
ISET
Description
Current Set Resistor Input
This pin sets the DAC current. A 1.2Kohm resistor should be connected between
this pin and DAC ground (pin 31) using short and wide traces.
34
36
Out
Out
HSYNC
VSYNC
Horizontal Sync Output
A buffered version of VGA horizontal sync can be acquired from this pin.
VSYNC
A buffered version of VGA vertical sync can be acquired from this pin.
46
47
48
50
Out
Out
Out
In
Reserved
Reserved
Reserved
RPLL
This pin should be left open.
This pin should be left open.
This pin should be left open.
PLL Resistor Input
External resistor 10Kohm should be connected between this pin and pin 49.
53,54,56,57 In
59,60
SDVO_R+/-,
SDVO_G+/-,
SDVO_B+/-
SDVO_CLK+/-
SDVO Data Channel Inputs
These pins accept 3 AC-coupled differential pair of inputs from a digital video port
of a graphics controller. These 3 pair of inputs can be R, G, B or Y, Cr, Cb.
Differential Clock Input associated with SDVOB Data channel (SDVOB_R+/-,
SDVOB_G+/-, SDVOB_B+/-)
62,63
In
These pins accept one AC-coupled differential pair of inputs from a digital video
port of a graphics controller. The range of this clock pair is 100~200MHz. For
specified pixel rates in specified modes this clock pair will run at an integer multiple
of the pixel rate. Refer to to section 2.1.3 for details.
13,35
10,37
16
Power
Power
Power
Power
Power
Power
Power
Power
DVDD
DGND
VDAC2
GDAC2
VDAC1
GDAC1
VDAC0
GDAC0
AVDD
AGND
Digital Supply Voltage (2.5V)
Digital Ground
DAC Supply Voltage (3.3V)
DAC Ground
17
19
DAC Supply Voltage (3.3V)
DAC Ground
23
27
DAC Supply Voltage (3.3V)
DAC Ground
31
52,58,64 Power
49,55,61 Power
Analog Supply Voltage (2.5V)
Analog Ground
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CH7317B
2.0 Functional Description
2.1 Input Interface
2.1.1
Overview
One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The input
data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate
(SDVOB_CLK+/-). The CH7317B de-serializes the input into 10-bit parallel data with synchronization and alignment.
Then the 10-bit characters are mapped into 8-bit color data or control data (HSYNC, VSYNC, DE).
2.1.2
Interface Voltage Levels
All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level for
the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The differential p-p
output voltage has a min of 0.8V, with a max of 1.2V.
2.1.3
Input Clock and Data Timing
A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of the
SDVOB_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.
The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate do
not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x, 4x depending on the pixel rate) so that the
clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a multiple of the
pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters (‘0001111010’) are used to stuff
the data stream. The CH7317B supports the following clock rate multipliers and fill patterns shown in Table 2.
Table 2: CH7317B supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns
Pixel Rate
Clock Rate – Multiplier
Stuffing Format
Data, Fill, Fill, Fill
Data, Fill
Data Transfer Rate - Multiplier
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
25~50 MP/s
50~100 MP/s
100~200 MHz – 4xPixel Rate
100~200 MHz – 2xPixel Rate
100~200 MP/s 100~200 MHz – 1xPixel Rate
Data
2.1.4 Synchronization
Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during the
blank period. The CH7317B synchronizes during the initialization period and subsequently uses the blank periods to re-
synch to the data stream.
2.2 VGA Output Operation
The CH7317B can operate in VGA RGB Bypass mode. In VGA RGB Bypass mode, data from the graphics device, after
proper decoding, are bypassed directly to the video DACs to implement a second RGB DAC function. Sync signals,
after proper decoding, are buffered internally, and can be output to drive the VGA Monitor. The CH7317B can support a
pixel rate of 200MHz. This operating mode uses 8-bits of three of the DAC’s 10-bit range, and provides a nominal
signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75Ω doubly
terminated load. No scaling, scan conversion or flicker filtering is applied in VGA RGB Bypass modes.
Table 3 lists some of the VGA resolutions.
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CH7317B
Table 3: Various VGA resolutions.
Name
Resolution
320x200
QVGA
320x240
400x300
640x350, 640x400
VGA
640x480
512x384
704x480, 704x576
720x350, 720x400, 720x480, 720x540, 720x576
768x480, 768x576
SVGA/WSVGA
800x600
832x624
848x480
920x766
960x600
1024x600
XGA/WXGA
1024x768
1124x768
1152x720
1280x768, 1280x720, 1280x800, 1280x960
SXGA/WSXGA
1280x1024
1360x768, 1360x1024, 1366x768, 1466x768
SXGA+/WSXGA+
1400x1050
1400x1200
1536x960
1680x1050
1600x1200
1704x960
UXGA/WUXGA
1920x1080
1920x1200 1
Note:
1. With reduced blanking.
Table 4 below lists the DAC output configurations of the CH7317B.
Table 4: Video DAC Configurations for CH7317B
Output Type
VGA RGB
DACA[0]
B
DACA[1]
G
DACA[2]
R
2.3 Command Interface
Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7317B accepts incoming control
clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card PROM, DDC, or
CH7317B internal registers. The control bus is able to run up to 1MHz when communicating with internal registers, up
to 400kHz for the PROM and up to 100kHz for the DDC.
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CH7317B
Internal
Device
Registers
control
the
observer
switch
on/off
SPC, SPD
DDC
default
position
PROM
Figure 4: Control Bus Switch
Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this stage, the
CH7317B observes the control bus traffic. If the observing logic sees a control bus transaction destined for the internal
registers (device address 70h or 72h), it disables the PROM output pairs, and switches to internal registers. In the
condition that traffic is to the internal registers, an Opcode command is used to set the redirection circuitry to the
appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal registers while at the stage of traffic
to DDC occurs on observing a STOP after a START on the control bus.
2.3.1
Boundary scan Test
CH7317B provides a called “NAND TREE Testing” to verify IO cell function at the PC board level. This test will check
the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads, open printed circuit
board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input mode, connects all
inputs with NAND gates as shown in the figure below and switches each signal to high or low according to the sequence
in Table 11. The test results then pass out at pin 51 (T2).
Figure 5: NAND Tree Connection
Set BSCAN =1; (internal weak pull-low)
Set all signals listed in to 1.
Set all signals listed in to 0, toggle one by one with certain time period, suggested 100 ns. Pin 51 (T2) will change its
value each time an input value changed.
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CH7317B
Table 5: Signal Order in the NAND Tree Testing
Order
1
Pin Name
SD_DDC
SC_DDC
SD_PROM
SC_ PROM
RESETB
AS
LQFP Pin
2
2
3
3
4
4
5
5
7
6
8
7
SPD
11
12
20
24
28
32
34
36
46
47
48
51
8
SPC
9
DACA[2]
DACA[1]
DACA[0]
ISET
10
11
12
13
14
15
16
17
18
HSYNC
VSYNC
Reserved
Reserved
Reserved
T2
Table 6: Signals not Tested in NAND Test besides power pins
Pin Name
SDVO_R+
SDVO_R-
SDVO_G+
SDVO_G-
SDVO_B+
SDVO_B-
SDVO_CLK+
SDVO_CLK-
RESET*
LQFP Pin
53
54
56
57
59
60
62
63
7
BSCAN
14
15
1
Reserved
T1
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CHRONTEL
CH7317B
3.0 Register Control
The CH7317B is controlled via a serial control port. The serial bus uses only the SC clock to latch data into registers,
and does not use any internally generated clocks so that the device can be written to in all power down modes. The
device will retain all register values during power down modes.
Registers 00h to 11h are reserved for Opcode use. All registers except bytes 00h to 11h are reserved for internal factory
use. For details regarding Intel® SDVO Opcodes, please contact Intel®.
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CH7317B
4.0 Electrical Specifications
4.1 Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
All 2.5V power supplies relative to GND
All 3.3V power supplies relative to GND
-0.5
-0.5
3.5
5.0
V
T
T
T
T
Analog output short circuit duration
Storage temperature
Indefinite
Sec
°C
SC
-65
150
150
STOR
J
Junction temperature
°C
Vapor phase soldering (5 second)
Vapor phase soldering (11 second)
Vapor phase soldering (1 minute)
260
245
225
VPS
°C
Note:
1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions above those
indicated under the normal operating condition of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability. The temperature requirements of vapor phase soldering
apply to all standard and lead free parts.
2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive
0.5V can induce
device. Voltage on any signal pin that exceeds the power supply voltages by more than
destructive latch-up.
4.2 Recommended Operating Conditions
Symbol
AVDD
DVDD
VDAC
VDD33
VDD25
Rset
Description
Min
Typ
2.5
Max
Units
V
Analog Power Supply Voltage
Digital Power Supply Voltage
DAC Power Supply
2.375
2.375
3.100
3.100
2.375
1188
9900
2.625
2.625
3.500
3.500
2.625
1212
2.5
V
3.3
V
Generic for all 3.3V supplies
Generic for all 2.5V supplies
Resistor on ISET pin (32)
Resistor on RPLL pin (50)
3.3
V
2.5
V
1200
10000
Ω
RRPLL
10100
Ω
Ambient operating temperature (Commercial / Automotive
Grade 4)
T
T
AMB
AMB
0
70
85
°C
°C
Ambient operating temperature (Industrial / Automotive
Grade 3)
-40
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CH7317B
4.3 Electrical Characteristics
(Operating Conditions: TA = 0°C to 70°C for parts qualified as Commercial / Automotive Grade 4, TA = –40°C to 85°C
for parts qualified as Industrial / Automotive Grade 3, VDD25 =2.5V 5%, VDD33 = 3. 3V 5%,)
Symbol
Description
Min
Typ
10
Max
Units
bits
mA
%
Video D/A Resolution
Full scale output current
Video level error
10
10
17.63
10
I
I
I
Total VDD25 supply current (2.5V supplies) with VGA By-
Pass output and 1024x768@60Hz input
VDD25,VGA
VDD33,VGA
PD
100
110
mA
Total VDD33 supply current (3.3V supplies) with VGA By-
Pass output and 1024x768@60Hz input
75
80
mA
mA
Total Power Down Current
0.1
4.4 DC Specifications
Symbol
Description
Test Condition
Min
Typ
Max
Units
SDVO Receiver Differential
Input Peak to Peak Voltage
0.175
1.200
120
60
V
VRX-DIFFp-p
VRX-DIFFp-p = 2 *
VRX-D+ - VRX-D-
SDVO Receiver DC Differential
Input Impedance
80
100
50
Ω
Ω
Ω
ZRX-DIFF-DC
SDVO Receiver DC Common
Mode Input Impedance
40
ZRX-COM-DC
SDVO Receiver Initial DC
Common Mode Input
Impedance
Impedance allowed
when receiver
5
50
60
ZRX-COM-INITIAL-
DC
terminations are first
turned on
SDVO Receiver Powered
Down DC Common Mode
Input Impedance
Impedance allowed
when receiver
20k
0.8
200k
Ω
ZRX-COM-High-
IMP-DC
terminations are not
powered
TVCLK Differential Pk – Pk
Output Voltage
1.2
0.4
V
V
V
V
VPP_TVCLK
1
SPD (serial port data) Output
Low Voltage
VSDOL
I
= 2.0 mA
OL
2
Serial Port (SPC, SPD) Input
High Voltage
1.0
GND-0.5
0.25
VDD33 +
0.5
VSPIH
2
Serial Port (SPC, SPD) Input
Low Voltage
0.4
VSPIL
Hysteresis of Serial Port Inputs
V
V
VHYS
VDDCIH
DDC Serial Port
+5V
+0.5
Input High Voltage
4.0
VDDCIL
DDC Serial Port
V
V
Input Low Voltage
GND-0.5
4.0
0.4
VPROMIH
PROM Serial Port
Input High Voltage
+5V
+0.5
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CH7317B
Symbol
Description
Test Condition
Min
Typ
Max
Units
VPROMIL
PROM Serial Port
Input Low Voltage
V
GND-0.5
0.4
3
Input is VINL at
SD_DDC or
SD_EPROM.
SPD (serial port data) Output
Low Voltage from SD_DDC (or
SD_EPROM)
0.9*VINL
0.25
+
V
VSD_DDCOL
4.0kΩ pull-up to 2.5V.
4
Input is VINL at SPC
and SPD.
SC_DDC and SD_DDC Output
Low Voltage
0.933*VINL
0.35
+
V
V
VDDCOL
5.6kΩ pull-up to 5.0V.
5
Input is VINL at SPC
and SPD.
SC_EPROM and SD_EPROM
Output Low Voltage
0.933*VINL
0.35
+
VEPROMOL
5.6kΩ pull-up to 5.0V.
6
RESET*
Input High Voltage
2.7
GND-0.5
2.0
VDD33 +
0.5
V
V
VMISC1IH
VMISC1IL
VMISC2IH
6
7
RESET*
0.5
Input Low Voltage
AS, BSCAN
Input High Voltage
VDD25 +
0.5
V
7
AS, BSCAN
Input Low Voltage
DVDD=2.5V
VIN = 0V
GND-0.5
10
0.5
V
VMISC2IL
IPU
AS, RESET*
Pull-Up Current
30
uA
BSCAN
IPD
V
I
IN = 2.5V
10
30
uA
V
Pull-Down Current
8
VSYNCOH
HSYNC, VSYNC
= -0.4mA
2.0
OH
Output High Voltage
8
VSYNCOL
HSYNC, VSYNC
IOL = 3.2mA
0.4
V
Output Low Voltage
Notes:
1. VSDOL is the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM.
2. VSPIH and VSPIL are the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate
requirements may exist for transmission to the DDC and EEPROM.
3. VSD_DDCOL is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is VINL. Maximum output
voltage has been calculated with the worst case of pull-up of 4.0kΩ to 2.5V on SPD.
4. VDDCOL is the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is VINL. Maximum output
voltage has been calculated with 5.6k pull-up to 5V on SC_DDC and SD_DDC.
5. VEPROMOL is the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is VINL
Maximum output voltage has been calculated with 5.6kΩ pull-up to 5V on SC_EPROM and SD_EPROM.
.
6.
7.
V
MISC1 - refers to RESET* input which is 3.3V compliant.
MISC2 - refers to AS, BSCAN, which are 2.5V compliant
V
8. VSYNC - refers to HSYNC and VSYNC outputs.
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CHRONTEL
CH7317B
4.5 AC Specifications
Symbol
Description
Test Condition
Min
Typ
Max
Units
UIDATA
SDVO Receiver Unit Interval
for Data Channels
Typ. –
1/[Data
Transfer
Rate]
Typ. +
ps
300ppm
300ppm
fSDVOB_CLK
fPIXEL
SDVO CLK Input Frequency
100
25
200
165
MHz
MHz
SDVO Receiver Pixel
frequency
fSYMBOL
SDVO Receiver Symbol
frequency
1
2
GHz
UI
tRX-EYE
SDVO Receiver Minimum Eye
Width
0.4
tRX-EYE-JITTER
SDVO Receiver Max. time
between jitter median and
max. deviation from median
0.3
UI
VRX-CM-ACp
SDVO Receiver AC Peak
150
mV
Common Mode Input Voltage
RLRX-DIFF
RLRX-CM
TSPR
Differential Return Loss
50MHz – 1.25GHz
50MHz – 1.25GHz
15
6
dB
dB
Common Mode Return Loss
SPC, SPD Rise Time
(20% - 80%)
Standard mode 100k
Fast mode 400k
1000
300
ns
ns
ns
1M running speed
150
TSPF
SPC, SPD Fall Time
(20% - 80%)
Standard mode 100k
Fast mode 400k
300
300
150
300
ns
ns
ns
ns
1M running speed
Fast mode 400K
TPROMR
TPROMF
TDDCR
TDDCF
SC_PROM, SD_PROM Rise
Time (20% - 80%)
SC_PROM, SD_PROM Rise
Time (20% - 80%)
Fast mode 400K
300
1000
300
ns
ns
ns
SC_DDC, SD_DDC Rise
Time (20% - 80%)
Standard mode 100k
Standard mode 100k
SC_DDC, SD_DDC Fall
Time (20% - 80%)
1
TDDCR-DELAY
SC_DDC, SD_DDC Rise
Time Delay (50%)
Standard mode 100k
Standard mode 100k
0
3
ns
ns
1
TDDCF-DELAY
SC_DDC, SD_DDC Fall
Time Delay (50%)
tSKEW
SDVO Receiver Total Lane to
Lane Skew of Inputs
Across all lanes
2
ns
ns
tR
HSYNC and VSYNC (when
configured as outputs)
15pF load
1.50
DVDD = 2.5V
Output Rise Time
(20% - 80%)
16
201-0000-097
Rev. 1.8,
1/07/2014
CHRONTEL
CH7317B
tF
H and V (when configured as
15pF load
1.50
ns
outputs)
DVDD = 2.5V
Output Fall Time
(20% - 80%)
Notes:
1. Refers to the figure below, the delay refers to the time pass through the internal switches.
3.3V typ.
2.5V typ.
R=5K
To SPC/SPD pin
To DDC pin
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Rev. 1.8, 1/07/2014
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CHRONTEL
CH7317B
5.0 Package Dimensions
A
B
1X 4
I
1
A B
H
3X
5
C
D
J
LEAD
CO-PLANARITY
E
.004 “
F
G
Figure 6: 64 Pin LQFP Package
Table of Dimensions
No. of Leads
SYMBOL
64 (10 X 10 mm)
A
B
C
D
E
F
G
H
I
J
Milli-
meters
MIN
11.80
-
0.17
0.27
1.35
1.45
0.05
0.15
0.45
0.75
0.09
0.20
0°
7°
0.50
1.00
MAX
12.20 10.00
Notes:
1. Conforms to JEDEC standard JESD-30 MS-026D.
2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.
3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.
4. (1X) Corner in quadrant with Pin1 identifier (dot) is always chamfered. Exact shape of chamfer is optional.
5. (3X) Corners in quadrants without Pin1 identifier (dot) may be square or chamfered. Exact shape of corner
or chamfer is optional.
18
201-0000-097
Rev. 1.8,
1/07/2014
CHRONTEL
CH7317B
TOP VIEW
BOTTOM VIEW
B
A
64
49
48
1
Pin 1
3
C
A
33
16
F
4
17
32
E
D
(4x)
2
I
G
H
Figure 7: 64 Pin QFN Package (8 X 8 mm)
Table of Dimensions
No. of Leads
SYMBOL
64 (8 X 8 mm)
A
B
C
D
E
F
G
0.7
1
H
I
Milli-
meters
MIN
7.9
8.1
4.85
6.3
4.85
6.3
0.15
0.25
0.30
0.50
0
0.4
0.2
MAX
0.05
Notes:
1. Conforms to JEDEC standard JESD-30 MO-220.
2
3
4
Side of body may be square or curved.
Exposed pad may have chamfer in area of Pin 1.
Pins may protrude from edge of body by 0.05 mm.
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Rev. 1.8, 1/07/2014
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CHRONTEL
CH7317B
6.0 Revision History
Table 7: Revisions
Rev. # Date
Section
Description
1.0
1.1
04/06/09 All
Official release.
05/06/09 2.2, 2.3
Update Table 3, Table 4 and Figure 4.
Update Ambient operating temperature.
Add some parameters and notes.
4.2
05/14/09 4.4, 4.5
06/12/09 1.0
1.2
1.2
1.3
Update Figure 2 and Figure 3, Pin definition of Pin34.
Update Table 1, Pin definition of Pin34.
Update Figure 7, QFN package drawing.
5.0
1.4
04/04/10 Figure 1, Table 1
Table 3
Make some pin type clear.
Make some description more clear.
1.5
1.6
01/14/11 4.1, 4.2
05/08/12 1.2, 4.1, 4.2, 4.3, 5.0
Update ambient operating temperature.
Update ambient operating temperature into Commercial /
Automotive Grade 4 and Industrial / Automotive Grade 3. Unify
the description of pin 14 and pin 15. Modify some “Absolute
Maximum Ratings”. Add some notes for “Package
Dimensions”.
1.7
1.8
11/26/12 1.2
Pin 14 and pin 15 should be connected to ground through a 10K
resistor.
01/07/14 1.2, 4.1, 4.2
Pins 62/63 (SDVO_CLK+/-) should be AC-coupled. Move
from 4.1 to 4.2.
T
AMB
20
201-0000-097
Rev. 1.8,
1/07/2014
CHRONTEL
CH7317B
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use
of our products and assume no liability for errors contained in this document. The customer should make sure that
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not
infringe upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Temperature Grade
Part Number
CH7317B-TF
Package Type
Lead Free LQFP
Lead Free LQFP
Number of Pins
Voltage Supply
2.5V & 3.3V
2.5V & 3.3V
2.5V & 3.3V
2.5V & 3.3V
2.5V & 3.3V
2.5V & 3.3V
2.5V & 3.3V
2.5V & 3.3V
Commercial /
Automotive Grade 4
64
64
64
64
64
64
64
64
Industrial /
Automotive Grade 3
CH7317B-TF-I
CH7317B-TF-TR
CH7317B-TF-I-TR
CH7317B-BF
Lead Free LQFP
in Tape & Reel
Commercial /
Automotive Grade 4
Lead Free LQFP
in Tape & Reel
Industrial /
Automotive Grade 3
Commercial /
Automotive Grade 4
Lead Free QFN
Lead Free QFN
Industrial /
Automotive Grade 3
CH7317B-BF-I
CH7317B-BF-TR
CH7317B-BF-I-TR
Lead Free QFN
in Tape & Reel
Commercial /
Automotive Grade 4
Lead Free QFN
in Tape & Reel
Industrial /
Automotive Grade 3
Chrontel
2210 O’Toole Avenue, Suite 100,
San Jose, CA 95131-1326
Tel: (408) 383-9328
Fax: (408) 383-9338
www.chrontel.com
E-mail: sales@chrontel.com
2014 Chrontel, Inc. All Rights Reserved.
Printed in the U.S.A.
201-0000-097
Rev. 1.8, 1/07/2014
21
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