CH7021A-TEF_技术文档

CH7021/CH7022

CH7021/CH7022 SDTV/EDTV/HDTV Encoder

Chrontel

Features

General Description

•

SDVO^[1]to SDTV/EDTV/HDTV conversion

The CH7021/CH7022 is a Display Controller device which

accepts a digital graphics high speed AC coupled serial

differential RGB input signal, and encodes and transmits data

through analog SDTV ports (analog composite, s-video, VGA

or YPrPb) or an analog EDTV/HDTV port (YPrPb). The

device is able to encode the video signals and generate

synchronization signals for NTSC, PAL and SECAM SDTV

standards, as well as analog EDTV and HDTV interface

standards and graphics standards up to UXGA. The device

accepts one channel of RGB data over three pairs of serial

data ports.

supporting up to 160 MHz pixel clock

SDVO to VGA conversion supporting up to

1600x1200 resolution^[2]

EDTV/HDTV support for 480p, 576p, 720p, 1080i

and 1080p

•

Support for NTSC, PAL, SECAM color modulation.

Macrovision^TM7.1.L1 copy protection support for

SDTV (CH7021 only)

•

Macrovision^TMcopy protection support for

progressive scan EDTV (480p, 576p) (CH7021 only)

CGMS-A support for SDTV, EDTV and HDTV

High-speed SDVO (1G~2Gbps) AC-coupled serial

differential RGB inputs

•

The TV-Out processor will perform scaling to convert VGA

frames to all the supported TV output standards. Adaptive de-

flicker filter provides superior text display. Large numbers of

input graphics resolutions are supported up to 160 MHz pixel

rate with full vertical and horizontal overscan compensation in

all output standards. A high accuracy low jitter phase locked

loop is integrated to create outstanding video quality.

•

Flexible true scale rendering engine supports

overscan compensation in all SDTV/EDTV and

HDTV output resolutions^[3]

•

Text enhancement filter in scan conversion

Adaptive de-flicker filter with up to 7 lines of

filtering in scan conversion

In addition to scaling modes, bypass modes are included

which perform color space conversion to all the TV standards

and generate and insert all the TV sync signals, or output

VGA style analog RGB.

•

Contrast/Brightness/Sharpness control for TV output.

Hue/Saturation Control for TV output.

Support for SCART connector

Support for EDTV / HDTV D-Connector

Outputs CVBS, S-Video, VGA and YPbPr

Support for VGA bypass

Different analog video connectors are supported including

composite, s-video, YPrPb, SCART, D-connector and VGA

connector.

TV / Monitor connection detect

Programmable power management

CGMS-A is also provided up to 1080i resolution. Content

protection support is provided for Macrovision^TMin SDTV

and EDTV modes for CH7021 only.

Four 10-bit video DAC outputs

Three sets of DAC outputs supporting SDTV /

EDTV / HDTV / VGA connectors

•

Fully programmable through serial port

Configuration through Intel® SDVO OpCode^[1]

Complete Windows driver support

The CH7021 is capable of adding Macrovision^TMencoding to

the output signal. CH7022 is the same chip without

Macrovision^TMencoding.

Offered in 64-pin LQFP and 64-pin QFN package

^[1]Intel Proprietary.

^[2]For the modes higher than 160 MHz pixel rate, please

contact Chrontel Application Department for detail.

^[3]Patent pending

201-0000-065

Rev. 2.5, 06/07/2011

1

CHRONTEL

CH7021/CH7022

AS

SPC

SPD

Serial

Port

Control

XI/FIN,XO

2

PLL

TVCLK(+,-)

RESET*

BCO/VSYNC

C/HSYNC

D1,D2,D3

SC_DDC

SD_DDC

SC_PROM

SD_PROM

Control

3

CVBS, S-Video,

RGB, YPbPr

NTSC/PAL/

SECAM

Encoder

Clock

Driver

Color Space

Conversion

SDVO_Clk(+,-)

2

DAC3

DAC2

Scaling

Scan Conv

Flicker Filt

DACA[3:0]

DACB[2:0]

DACC[2:0]

Video

Switch

10bit-8bit

decoder

MUX

DAC1

DAC0

YPbPr

HDTV

Encoder

SDVO_R(+,-)

SDVO_G(+,-)

SDVO_B(+,-)

RGB, Bypass

Data Latch,

Serial to Parallel

Four

10-bit DAC's

6

ISET

Figure 1: Functional Block Diagram

2

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Table of Contents

1.0 Pin-Out ____________________________________________________________________ 5

1.1

1.2

Package Diagram ___________________________________________________________________5

Pin Description _____________________________________________________________________7

2.0 Functional Description_______________________________________________________ 10

2.1

2.2

2.3

2.4

2.5

2.6

Input Interface_____________________________________________________________________10

TV Output Operation _______________________________________________________________10

VGA Bypass Operation _____________________________________________________________13

Command Interface ________________________________________________________________13

D-Connector ______________________________________________________________________14

Boundary scan Test_________________________________________________________________14

3.0 Register Control ____________________________________________________________ 17

4.0 Electrical Specifications______________________________________________________ 18

4.1

4.2

4.3

4.4

4.5

Absolute Maximum Ratings __________________________________________________________18

Recommended Operating Conditions___________________________________________________18

Electrical Characteristics ____________________________________________________________19

DC Specifications __________________________________________________________________20

AC Specifications __________________________________________________________________22

5.0 Package Dimensions_________________________________________________________ 24

6.0 Revision History ____________________________________________________________ 26

201-0000-065

Rev. 2.5,

06/07/2011

3

CHRONTEL

CH7021/CH7022

Figures and Tables

List of Figures

Figure 1: Functional Block Diagram .............................................................................................................................2

Figure 2: 64-Pin LQFP Package....................................................................................................................................5

Figure 3: 64-Pin QFN Package......................................................................................................................................6

Figure 4: Control Bus Switch ......................................................................................................................................13

Figure 5: NAND Tree Connection ..............................................................................................................................14

Figure 6: 64 Pin LQFP (Exposed Pad) Package ..........................................................................................................24

Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm) .........................................................................................................25

List of Tables

Table 1: Pin Description................................................................................................................................................7

Table 2: CH7021/CH7022 supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns .....................10

Table 3: Various VGA resolutions. .............................................................................................................................11

Table 4: Supported SDTV standards ...........................................................................................................................11

Table 5: Supported EDTV/HDTV standards...............................................................................................................12

Table 6: Video DAC Configurations for CH7021/CH7022 ........................................................................................12

Table 7: Video Format Identification Using DL1, DL2 and DL3 ...............................................................................14

Table 8: Signal Order in the NAND Tree Testing.......................................................................................................15

Table 9: Signals not Tested in NAND Test besides power pins..................................................................................15

Table 10: Revisions .....................................................................................................................................................26

4

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

1.0 Pin-Out

1.1 Package Diagram

1.1.1

The 64-Pin LQFP Package Diagram

T1

48

1

DL3

SD_DDC

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2

DL2

SC_DDC

SD_PROM

SC_PROM

DVDD

RESET*

AS

3

DL1

4

AGND_TVPLL2

TVCLK-

TVCLK+

5

6

Chrontel

CH7021/CH7022

7

AVDD_TVPLL2

AVDD_TVPLL1

8

DGND

SPD

9

XO

XI/FIN

10

11

12

13

14

15

16

AGND_TVPLL1

DGND

SPC

VSYNC

DVDD

BSCAN

T3

CHSYNC

V5V

VDAC2

Figure 2: 64-Pin LQFP Package

201-0000-065

Rev. 2.5,

06/07/2011

5

CHRONTEL

CH7021/CH7022

1.1.2

The 64-Pin QFN Package Diagram

48

DL3

T1

1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DL2

SD_DDC

SC_DDC

SD_PROM

SC_PROM

DVDD

2

DL1

3

AGND_TVPLL2

TVCLK-

TVCLK+

AVDD_TVPLL2

AVDD_TVPLL1

XO

4

5

6

7

RESET*

AS

Chrontel

CH7021/CH7022

8

9

DGND

SPD

XI/FIN

10

11

12

13

14

15

16

AGND_TVPLL1

DGND

SPC

VSYNC

DVDD

BSCAN

T3

CHSYNC

V5V

VDAC2

Figure 3: 64-Pin QFN Package

6

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

1.2 Pin Description

Table 1: Pin Description

Pin #

Type

Symbol

Description

Test

1,51

Out

T1,T2

These pins are reserved for factory test and default to high impedance. These

pins should be left open in normal operations.

Routed Serial Port Data Output to DDC

2

In/Out

SD_DDC

This pin functions as the bi-directional data pin of the serial port to DDC receiver. This

pin will require a 10k pull-up resistor to the desired high state voltage. Leave open if

unused.

Routed Serial Port Clock Output to DDC

3

4

In/Out

SC_DDC

This pin functions as the clock bus of the serial port to DDC receiver. This pin will

require a 10k pull-up resistor to the desired high state voltage. Leave open if unused.

Routed Data Output to PROM

SD_PROM

This pin functions as the bi-directional data pin of the serial port for PROM on ADD2^◊

card. This pin will require a 10k pull-up resistor to the desired high state voltage. Leave

open if unused.

Routed Clock Output to PROM

5

In/Out

SC_PROM

This pin functions as the clock bus of the serial port to PROM on ADD2 card. This pin

will require a 10k pull-up resistor to the desired high state voltage. Leave open if

unused.

7

In

RESET*

AS

Reset* Input (Internal pull-up)

When this pin is low, the device is held in the power-on reset condition. When this pin

is high, reset is controlled through the serial port register. This pin is 3.3V compliant.

8

In

Address Select (Internal pull-up)

This pin determines the serial port address of the device (0,1,1,1,0,0,AS*,0). When AS

is low the address is 72h, when high the address is 70h.

11

In/Out

SPD

Serial Port Data Input / Output

This pin functions as the bi-directional data pin of the serial port and operates with

inputs from 0 to 2.5V. Outputs are driven from 0 to 2.5V. This pin requires an external

4kΩ - 9 kΩ pull up resistor to 2.5V.

12

14

In/Out

In

SPC

Serial Port Clock Input

This pin functions as the clock input of the serial port and operates with inputs from 0 to

2.5V. This pin requires an external 4kΩ - 9kΩ pull up resistor to 2.5V.

BSCAN

(internal pull low)

BSCAN

This pin should be left open or pulled low with a 10k resistor in the

application. This pin enables the boundary scan for in-circuit testing. Voltage

level is 0 to DVDD. This pin should be pulled low during normal operation.

Test

15

In

T3

(internal pull-down)

This pin should be left open or pulled low with a 10k resistor in the

application.

DAC Output A

Video Digital-to-Analog outputs. Refer to section 2.2.2 for information regarding

support for Composite Video, S-Video, SCART, YPrPb and VGA Bypass outputs.

Each output is capable of driving a 75-ohm doubly terminated load.

18,20,24,28 Out

21,25,29 Out

DACA[3:0]

DACB[2:0]

DAC Output B

Video Digital-to-Analog outputs. Refer to section 2.2.2 for information regarding

supports for Composite Video, S-Video, SCART, YPrPb and VGA Bypass outputs.

Each output is capable of driving a 75-ohm doubly terminated load.

◊

Intel Proprietary.

201-0000-065

Rev. 2.5,

06/07/2011

7

CHRONTEL

CH7021/CH7022

Table 1: Pin Description (contd.)

Pin # Type

22,26,30 Out

Symbol

DACC[2:0]

Description

DAC Output C

Video Digital-to-Analog outputs. Refer to section 2.2.2 for information regarding

supports for Composite Video, S-Video, SCART, YPrPb and VGA Bypass

outputs. Each output is capable of driving a 75-ohm doubly terminated load.

32

34

In

ISET

Current Set Resistor Input

This pin sets the DAC current. A 1.2Kohm (+/- 1%) resistor should be connected

between this pin and DAC ground (pin 31) using short and wide traces.

Out

CHSYNC

Composite / Horizontal Sync Output

A buffered version of VGA composite sync as well as horizontal sync can be

acquired from this pin.

36

39

Out

In

VSYNC

XI/FIN

VSYNC

A buffered version of VGA vertical sync can be acquired from this pin.

Crystal Input / External Reference Input

A parallel resonant 27MHz crystal ( 20 ppm) should be attached between

this pin and XO. However, an external CMOS clock can drive the XI/FIN

input.

40

Out

XO

Crystal Output

A parallel resonance 27MHz crystal ( 20 ppm) should be attached

between this pin and XI/FIN. However, if an external CMOS clock is

attached to the XI/FIN input, XO should be left open.

43,44

TVCLK+/-

Pixel Clock Output

When the chip is operating as a TV encoder in master clock mode, this pair

outputs a differential clock to the VGA controller. The VGA controller uses this

as a reference frequency to generate SDVO_CLK+/- to the chip. The clock

frequency is between 100MHz ~ 200MHz. This clock pair will run at an integer

multiple of the desired input pixel rate. Refer to section 2.1.3 for details.

D-Connector Line 1

Video format identification line for EDTV / HDTV D-Connector. See section 2.5.

D-Connector Line 2

Video format identification line for EDTV / HDTV D-Connector. See section 2.5.

D-Connector Line 3

Video format identification line for EDTV / HDTV D-Connector. See section 2.5.

46

47

48

50

Out

In

DL1

DL2

DL3

RPLL

PLL Resistor Input

External resistor 10Kohm should be connected between this pin and pin

49.

53,54,56,57 In

59,60

SDVO_R+/-,

SDVO_G+/-,

SDVO_B+/-

SDVO_CLK+/-

SDVO Data Channel Inputs

These pins accept 3 AC-coupled differential pair of RGB inputs from a digital

video port of a graphics controller.

Differential Clock Input associated with SDVO Data channel (SDVO_R+/-,

SDVO_G+/-, SDVO_B+/-)

62,63

In

The range of this clock pair is 100~200MHz. For specified pixel rates in specified

modes this clock pair will run at an integer multiple of the pixel rate. Refer to

section 2.1.3 for details.

8

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Table 1: Pin Description (contd.)

Pin #

6,13,35

9,10,37

16

Type

Symbol

DVDD

Description

Digital Supply Voltage (2.5V)

Digital Ground

Power

DGND

VDAC2

DAC Supply Voltage (3.3V)

DAC Ground

17

GDAC2

19

VDAC1

DAC Supply Voltage (3.3V)

DAC Ground

23

GDAC1

27

VDAC0

DAC Supply Voltage (3.3V)

DAC Ground

31

GDAC0

41

AVDD_TVPLL1

AGND_TVPLL1

AVDD_TVPLL2

AGND_TVPLL2

AVDD

TV PLL1 Supply Voltage (2.5V)

TV PLL1 Ground

38

42

TV PLL2 Supply Voltage (2.5V)

TV PLL2 Ground

45

52,58,64 Power

49,55,61 Power

Analog Supply Voltage (2.5V)

Analog Ground

D-Connector Supply Voltage (5V)

AGND

33

Power

V5V

201-0000-065

Rev. 2.5,

06/07/2011

9

CHRONTEL

CH7021/CH7022

2.0 Functional Description

2.1 Input Interface

2.1.1 Overview

One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The

input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate

(SDVO_CLK+/-). The CH7021/CH7022 de-serializes the input into 10-bit parallel data with synchronization and

alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE).

2.1.2 Interface Voltage Levels

All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level

for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The

differential p-p output voltage has a min of 0.8V, with a max of 1.2V.

2.1.3 Input Clock and Data Timing

A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of

the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.

The clock rate runs at 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate

do not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x or 4x depending on the pixel rate) so

that the clock rate will be stay in the 100MHz~200MHz range. In the condition that the clock rate is running at a

multiple of the pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters

(‘0001111010’) are used to stuff the data stream. The CH7021/CH7022 supports the following clock rate multipliers

and fill patterns shown in Table 2.

Table 2: CH7021/CH7022 supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns

Pixel Rate

Clock Rate – Multiplier

Stuffing Format

Data, Fill, Fill, Fill

Data, Fill

Data Transfer Rate - Multiplier

1.00~2.00 Gbits/s – 10xClock Rate

25~50 MP/s

50~100 MP/s

100~200 MHz – 4xPixel Rate

100~200 MHz – 2xPixel Rate

100~200 MP/s 100~200 MHz – 1xPixel Rate

Data

2.1.4 Synchronization

Synchronization and channel-to-channel deskewing is facilitated by the transmission of special characters during the

blank period. The CH7021/CH7022 synchronizes during the initialization period and subsequently uses the blank

periods to re-synch to the data stream.

2.2 TV Output Operation

2.2.1 Overview

The CH7021/CH7022 is capable of being operated as a RGB to SDTV/EDTV/HDTV scaler/encoder, or as an

SDTV/EDTV/HDTV bypass encoder. The output can be CVBS, S-video, SCART or YPrPb. In scaler/encoder

mode, the input can be any resolution of RGB input. The CH7021/CH7022 will scale and format the data and sync

signals to the proper output TV format. Table 3 lists some of the VGA resolutions. Table 4 lists the supported SDTV

standards (refer to SMPTE170, ITU-R BT470). Table 5 lists the supported EDTV/HDTV standards. In TV bypass

mode, input graphics frame size and timing is the same as the required output TV format. The CH7021/CH7022

will format the data and insert proper sync signals according to the output TV standard.

10

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Table 3: Various VGA resolutions.

Name

Resolution

320x200

QVGA

320x240

400x300

640x350, 640x400

VGA

640x480

512x384

704x480, 704x576

720x350, 720x400, 720x480, 720x540, 720x576

768x480, 768x576

SVGA/WSVGA

800x600

832x624

848x480

920x766

960x600

1024x600

XGA/WXGA

1024x768

1124x768

1152x720

1280x768, 1280x720, 1280x800, 1280x960

1280x1024

SXGA/WSXGA

1360x768, 1366x768, 1466X768, 1360x1024

SXGA+/WSXGA+ 1400x1050

1400x1200

1536x960

1680x1050

UXGA/WUXGA

1600x1200

1704x960

1920x1080

1900x1200^[4]

^[4]With reduced blanking.

Table 4: Supported SDTV standards

Standards

NTSC-M

Field Rate (Hz) Total

Scan Type

60/1.001

50

858x525

864x625

Interlaced

NTSC-J

NTSC-443

PAL-60

PAL-M

SECAM-60

PAL-B/D/G/H/I

PAL-N

50

PAL-Nc

50

SECAM-B/D/G/K/K1/L

50

201-0000-065

Rev. 2.5,

06/07/2011

11

CHRONTEL

CH7021/CH7022

Table 5: Supported EDTV/HDTV standards

Standards

Field/Frame Rate(Hz) Total

Active

Clock(MHz) Scan Type

480/60p

SMPTE293M

EIA770.2A

60/1.001

858x525

720x480

27

Progressive

576/50p

720/60p

720/50p

ITU-R BT1358 50

864x625

1650x750

1980x750

720x576

1280x720

27

Progressive

Interlaced

SMPTE296M

60 or 60/1.001

74.25

148.5

74.25

50

1080/60i SMPTE274M

1080/50i SMPTE274M

1080/50i SMPTE295M

1080/30p SMPTE274M

1080/25p SMPTE274M

1080/24p SMPTE274M

1080/60p SMPTE274M

1080/50p SMPTE274M

1080/50p SMPTE295M

1035/60i SMPTE240M

60 or 60/1.001

2200x1125 1920x1080

2640x1125 1920x1080

2376x1250 1920x1080

2200x1125 1920x1080

2640x1125 1920x1080

2750x1125 1920x1080

2200x1125 1920x1080

2640x1125 1920x1080

2376x1250 1920x1080

2200x1125 1920x1035

50

Interlaced

50

Interlaced

30 or 30/1.001

25

Progressive

Interlaced

24 or 24/1.001

60 or 60/1.001

50

60 or 60/1.001

2.2.2 Video DAC Outputs

Table 6 below lists the DAC output configurations of the CH7021/CH7022.

Table 6: Video DAC Configurations for CH7021/CH7022

Output Type

SCART

DACA[0]

DACA[1]

G

DACA[2]

R

DACA[3]

CVBS

B

VGA

G

R

DACB[0]

CVBS

DACB[1]

DACB[2]

CVBS

S-Video

Y

C

DACC[0]

Pb

DACC[1]

Y

DACC[2]

Pr

YPrPb

2.2.3 Adaptive Flicker Filter

The CH7021/CH7022 integrates an advanced up to 7-line (depending on input/output ratio) vertical deflickering

filter circuit to help eliminate the flicker associated with interlaced displays. This flicker circuit provides an adaptive

filter algorithm for implementing flicker reduction with selections of high, medium or low flicker content for both

luma and chroma channels. In addition, a special text enhancement circuit incorporates additional filtering for

enhancing the readability of text. The circuit can automatically calculate the possible flicker settings and it is also

programmable through user input.

2.2.4 Overscan Compensation

The CH7021/CH7022 has the capability of compensating overscan of regular TV displays. Horizontal overscan

adjustment is continuous and has a maximum of –50% compensation depending on input resolution and output

standard. Vertical overscan adjustment requires the input timing to be changed and has a maximum of –50%

compensation. In vertical scaling and overscan compensation mode the input vertical total is required to be a

multiple of 10 lines when the output is interlaced scan type, or a multiple of 20 lines when the output is progressive

scan type.

12

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

2.2.5 SDTV color sub-carrier generation

The CH7021/CH7022 allows the sub-carrier (NTSC, PAL, SECAM) frequency to be accurately generated from a 27

MHz crystal oscillator, leaving the subcarrier frequency independent of the graphics pixel clock frequency. This

feature is important since even a 0.01% subcarrier frequency variation is enough to cause some televisions to lose

color lock.

2.2.6 TV picture adjustment

The CH7021/CH7022 has the capability of vertical and horizontal output picture position adjustment. The

CH7021/CH7022 will automatically put the picture in the display center, and the position is also programmable

through user input. The CH7021/CH7022 also provides brightness/sharpness/contrast adjustment. Hue and

saturation adjustment are also available for NTSC/PAL output formats.

2.2.7 TV reference clock output

The CH7021/CH7022 will operate in Clock Master Mode. The CH7021/CH7022 integrates the low jitter PLL to

generate a reference clock for the graphics controller. The reference clock will be at the input pixel rate and within

100-200MHz. If in some modes the clock rate is below 100MHz, it will be multiplied by 2 or 4 to fall within the

required range.

2.2.8 TV Bypass mode

The CH7021/CH7022 can operate in TV Bypass mode. Input frame size and sync signal are the same as the selected

TV output format. The data and sync signals are extracted and then formatted to the selected TV output standard.

2.3 VGA Bypass Operation

The CH7021/CH7022 can operate in VGA Bypass mode. In VGA Bypass mode, data from the graphics device, after

proper decoding, are bypassed directly to the video DACs to implement a second RGB DAC function. Sync signals,

after proper decoding, are buffered internally, and can be output to drive the RGB. The CH7021/CH7022 can

support a pixel rate of 200MHz. This operating mode uses 8-bits of the DAC’s 10-bit range, and provides a nominal

signal swing of 0.661V (or 0.7V depending on DAC Gain setting in control registers) when driving a 75Ω doubly

terminated load. No scaling, scan conversion or flicker filtering is applied in VGA Bypass modes.

2.4 Command Interface

Communication is through two-wire path, control clock (SPC) and data (SPD). The CH7021/CH7022 accepts

incoming control clock and data from graphics controller, and is capable of redirecting that stream to an ADD2 card

PROM, DDC, or CH7021/CH7022 internal registers. The control bus is able to run up to 1MHz when

communicating with internal registers, up to 400kHz for the PROM and up to 100kHz for the DDC.

Internal

Device

Registers

control

the

observer

switch

on/off

SPC,SPD

DDC

default

position

PROM

Figure 4: Control Bus Switch

201-0000-065

Rev. 2.5,

06/07/2011

13

CHRONTEL

CH7021/CH7022

Upon reset, the default state of the directional switch is to redirect the control bus to the ADD2 PROM. At this

stage, the CH7021/CH7022 observes the control bus traffic. If the observing logic sees a control bus transaction

destined for the internal registers (device address 70h or 72h), it disables the PROM output pairs, and switches to

internal registers. In the condition that traffic is to the internal registers, an opcode command is used to set the

redirection circuitry to the appropriate destination (ADD2 PROM or DDC). Redirecting the traffic to internal

registers while at the stage of traffic to DDC occurs on observing a STOP after a START on the control bus.

2.5 D-Connector

The CH7021/CH7022 provides 3 pins ( DL[3:1] ) to identify the video scanning format and aspect ratio of the

output signal from the encoder for digital broadcasting. An identification signal is discriminated using the voltage

level of the 3 lines. The format of the signals follows EIAJ CP-4120 Interface Between Digital Tuner and Television

Receiver using D-Connector. Table 7 below provides the specification of DL1, DL2 and DL3 for video format

identification. Each line has 3 states depending on its DC voltage.

Table 7: Video Format Identification Using DL1, DL2 and DL3

Typical Voltage

[V]

DL1

Total Scanning Lines

(Effective Scanning Lines)

1125 (1080)

DL2

i or p

DL3

Aspect Ratio

(Note 1)

59.94p, 60p

-

5

2.2

0

16:9

4:3 (Letter Box)

4:3

750 (720)

525 (480)

59.94i, 60i

Note 1: “i” = interlaced scanning, “p” = progressive scanning.

2.6 Boundary scan Test

CH7021/CH7022 provides so called “NAND TREE Testing” to verify IO cell function at the PC board level. This

test will check the interconnection between chip I/O and the printed circuit board for faults (soldering, bend leads,

open printed circuit board traces, etc.). NAND tree test is a simple serial logic which turns all IO cell signals to input

mode, connects all inputs with NAND gates as shown in the figure below and switches each signal to high or low

according to the sequence in Table 8. The test results then pass out at pin 51 (T2).

Figure 5: NAND Tree Connection

Testing Sequence

Set BSCAN =1; (internal weak pull low)

Set all signals listed in Table 8 to 1.

Set all signals listed in Table 8 to 0, toggle one by one with certain time period, suggested 100ns. Pin 51 (T2) will

change its value each time an input value changed.

14

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Table 8: Signal Order in the NAND Tree Testing

Order Pin Name

LQFP Pin

2

1

SD_DDC

SC_DDC

SD_PROM

SC_ PROM

RESETB

AS

2

3

4

5

7

6

8

7

SPD

SPC

11

12

18

20

21

22

24

25

26

28

29

30

32

34

36

39

40

41

42

46

47

48

51

8

9

DACA[3]

DACA[2]

DACB[2]

DACC[2]

DACA[1]

DACB[1]

DACC[1]

DACA[0]

DACB[0]

DACC[0]

ISET

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

CHSYNC

VSYNC

XI/FIN

XO

TVCLK+

TVCLK-

DL1

DL2

DL3

T2

Table 9: Signals not Tested in NAND Test besides power pins

Pin Name

SDVO_R+

SDVO_R-

SDVO_G+

SDVO_G-

SDVO_B+

SDVO_B-

SDVO_CLK+

SDVO_CLK-

RESET*

BSCAN

LQFP Pin

53

54

56

57

59

60

62

63

7

14

15

1

T3

T1

201-0000-065

Rev. 2.5,

06/07/2011

15

CHRONTEL

CH7021/CH7022

16

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

3.0 Register Control

The CH7021/CH7022 is controlled via a serial control port. The serial bus uses only the SC clock to latch data into

registers, and does not use any internally generated clocks so that the device can be written to in all power down

modes. The device will retain all register values during power down modes.

Registers 00h to 11h are reserved for opcode use. All registers except bytes 00h to 11h are reserved for internal

factory use. For details regarding Intel^®SDVO opcodes, please contact Intel^®.

201-0000-065

Rev. 2.5,

06/07/2011

17

CHRONTEL

CH7021/CH7022

4.0 Electrical Specifications

4.1 Absolute Maximum Ratings

Symbol

Description

Min

Typ

Max

Units

All 2.5V power supplies relative to GND

All 3.3V power supplies relative to GND

-0.5

3.0

5.0

V

T

Analog output short circuit duration

Ambient operating temperature

Storage temperature

Indefinite

Sec

°C

SC

-40

-65

85

AMB

STOR

J

150

°C

Junction temperature

°C

Vapor phase soldering (5 second)

Vapor phase soldering (11 second)

Vapor phase soldering (1 minute)

260

245

225

VPS

°C

Note:

1) Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device.

These are stress ratings only. Functional operation of the device at these or any other conditions above those

indicated under the normal operating condition of this specification is not recommended. Exposure to absolute

maximum rating conditions for extended periods may affect reliability. The temperature requirements of vapor

phase soldering apply to all standard and lead free parts.

2) The device is fabricated using high-performance CMOS technology. It should be handled as an ESD sensitive

device. Voltage on any signal pin that exceeds the power supply voltages by more than 0.5V can induce

destructive latchup.

4.2 Recommended Operating Conditions

Symbol

Description

Min

Typ

Max

Units

AVDD

Analog Power Supply Voltage

2.375

2.5

2.625

V

DVDD

Digital Power Supply Voltage

DAC Power Supply

2.375

3.100

2.375

3.100

2.375

4.75

2.5

3.3

2.625

3.500

2.625

3.500

2.625

5.25

V

VDAC

AVDD_TVPLL

VDD33

VDD25

V5V

Analog PLL Power Supply Voltage

Generic for all 3.3V supplies

Generic for all 2.5V supplies

D-Connector Power Supply

Resistor on Iset pin (32)

2.5

V

3.3

V

2.5

V

5.0

V

Rset

1188

-40

1200

1212

85

Ω

°C

Ambient operating temperature

18

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

4.3 Electrical Characteristics

(Operating Conditions: T_A= –40°C to 85°C, VDD25 =2.5V 5%, VDD33 = 3. 3V 5%,)

Symbol

Description

Min

Typ

10

Max

Units

bits

mA

%

Video D/A Resolution

Full scale output current

Video level error

10

35.3

10

I

Total VDD25 supply current (2.5V supplies) with CVBS

output and 1024x768 input

VDD25,CVBS

250

300

310

330

50

280

mA

I

Total VDD25 supply current (2.5V supplies) with S-Video

output and 1024x768 input

VDD25,S-Video

280

350

330

350

60

I

Total VDD25 supply current (2.5V supplies) with YPrPb

720p output and 1024x768 input

VDD25,720p

I

Total VDD25 supply current (2.5V supplies) with YPrPb

1080i output and 1704x960 input

VDD25,1080i

I

Total VDD25 supply current (2.5V supplies) with YPrPb

1080p output and 1704x960 input

VDD25,1080p

I

Total VDD33 supply current (3.3V supply) with CVBS

output and 1024x768 input

VDD33,CVBS

I

Total VDD25 supply current (2.5V supplies) with S-Video

output and 1024x768 input

VDD33,S-Video

90

100

180

160

I

Total VDD33 supply current (3.3V supply) with YPrPb

720p output and 1024x768 input

VDD33,720p

160

140

160

I

Total VDD33 supply current (3.3V supplies) with YPrPb

1080i output and 1704x960 input

VDD25,1080i

I

Total VDD33 supply current (3.3V supplies) with YPrPb

1080p output and 1704x960 input

VDD25,1080p

180

300

I

Total V5V current (5.0V supply)

Total Power Down Current

100

0.1

µA

VDDV

I

mA

PD

201-0000-065

Rev. 2.5,

06/07/2011

19

CHRONTEL

CH7021/CH7022

4.4 DC Specifications

Symbol

Description

Test Condition

Min

Typ

Max

Unit

SDVO Receiver Differential

Input Peak to Peak Voltage

0.175

1.200

V

V_RX-DIFFp-p

V_RX-DIFFp-p= 2 *

V_RX-D+- V_RX-D-



SDVO Receiver DC Differential

Input Impedance

80

40

5

100

50

120

60

Ω

Z_RX-DIFF-DC

SDVO Receiver DC Common

Mode Input Impedance

Z_RX-COM-DC

SDVO Receiver Initial DC

Common Mode Input

Impedance

Impedance allowed

when receiver

terminations are first

turned on

50

60

Z_{RX-COM-INITIAL-}

DC

SDVO Receiver Powered

Down DC Common Mode

Input Impedance

Impedance allowed

when receiver

terminations are not

powered

20k

0.8

200k

Ω

Z_RX-COM-High-

IMP-DC

TVCLK Differential Pk – Pk

Output Voltage

1.2

0.4

V

V_{PP_TVCLK}

1

SPD (serial port data) Output

Low Voltage

V_SDOL

I

= 2.0 mA

OL

2

Serial Port (SPC, SPD) Input

High Voltage

2.0

GND-0.5

0.25

+5V

+0.5

V_SPIH

2

Serial Port (SPC, SPD) Input

Low Voltage

0.4

V_SPIL

Hysteresis of Serial Port Inputs

V

V_HYS

DDC Serial Port

+5V

+0.5

V_DDCIH

Input High Voltage

DDC Serial Port

4.0

V

V_DDCIL

V_PROMIH

V_PROMIL

Input Low Voltage

PROM Serial Port

Input High Voltage

PROM Serial Port

Input Low Voltage

SPD (serial port data) Output

GND-0.5

4.0

0.4

+5V

+0.5

GND-0.5

0.4

3

Input is V_INLat

0.9*V_INL

V_{SD_DDCOL}

Low Voltage from SD_DDC (or SD_DDC or

SD_EPROM.

+ 0.25

SD_EPROM)

4.0kΩ pullup to 2.5V.

4

SC_DDC and SD_DDC Output Input is V_INLat SPC

and SPD.

0.933*V_INL

+ 0.35

V

V_DDCOL

Low Voltage

5.6kΩ pullup to 5.0V.

5

SC_EPROM and SD_EPROM Input is V_INLat SPC

and SPD.

0.933*V_INL

+ 0.35

V_EPROMOL

Output Low Voltage

5.6kΩ pullup to 5.0V.

20

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Symbol

Description

Test Condition

Min

Typ

Max

VDD33

+ 0.5

0.5

Unit

6

7

RESET*

2.7

V

V_MISC1IH

Input High Voltage

RESET*

GND-0.5

V

V_MISC1IL

Input Low Voltage

AS, BSCAN, T3

2.0

GND-0.5

10

VDD25

+ 0.5

V

V_MISC2IH

Input High Voltage

7

AS, BSCAN, T3

DVDD=2.5V

0.5

30

V_MISC2IL

Input Low Voltage

AS, RESET*

V_IN= 0V

µA

I_PU

Pull Up Current

BSCAN, T3

V_IN= 2.5V

10

µA

I_PD

Pull Down Current

CHSYNC, VSYNC

Output High Voltage

8

2.0

V

V_SYNCOH

I

= -0.4mA

OH

8

CHSYNC, VSYNC

Output Low Voltage

I_OL= 3.2mA

0.4

V

V_SYNCOL

DL[3:1]

3.5

1.4

0

5.0

2.4

0.8

13

V

100kΩ load

DC

DL_OH

DL_OM

DL_OL

Z_DL

Output High Voltage

DL[3:1]

2.0

10

Output Mid Voltage

DL[3:1]

V

Output Low Voltage

DL[3:1]

7

kΩ

Output Impedance

Notes:

1.

V

_SDOLis the SPD output low voltage when transmitting from internal registers, not from DDC or EEPROM.

2. V_SPIHand V_SPILare the serial port (SPC and SPD) input low voltage when transmitting to internal registers. Separate

requirements may exist for transmission to the DDC and EEPROM.

3. V_{SD_DDCOL}is the output low voltage at the SPD pin when the voltage at SD_DDC or SD_EPROM is V_INL. Maximum output

voltage has been calculated with a worst case pullup of 4.0kΩ to 2.5V on SPD.

4. V_DDCOLis the output low voltage at the SC_DDC and SD_DDC pins when the voltage at SPC and SPD is V_INL. Maximum output

voltage has been calculated with 5.6k pullup to 5V on SC_DDC and SD_DDC.

5. V_EPROMOLis the output low voltage at the SC_EPROM and SD_EPROM pins when the voltage at SPC and SPD is V_INL

Maximum output voltage has been calculated with 5.6kΩ pullup to 5V on SC_EPROM and SD_EPROM.

.

6.

7.

V

MISC1 - refers to RESET* input which is 3.3V compliant.

MISC2 - refers to AS, BSCAN, T3 which are 2.5V compliant

V

8. V_SYNC– refers to CHSYNC and VSYNC outputs.

201-0000-065

Rev. 2.5,

06/07/2011

21

CHRONTEL

CH7021/CH7022

4.5 AC Specifications

Symbol

Description

Test Condition

Min

Typ

Max

Unit

SDVO Receiver Unit Interval for

Data Channels

Typ. –

300ppm

1/[Data

Transfer

Rate]

Typ.

+ 300ppm

ps

UI_DATA

SDVO CLK Input Frequency

100

25

200

165

MHz

f_{SDVO_CLK}

f_PIXEL

SDVO Receiver Pixel

frequency

SDVO Receiver Symbol

frequency

1

2

GHz

UI

f_SYMBOL

t_RX-EYE

SDVO Receiver Minimum Eye

Width

0.4

SDVO Receiver Max. time

between jitter median and max.

deviation from median

0.3

UI

t_{RX-EYE-JITTER}

SDVO Receiver AC Peak

Common Mode Input Voltage

150

mV

V_RX-CM-ACp

Differential Return Loss

50MHz – 1.25GHz

15

6

dB

RL_RX-DIFF

RL_RX-CM

T_SPR

Common Mode Return Loss

SPC, SPD Rise Time

(20% - 80%)

Standard mode 100k

Fast mode 400k

1000

300

150

300

150

300

ns

1M running speed

Standard mode 100k

Fast mode 400k

SPC, SPD Fall Time

(20% - 80%)

T_SPF

1M running speed

Fast mode 400K

SC_PROM, SD_PROM Rise

Time (20% - 80%)

T_PROMR

T_PROMF

T_DDCR

T_DDCF

SC_PROM, SD_PROM Rise

Time (20% - 80%)

Fast mode 400K

300

1000

300

ns

SC_DDC, SD_DDC Rise Time Standard mode 100k

(20% - 80%)

SC_DDC, SD_DDC Fall

Time (20% - 80%)

Standard mode 100k

1

SC_DDC, SD_DDC Rise Time Standard mode 100k

Delay (50%)

0

3

ns

T_DDCR-DELAY

1

SC_DDC, SD_DDC Fall

Time Delay (50%)

Standard mode 100k

T_DDCF-DELAY

SDVO Receiver Total Lane to

Lane Skew of Inputs

Across all lanes

2

ns

t_SKEW

t_R

CHSYNC and VSYNC (when

configured as outputs)

15pF load

1.50

DVDD = 2.5V

Output Rise Time

(20% - 80%)

H and V (when configured as

outputs)

15pF load

1.50

ns

t_F

DVDD = 2.5V

Output Fall Time

(20% - 80%)

22

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Notes:

1. Refers to the figure below, the delay refers to the time pass through the internal switches.

3.3V typ.

2.5V typ.

R=5K

To SPC/SPD pin

To DDC pin

201-0000-065

Rev. 2.5,

06/07/2011

23

CHRONTEL

CH7021/CH7022

5.0 Package Dimensions

TOP VIEW

BOTTOM VIEW

A

B

K

48

49

33

32

B

A

K

64

17

1

16

EXPOSED PAD

C

D

F

E

I

.008"

J

H

G

Figure 6: 64 Pin LQFP (Exposed Pad) Package

SYMBOL

Table of Dimensions

No. of Leads

A

B

C

D

E

F

G

H

I

J

K

64 (10 X 10 mm)

Milli-

meters

MIN

0.17

0.27

1.35

1.45

0.05

0.15

0.45

0.75

0.09

0.20

0°

7°

5.85

7

12

10

0.50

1.00

MAX

Notes:

1. Conforms to JEDEC standard JESD-30 MS-026D.

2. Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm.

3. Dimension B does not include allowable mold protrusions up to 0.25 mm per side.

24

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

TOP VIEW

BOTTOM VIEW

B

A

B/2

16

1

16

17

64

Pin 1

A

C

C/2

32

49

32

F

48

33

48

E

D

I

G

H

Figure 7: 64 Pin QFN Package (8 x 8 x 0.8mm)

SYMBOL

Table of Dimensions

No. of Leads

64 (8 X 8 mm)

A

8

B

C

D

E

F

G

H

0

I

Milli-

meters

MIN

6.1

6.3

6.1

6.3

0.15

0.25

0.35

0.45

0.7

0.8

0.4

0.203

MAX

0.05

Notes:

1. Conforms to JEDEC standard JESD-30 MO-220.

201-0000-065

Rev. 2.5,

06/07/2011

25

CHRONTEL

CH7021/CH7022

6.0 Revision History

Table 10: Revisions

Rev. # Date

Section

All

Description

1.0

1.1

3/21/05

First official release.

4/28/05

9/14/05

4.3

Updated symbol names and descriptions

Changed DL_OMlimits

Added video switch

4.4

1.2

Figure 1

4.2

Added reset specification

1.2

Added “10k resistor” to descriptions of pin 3, 4, 5.

Updated descriptions of SPD, SPC, DDC, and PROM

Updated section 4.3 Electrical Characteristics

Added a 64-QFN package.

10/12/05 4.4, 4.5

1.22

1.3

1.31

2.0

2.1

2.2

2.3

2.4

2.5

4/6/07

4.3

10/3/07

1.1, 5.0

10/26/07 4.4

Change VDD5+ to +5V

3/21/08

4/21/08

All

Combined CH7021 and CH7022.

Ordering Information

Added 64 QFN package for CH7022A

Added Ambient operating temperature.

Make some description more clear.

10/30/08 4.2

03/02/10 Features, Table3

05/10/10 Figure 1, Table 1

06/07/11 4.1, 4.2, 4.3

Make some pin type clear.

Update ambient operating temperature to industrial standard.

26

201-0000-065

Rev. 2.5,

06/07/2011

CHRONTEL

CH7021/CH7022

Disclaimer

This document provides technical information for the user. Chrontel reserves the right to make changes at any time

without notice to improve and supply the best possible product and is not responsible and does not assume any

liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use

of our products and assume no liability for errors contained in this document. The customer should make sure that

they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the

products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not

infringe upon or assist others to infringe upon such rights.

Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT

SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF

Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used

as directed can reasonably expect to result in personal injury or death.

ORDERING INFORMATION

Number of

Pins

Part Number

Package Type

Voltage Supply

2.5V & 3.3V

Lead Free LQFP

with exposed pad

Lead Free LQFP

with exposed pad

in Tape & Reel

CH7021A-TEF

64

CH7021A-TEF-TR

64

2.5V & 3.3V

CH7021A-BF

CH7021A-BF-TR

CH7022A-TEF

Lead Free QFN

64

2.5V & 3.3V

Lead Free QFN

in Tape & Reel

Lead Free LQFP

with exposed pad

Lead Free LQFP

with exposed pad

in Tape & Reel

CH7022A-TEF-TR

64

2.5V & 3.3V

CH7022A-BF

Lead Free QFN

64

2.5V & 3.3V

Lead Free QFN

in Tape & Reel

CH7022A-BF-TR

Chrontel

2210 O’Toole Avenue, Suite 100,

San Jose, CA 95131-1326

Tel: (408) 383-9328

Fax: (408) 383-9338

www.chrontel.com

E-mail: sales@chrontel.com

Printed in the U.S.A.

201-0000-065

Rev. 2.5,

06/07/2011

27


型号：	CH7021A-TEF
厂家：	CHRONTEL, INC
描述：	Color Signal Encoder, CMOS, PQFP64, 10 X 10 MM, LEAD FREE, MS-026D, LQFP-64 编码器商用集成电路
文件：	总27页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CH7021A-TEF [CHRONTEL]

相关型号：

CH7021A-TEF-TR

CH7021A-TEW

CH7021A-TEW-TR

CH70220UH+/-10%B

CH70220UH+/-10%V

CH70220UH10%V

CH7022A-BF

CH7022A-BF-I

CH7022A-BF-I-TR

CH7022A-BF-TR

CH7022A-TEF

CH7022A-TEF-I