CM6904IZ [CHAMP]
Low Pin Count PFC/PWM Controller Combo; 低引脚数PFC / PWM控制器组合
| 型号： | CM6904IZ |
| 厂家： | 
CHAMPION MICROELECTRONIC CORP. |
| 描述： | Low Pin Count PFC/PWM Controller Combo |
| 文件： | 总14页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
GENERAL DESCRIPTION
FEATURES
The CM6903/4 is a space-saving PFC-PWM controller for ꢀ
power factor corrected, switched mode power supplies that
Patent Number #5,565,761, #5,747,977, #5,742,151,
#5,804,950, #5,798,635
offers very low start-up and operating currents. For the
ꢀ
Pin to pin compatible with FAN6903/4
power supply less than 500Watt, its input current shaping ꢀ
Enable lowest BOM for power supply with PFC
Internally synchronized PFC and PWM in one IC
Patented slew rate enhanced voltage error amplifier with
advanced input current shaping technique
Universal Line Input Voltage
CCM boost or DCM boost with leading edge modulation
PFC using Input Current Shaping Technique
Feedforward IAC pin to do the automatic slope
compensation
PFC performance could be very close to CM6800 or
ML4800 architecture.
ꢀ
ꢀ
Power Factor Correction (PFC) offers the use of smaller, ꢀ
lower cost bulk capacitors, reduces power line loading and ꢀ
stress on the switching FETs, and results in a power supply
fully compliant to IEC1000-3-2 specifications. The
CM6903/4 includes circuits for the implementation of a
ꢀ
leading edge, input current shaping technique “boost” type ꢀ
PFC and a trailing edge, PWM.
PFCOVP, PFC VCCOVP, Precision -1V PFC ILIMIT,
Tri-Fault Detect comparator to meet UL1950
No bleed resistor required
ꢀ
The CM6903’s PFC and PWM operate at the same
frequency, 67kHz. The PFC frequency of the CM6904 is
automatically set at half that of the 134kHz PWM. This
higher frequency allows the user to design with smaller
PWM components while maintaining the optimum operating
frequency for the PFC. An PFC OVP comparator shuts
ꢀ
Low supply currents; start-up: 100uA typical, operating
current: 2mA typical.
Synchronized leading PFC and trailing edge modulation
PWM to reduce ripple current in the storage capacitor
between the PFC and PWM sections and to reduce
switching noise in the system
ꢀ
down the PFC section in the event of a sudden decrease in ꢀ
load. The PFC section also includes peak current limiting
VINOK Comparator to guarantee to enable PWM when
PFC reach steady state
for enhanced system reliability.
ꢀ
ꢀ
ꢀ
ꢀ
High efficiency trailing-edge current mode PWM
UVLO, REFOK, and brownout protection
Digital PWM softstart: CM6903 (10ms), CM6904 (5ms)
Precision PWM 1.5V current limit for current mode
operation
24 Hours Technical Support---WebSIM
Champion provides customers an online circuit simulation tool
called WebSIM. You could simply logon our website at
www.champion-micro.com for details.
APPLICATIONS
PIN CONFIGURATION
SIP-09 (Z09)
SOP-16 (S16)
Top View
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Desktop PC Power Supply
AC Adaptor
Front View
1
2
3
4
5
6
7
8
NC
16
15
14
13
12
11
10
9
Internet Server Power Supply
IPC Power Supply
PFCOUT
NC
GND
GND
PWMOUT
UPS
Battery Charger
DC Motor Power Supply
Monitor Power Supply
Telecom System Power Supply
Distributed Power
NC
VCC
NC
ISENSE
VEAO
1
2
3
4
5
6
7
8
9
VFB
IAC
DC ILIMIT
NC
NC
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 1
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
PIN DESCRIPTION
Operating Voltage
Description
Pin No.
Symbol
Min.
Typ.
Max.
Unit
1
DC ILIMIT
PWM current limit comparator input
Positive supply
0
1.5
V
2
3
4
5
6
7
8
9
VCC
10
0
15
23
V
V
V
PWM OUT
PFC OUT
GND
PWM driver output
PFC driver output
Ground
VCC
VCC
0
ISENSE
VEAO
VFB
Current sense input to the PFC current limit comparator
PFC transconductance voltage error amplifier output
-5
0
0.7
6
V
V
V
V
PFC transconductance voltage error amplifier input
0
2.5
3
IAC
Feedforward input to do slope compensation and to start up
the system
0
1
BLOCK DIAGRAM
9
2
IAC
VCC
VREFOK
R1C
4K ohm
R1B
+
U1
.
ISENSE
400K ohm
R1A
-
6
+
OUT
.
-
+
100K ohm
.
S
Q
ISENSEAMP
4
+
SUM
R
R
VREF OK
PFCCMP
PFCOUT
Q
VFB
gmv
8
-
UVLO
RAMP
.
.
.
2.5V
+
VCC
UVLO
.
.
FAULTB
7
VEAO
VCC OVP
VCC
+
17.9V
16.4V
.
-
-
OSC
PFCCLKB
PWMCLK
PFCCLKB
PWMCLK
Tri-Fault
Detect
.
.
-
.
3
VIN OK
-
0.5V
+
VREF OK
VFB
S
Q
Q
PWMOUT
.
R
R
2.45V
+
+
PFC OVP
0.75V
+
R
2.75V
2.5V
.
-
-
1.5V
-
-
.
+
10mS
-
PWMCMP
.
.
.
CM6903
fpfc= 67KHz
fpwm=67KHz
CM6904
fpfc= 67KHz
fpwm=134KHz
-1V
+
.
PFC ILIMIT
PWM CLK
SS
1V
1
5
DCILIMIT
GND
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 2
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
ORDERING INFORMATION
Part Number
CM6903IZ
CM6903IS
CM6904IZ
Temperature Range
-40℃ to 125℃
-40℃ to 125℃
-40℃ to 125℃
Package
9-Pin SIP (Z09)
16-Pin SOP (S16)
9-Pin SIP (Z09)
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are those values beyond which the device could be permanently damaged.
Parameter
Min.
Max.
23
Units
V
VCC MAX
IAC (after start up)
ISENSE Voltage
PFC OUT
GND-0.3
-5
1.0
V
0.7
V
GND – 0.3
GND – 0.3
0
VCC + 0.3
VCC + 0.3
6.3
V
PWM OUT
V
VEAO
V
Voltage on Any Other Pin
ICC Current (Average)
GND – 0.3
VREF + 0.3
40
V
mA
A
Peak PFC OUT Current, Source or Sink
Peak PWM OUT Current, Source or Sink
PFC OUT, PWM OUT Energy Per Cycle
Junction Temperature
0.5
0.5
A
1.5
µJ
℃
℃
150
Storage Temperature Range
-65
-40
150
℃
℃
℃/W
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Thermal Resistance (θJA)
125
260
80
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=+15V,
TA=Operating Temperature Range (Note 1)
CM6903/4
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
Voltage Error Amplifier (gmv
)
Input Voltage Range
0
30
2.45
5
90
2.55
-1.0
V
µmho
V
µA
V
Transconductance
Feedback Reference Voltage
Input Bias Current
Output High Voltage
Output Low Voltage
Sink Current
Source Current
Open Loop Gain
Power Supply Rejection Ratio
VNONINV = VINV, VEAO = 3.75V
Note 2
65
2.5
-0.5
6.0
0.1
-35
40
5.8
0.4
V
VFB = 3V, VEAO = 6V
VFB = 1.5V, VEAO = 1.5V
-20
30
50
50
µA
µA
dB
dB
60
60
11V < VCC < 16.5V
IAC
Input Impedance
ISENSE = 0V
850
1000
1150
Ohm
VCC OVP Comparator
Threshold Voltage
Hysteresis
17.4
1.4
17.9
1.5
18.4
1.65
V
V
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 3
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply
Vcc=+15V, RT = 52.3kΩ, CT = 470pF, TA=Operating Temperature Range (Note 1)
CM6903/4
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
PFC OVP Comparator
Threshold Voltage
Hysteresis
2.70
230
2.77
2.85
290
V
mV
PFC ILIMIT Comparator
VIN OK Comparator
Threshold Voltage
Delay to Output
-0.9
-1
150
-1.15
300
V
ns
Threshold Voltage
Hysteresis
2.35
1.65
2.45
1.75
2.55
1.85
V
V
PWM Digital Soft Start
Right After Start Up (CM6903)
Right After Start Up (CM6904)
DC ILIMIT Comparator
10
5
ms
ms
Digital Soft Start Timer (Note 2)
Threshold Voltage
1.4
1.5
1.6
V
Delay to Output (Note 2)
150
300
ns
Tri-Fault Detect Comparator
Fault Detect HIGH
2.65
2.75
2
2.85
4
V
ms
V
VFB=VFAULT DETECT LOW to VFB = OPEN,
470pF from VFB to GND
Time to Fault Detect HIGH
Fault Detect LOW
0.4
62
0.5
0.6
Oscillator
TA = 25℃
Initial Accuracy
Voltage Stability
Temperature Stability
Total Variation
PFC Dead Time (Note 2)
67
1
2
67
0.45
74
kHz
%
%
kHz
µs
10V < VCC < 15V
Line, Temp
60
0.3
74.5
0.65
PFC
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Impedance
IAC=100uA,VFB=2.55V, ISENSE = 0V
IAC=0uA,VFB=2.0V, ISENSE = 0V
0
%
%
ohm
V
V
ohm
V
90
95
8
0.8
0.4
8
15
1.5
0.8
15
IOUT = -100mA
IOUT = -10mA, VCC = 8V
Output Low Voltage
Output High Impendence
Output High Voltage
Rise/Fall Time (Note 2)
IOUT = 100mA, VCC = 15V
CL = 1000pF
13.5
14.2
50
ns
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 4
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply
Vcc=+15V, RT = 52.3kΩ, CT = 470pF, TA=Operating Temperature Range (Note 1)
CM6903/4
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
PWM
CM6903
CM6904
0-49.5
0-49.5
0-50
0-50
15
1.5
1.5
15
%
%
ohm
V
V
ohm
V
Duty Cycle Range
Output Low Impedance
Output Low Voltage
8
0.8
0.7
8
14.2
50
IOUT = -100mA
IOUT = -10mA, VCC = 8V
Output High Impendence
Output High Voltage
Rise/Fall Time (Note 2)
IOUT = 100mA, VCC = 15V
CL = 1000pF
13.5
ns
Supply
Start-Up Current
Operating Current
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
VCC = 11V, CL = 0
VCC = 15V, CL = 0
100
2.5
15
5
150
4.0
15.3
5.15
uA
mA
V
14.7
4.85
V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Guaranteed by design, not 100% production test.
TYPICAL PERFORMANCE CHARACTERISTIC
127
120
113
106
99
92
85
78
71
64
57
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VFB (V)
3
Voltage Error Amplifier (gmv) Transconductance
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 5
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
Functional Description
Detailed Pin Descriptions
The CM6903/4 consists of an ICST (Input Current Shaping
Technique), CCM (Continuous Conduction Mode) or DCM
(Discontinuous Conduction Mode) boost PFC (Power
Factor Correction) front end and a synchronized PWM
(Pulse Width Modulator) back end. The CM6903/4 is pin to
pin compatible with FAN6903/4 (9 pin SIP package), which
is the second generation of the ML4803 with 8 pin package.
It is distinguished from earlier combo controllers by its low
count, innovative input current shaping technique, and very
low start-up and operating currents. The PWM section is
dedicated to peak current mode operation. It uses
DCILIMIT (Pin 1)
This pin is tied to the primary side PWM current sense
resistor or transformer. It provides the internal pulse-by-pulse
current limit for the PWM stage (which occurs at 1.5V) and
the peak current mode feedback path for the current mode
control of the PWM stage. Besides current information, the
optocouple also goes into DCILIMIT pin. Therefore, it is the
SUM Amplifier input.
VCC (Pin 2)
VCC is the power input connection to the IC. The VCC
start-up current is 100uA. The no-load ICC current is 2mA.
VCC quiescent current will include both the IC biasing
currents and the PFC and PWM output currents. Given the
operating frequency and the MOSFET gate charge (Qg),
average PFC and PWM output currents can be calculated as
IOUT = Qg x F. The average magnetizing current required for
any gate drive transformers must also be included. The VCC
pin is also assumed to be proportional to the PFC output
voltage. Internally it is tied to the VCC OVP comparator
(17.9V) providing redundant high-speed over-voltage
protection (OVP) of the PFC stage. VCC also ties internally
to the UVLO circuitry and VREFOK comparator, enabling the
IC at 15V and disabling it at 10V. VCC must be bypassed
with a high quality ceramic bypass capacitor placed as close
as possible to the IC. Good bypassing is critical to the proper
operation of the CM6903/4.
conventional trailing-edge modulation, while the PFC uses
leading-edge modulation. This patented Leading
Edge/Trailing Edge (LETE) modulation technique helps to
minimize ripple current in the PFC DC buss capacitor.
The main improvements from ML4803 are:
1.) Remove the one pin error amplifier and add back
the slew rate enhancement gmv, which is using
voltage input instead of current input. This
transconductance amplifier will increase the
transient response 5 to 10 times from the
conventional OP
2.) VFB PFC OVP comparator
3.) Tri-fault Detect for UL1950 compliance and
enhanced safety
4.) A feedforward signal from IAC pin is added to do
the automatic slope compensation. This
increases the signal to noise ratio during the light
load; therefore, THD is improved at light load and
high input line voltage.
VCC is typically produced by an additional winding off the
boost inductor or PFC Choke, providing a voltage that is
proportional to the PFC output voltage. Since the VCC OVP
max voltage is 17.9V, an internal shunt limits VCC
5.) CM6903 does not require the bleed resistor and
it uses the less than 500k ohm resistor between
IAC pin and rectified line voltage to feed the
initial current before the chip wakes up.
6.) VINOK comparator is added to guaranteed PWM
cannot turn on until VFB reaches 2.5V in which PFC
boost output is about steady state, typical 380V.
7.) A 10mS digital PWM soft start circuit is added
8.) 9 pin SIP package
overvoltage to an acceptable value. An external clamp, such
as shown in Figure 1, is desirable but not necessary.
VCC
9.) No internal Zener but with VCCOVP comparator
The CM6903 operates both PFC and PWM sections at
67kHz, while the CM6904 operates the PWM section at
twice the frequency (134kHz) of the PFC. This allows the
use of smaller PWM magnetic and output filter components,
while minimizing switching losses in the PFC stage.
1N5250B
Several protection features have been built into the
CM6903/4. These include soft-start, redundant PFC
overvoltage protection, Tri-Fault Detect, VINOK, peak
current limiting, duty cycle limiting, under-voltage lockout,
reference ok comparator and VCCOVP.
GND
Figure 1. Optional VCC Clamp
This limits the maximum VCC that can be applied to the IC
while allowing a VCC which is high enough to trip the VCC
OVP. An RC filter at VCC is required between boost trap
winding and VCC.
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 6
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
PFC OUT (Pin 4) and PWM OUT (Pin3)
the input filter capacitor in these supplies, causes brief
PFC OUT and PWM OUT are the high-current power driver
capable of directly driving the gate of a power MOSFET
with peak currents up to -1A and +0.5A. Both outputs are
actively held low when VCC is below the UVLO threshold
level which is 15V or VREFOK comparator is low.
high-amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line
voltage. Such supplies present a power factor to the line of
less than one (i.e. they cause significant current harmonics of
the power line frequency to appear at their input). If the input
current drawn by such a supply (or any other nonlinear load)
can be made to follow the input voltage in instantaneous
amplitude, it will appear resistive to the AC line and a unity
power factor will be achieved.
GND (Pin 5)
GND is the return point for all circuits associated with this
part. Note: a high-quality, low impedance ground is critical
to the proper operation of the IC. High frequency grounding
techniques should be used.
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the CM6903/4 uses a
boost-mode DC-DC converter to accomplish this. The input
to the converter is the full wave rectified AC line voltage. No
bulk filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges (at twice line
frequency) from zero volts to the peak value of the AC input
and back to zero.
ISENSE (Pin 6)
This pin ties to a resistor which senses the PFC input
current. This signal should be negative with respect to the
IC ground. It internally feeds the pulse-by-pulse current limit
comparator and the current sense feedback signal. The
ILIMIT trip level is –1V. The ISENSE feedback is internally
multiplied by a gain of four and compared against the
internal programmed ramp to set the PFC duty cycle. The
intersection of the boost inductor current downslope with
the internal programming ramp determines the boost
off-time.
By forcing the boost converter to meet two simultaneous
conditions, it is possible to ensure that the current draws
from the power line matches the instantaneous line voltage.
One of these conditions is that the output voltage of the
boost converter must be set higher than the peak value of
the line voltage. A commonly used value is 385VFB, to allow
for a high line of 270VACrms. The other condition is that the
current that the converter is allowed to draw from the line at
any given instant must be proportional to the line voltage.
It requires a RC filter between ISENSE and PFC boost
sensing resistor.
VEAO (Pin 7)
This is the PFC slew rate enhanced transconductance
amplifier output which needs to connected with a
compensation network.
VFB (Pin 8)
PFC Control: Leading Edge Modulation with Input
Current Shaping Technique
(I.C.S.T.)
Besides this is the PFC slew rate enhanced
transconductance input, it also tie to a couple of protection
comparators, PFCOVP, and Tri-Fault Detect
The only differences between the conventional PFC control
topology and I.C.S.T. is:
IAC (pin 9)
Typically, it has a feedforward resistor, RAC, 100K~200K
ohm resistor connected between this pin and rectified line
input voltage.
the current loop of the conventional control method is a close
loop method and it requires a detail understanding about the
system loop gain to design. With I.C.S.T., since the current
loop is an open loop, it is very straightforward to implement it.
This pin serves 2 purposes:
1.) During the startup condition, it supplies the startup
current; therefore, the system does not requires
additional bleed resistor to start up the chip.
2.) The current of RAC will program the automatic
slope compensation for the system. This
feedforward signal can increase the signal to noise
ratio for the light load condition or the high input
line voltage condition.
The end result of the any PFC system, the power supply is
like a pure resistor at low frequency. Therefore, current is in
phase with voltage.
In the conventional control, it forces the input current to
follow the input voltage. In CM6903, the chip thinks if a boost
converter needs to behave like a low frequency resistor, what
the duty cycle should be.
Power Factor Correction
The following equations is CM6903 try to achieve:
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to the
line voltage, so the power factor is unity (one). A common
class of nonlinear load is the input of most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect, which occurs on
Vin
Re =
(1)
(2)
Iin
Il = Iin
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 7
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
Equation 2 means: average boost inductor current equals
(d ' )2 ×Vout
to input current.
Id × d ' =
Vin × Il ≈ Vout × Id
(3)
Re
Therefore, input instantaneous power is about to equal to
the output instantaneous power.
d' ×Vout
Id =
Id =
(8)
Re
For steady state and for the each phase angle, boost
converter DC equation at continuous conduction mode is:
toff
Vout
×
Re Tsw
Vout
1
=
(4)
Vin
(1− d)
From this simple equation (8), we implement the PFC control
section of the CM6903.
Rearrange above equations, (1), (2),(3), and (4) in term of
Vout and d, boost converter duty cycle and we can get
average boost diode current equation (5):
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
ON right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned OFF. When
the switch is ON, the inductor current will ramp up. The
effective duty cycle of the trailing edge modulation is
determined during the ON time of the switch. Figure 2 shows
a typical trailing edge control scheme.
(1− d)2 ×Vout
Id =
(5)
Re
Also, the average diode current can be expressed as:
Toff
1
Id =
Id (t) dt
(6)
∫
0
Tsw
If the value of the boost inductor is large enough, we can
assume Id (t) ~ Id . It means during each cycle or we
can say during the sampling, the diode current is a
constant.
In case of leading edge modulation, the switch is turned OFF
right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during OFF time of the switch. Figure 3 shows a leading
edge control scheme.
Therefore, equation (6) becomes:
Id × toff
Id =
= Id × d ' = Id × (1− d) (7)
Tsw
Combine equation (7) and equation (5), and we get:
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 8
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
One of the advantages of this control technique is that it
ZCV: Compensation Net Work for the Voltage Loop
GMv: Transconductance of VEAO
PIN: Average PFC Input Power
required only one system clock. Switch 1(SW1) turns OFF
and switch 2 (SW2) turns ON at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With such
synchronized switching, the ripple voltage of the first stage
is reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method,
substantially reducing dissipation in the high-voltage PFC
capacitor.
VOUTDC: PFC Boost Output Voltage; typical designed value is
380V.
CDC: PFC Boost Output Capacitor
∆VEAO: This is the necessary change of the VEAO to deliver
the designed average input power. The average value is
6V-3V=3V since when the input line voltage increases, the
delta VEAO will be reduced to deliver the same to the output.
To over compensate, we choose the delta VEAO is 3V.
Typical Applications
Internal Voltage Ramp
PFC Section:
The internal ramp current source is programmed by way of
VEAO pin voltage. When VEAO increases the ramp current
source is also increase. This current source is used to
develop the internal ramp by charging the internal 30pF +12/
-10% capacitor. The frequency of the internal programming
ramp is set internally to 67kHz.
PFC Voltage Loop Error Amp, VEAO
The ML4803 utilizes an one pin voltage error amplifier in
the PFC section (VEAO). In the CM6903/4, it is using the
slew rate enhanced transconductance amplifier, which is
the same as error amplifier in the CM6800. The unique
transconductance profile can speed up the conventional
transient response by 10 times. The internal reference of
the VEAO is 2.5V. The input of the VEAO is VFB pin.
Design PFC ISENSE Filtering
ISENSE Filter, the RC filter between Rs and ISENSE:
PFC Voltage Loop Compensation
There are 2 purposes to add a filter at ISENSE pin:
1.) Protection: During start up or inrush current
conditions, it will have a large voltage cross Rs,
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE Filter to attenuate
the energy.
The voltage-loop bandwidth must be set to less than 120Hz
to limit the amount of line current harmonic distortion. A
typical crossover frequency is 30Hz.
The Voltage Loop Gain (S)
2.) Reduce L, the Boost Inductor: The ISENSE Filter
also can reduce the Boost Inductor value since the
ISENSE Filter behaves like an integrator before
going ISENSE which is the input of the current error
amplifier, IEAO.
∆VOUT
∆VFB ∆VEAO
=
≈
*
*
∆VEAO ∆VOUT
∆VFB
P
IN *2.5V
*GM *ZCV
V
V
OUTDC2 *∆VEAO *S*CDC
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 9
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
PWM section wakes up after PFC reaches steady state
The ISENSE Filter is a RC filter. The resistor value of the
ISENSE Filter is between 100 ohm and 50 ohm. By selecting
RFILTER equal to 50 ohm will keep the offset of the IEAO less
than 5mV. Usually, we design the pole of ISENSE Filter at
fpfc/6, one sixth of the PFC switching frequency. Therefore,
the boost inductor can be reduced 6 times without
disturbing the stability. Therefore, the capacitor of the ISENSE
Filter, CFILTER, will be around 283nF.
PWM section is off all the time before PFC VFB reaches
2.45V. Then internal 10mS digital PWM soft start circuit
slowly ramps up the soft-start voltage.
PFC OVP Comparator
PFC OVP Comparator sense VFB pin which is the same the
voltage loop input. The good thing is the compensation
network is connected to VEAO. The PFC OVP function is a
relative fast OVP. It is not like the conventional error amplifier
which is an operational amplifier and it requires a local
feedback and it make the OVP action becomes very slow.
The threshold of the PFC OVP is 2.5V+10% =2.75V with
250mV hysteresis.
IAC, RAC, Automatic Slope Compensation, DCM at high line
and light load, and Startup current
There are 4 purposes for IAC pin:
1.) For the leading edge modulation, when the duty
cycle is less than 50%, it requires the similar slope
compensation, as the duty cycle of the trailing
edge modulation is greater than 50%. In the
CM6903/4, it is a relatively easy thing to design.
Use an less than 500K ohm resistor, RAC to
connect IAC pin and the rectified line voltage. It
will do the automatic slope compensation. If the
input boost inductor is too small, the RAC may
need to be reduced more.
Tri-Fault Detect Comparator
To improve power supply reliability, reduce system
component count, and simplify compliance to UL1950 safety
standards, the CM6903/4 includes Tri-Fault Detect. This
feature monitors VFB (Pin 8) for certain PFC fault conditions.
In case of a feedback path failure, the output of the PFC
could go out of safe operating limits. With such a failure, VFB
will go outside of its normal operating area. Should VFB go
too low, too high, or open, Tri-Fault Detect senses the error
and terminates the PFC output drive.
2.) During the startup period, Rac also provides the
initial startup current, 100uA;therefore, the bleed
resistor is not needed.
3.) Since IAC pin with RAC behaves as a feedforward
signal, it also enhances the signal to noise ratio
and the THD of the input current.
Tri-Fault detect is an entirely internal circuit. It requires no
external components to serve its protective function.
4.) It also will try to keep the maximum input power to
be constant. However, the maximum input power
will still go up when the input line voltage goes up.
VCC OVP and generate VCC
For the CM6903/4 system, if VCC is generated from a source
that is proportional to the PFC output voltage and once that
source reaches 17.9V, PFCOUT, PFC driver will be off.
Start Up of the system, UVLO, and VREFOK
During the Start-up period, RAC resistor will provide the start
up current~100uA from the rectified line voltage to IAC pin.
Inside of CM6903/4 during the start-up period, IAC is
connected to VCC until the VCC reaches UVLO voltage
which is 15V and internal reference voltage is stable, it will
disconnect itself from VCC.
The VCC OVP resets once the VCC discharges below
16.4V, PFC output driver is enabled. It serves as redundant
PFC OVP function.
Typically, there is a bootstrap winding off the boost inductor.
The VCC OVP comparator senses when this voltage
exceeds 17.9V, and terminates the PFC output drive. Once
the VCC rail has decreased to below 16.4V the PFC output
drive be enabled. Given that 16V on VCC corresponds to
380V on the PFC output, 17.9V on VCC corresponds to an
OVP level of 460V.
PFC section wakes up after Start up period
After Start up period, PFC section will softly start since
VEAO is zero before the start-up period. Since VEAO is a
slew rate enhanced transconductance amplifier (see figure
3), VEAO has a high impedance output like a current
source and it will slowly charge the compensation net work
which needs to be designed by using the voltage loop gain
equation.
It is a necessary to put RC filter between bootstrap winding
and VCC. For VCC=15V, it is sufficient to drive either a
power MOSFET or a IGBT.
Before PFC boost output reaches its design voltage, it is
around 380V and VFB reaches 2.5V, PWM section is off.
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 10
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
UVLO
Therefore, DCILIMIT actually is a summing node from
voltage information which is from photo couple and CM431
and current information which is from one end of PWM
sensing resistor and the signal goes through a single pole,
RC filter then enter the DCILIMIT pin.
The UVLO threshold is 15V providing 5V hysteresis.
PFCOUT and PWMOUT
Both PFCOUT and PWMOUT are CMOS drivers. They both
have adaptive anti-shoot through to reduce the switching
loss. Its pull-up is a 30ohm PMOS driver and its pull-down
is a 15ohm NMOS driver. It can source 0.5A and sink 1A if
the VCC is above 15V.
This RC filter at DCILMIT also serves several functions:
1.) It protects IC.
2.) It provides level shift for voltage information.
3.) It filters the switching noise from current information.
PWM Section
The pole location of the RC filter should be greater than one
sixth of the PWM switching frequency which is 67Khz for
CM6903 and which is 134Khz for CM6904. Since the typical
photo couple should be biased around 1mA, the resistor of
the RC filter should be around 1.5V/1mA~1.5K ohm and we
suggest R is 1K ohm. Therefore, for CM6903, C should be
around 14nF and for CM6904, C should be around 1.2nF.
After 10mS digital soft start, CM6903/4’s PWM is operating
as a typical current mode. It requires a secondary
feedback, typically, it is configured with CM431, and photo
couple.
Since PWM Section is different from CM6800 family, it
needs the emitter of the photo couple to connected with
DCILIMIT instead of the collector. The PWM current
information also goes into DCILIMIT. Usually, the PWM
current information requires a RC filter before goes into the
DCILIMIT.
The maximum input voltage of the DCILIMIT pin is 1.5V.
Component Reduction
Components associated with the VRMS and IEAO pins of a
typical PFC controller such as the CM6800 have been
eliminated. The PFC power limit and bandwidth does vary
with line voltage. Double the power can be delivered from a
220V AC line versus a 110V AC line. Since this is a
combination PFC/PWM, the power to the load is limited by
the PWM stage.
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 11
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
APPLICATION CIRCUIT (CM6903/4)
VOUT
R14
D1
R13
R17
C21
L1
D12
L2
R8
R9
Q2
U2
R7
R2
C9
Z1
C10
D13
C17
D2
C19
R16
C1
R12
D7
AC IN
F1
RAC
D5
T1
C4
R20
T2
C18
SR1
R15
C5
R5
Q1
VCC_CIRCLE
Q3
R10
R4
C16
D6
R22
D3
R3
R19
T1
D8
D10
Q4
D11
D9
C13
C14
C15
R11
C11
C7
C8
D14
R23
9
2
IAC
VCC
VREFOK
R1C
4K ohm
R1B
RFIlter
CFilter
+
U1
.
ISENSE
400K ohm
R1A
100K ohm
-
6
8
+
OUT
.
-
+
D15
D16
.
S
Q
Q
ISENSEAMP
4
+
SUM
R
R
VREF OK
PFCCMP
PFCOUT
VFB
gmv
.
D8
-
RAMP
UVLO
.
.
2.5V
+
VCC
UVLO
.
.
7
FAULTB
VEAO
VCC OVP
.
VCC
+
17.9V
-
-
16.4V
R21
C8
OSC
PFCCLKB
C9
PFCCLKB
PWMCLK
Tri-Fault
Detect
.
.
-
PWMCLK
.
.
3
VIN OK
-
0.5V
+
VREF OK
VFB
S
Q
Q
PWMOUT
R
R
2.5V
+
+
PFC OVP
.
1.5V
+
R
2.75V
2.5V
-
-
1.5V
-
-
.
D10
+
10mS
-
PWMCMP
.
.
CM6903
fpfc= 67KHz
fpwm=67KHz
CM6904
-1V
+
SS
.
.
PFC ILIMIT
fpfc= 67KHz
PWM CLK
1V
fpwm=134KHz
1
5
DCILIMIT
GND
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 12
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
PACKAGE DIMENSION
9-PIN SIP (Z09)
16-PIN SOP (S16)
PIN 1 ID
θ
2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 13
CM6903/4
Low Pin Count PFC/PWM CONTROLLER COMBO
IMPORTANT NOTICE
Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to discontinue any integrated
circuit product or service without notice, and advises its customers to obtain the latest version of relevant information to verify,
before placing orders, that the information being relied on is current.
A few applications using integrated circuit products may involve potential risks of death, personal injury, or severe property or
environmental damage. CMC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for
use in life-support applications, devices or systems or other critical applications. Use of CMC products in such applications is
understood to be fully at the risk of the customer. In order to minimize risks associated with the customer’s applications, the
customer should provide adequate design and operating safeguards.
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2002/12/16 Preliminary Rev. 0.4
Champion Microelectronic Corporation
Page 14
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