CM6800A [CHAMP]
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO; 低启动电流PFC / PWM控制器， COMBO
| 型号： | CM6800A |
| 厂家： | 
CHAMPION MICROELECTRONIC CORP. |
| 描述： | LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO |
| 文件： | 总18页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
GENERAL DESCRIPTION
FEATURES
The CM6800A is a controller for power factor corrected,
switched mode power suppliers. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching
FETs, and results in a power supply that fully compiles with
Patent Number #5,565,761, #5,747,977, #5,742,151,
#5,804,950, #5,798,635
Pin to pin compatible with ML4800 and FAN6800
Additional folded-back current limit for PWM section.
23V Bi-CMOS process
IEC-1000-3-2 specifications. Intended as
a
BiCMOS
VIN OK turn on PWM at 2.25V instead of 1.5V(ML4800).
Internally synchronized leading edge PFC and trailing edge
PWM in one IC
version of the industry-standard ML4824, CM6800A
includes circuits for the implementation of leading edge,
average current, “boost” type power factor correction and a
trailing edge, pulse width modulator (PWM). Gate-driver
with 1A capabilities minimizes the need for external driver
circuits. Low power requirements improve efficiency and
reduce component costs.
Slew rate enhanced transconductance error amplifier for
ultra-fast PFC response
Low start-up current (100μA typ.)
Low operating current (3.0mA type.)
Low total harmonic distortion, high PF
Reduces ripple current in the storage capacitor between the
PFC and PWM sections
An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section
also includes peak current limiting and input voltage
brownout protection. The PWM section can be operated in
current or voltage mode, at up to 250kHz, and includes an
accurate 50% duty cycle limit to prevent transformer
saturation.
Average current, continuous or discontinuous boost leading
edge PFC
VCC OVP Comparator, Low Power Detect Comparator
PWM configurable for current mode or voltage mode
operation
Current fed gain modulator for improved noise immunity
Brown-out control, over-voltage protection, UVLO, and soft
start, and Reference OK
CM6800A includes an additional folded-back current limit
for PWM section to provide short circuit protection function.
APPLICATIONS
PIN CONFIGURATION
SOP-16 (S16) / PDIP-16 (P16)
Top View
Desktop PC Power Supply
Internet Server Power Supply
IPC Power Supply
1
2
3
4
5
6
7
8
VEAO
VFB
16
15
14
13
12
11
10
9
IEAO
IAC
UPS
Battery Charger
VREF
ISENSE
DC Motor Power Supply
Monitor Power Supply
Telecom System Power Supply
Distributed Power
VCC
PFC OUT
PWM OUT
GND
VRMS
SS
VDC
RAMP1
RAMP2
DC ILIMIT
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 1
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
PIN DESCRIPTION
Operating Voltage
Description
Pin No.
Symbol
Min.
Typ.
Max.
Unit
1
IEAO
PFC transconductance current error amplifier output
PFC gain control reference input
0
4.25
V
2
3
IAC
0
-5
0
1
0.7
6
mA
V
ISENSE
VRMS
SS
Current sense input to the PFC current limit comparator
Input for PFC RMS line voltage compensation
Connection point for the PWM soft start capacitor
PWM voltage feedback input
4
V
5
0
8
V
6
0
8
V
VDC
7
Oscillator timing node; timing set by RT CT
1.2
0
3.9
6
V
RAMP 1
(RTCT)
When in current mode, this pin functions as the current sense
input; when in voltage mode, it is the PWM input from PFC
output (feed forward ramp).
8
RAMP 2
V
(PWM RAMP)
9
DC ILIMIT
PWM current limit comparator input
0
1
V
10
11
12
13
14
15
16
GND
Ground
PWM OUT
PFC OUT
VCC
PWM driver output
0
0
VCC
VCC
18
V
V
V
V
V
V
PFC driver output
Positive supply
10
15
7.5
2.5
VREF
Buffered output for the internal 7.5V reference
VFB
PFC transconductance voltage error amplifier input
PFC transconductance voltage error amplifier output
0
0
3
6
VEAO
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 2
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
BLOCK DIAGRAM (CM6800A)
1
13
16
VEAO
IEAO
VCC
VCC
VCC OVP
PFC OVP
VREF
-
+
VCC
7.5V
+
-
+
-
14
0.3V
17.9V
REFERENCE
.
POWER
FACTOR
LOW POWER
DETECT
2.75V
VFB
gmv
15
-
COMPARATOR
CORRECTOR
3.5K
gmi
.
S
R
Q
Q
+
-
2.5V
VCC
+
MPPFC
+
-
.
IAC
2
-1V
+
-
GAIN
MODULATOR
PFC OUT
12
VRMS
S
R
Q
Q
4
PFC ILIMIT
3.5K
ISENSE
RAMP1
3
7
MNPFC
GND
OSCILLATOR
CLK
PFCOUT
350
PWMOUT
PWM
DUTY
DUTY CYCLE
LIMIT
RAMP2
8
SW SPST
VCC
-
+
MPPWM
1V
VDC
Vcc
6
5
PWM OUT
11
S
R
Q
Q
-
+
20uA
350
VFB
-
-
+
1V
.
SS
MNPWM
2.25V
+
GND
VIN OK
DC ILIMIT
SW SPST
SW SPST
SW SPST
VREF
PULSE
WIDTH
MODULATOR
Q
S
R
VCC
UVLO
DC ILIMIT
GND
9
CM6800A(ON:13V/OFF:10V)
10
ORDERING INFORMATION
Part Number
Temperature Range
-40℃ to 125℃
Package
CM6800AGIP*
16-Pin PDIP (P16)
-40℃ to 125℃
CM6800AGIS*
16-Pin Wide SOP (S16)
*Note: G : Suffix for Pb Free Product
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 3
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum ratings are those values beyond which the device could be permanently damaged.
Parameter
Min.
Max.
20
Units
V
VCC
IEAO
0
7.5
V
ISENSE Voltage
PFC OUT
PWMOUT
Voltage on Any Other Pin
IREF
IAC Input Current
Peak PFC OUT Current, Source or Sink
Peak PWM OUT Current, Source or Sink
-5
0.7
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
V
mA
mA
A
GND – 0.3
GND – 0.3
GND – 0.3
10
1
1
1
A
μJ
PFC OUT, PWM OUT Energy Per Cycle
Junction Temperature
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
1.5
150
150
125
260
℃
℃
℃
℃
-65
-40
Thermal Resistance (θJA)
Plastic DIP
Plastic SOIC
℃/W
℃/W
80
105
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply Vcc=+15V, RT
= 30.16kΩ, CT = 1000pF, TA=Operating Temperature Range (Note 1)
CM6800A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
Voltage Error Amplifier (gmv
)
Input Voltage Range
0
6
V
V
NONINV = VINV, VEAO = 3.75V
μmho
Transconductance
50
70
90
at room temp
Feedback Reference Voltage
Input Bias Current
2.45
-1.0
5.8
2.5
-0.05
6.0
0.1
-35
40
2.55
V
μA
Note 2
Output High Voltage
Output Low Voltage
Sink Current
V
0.4
-20
V
μA
μA
VFB = 3V, VEAO = 6V
Source Current
VFB = 1.5V, VEAO = 1.5V
30
50
50
Open Loop Gain
60
dB
dB
Power Supply Rejection Ratio
11V < VCC < 16.5V
60
Current Error Amplifier (gmi)
Input Voltage Range
Transconductance
-1.5
50
0.7
100
25
V
VNONINV = VINV, VEAO = 3.75V
at room temp
μmho
85
Input Offset Voltage
Output High Voltage
Output Low Voltage
-25
4.0
mV
V
4.25
1.0
1.2
V
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 4
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply
Vcc=+15V, RT =30.16kΩ, CT = 1000pF, TA=Operating Temperature Range (Note 1)
CM6800A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
-65
75
Max.
μA
μA
Sink Current
ISENSE = +0.6V, IEAO = 4.0V
ISENSE = -0.6V, IEAO = 1.5V
-35
Source Current
35
60
60
Open Loop Gain
70
dB
dB
Power Supply Rejection Ratio
11V < VCC < 16.5V
75
PFC OVP Comparator
Threshold Voltage
Hysteresis
2.70
230
2.77
0.3
2.85
300
V
mV
Low Power Detect Comparator
VCC OVP Comparator
Threshold Voltage
0.2
0.4
V
Threshold Voltage
Hysteresis
17.5
1.40
17.9
1.5
18.5
1.65
V
V
Tri-Fault Detect
Fault Detect HIGH
2.65
0.4
2.75
2
2.85
4
V
Time to Fault Detect HIGH
VFB=VFAULT DETECT LOW to
ms
VFB=OPEN.470pF from VFB to GND
Fault Detect LOW
0.5
0.6
V
PFC ILIMIT Comparator
Threshold Voltage
-1.10
20
-1.00
100
-0.90
V
(PFC ILIMIT VTH – Gain Modulator
Output)
mV
ns
Delay to Output (Note 4)
Overdrive Voltage = -100mV
250
DC ILIMIT Comparator
Threshold Voltage
0.95
1.0
1.05
V
Delay to Output (Note 4)
Overdrive Voltage = 100mV
250
ns
VIN OK Comparator
OK Threshold Voltage
Hysteresis
2.16
0.9
2.25
1.1
2.36
1.3
V
V
GAIN Modulator
IAC = 100μA, VRMS =0, VFB = 1V
0.70
1.80
0.90
0.25
0.84
2.00
1.00
0.95
2.20
1.10
0.40
at room temp
IAC = 100μA, VRMS = 1.1V, VFB = 1V
at room temp
Gain (Note 3)
I
AC = 150μA, VRMS = 1.8V, VFB = 1V
at room temp
IAC = 300μA, VRMS = 3.3V, VFB = 1V
0.32
10
at room temp
IAC = 100μA
Bandwidth
MHz
V
Output Voltage =
I
AC = 250μA, VRMS = 1.1V, VFB = 1V
0.84
0.90
0.95
3.5K*(ISENSE-IOFFSET
)
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 5
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
ELECTRICAL CHARACTERISTICS (Conti.) Unless otherwise stated, these specifications apply
Vcc=+15V, RT = 30.16kΩ, CT = 1000pF, TA=Operating Temperature Range (Note 1)
CM6800A
Symbol
Parameter
Test Conditions
Unit
Min.
Typ.
Max.
Oscillator
TA = 25℃
Initial Accuracy
60
70
kHz
%
Voltage Stability
11V < VCC < 16.5V
1
2
Temperature Stability
Total Variation
%
Line, Temp
52
74
kHz
V
Ramp Valley to Peak Voltage
PFC Dead Time (Note 4)
CT Discharge Current
2.5
360
6.5
640
15
ns
VRAMP2 = 0V, VRAMP1 = 2.5V
Reference
mA
TA = 25℃, I(VREF) = 1mA
Output Voltage
Line Regulation
7.4
7.5
10
7.6
25
20
20
V
11V < VCC < 16.5V
mV
mV
mV
%
0mA < I(VREF) < 7mA; TA = 0℃~70℃
0mA < I(VREF) < 5mA; TA = -40℃~85℃
10
Load Regulation
10
Temperature Stability
Total Variation
0.4
Line, Load, Temp
7.35
5
7.65
25
V
TJ = 125℃, 1000HRs
Long Term Stability
mV
PFC
Minimum Duty Cycle
Maximum Duty Cycle
VIEAO > 4.0V
0
%
%
VIEAO < 1.2V
90
95
IOUT = -20mA at room temp
IOUT = -100mA at room temp
IOUT = 10mA, VCC = 9V at room temp
IOUT = 20mA at room temp
IOUT = 100mA at room temp
CL = 1000pF
15
15
0.8
20
20
ohm
ohm
V
Output Low Rdson
0.4
15
15
50
ohm
ohm
ns
Output High Rdson
Rise/Fall Time (Note 4)
PWM
Duty Cycle Range
Output Low Rdson
0-45
0-47
0-49
15
%
ohm
ohm
V
IOUT = -20mA at room temp
IOUT = -100mA at room temp
IOUT = 10mA, VCC = 9V
IOUT = 20mA at room temp
IOUT = 100mA at room temp
CL = 1000pF
15
0.4
15
15
50
0.8
20
ohm
ohm
ns
Output High Rdson
20
Rise/Fall Time (Note 4)
PWM Comparator Level Shift
0.7
1.0
1.1
V
Supply
VCC = 12V, CL = 0 at room temp
14V, CL = 0
μA
Start-Up Current
100
3.0
13
150
7.0
Operating Current
mA
V
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
CM6800A
12.74
2.85
13.26
3.15
CM6800A
3.0
V
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the VFB pin.
Note 3: Gain = K x 5.375V; K = (ISENSE – IOFFSET) x [IAC (VEAO – 0.625)]-1; VEAOMAX = 6V
Note 4: Guaranteed by design, not 100% production test.
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 6
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
TYPICAL PERFORMANCE CHARACTERISTIC
100
90
127
120
113
106
99
80
70
60
50
40
30
20
10
0
92
85
78
71
64
57
-500
0
500
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VFB (V)
3
ISENSE(mV)
Voltage Error Amplifier (gmv) Transconductance
Current Error Amplifier (gmi) Transconductance
2.2
2
0.4
0.35
0.3
1.8
1.6
1.4
1.2
1
0.25
0.2
0.15
0.1
0.8
0.6
0.4
0.2
0
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VRMS (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VRMS (V)
Gain Modulator Transfer Characteristic (K)
Gain
- 1
I
GAINMOD −I
AC x (6 - 0.625)
I
SENSE −IOFFSET
K =
OFFSET mV
Gain =
I
I
AC
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
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CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
Functional Description
The CM6800A consists of an average current controlled,
continuous boost Power Factor Correction (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation. In
either mode, the PWM stage uses conventional trailing
edge duty cycle modulation, while the PFC uses leading
edge modulation. This patented leading/trailing edge
modulation technique results in a higher usable PFC error
amplifier bandwidth, and can significantly reduce the size of
the PFC DC buss capacitor.
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VACrms. The other
condition is that the current drawn from the line at any given
instant must be proportional to the line voltage. Establishing
a suitable voltage control loop for the converter, which in turn
drives a current error amplifier and switching output driver
satisfies the first of these requirements. The second
requirement is met by using the rectified AC line voltage to
modulate the output of the voltage control loop. Such
modulation causes the current error amplifier to command a
power stage current that varies directly with the input voltage.
In order to prevent ripple, which will necessarily appear at the
output of boost circuit (typically about 10VP-P ripple at low
frequency on a 385V DC level), from introducing distortion
back through the voltage error amplifier, the bandwidth of the
voltage loop is deliberately kept low. A final refinement is to
adjust the overall gain of the PFC such to be proportional to
1/VIN^2, which linearizes the transfer function of the system
as the AC input to voltage varies.
The synchronized of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the CM6800A runs at the same frequency as the
PFC.
In addition to power factor correction, a number of
protection features have been built into the CM6800A.
These include soft-start, PFC overvoltage protection, peak
current limiting, brownout protection, duty cycle limiting, and
under-voltage lockout.
Since the boost converter topology in the CM6800A PFC is
of the current-averaging type, no slope compensation is
required.
PFC Section
Power Factor Correction
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to the
line voltage, so the power factor is unity (one). A common
class of nonlinear load is the input of most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect, which occurs on
the input filter capacitor in these supplies, causes brief
high-amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line
voltage. Such supplies present a power factor to the line of
less than one (i.e. they cause significant current harmonics
of the power line frequency to appear at their input). If the
input current drawn by such a supply (or any other
nonlinear load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.
Gain Modulator
Figure 1 shows a block diagram of the PFC section of the
CM6800A. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line
voltage, and PFC output voltages. There are three inputs to
the gain modulator. These are:
1. A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current via a
resistor and is then fed into the gain modulator at IAC
.
Sampling current in this way minimizes ground noise, as is
required in high power switching power conversion
environments. The gain modulator responds linearly to this
current.
2. A voltage proportional to the long-term RMS AC line
voltage, derived from the rectified line voltage after scaling
and filtering. This signal is presented to the gain modulator
at VRMS. The gain modulator’s output is inversely
To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous
line voltage. The PFC section of the CM6800A uses a
boost-mode DC-DC converter to accomplish this. The input
to the converter is the full wave rectified AC line voltage. No
bulk filtering is applied following the bridge rectifier, so the
input voltage to the boost converter ranges (at twice line
frequency) from zero volts to the peak value of the AC input
and back to zero. By forcing the boost converter to meet
two simultaneous conditions, it is possible to ensure that
the current drawn from the power line is proportional to the
input
2
proportional to VRMS (except at unusually low values of
VRMS where special gain contouring takes over, to limit
power dissipation of the circuit components under heavy
brownout conditions). The relationship between VRMS and
gain is called K, and is illustrated in the Typical
Performance Characteristics.
3. The output of the voltage error amplifier, VEAO. The gain
modulator responds linearly to variations in this voltage.
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
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CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
The output of the gain modulator is a current signal, in the
In higher power applications, two current transformers are
sometimes used, one to monitor the IF of the boost diode. As
stated above, the inverting input of the current error amplifier
is a virtual ground. Given this fact, and the arrangement of
the duty cycle modulator polarities internal to the PFC, an
increase in positive current from the gain modulator will
cause the output stage to increase its duty cycle until the
voltage on ISENSE is adequately negative to cancel this
increased current. Similarly, if the gain modulator’s output
decreases, the output duty cycle will decrease, to achieve a
less negative voltage on the ISENSE pin.
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way the
gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC form the power line. The general for of the
output of the gain modulator is:
I
AC× VEAO x 1V
2
IGAINMOD
=
(1)
V
RMS
Cycle-By-Cycle Current Limiter and Selecting RS
More exactly, the output current of the gain modulator is
given by:
The ISENSE pin, as well as being a part of the current feedback
loop, is a direct input to the cycle-by-cycle current limiter for
the PFC section. Should the input voltage at this pin ever be
more negative than –1V, the output of the PFC will be
disabled until the protection flip-flop is reset by the clock
pulse at the start of the next PFC power cycle.
IGAINMOD = K x (VEAO – 0.625V) x IAC
Where K is in units of V-1
Note that the output current of the gain modulator is limited
around 228.47 μA and the maximum output voltage of the
gain modulator is limited to 228.47uA x 3.5K=0.8V. This
RS is the sensing resistor of the PFC boost converter. During
the steady state, line input current x RS = IGAINMOD x 3.5K.
Since the maximum output voltage of the gain modulator is
IGAINMOD max x 3.5K= 0.8V during the steady state, RS x line
input current will be limited below 0.8V as well. Therefore, to
choose RS, we use the following equation:
0.8V also will determine the maximum input power.
However, IGAINMOD cannot be measured directly from ISENSE
.
ISENSE = IGAINMOD-IOFFSET and IOFFSET can only be measured
when VEAO is less than 0.5V and IGAINMOD is 0A. Typical
IOFFSET is around 60uA.
RS =0.8V x Vinpeak/(2x Line Input power)
For example, if the minimum input voltage is 80VAC, and the
maximum input rms power is 200Watt, RS = (0.8V x 80V x
1.414)/(2 x 200) = 0.226 ohm.
Selecting RAC for IAC pin
IAC pin is the input of the gain modulator. IAC also is a
current mirror input and it requires current input. By
selecting a proper resistor RAC, it will provide a good sine
wave current derived from the line voltage and it also helps
program the maximum input power and minimum input line
voltage.
PFC OVP
In the CM6800A, PFC OVP comparator serves to protect the
power circuit from being subjected to excessive voltages if
the load should suddenly change. A resistor divider from the
high voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.75V, the PFC output driver is shut
down. The PWM section will continue to operate. The OVP
comparator has 250mV of hysteresis, and the PFC will not
restart until the voltage at VFB drops below 2.50V. The VFB
power components and the CM6800A are within their safe
operating voltages, but not so low as to interfere with the
boost voltage regulation loop. Also, VCC OVP can be served
as a redundant PFCOVP protection. VCC OVP threshold is
17.9V with 1.5V hysteresis.
RAC=Vin peak x 7.9K. For example, if the minimum line
voltage is 80VAC, the RAC=80 x 1.414 x 7.9K=894Kohm.
Current Error Amplifier, IEAO
The current error amplifier’s output controls the PFC duty
cycle to keep the average current through the boost
inductor a linear function of the line voltage. At the inverting
input to the current error amplifier, the output current of the
gain modulator is summed with a current which results from
a negative voltage being impressed upon the ISENSE pin.
The negative voltage on ISENSE represents the sum of all
currents flowing in the PFC circuit, and is typically derived
from a current sense resistor in series with the negative
terminal of the input bridge rectifier.
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 9
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
1
13
16
VEAO
IEAO
VCC
PFC OVP
+
-
VREF
VCC OVP
2.75V
-
VCC
7.5V
+
-
.
14
+
17.9V
REFERENCE
0.3V
LOW POWER
DETECT
POWER
FACTOR
TRI-FAULT
VFB
GMv
-
18
0.5V
-
+
CORRECTOR
3.5K
GMi
.
S
R
Q
Q
+
PFC CMP
2.5V
+
+
.
MPPFC
VCC
IAC
-
-
2
-1V
+
-
GAIN
MODULATOR
PFC OUT
12
VRMS
S
Q
4
PFC ILIMIT
R
Q
3.5K
ISENSE
RAMP1
MNPFC
3
7
GND
OSCILLATOR
CLK
Figure 1. PFC Section Block Diagram
Error Amplifier Compensation
The Voltage Loop Gain (S)
The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the types
of compensation networks most commonly used for the
voltage and current error amplifiers, along with their
respective return points. The current loop compensation is
returned to VREF to produce a soft-start characteristic on the
PFC: as the reference voltage comes up from zero volts, it
creates a differentiated voltage on IEAO which prevents the
PFC from immediately demanding a full duty cycle on its
boost converter.
ΔVOUT
ΔVEAO ΔVOUT
ΔVFB ΔVEAO
=
≈
*
*
ΔVFB
P
IN *2.5V
*GM
V
*ZCV
V
OUTDC2 *ΔVEAO *S*CDC
ZCV: Compensation Net Work for the Voltage Loop
GMv: Transconductance of VEAO
PIN: Average PFC Input Power
VOUTDC: PFC Boost Output Voltage; typical designed value is
380V.
CDC: PFC Boost Output Capacitor
PFC Voltage Loop
PFC Current Loop
There are two major concerns when compensating the
voltage loop error amplifier, VEAO; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest anticipated
international power frequency). The gain vs. input voltage
of the CM6800A’s voltage error amplifier, VEAO has a
specially shaped non-linearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbation in line or
load conditions will cause the input to the voltage error
amplifier (VFB) to deviate from its 2.5V (nominal) value. If
this happens, the transconductance of the voltage error
amplifier will increase significantly, as shown in the Typical
The current amplifier, IEAO compensation is similar to that of
the voltage error amplifier, VEAO with exception of the choice
of crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage loop.
It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.
The Current Loop Gain (S)
ΔVISENSE ΔDOFF
ΔIEAO
=
≈
*
*
ΔDOFF
OUTDC *R
ΔIEAO ΔISENSE
S *GM
V
Performance
Characteristics.
This
raises
the
I
* ZCI
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristics.
S*L*2.5V
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 10
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
ZCI: Compensation Net Work for the Current Loop
GMI: Transconductance of IEAO
ISENSE Filter, the RC filter between RS and ISENSE :
VOUTDC: PFC Boost Output Voltage; typical designed value
is 380V and we use the worst condition to calculate the ZCI
RS: The Sensing Resistor of the Boost Converter
2.5V: The Amplitude of the PFC Leading Modulation Ramp
L: The Boost Inductor
There are 2 purposes to add a filter at ISENSE pin:
1.) Protection: During start up or inrush current
conditions, it will have a large voltage cross Rs
which is the sensing resistor of the PFC boost
converter. It requires the ISENSE Filter to attenuate
the energy.
There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.
2.) To reduce L, the Boost Inductor: The ISENSE Filter
also can reduce the Boost Inductor value since the
ISENSE Filter behaves like an integrator before going
ISENSE which is the input of the current error
amplifier, IEAO.
The ISENSE Filter is a RC filter. The resistor value of the ISENSE
Filter is between 100 ohm and 50 ohm because IOFFSET x the
resistor can generate an offset voltage of IEAO. By selecting
RFILTER equal to 50 ohm will keep the offset of the IEAO less
than 5mV. Usually, we design the pole of ISENSE Filter at
fpfc/6, one sixth of the PFC switching frequency. Therefore,
the boost inductor can be reduced 6 times without disturbing
the stability. Therefore, the capacitor of the ISENSE Filter,
CFILTER, will be around 283nF.
Figure 3. External Component Connections to VCC
Figure 2. Compensation Network Connections for the
Voltage and Current Error Amplifiers
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 11
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
of the current flowing in the converter’s output stage.
DCILIMIT, which provides cycle-by-cycle current limiting, is
Oscillator (RAMP1)
The oscillator frequency is determined by the values of RT
and CT, which determine the ramp and off-time of the
oscillator output clock:
typically connected to RAMP2 in such applications. For
voltage-mode, operation or certain specialized applications,
RAMP2 can be connected to a separate RC timing network
to generate a voltage ramp against which VDC will be
compared. Under these conditions, the use of voltage
feedforward from the PFC buss can assist in line regulation
accuracy and response. As in current mode operation, the
DC ILIMIT input is used for output stage overcurrent protection.
1
fOSC
=
t
RAMP + tDEADTIME
The dead time of the oscillator is derived from the following
equation:
No voltage error amplifier is included in the PWM stage of
the CM6800A, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate the
design of optocoupler feedback circuitry, an offset has been
built into the PWM’s RAMP2 input which allows VDC to
command a zero percent duty cycle for input voltages below
0.7V.
V
REF −1.25
tRAMP = CT x RT x In
at VREF = 7.5V:
VREF − 3.75
tRAMP = CT x RT x 0.51
The dead time of the oscillator may be determined using:
2.5V
tDEADTIME
=
x CT = 943 x CT
PWM Current Limit
2.65mA
The DC ILIMIT pin is a direct input to the cycle-by-cycle current
limiter for the PWM section. Should the input voltage at this
pin ever exceed 1V, the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle. Beside, the
cycle-by-cycle current, when the DC ILIMIT triggered the
cycle-by-cycle current, it also softly discharge the voltage of
soft start capacitor. It will limit PWM duty cycle mode.
Therefore, the power dissipation will be reduced during the
dead short condition.
The dead time is so small (tRAMP >> tDEADTIME ) that the
operating frequency can typically be approximately by:
1
fOSC
=
t
RAMP
EXAMPLE:
For the application circuit shown in the datasheet, with the
oscillator running at:
VIN OK Comparator
The VIN OK comparator monitors the DC output of the PFC
and inhibits the PWM if this voltage on VFB is less than its
nominal 2.25V. Once this voltage reaches 2.45V, which
corresponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start begins.
1
fOSC = 67.5kHz =
t
RAMP
Solving for CT x RT yields 2.9 x 10-5. Selecting standard
components values, CT = 470pF, and RT =61.9kΩ
PWM Control (RAMP2)
When the PWM section is used in current mode, RAMP2 is
generally used as the sampling point for
a voltage
The dead time of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator dead time, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken
that CT not be made so large as to extend the Maximum
Duty Cycle beyond 50%. This can be accomplished by
using a stable 390pF capacitor for CT.
representing the current on the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a
ramp voltage generated by
a second set of timing
components (RRAMP2, CRAMP2),that will have a minimum value
of zero volts and should have a peak value of approximately
5V. In voltage mode operation, feedforward from the PFC
output buss is an excellent way to derive the timing ramp for
the PWM stage.
PWM Section
Pulse Width Modulator
The PWM section of the CM6800A is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing. The PWM is capable of current-mode or
voltage-mode operation. In current-mode applications, the
PWM ramp (RAMP2) is usually derived directly from a
current sensing resistor or current transformer in the
primary of the output stage, and is thereby representative
Soft Start
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 20μA supplies
the charging current for the capacitor, and start-up of the
PWM begins at around 0.7V. Start-up delay can be
programmed by the following equation:
20μA
x
CSS = tDELAY
0.7V
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 12
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
where CSS is the required soft start capacitance, and the
tDEALY is the desired start-up delay.
The ratio of winding transformer for the bootstrap should be
set between 18V and 15V. A filter network is recommended
between VCC (pin 13) and bootstrap winding. The resistor of
the filter can be set as following.
RFILTER x IVCC ~ 2V, IVCC = IOP + (QPFCFET + QPWMFET ) x fsw
IOP = 3mA (typ.)
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at
least 5ms.
If anything goes wrong, and VCC goes beyond 17.9V, the
PFC gate (pin 12) drive goes low and the PWM gate drive
(pin 11) remains function. The resistor’s value must be
chosen to meet the operating current requirement of the
CM6800A itself (5mA, max.) plus the current required by the
two gate driver outputs.
Solving for the minimum value of CSS
:
20μA
CSS = 5ms x
= 142nF
0.7V
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the
SS capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the VIN OK comparator at
start-up. The magnitude of VFB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a
1.0μF soft start capacitor will allow time for VFB and PFC
out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.
In today’s PC power supply, since it has the house-keeping
IC in the secondary, the time sequence maybe different
from the last paragraph. The 5mS delay and the 1uF Soft
Start Capacitor may vary and they may vary base on the
application conditions.
EXAMPLE:
With a wanting voltage called, VBIAS ,of 18V, a VCC of 15V
and the CM6800A driving a total gate charge of 90nC at
100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET),
the gate driver current required is:
IGATEDRIVE = 100kHz x 90nC = 9mA
V
BIAS − VCC
I
RBIAS
=
=
CC + I
G
18V −15V
RBIAS
5mA + 9mA
Choose RBIAS = 214Ω
Generating VCC
The CM6800A should be locally bypassed with a 1.0 μ F
ceramic capacitor. In most applications, an electrolytic
capacitor of between 47 μ F and 220 μ F is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
After turning on CM6800A at 13V, the operating voltage
can vary from 10V to 17.9V. The threshold voltage of VCC
OVP comparator is 17.9V. The hysteresis of VCC OVP is
1.5V. When VCC see 17.9V, PFCOUT will be low, and
PWM section will not be disturbed. That’s the two ways to
generate VCC. One way is to use auxiliary power supply
around 15V, and the other way is to use bootstrap winding
to self-bias CM6800A system. The bootstrap winding can
be either taped from PFC boost choke or from the
transformer of the DC to DC stage.
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 13
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
One of the advantages of this control technique is that it
required only one system clock. Switch 1(SW1) turns off and
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
on right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp
up. The effective duty cycle of the trailing edge modulation
is determined during the ON time of the switch. Figure 4
shows a typical trailing edge control scheme.
switch 2 (SW2) turns on at the same instant to minimize the
momentary “no-load” period, thus lowering ripple voltage
generated by the switching action. With such synchronized
switching, the ripple voltage of the first stage is reduced.
Calculation and evaluation have shown that the 120Hz
component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
In case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When
the modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during OFF time of the switch. Figure 5 shows a leading
edge control scheme.
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 14
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
APPLICATION CIRCUIT (Voltage Mode)
R5
R3
EMC FILTER
IVIN
IVIN_EMC
PFC_VIN
D4
L1
L2
L3
IL1
D5
RT1
IVIN
PFC_VIN
IBOOT
D5
PFC_Vout
PFC_Vout
IAC
IC10
Q3
Q4
VIN
AC
C2
R2
C3
C8
R1
R10
R11
R12
R14
R15
C33
100n
D12
D10
R22
22
PFC_DC
Q1
R26
18k
R16A
R17A
R65A
Q2N2222
MUR1100
1N4148
R23
C10
Q2
Q2N904
C23
R24
22
470p
R13
R18
75
R25
10k
VFB
D6
D7
C55A
C41
C30
1N4002
1N4002
R58
C43
R64
R59
IEAO
U2 CM6800/01/24
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VEAO
IEAO
IAC
VEAO
VFB
ISENSE
VREF
VREF
C54
I-SENSE VREF
R60
VRMS
VCC
VCC
VRMS
SS
VCC
C46
C52
1u
C53
SS
PFC-OUT
100n
VDC
C47 VREF
VDC PWM-OUT
RAMP1 GND
RAMP2 ILIMIT
R66
C45
PWM_OUT
R63
ZD2
R56
R57
C49
C57
C44
VCC
C56
R62
C48
C50
R61
470
ILIMIT
C51
R44
C4
ISO1
VDC
C14
PWM_IN
PFC_Vout
R34
C38
C7
10n
R27
100k
C22
10n
10n
4.7
R49
C39
R43
IL4
L4
L5
R46
C40
D9A
PWM_Vout
IC17
C17
IC18
R45
ILOAD
D8
MUR1100
R35
4.7
D13
T1
D9B
C18
C19
PWM_Rload
500m
U1
CM431
MUR1100
C22
10n
R48
C15
10n
VCC
IBIAS
R32A
R32
D16
C34
100n
VCC
C31
1N4148
R33
Q6
Q2N2222
PWM_DC
R28
22
T 2:3
PWM_OUT
Q7
Q2N904
Q3
R29
10k
ILIMIT
R31
ZD1
6.8V
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 15
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
APPLICATION CIRCUIT (Current Mode)
R5
R3
EMC FILTER
IVIN
IVIN_EMC
PFC_VIN
D4
L1
L2
L3
IL1
D5
RT1
IVIN
PFC_VIN
IBOOT
D5
PFC_Vout
PFC_Vout
IAC
IC10
Q3
Q4
VIN
AC
C2
R2
C3
C8
R1
R10
R11
R12
R14
R15
C33
100n
D12
D10
R22
22
PFC_DC
Q1
R26
18k
R16A
R17A
R65A
Q2N2222
MUR1100
1N4148
R23
C10
Q2
Q2N904
C23
R24
22
470p
R13
R18
75
R25
10k
VFB
D6
D7
C55A
C41
C30
1N4002
1N4002
R58
C43
R64
R59
IEAO
U2 CM6800/01/24
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VEAO
IEAO
IAC
VEAO
VFB
ISENSE
VREF
VREF
C54
I-SENSE VREF
R60
VRMS
VCC
VCC
VRMS
SS
VCC
C46
C52
1u
C53
SS
PFC-OUT
100n
VDC
C47 VREF
VDC PWM-OUT
RAMP1 GND
RAMP2 ILIMIT
R66
C45
PWM_OUT
R63
ZD2
R56
R57
C49
C57
C44
ILIMIT
C56
R62
R67
C48
C50
R61 470
ILIMIT
C51
R68
R44
C4
ISO1
VDC
C14
PWM_IN
PFC_Vout
R34
C38
C7
10n
R27
100k
C22
10n
10n
4.7
R49
C39
R43
IL4
L4
L5
R46
C40
D9A
PWM_Vout
IC17
C17
IC18
R45
ILOAD
D8
MUR1100
R35
4.7
D13
T1
D9B
C18
C19
PWM_Rload
500m
U1
CM431
MUR1100
C22
10n
R48
C15
10n
VCC
IBIAS
R32A
R32
D16
C34
100n
VCC
C31
1N4148
R33
Q6
Q2N2222
PWM_DC
R28
22
T
2:3
PWM_OUT
Q7
Q2N904
Q3
R29
10k
ILIMIT
R31
ZD1
6.8V
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 16
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
PACKAGE DIMENSION
16-PIN PDIP (P16)
PIN 1 ID
θ
16-PIN SOP (S16), 0.300” Wide Body
PIN 1 ID
θ
ꢀ
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 17
CM6800A
LOW START-UP CURRENT PFC/PWM CONTROLLER COMBO
IMPORTANT NOTICE
Champion Microelectronic Corporation (CMC) reserves the right to make changes to its products or to
discontinue any integrated circuit product or service without notice, and advises its customers to obtain
the latest version of relevant information to verify, before placing orders, that the information being relied
on is current.
A few applications using integrated circuit products may involve potential risks of death, personal injury, or
severe property or environmental damage. CMC integrated circuit products are not designed, intended,
authorized, or warranted to be suitable for use in life-support applications, devices or systems or other
critical applications. Use of CMC products in such applications is understood to be fully at the risk of the
customer. In order to minimize risks associated with the customer’s applications, the customer should
provide adequate design and operating safeguards.
HsinChu Headquarter
Sales & Marketing
5F, No. 11, Park Avenue II,
Science-Based Industrial Park,
HsinChu City, Taiwan
7F-6, No.32, Sec. 1, Chenggong Rd.,
Nangang District, Taipei City 115,
Taiwan, R.O.C.
TEL: +886-3-567 9979
FAX: +886-3-567 9909
T E L : +886-2-2788 0558
F AX: +886-2-2788 2985
http://www.champion-micro.com
2006/10/11 Rev. 1.3
Champion Microelectronic Corporation
Page 18
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