CAT9532HV6I-T2 [CATALYST]
Parallel I/O Port, 16 I/O, CMOS, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-24;
| 型号： | CAT9532HV6I-T2 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Parallel I/O Port, 16 I/O, CMOS, 4 X 4 MM, ROHS COMPLIANT, MO-220, TQFN-24 外围集成电路 |
| 文件： | 总17页 (文件大小：307K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT9532
16-bit Programmable LED Dimmer with I2C Interface
FEATURES
DESCRIPTION
16 LED drivers with dimming control
256 brightness steps
The CAT9532 is a CMOS device that provides 16-bit
parallel input/output port expander optimized for LED
dimming control. The CAT9532 outputs can drive
directly 16 LEDs in parallel. Each individual LED may
be turned ON, OFF, or blinking at one of two
programmable rates. The device provides a simple
solution for dimming LEDs in 256 brightness steps for
backlight and color mixing applications. The CAT9532
is suitable in I2C and SMBus compatible applications
where it is necessary to limit the bus traffic or free-up
the bus master’s timer.
16 open drain outputs drive 25 mA each
2 selectable programmable blink rates:
– frequency: 0.593Hz to 152Hz
– duty cycle: 0% to 99.6%
I/Os can be used as GPIOs
400kHz I2C bus compatible*
2.3V to 5.5V operation
The CAT9532 contains an internal oscillator and two
PWM signals that drive the LED outputs. The user can
program the period and duty cycle for each individual
PWM signal. After the initial set-up command to
program the Blink Rate 1 and Blink Rate 2 (frequency
and duty cycle), only one command from the bus master
is required to turn each individual open drain output ON,
OFF, or cycle at Blink Rate 1 or Blink Rate 2. Each
open drain LED output can provide a maximum output
current of 25mA. The total current sunk by all I/Os must
not exceed 200mA.
5V tolerant I/Os
Active low reset input
RoHS-compliant 24-Lead SOIC, TSSOP and
24-pad TQFN (4 x 4mm) packages
APPLICATIONS
Backlighting
RGB color mixing
Sensors control
Power switches, push-buttons
Alarm systems
TYPICAL APPLICATION CIRCUIT
For Ordering Information details, see page 16.
5 V
5 V
3 x 10kΩ
RS0
RS1
RS11
V
CC
SDA
SDA
SCL
LED0
LED1
SCL
RESET
RESET
CAT9532
LED11
2
I C/SMBus
Master
A2
A1
A0
LED12
GPIOs
V
SS
LED15
* Catalyst Semiconductor is licensed by Philips Corporation to
carry the I2C Protocol.
Notes: LED0 to LED11 are used as LED drivers
LED12 to LED15 are used as regular GPIOs
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-9001 Rev. B
CAT9532
PIN CONFIGURATION
SOIC (W), TSSOP (Y)
TQFN (HV6)
AO
A1
1
24
23
22
21
20
19
19
17
16
15
14
13
V
CC
2
SDA
A2
3
SCL
1
2
3
4
5
6
18
17
16
15
14
LED0
LED1
LED2
LED3
LED4
LED5
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
4
RESET
LED15
LED14
LED13
LED12
LED11
LED10
LED9
RESET
LED15
LED14
LED13
LED12
5
6
7
8
9
10
11
12
13 LED11
V
LED8
SS
PIN DESCRIPTION
DIP / SOIC / TSSOP
TQFN
22
PIN NAME
FUNCTION
1
2
AO
A1
Address Input 0
Address Input 1
Address Input 2
23
3
24
A2
4-11
12
1-8
9
LED0 - LED7
VSS
LED Driver Output 0 to 7, I/O Port 0 to 7
Ground
13-20
21
10-17
18
LED8 - LED15
LED Driver Output 8 to 15, I/O Port 8 to 15
¯¯¯¯¯¯
RESET
Reset Input
Serial Clock
Serial Data
Power Supply
22
19
SCL
SDA
VCC
23
20
24
21
BLOCK DIAGRAM
A2 A1 A0
V
CC
POWER ON
RESET
INPUT
REGISTER
RESET
SCL
SDA
LED SELECT (LSx)
REGISTER
INPUT
FILTERS
I2C BUS
CONTROL
LEDx
PRESCALER 0
REGISTER
PWM 0
REGISTER
BLINK 0
BLINK 1
CONTROL
LOGIC
OSCILLATOR
PRESCALER 1
REGISTER
PWM 1
REGISTER
V
SS
CAT9532
Note: Only one I/O is shown for clarity
Doc. No. MD-9001 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
-2.0 to +7.0
-0.5 to +5.5
±25
Units
V
VCC with Respect to Ground
Voltage on Any Pin with Respect to Ground
DC Current on I/Os
V
mA
mA
W
Supply Current
200
Package Power Dissipation Capability (TA = 25ºC)
Junction Temperature
1.0
+150
°C
ºC
Storage Temperature
-65 to +150
300
Lead Soldering Temperature (10 seconds)
Operating Ambient Temperature
ºC
-40 to +85
ºC
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-9001 Rev. B
CAT9532
D.C. OPERATING CHARACTERISTICS
VCC = 2.3 to 5.5V, VSS = 0V; TA = -40ºC to +85ºC, unless otherwise specified
Symbol Parameter
Supplies
Conditions
Min
Typ
Max
Unit
VCC
Supply Voltage
2.3
—
—
5.5
V
Operating mode; VCC = 5.5V; no
load; fSCL = 100kHz
ICC
Supply Current
250
550
µA
Standby mode; VCC = 5.5V; no load;
VI = VSS or VCC, fSCL = 0kHz
Istb
Standby Current
—
—
—
2.1
—
5.0
2
µA
mA
V
Standby mode; VCC = 5.5V; every
LED I/O = VIN = 4.3V, fSCL = 0kHz
I
Additional Standby Current
Power-on Reset Voltage
Δ stb
(1)
VCC = 3.3V, No load;
VI = VCC or VSS
VPOR
1.5
2.2
¯¯¯¯¯¯
SCL, SDA, RESET
(2)
VIL
VIH
Low Level Input Voltage
-0.5
0.7 VCC
3
—
—
—
—
—
—
0.3 VCC
V
V
(2)
High Level Input Voltage
Low Level Output Current
Leakage Current
5.5
—
+1
6
IOL
VOL = 0.4V
VI = VCC = VSS
VI = VSS
mA
µA
pF
pF
IIL
CI(3)
-1
Input Capacitance
—
(3)
CO
Output Capacitance
VO = VSS
—
8
A0, A1, A2
(2)
VIL
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
-0.5
2.0
-1
—
—
—
0.8
5.5
1
V
V
(2)
VIH
IIL
µA
I/Os
(2)
VIL
Low Level Input Voltage
High Level Input Voltage
-0.5
2.0
9
—
—
—
—
—
—
—
—
—
—
0.8
5.5
—
—
—
—
—
—
1
V
V
(2)
VIH
VOL = 0.4V; VCC = 2.3V
VOL = 0.4V; VCC = 3.0V
VOL = 0.4V; VCC = 5.0V
VOL = 0.7V; VCC = 2.3V
VOL = 0.7V; VCC = 3.0V
12
15
15
20
25
-1
(4)
IOL
Low Level Output Current
mA
VOL = 0.7V; VCC = 5.0V
IIL
Input Leakage Current
VCC = 3.6V; VI = VSS or VCC
µA
pF
(3)
CI/O
Input/Output Capacitance
—
8
Notes:
(1) VDD must be lowered to 0.2V in order to reset the device.
(2) VIL min and VIH max are reference values only and are not tested.
(3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(4) The output current must be limited to a maximum 25mA per each I/O; the total current sunk by all I/O must be limited to 200mA (or 100mA
for eight I/Os)
Doc. No. MD-9001 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
A.C. CHARACTERISTICS
VCC = 2.3V to 5.5V, TA = -40ºC to +85ºC, unless otherwise specified(1)
Symbol Parameter
Min
Typ
Max
400
50
Units
kHz
ns
fSCL
Clock Frequency
(2)
tSP
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
tLOW
tHIGH
1.3
0.6
µs
Clock High Period
µs
(2)
tR
SDA and SCL Rise Time
300
300
ns
(2)
tF
SDA and SCL Fall Time
ns
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA
Start Condition Hold Time
Start Condition Setup Time (for a Repeater Start)
Data Input Hold Time
0.6
0.6
0
µs
µs
ns
Data in Setup Time
100
0.6
ns
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
µs
900
200
ns
tDH
50
ns
(2)
tBUF
Time the Bus must be Free Before a New Transmission Can Start
1.3
µs
Port Timing
tPV
tPS
Output Data Valid
ns
ns
µs
Input Data Setup Time
Input Data Hold Time
100
1
tPH
Reset
(2)
tW
Reset Pulse Width
Reset Recovery Time
Time to Reset
10
0
ns
ns
ns
tREC
(3)
tRESET
400
Notes:
(1) Test conditions according to "AC Test Conditions" table.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(3) The full delay to reset the part will be the sum of tRESET and the RC time constant of the SDA line.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-9001 Rev. B
CAT9532
AC TEST CONDITIONS
Input Pulse Voltage
0.2VCC to 0.8VCC
Input Rise and Fall Times
Input Reference Voltage
Output Reference Voltage
Output Load
≤5ns
0.3VCC, 0.7VCC
0.5VCC
Current source: IOL = 3mA; 400pF for fSCL(max) = 400kHz
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 1. 2-Wire Serial Interface Timing
PIN DESCRIPTION
SCL: Serial Clock
LED0 to LED15: LED Driver Outputs / General
Purpose I/Os
The serial clock input clocks all data transferred into
or out of the device. The SCL line requires a pull-up
resistor if it is driven by an open drain output.
The pins are open drain outputs used to drive directly
LEDs. Any of these pins can be programmed to drive
the LED ON, OFF, Blink Rate1 or Blink Rate2. When
not used for controlling the LEDs, these pins may be
used as general purpose parallel input/output.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs. A pull-
up resistor must be connected from SDA line to VCC.
¯¯¯¯¯¯
RESET: External Reset Input
Active low Reset input is used to initialize the
CAT9532 internal registers and the I2C state machine.
The internal registers are held in their default state
while Reset input is active. An external pull-up resistor
of maximum 25kΩ is required when this pin is not
actively driven.
Doc. No. MD-9001 Rev. B
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
FUNCTIONAL DESCRIPTION
The CAT9532 is a 16-bit I/O bus expander that
provides a programmable LED dimmer, controlled
through an I2C compatible serial interface.
SDA when SCL is HIGH. The CAT9532 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The CAT9532 supports the I2C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master
device which generates the serial clock and all
START and STOP conditions for bus access. The
CAT9532 operates as a Slave device. Both the
Master device and Slave device can operate as either
transmitter or receiver, but the Master device controls
which mode is activated.
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
Device Addressing
After the bus Master sends a START condition, a
slave address byte is required to enable the CAT9532
for a read or write operation. The four most significant
bits of the slave address are fixed as binary 1100
(Figure 3). The CAT9532 uses the next three bits as
address bits.
I2C Bus Protocol
The features of the I2C bus protocol are defined as
follows:
The address bits A2, A1 and A0 are used to select
which device is accessed from maximum eight
devices on the same bus. These bits must compare to
their hardwired input pins. The 8th bit following the 7-
bit slave address is the R/W bit that specifies whether
a read or write operation is to be performed. When
this bit is set to “1”, a read operation is initiated, and
when set to “0”, a write operation is selected.
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition (Figure 2).
Following the START condition and the slave address
byte, the CAT9532 monitors the bus and responds
with an acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
CAT9532 then performs a read or a write operation
depending on the state of the R/W bit.
START and STOP Conditions
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 2. Start/Stop Timing
SDA
SCL
START CONDITION
STOP CONDITION
Figure 3. CAT9532 Slave Address
SLAVE ADDRESS
1
1
0
0
A2
A1
A0 R/W
FIXED
PROGRAMMABLE
HARDWARE
SELECTABLE
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-9001 Rev. B
CAT9532
The Control Register acts as a pointer to determine
which register will be written or read. The four least
significant bits, B0, B1, B2, B3, are used to select
which internal register is accessed, according
to the Table 1.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data. The SDA line remains stable LOW during
the HIGH period of the acknowledge related clock
pulse (Figure 4).
If the auto increment flag (AI) is set, the four least
significant bits of the Control Register are
automatically incremented after a read or write
operation. This allows the user to access the
CAT9532 internal registers sequentially. The content
of these bits will rollover to “0000” after the last
register is accessed.
The CAT9532 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8- bit byte.
Table 1. Internal Registers Selection
Register
Name
Register
Function
When the CAT9532 begins a READ mode it transmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT9532 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT9532 to the standby power
mode and place the device in a known state.
B3
B2
B1
B0
Type
Input
Register 0
0
0
0
0
INPUT0
INPUT1
PSC0
PWM0
PSC1
PWM1
LS0
READ
Input
Register 1
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
READ
READ/
WRITE
Frequency
Prescaler 0
READ/
WRITE
PWM
Register 0
READ/
WRITE
Frequency
Prescaler 1
Registers and Bus Transactions
READ/
WRITE
PWM
Register 1
After the successful acknowledgement of the slave
address, the bus master will send a command byte to
the CAT9532 which will be stored in the Control
Register. The format of the Control Register is shown
in Figure 5.
READ/
WRITE
LED 0-3
Selector
READ/
WRITE
LED 4-7
Selector
LS1
READ/
WRITE
LED 8-11
Selector
LS2
READ/
WRITE
LED 12-15
Selector
LS3
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
B0
Figure 5. Control Register
0
0
0
AI
B3
B2
B1
REGISTER ADDRESS
RESET STATE: 00h
AUTO-INCREMENT FLAG
Doc. No. MD-9001 Rev. B
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
Table 4. PWM Register 0 and PWM Register 1
The Input Register 0 and Input Register 1 reflect the
incoming logic levels of the I/O pins, regardless of
whether the pin is defined as an input or an output.
These registers are read only ports. Writes to the input
registers will be acknowledged but will have no effect.
PWM0
bit
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
default
PWM1
bit
Table 2. Input Register 0 and Input Register 1
7
1
6
0
5
0
4
0
3
0
2
0
1
0
0
0
INPUT0
default
LED
7
LED
6
LED
5
LED
4
LED
3
LED
2
LED
1
LED
0
Every LED driver output can be programmed to one of
four states, LED OFF, LED ON, LED blinks at BLINK0
rate and LED blinks at BLINK1 rate using the LED
Selector Registers (Table 5).
bit
7
6
5
4
3
2
1
0
default
INPUT1
X
X
X
X
X
X
X
X
LED
15
LED
14
LED
13
LED
12
LED
11
LED
10
LED
9
LED
8
Table 5. LED Selector Registers
bit
7
6
5
4
3
2
1
0
LS0
default
X
X
X
X
X
X
X
X
LED 3
LED 2
LED 1
LED 0
bit
default
LS1
7
0
6
0
5
0
4
3
0
2
1
0
0
The Frequency Prescaler 0 and Frequency Prescaler
1 registers (PSC0, PSC1) are used to program the
period of the pulse width modulated signals BLINK0
and BLINK1 respectively:
0
0
0
LED 7
LED 6
LED 5
LED 4
bit
default
LS2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
T_BLINK0 = (PSC0 + 1) / 152;
T_BLINK1 = (PSC1 + 1) / 152
LED 11
LED 10
LED 9
LED 8
Table 3. Frequency Prescaler 0 and Frequency
Prescaler 1 Registers
bit
default
LS3
7
6
0
5
4
0
3
0
2
0
1
0
0
0
PSC0
0
0
bit
default
PSC1
bit
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
LED 15
LED 14
LED 13
LED 12
bit
7
6
0
5
4
0
3
2
0
1
0
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
default
0
0
0
0
default
The LED output (LED0 to LED15) is set by the 2 bits
value from the corresponding LSx Register (x = 0 to 3):
The PWM Register 0 and PWM Register 1 (PWM0,
PWM1) are used to program the duty cycle of BLINK0
and BLINK1 respectively:
00 = LED Output set Hi-Z (LED Off – Default)
01 = LED Output set LOW (LED On)
10 = LED Output blinks at BLINK0 Rate
11 = LED Output blinks at BLINK1 Rate
Duty Cycle_BLINK0 = PWM0 / 256;
Duty Cycle_BLINK1 = PWM1 / 256
After writing to the PWM0/1 register an 8-bit internal
counter starts to count from 0 to 255. The outputs are
low (LED on) when the counter value is less than the
value programmed into PWM register. The LED is off
when the counter value is higher than the value
written into PWM register.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-9001 Rev. B
CAT9532
Write Operations
Data is transmitted to the CAT9532 registers using the
write sequence shown in Figure 6.
LED Pins Used as General Purpose I/O
Any LED pins not used to drive LEDs can be used as
general purpose input/output, GPIO.
If the AI bit from the command byte is set to “1”, the
CAT9532 internal registers can be written
sequentially. After sending data to one register, the
next data byte will be sent to the next register
sequentially addressed.
When used as input, the user should program the
corresponding LED pin to Hi-Z (“00” for the LSx
register bits). The pin state can be read via the
Input Register according to the sequence shown in
Figure 8.
Read Operations
For use as output, an external pull-up resistor should
be connected to the pin. The value of the pull-up
resistor is calculated according to the DC operating
characteristics. To set the LED output high, the user
has to program the output Hi-Z writing “00” into the
corresponding LED Selector (LSx) register bits. The
output pin is set low when the LED output is
programmed low through the LSx register bits (“01” in
LSx register bits).
The CAT9532 registers are read according to the
timing diagrams shown in Figure 7 and Figure 8. Data
from the register, defined by the command byte, will
be sent serially on the SDA line.
After the first byte is read, additional data bytes may
be read when the auto-increment flag, AI, is set. The
additional data byte will reflect the data read from the
next register sequentially addressed by the (B3 B2 B1
B0) bits of the command byte.
When reading Input Port Registers (Figure 8), data is
clocked into the register on the failing edge of the
acknowledge clock pulse. The transfer is stopped
when the master will not acknowledge the data byte
received and issue the STOP condition.
Figure 6. Write to Register Timing Diagram
1
2
3
4
5
6
7
8
9
SCL
Command Byte
Slave Address
Data To Register 1
DATA 1
Data To Register 2
SDA
A
1.0
S
1
1
0
0
A2 A1 A0
0
0
0
0
AI B3 B2 B1 B0
A
A
A
Start Condition
R/W Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
WRITE TO
REGISTER
DATA OUT
FROM PORT
t
pv
Figure 7. Read from Register Timing Diagram
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Slave
Acknowledge
From Master
Slave Address
Slave Address
Data From Register
COMMAND BYTE
DATA
MSB
S
1
1
0
0
A2 A1 A0
0
A
A
S
1
1
0
0
A2 A1 A0
1
A
LSB
A
First Byte
R/W
R/W
At This Moment Master-Transmitter
Becomes Master-receiver and
Slave-Receiver Becomes
Slave-Transmitter
Auto-increment
Register Address
If Al = 1
No Acknowledge
From Master
Data From Register
MSB
LSB NA
P
DATA
Note: Transfer can be stopped at any time by a STOP condition.
Last Byte
Doc. No. MD-9001 Rev. B
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
External Reset Operation
Power-On Reset Operation
The CAT9532 registers and the I2C state machine are
initialized to their default state when the RESET input
is held low for a minimum of tW. The external Reset
timing is shown in Figure 9.
The CAT9532 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state. The device is in a
reset state for VCC less than the internal POR
threshold level (VPOR). When VCC exceeds the VPOR
level, the reset state is released and the CAT9532
internal state machine and registers are initialized to
their default state.
Figure 8. Read Input Port Register Timing Diagram
Slave Address
Data From Port
Data From Port
DATA 4
SDA
DATA 1
1
1
0
0
A2 A1 A0
S
A
A
NA
P
Start Condition
R/W Acknowledge
From Slave
Acknowledgeꢀ
From Master
No Acknowledgeꢀ Stop ꢀ
From Master Condition
READ FROM
PORT
DATA INTO
PORT
DATA 1
DATA 2
DATA 3
DATA 4
t
ph
t
ps
¯¯¯¯¯¯
Figure 9. RESET Timing Diagram
START
ACK OR READ CYCLE
SCL
SDA
30%
tRESET
50%
RESET
LEDx
50%
50%
tREC
tW
tRESET
50%
LED OFF
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-9001 Rev. B
CAT9532
APPLICATION INFORMATION
Programming Example
Command Description
START
I2C Data
The following programming sequence is an
example how to set:
1
2
3
Send Slave address, A0-A2 = low
Command Byte: AI=”1”; PSC0 Addr
C0h
12h
– LED0 to LED3: ON
– LED4 to LED7: Dimming at 30% brightness;
Blink 1: 152Hz, duty cycle 30%
Set Blink 1 at 152Hz, T_Blink1 = 1/152
Write PSC0 = 0
Set PWM0 duty cycle to 30%
PWM0 / 256 = 0.3; Write PWM0=77
Set Blink 2 at 2Hz, T_Blink1 = 1/2
Write PSC1 = 75
4
5
6
7
00h
4Dh
4Bh
80h
– LED8 to LED11: Blink at 2Hz with 50% duty
cycle (Blink 2)
– LED12 to LED15: OFF
Set PWM1 duty cycle to 50%
PWM1 / 256 = 0.5; Write PWM1=128
8
9
Write LS0: LED0 to LED3 = ON
55h
AAh
FFh
00h
Write LS1: LED4 to LED7 at Blink1
10 Write LS2: LED8 to LED11 at Blink2
11 Write LS3: LED12 to LED15 = OFF
12 STOP
5V
5V
V
CC
10kꢀ (x 3)
V
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
LED8
LED9
LED10
LED11
LED12
LED13
LED14
LED15
CC
SDA
SCL
SDA
SCL
RESET
GND
RESET
CAT9532
2
I C/SMBus MASTER
A2
A1
A0
V
SS
GPIOs
Note: LED0 to LED11 are used as LED drivers and LED12 to LED15 are used as regular GPIOs.
Figure 10. Typical Application
Doc. No. MD-9001 Rev. B
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
PACKAGE OUTLINE DRAWINGS
SOIC 24-Lead (W)(1)(2)
SYMBOL
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
A
A1
A2
b
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
b
e
L
θ
PIN#1 IDENTIFICATION
θ1
5°
15°
TOP VIEW
h
D
h
θ1
A2
θ
A
θ1
L
c
A1
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-9001 Rev. B
CAT9532
TSSOP 24-Lead 4.4mm (Y)(1)(2)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.70
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
Doc. No. MD-9001 Rev. B
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT9532
TQFN 24-Lead 4 x 4mm (HV6)(1)(2)
A
D
DETAIL A
E
E2
PIN#1 ID
D2
PIN#1 INDEX AREA
A1
SIDE VIEW
TOP VIEW
BOTTOM VIEW
b
e
SYMBOL
MIN
NOM
0.75
MAX
0.80
0.05
0.30
4.10
2.90
4.10
2.90
L
A
A1
b
0.70
0.00
0.20
3.90
2.70
3.90
2.70
0.02
DETAIL A
0.25
D
4.00
D2
E
2.80
4.00
E2
e
2.80
A
0.50 BSC
0.40
L
0.30
0.50
A1
FRONT VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-220.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. MD-9001 Rev. B
CAT9532
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
9532
W
I
–
G
T1
Package
Tape & Reel
Company ID
Lead Finish
W: SOIC, JEDEC
Y: TSSOP
HV6: TQFN
T: Tape & Reel
1: 1000/Reel SOIC only
2: 2000/Reel
Blank: Matte-Tin
G: NiPdAu
Product Number
9532
Temperature Range
I = Industrial (-40ºC to 85ºC)
ORDERING PART NUMBER
Part Number
Package
Lead Finish
CAT9532WI
SOIC
SOIC
Matte-Tin
Matte-Tin
Matte-Tin
Matte-Tin
Matte-Tin (5)
Matte-Tin (5)
NiPdAu
CAT9532WI-T1
CAT9532YI
TSSOP
TSSOP
TQFN
TQFN
TQFN
TQFN
CAT9532YI-T2
CAT9532HV6I
CAT9532HV6I-T2
CAT9532HV6I-G
CAT9532HV6I-GT2
NiPdAu
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard plated finish is Matte-Tin for SOIC and TSSOP packages. The standard plated finish is NiPdAu for TQFN package.
(3) The device used in the above example is a CAT9532WI-T1 (SOIC, Industrial Temperature, Matte-Tin, Tape & Reel).
(4) For additional temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(5) For package availability, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. MD-9001 Rev. B
16
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
10/23/07
12/07/07
A
B
Initial Issue
Update Example of Ordering Information and Ordering Part Number
Copyrights, Trademarks and Patents
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
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Document No: MD-9001
Revision:
B
Issue date:
12/07/07
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