CAT93C76LE-T3 [CATALYST]
8K-Bit Microwire Serial EEPROM; 8K位Microwire串行EEPROM型号: | CAT93C76LE-T3 |
厂家: | CATALYST SEMICONDUCTOR |
描述: | 8K-Bit Microwire Serial EEPROM |
文件: | 总13页 (文件大小:231K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAT93C76 (Rev. A)
8K-Bit Microwire Serial EEPROM
FEATURES
DESCRIPTION
High speed operation: 3MHz @ VCC ≥ 2.5V
Low power CMOS technology
1.8 to 5.5 volt operation
The CAT93C76 is an 8K-bit Serial EEPROM memory
device which is configured as either registers of 16
bits (ORG pin at VCC or Not Connected) or 8 bits
(ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The
CAT93C76 is manufactured using Catalyst’s
advanced CMOS EEPROM floating gate technology.
The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The device is available in 8-pin PDIP, SOIC,
TSSOP and 8-pad TDFN packages.
Selectable x8 or x16 memory organization
Self-timed write cycle with auto-clear
Software write protection
Power-up inadvertant write protection
1,000,000 Program/erase cycles
100 year data retention
Industrial and extended temperature ranges
Sequential read
“Green” package option available
PIN CONFIGURATION
FUNCTIONAL SYMBOL
V
CC
PDIP (L), SOIC (V)
TSSOP (Y), TDFN (ZD4)
ORG
CS
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DI
NC
DO
ORG
GND
SK
DO
GND
PIN FUNCTION
Pin Name
CS
Function
Chip Select
SK
Serial Clock Input
Serial Data Input
Serial Data Output
Power Supply
DI
For Ordering Information details, see page 12.
DO
VCC
GND
ORG
NC
Ground
Memory Organization
No Connection
Note: When the ORG pin is connected to VCC, x16 organization is
selected. When it is connected to ground, x8 organization
is selected. If the ORG pin is left unconnected, then an
internal pull-up device will select x16 organization.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
–55 to +125
–65 to 150
-2.0 to +VCC +2.0
-2.0 to +7.0
300
Units
ºC
Temperature Under Bias
Storage Temperature
ºC
Voltage on any Pin with Respect to Ground(2)
VCC with Respect to Ground
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current(3)
V
V
ºC
100
mA
RELIABILITY CHARACTERISTICS(3)
Symbol
Parameter
Reference Test Method
Min
Units
(4)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
Cycles/Byte
(4)
TDR
Data Retention
ESD Susceptibility
Latch-Up
Years
V
(4)
VZAP
2000
(4)(5)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
CC = +1.8V to +5.5V unless otherwise specified.
V
Symbol
ICC1
Parameter
Test Conditions
Min
Typ
Max
3
Units
fSK = 1MHz; VCC = 5.0V
fSK = 1MHz; VCC = 5.0V
Power Supply Current (Write)
Power Supply Current (Read)
1
mA
µA
ICC2
300
500
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
CS = 0V ORG = GND
ISB1
ISB2
2
10
10
µA
µA
0(6)
CS = 0V ORG = Float or VCC
ILI
Input Leakage Current
Output Leakage Current
ORG Pin Leakage Current
Input Low Voltage
0(6)
0(6)
1
10
10
µA
µA
µA
V
VIN = 0V to VCC
VOUT = 0V to VCC, CS = 0V
ORG = GND or ORG = VCC
4.5V ≤ VCC ≤ 5.5V
ILO
ILORG
VIL1
10
-0.1
0.8
4.5V ≤ VCC ≤ 5.5V
VIH1
VIL2
Input High Voltage
2
0
VCC + 1
VCC x 0.2
VCC + 1
0.4
V
1.8V ≤ VCC < 4.5V
Input Low Voltage
V
1.8V ≤ VCC < 4.5V
VIH2
VOL1
VOH1
VOL2
VOH2
Input High Voltage
VCC x 0.7
V
4.5V ≤ VCC ≤ 5.5V; IOL = 2.1mA
4.5V ≤ VCC ≤ 5.5V; IOH = -400µA
1.8V ≤ VCC < 4.5V; IOL = 100µA
1.8V ≤ VCC < 4.5V; IOH = -100µA
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
2.4
V
0.1
V
VCC - 0.2
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Output shorted for no more than one second.
(4) These parameters are tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1V to VCC +1V.
(6) 0µA is defined as less than 900nA.
Doc. No. MD-1090 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
PIN CAPACITANCE(1)
Symbol Test
Conditions
VOUT = 0V
VIN = 0V
Min
Typ
Max
5
Units
pF
COUT
CIN
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
5
pF
INSTRUCTION SET(2)
Start
Address
Data
Instruction
Bit
Opcode
10
Comments
x8
x16
x8
x16
READ
1
A10-A0
A10-A0
A10-A0
A9-A0
A9-A0
A9-A0
Read Address AN– A0
Clear Address AN– A0
ERASE
WRITE
EWEN
EWDS
ERAL
1
11
1
01
D7-D0 D15-D0 Write Address AN– A0
Write Enable
1
00
11XXXXXXXXX 11XXXXXXXX
00XXXXXXXXX 00XXXXXXXX
10XXXXXXXXX 10XXXXXXXX
1
00
Write Disable
1
00
Clear All Addresses
WRAL
1
00
01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0 Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC = 1.8V - 2.5V VCC = 2.5V - 5.5V
Test
Symbol
tCSS
Parameter
Conditions
Units
ns
Min
100
0
Max
Min
50
0
Max
CS Setup Time
tCSH
CS Hold Time
ns
tDIS
DI Setup Time
100
100
50
50
ns
tDIH
DI Hold Time
ns
tPD1
Output Delay to 1
250
250
150
5
150
150
100
5
ns
tPD0
Output Delay to 0
CL = 100pF(3)
ns
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
ns
tEW
tCSMIN
tSKHI
ms
ns
200
250
250
150
150
150
ns
tSKLOW
tSV
ns
250
100
ns
SKMAX
DC
1000
DC
3000
kHz
POWER-UP TIMING(1)(4)
Symbol
tPUR
Parameter
Max
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ,
WRITE and ERASE commands.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
DEVICE OPERATION
Read
The CAT93C76 is a 8192-bit nonvolatile memory
intended for use with industry standard micropro-
cessors. The CAT93C76 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 13-bit instructions control the read, write and
erase operations of the device. When organized as
X8, seven 14-bit instructions control the read, write
and erase operations of the device. The CAT93C76
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C76
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (tPD0 or tPD1).
For the CAT93C76, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will
automatically increment to the next address and shift
out the next data word in a sequential READ mode.
As long as CS is continuously asserted and SK
continues to toggle, the device will keep incrementing
to the next address automatically until it reaches the
end of the address space, then loops back to address
0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All
subsequent data words will follow without a dummy
zero bit.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The ready/busy status can be determined after the
start of a write operation by selecting the device (CS
high) and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high
indicates that the device is ready for the next
instruction. If necessary, the DO pin may be placed
back into a high impedance state during chip select by
shifting a dummy “1” into the DI pin. The DO pin will
enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high
impedance state is recommended in applications
where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start
the self clocking clear and data store cycle of the
memory location specified in the instruction. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The most significant bit of the address
is “don’t care” but it must be present.
Doc. No. MD-1090 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
Figure 1. Sychronous Data Timing
t
t
t
CSH
SKLOW
SKHI
SK
t
DIS
t
t
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
CSMIN
DIS
PD0, PD1
DO
DATA VALID
Figure 2. Read Instruction Timing
SK
CS
Don't Care
A
A
N-1
A
0
N
DI
1
1
0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
0
15 . . .
D
D
0
or
or
or
7 . . .
D
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Figure 3. Write Instruction Timing
SK
t
CSMIN
STATUS
STANDBY
CS
VERIFY
A
N
A
A
0
D
D
0
N-1
N
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
determined by selecting the device and polling the DO
pin. Once cleared, the contents of all memory bits
return to a logical “1” state.
Erase
Upon receiving an ERASE command and address,
the CS (Chip Select) pin must be deasserted for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear cycle of the selected memory
location. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Erase/Write Enable and Disable
The CAT93C76 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the
EWEN (write enable) instruction. Once the write
instruction is enabled, it will remain enabled until
power to the device is removed, or the EWDS
instruction is sent. The EWDS instruction can be used
to disable all CAT93C76 write and clear instructions,
and will prevent any accidental writing or clearing of
the device. Data can be read normally from the device
regardless of the write enable/disable status.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next
rising edge of the clock (SK) in order to start the self-
timed high voltage cycle. This is important because if
CS is brought low before or after this specific frame
window, the addressed location will not be
programmed or erased.
Power-On Reset (POR)
The CAT93C76 incorporates Power-On Reset (POR)
circuitry which protects the device against
malfunctioning while VCC is lower than the
recommended operating voltage.
Erase All
Upon receiving an ERAL command, the CS (Chip
Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
The device will power up into a read-only state and
will power-down into a reset state when VCC crosses
the POR level of ~1.3 V.
Figure 4. Erase Instruction Timing
SK
STANDBY
STATUS VERIFY
CS
t
CS
A
A
0
A
N-1
N
DI
1
1
1
t
t
SV
HZ
HIGH-Z
DO
BUSY
EW
READY
HIGH-Z
t
Doc. No. MD-1090 Rev. B
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
Figure 5. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS
DI
1
0
0
1
0
t
t
HZ
SV
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CSMIN
D
D
0
DI
1
0
0
0
1
N
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
PACKAGE OUTLINE DRAWING
PDIP 8-Lead 300mils (L) (1)(2)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
L
c
b2
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-001.
Doc. No. MD-1090 Rev. B
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
SOIC 8-Lead 150mils (V) (1)(2)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
TSSOP 8-Lead (Y) (1)(2)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.40
E
E1
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.75
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
Doc. No. MD-1090 Rev. B
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
TDFN 8-Pad 3 x 3mm (ZD4) (1)(2)
PIN#1
IDENTIFICATION
SYMBOL
MIN
0.70
0.00
0.50
NOM
0.75
MAX
0.80
0.05
0.60
A
A1
A2
A3
b
0.02
0.55
0.20 REF
0.30
0.23
2.90
2.20
2.90
1.40
0.37
3.10
2.40
3.10
1.60
D
3.00
D2
E
2.30
3.00
E2
e
1.50
0.65 TYP
0.30
L
0.20
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-229.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
Device # Suffix
CAT
93C76
V
I
-G
T3
Package
L: PDIP
V: SOIC, JEDEC
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
E = Extended (-40ºC to 125ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Company ID
Product Number
93C76
ZD4: TDFN (3 x 3mm)
Tape & Reel
T: Tape & Reel
2: 2000 units/Reel(5)
3: 3000 units/Reel
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a 93C76VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel)
(4) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA.) For additional
information, please contact your Catalyst sales office.
(5) For TDFN 3 x 3mm package Tape and Reel = 2000 pcs/reel, all others = 3000 pcs/reel.
(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Doc. No. MD-1090 Rev. B
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Comments
Initial Issue
08/11/2004
09/21/2007
A
B
Added Package Outline Drawings
Updated the Example of Ordering Information
Copyrights, Trademarks and Patents
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
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Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
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Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
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Document No: MD-1090
Revision:
B
Issue date:
09/21/07
相关型号:
CAT93C76LI-1.8REVA
512X16 MICROWIRE BUS SERIAL EEPROM, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8
ONSEMI
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