CAT5401WI-10 [CATALYST]
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface; 四路数字可编程电位计（ DPP ™ ）与64丝锥和SPI接口
| 型号： | CAT5401WI-10 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface |
| 文件： | 总15页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT5401
Quad Digitally Programmable Potentiometers
(DPP™) with 64 Taps and SPI Interface
FEATURES
DESCRIPTION
Four linear taper digitally programmable
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists
of a series of 63 resistive elements connected
between two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DPP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5kΩ, 10kΩ, 50kΩ or
100kΩ
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 80Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
For Ordering Information details, see page 14.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
SOIC Package (W)
TSSOP Package (Y)
R
H0
R
H1
R
R
H3
H2
24
23
22
21
20
19
18
17
16
15
14
13
NC
R
24
23
22
21
20
19
18
17
16
15
14
13
WP
CS
R
1
1
V
SI
CC
CS
SCK
SI
R
2
A
2
L3
L0
1
SPI BUS
INTERFACE
ꢀ
WIPER CONTROL
REGISTERS
ꢀ
R
W0
R
W1
R
W2
R
W3
R
H3
R
3
R
R
3
W0
H0
L1
SO
R
W3
R
H0
R
W0
CS
4
4
H1
A
0
R
L0
5
R
5
W1
SO
V
CC
NC
WP
SI
6
GND
6
CAT
5401
CAT
5401
WP
NONVOLATILE
DATA
REGISTERS
HOLD
SCK
7
NC
7
A
0
CONTROL LOGIC
A
1
R
A
1
8
R
8
L3
W2
R
L2
R
H3
R
9
R
9
L1
H2
R
H2
R
W3
R
10
11
12
R
10
11
12
H1
L2
R
L0
R
L1
R
R
L3
L2
R
W2
A
0
SO
R
W1
SCK
NC
GND
HOLD
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2012 Rev. G
CAT5401
PIN DESCRIPTIONS
SI: Serial Input
Pin#
Pin#
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses and data to be written to the
CAT5401. Input data is latched on the rising edge of the
serial clock.
(SOIC) (TSSOP) Name Function
Supply Voltage
1
2
19
20
VCC
RL0
Low Reference Terminal
for Potentiometer 0
SO: Serial Output
High Reference Terminal
for Potentiometer 0
3
4
21
22
RH0
RW0
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5401. During a read cycle,
data is shifted out on the falling edge of the serial
clock.
Wiper Terminal for
Potentiometer 0
¯¯¯
CS
Chip Select
5
6
7
8
23
24
1
SCK: Serial Clock
¯¯¯
WP
Write Protection
Serial Input
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5401. Opcodes, byte
addresses or data present on the SI pin are latched on
the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
SI
Device Address
2
A1
Low Reference Terminal
for Potentiometer 1
9
3
4
5
RL1
RH1
RW1
High Reference Terminal
for Potentiometer 1
10
11
A0, A1: Device Address Inputs
Wiper Terminal for
Potentiometer 1
These inputs set the device address when addressing
multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in order
to initiate communication with the CAT5401.
Ground
12
13
6
7
GND
NC
No Connect
Wiper Terminal for
Potentiometer 2
14
15
16
8
9
RW2
RH2
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
High Reference Terminal
for Potentiometer 2
Low Reference Terminal
for Potentiometer 2
10
RL2
RW: Wiper
The four RW pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Bus Serial Clock
Hold
17
18
19
20
11
12
13
14
SCK
¯¯¯¯¯
HOLD
¯¯¯
CS: Chip Select
Serial Data Output
Device Address, LSB
SO
A0
¯¯¯
¯¯¯
CS is the Chip select pin. CS low enables the
¯¯¯
¯¯¯
CAT5401 and CS high disables the CAT5401. CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5401
draws ZERO current in the Standby mode. A high to
Wiper Terminal for
Potentiometer 3
21
22
15
16
RW3
RH3
High Reference Terminal
for Potentiometer 3
Low Reference Terminal
for Potentiometer 3
23
24
17
18
RL3
NC
¯¯¯
low transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a
¯¯¯
No Connect
valid write sequence is what initiates an internal write
cycle.
¯¯¯
WP: Write Protect
¯¯¯
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When
¯¯¯
WP is tied low, all non-volatile write operations to the Data registers are inhibited (change of wiper control register
¯¯¯
¯¯¯
is allowed). WP going low while CS is still low will interrupt a write to the registers. If the internal write cycle has
¯¯¯
already been initiated, WP going low will have no effect on any write operation.
¯¯¯¯¯
HOLD: Hold
¯¯¯¯¯
The HOLD pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without
¯¯¯¯¯
having to retransmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The
SO pin is in a high impedance state during the time the part is paused, and transitions on the SI pins will be
¯¯¯¯¯
¯¯¯¯¯
ignored. To resume communication, HOLD is brought high, while SCK is low. (HOLD should be held high any
¯¯¯¯¯
time this function is not being used.) HOLD may be tied high directly to VCC or tied to VCC through a resistor.
Doc. No. MD-2012 Rev. G
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
SERIAL BUS PROTOCOL
¯¯¯
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5401 to interface directly with
many of today's popular microcontrollers. The
CAT5041 contains an 8-bit instruction register. The
instruction set and the operation codes are detailed in
the instruction set table 3.
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI
pin, with data being clocked in on the rising edge of
SCK. The first byte contains one of the six op-codes
that define the operation to be performed.
DEVICE OPERATION
The CAT5401 is four resistor arrays integrated with
SPI serial interface logic, four 6-bit wiper control
registers and sixteen 6-bit, non-volatile memory data
registers. Each resistor array contains 63 separate
resistive elements connected in series. The physical
ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL).
RH and RL are symmetrical and may be interchanged.
The tap positions between and at the ends of the
series resistors are connected to the output wiper
terminals (RW) by a CMOS transistor switch. Only one
tap point for each potentiometer is connected to its
wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read
or written to the wiper control registers or the non-
volatile memory data registers via the SPI bus.
Additional instructions allows data to be transferred
between the wiper control registers and each
respective potentiometer's non-volatile data registers.
Also, the device can be instructed to operate in an
"increment/decrement" mode.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2012 Rev. G
CAT5401
Absolute Maximum Ratings(1)
Parameters
Ratings
-55 to +125
-65 to +150
-2.0 to +VCC + 2.0
-0.2 to +7.0
1.0
Units
ºC
Temperature Under Bias
Storage Temperature
°C
V
(1) (2)
Voltage on Any Pin with Respect to VSS
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25ºC)
Lead Soldering Temperature (10s)
Wiper Current
W
300
ºC
±12
mA
Recommended Operating Conditions
Parameters
VCC
Ratings
+2.5 to +6
-40 to +85
Units
V
Industrial Temperature
°C
Potentiometer Characteristics
Over recommended operating conditions unless otherwise stated.
Min
Typ
100
50
Max
Symbol Parameter
Test Conditions
Units
kΩ
RPOT
RPOT
RPOT
RPOT
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
kΩ
10
kΩ
2.5
kΩ
Potentiometer Resistance
Tolerance
±20
%
RPOT Matching
1
%
mW
mA
Ω
Power Rating
25°C, each pot
50
IW
RW
Wiper Current
+3
Wiper Resistance
Wiper Resistance
Voltage on any RH or RL Pin
Noise
IW = ±3mA @ VCC = 3V
IW = ±3mA @ VCC = 5V
VSS = 0V
200
100
300
150
VCC
RW
Ω
VTERM
VN
GND
V
(4)
nV√Hz
Resolution
0.4
%
Absolute Linearity (5)
Relative Linearity (6)
RW(n)(actual) - R(n)(expected)(8)
RW(n+1) - [RW(n) + LSB](8)
+1
LSB (7)
+0.2 LSB (7)
ppm/ºC
TCRPOT
TCRATIO
Temperature Coefficient of RPOT (4)
Ratiometric Temp. Coefficient (4)
CH/CL/CW Potentiometer Capacitances
fc Frequency Response
+300
20
ppm/ºC
pF
MHz
(4)
10/10/25
0.4
RPOT = 50kΩ (4)
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20ns.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = RTOT / 255 or (RH - RL) / 255, single pot
(8) n = 0, 1, 2, ..., 255
Doc. No. MD-2012 Rev. G
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Test Conditions
SCL = 2MHz, SO = Open
Inputs = GND
Min
Max
Units
f
ICC
Power Supply Current
1
mA
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC, SO = Open
VIN = GND to VCC
5
µA
µA
µA
10
10
ILO
VOUT = GND to VCC
VIL
VIH
VOL1
-1
VCC x 0.3
V
V
V
Input High Voltage
VCC x 0.7 VCC + 1.0
0.4
Output Low Voltage (VCC = 3.0V) IOL = 3 mA
PIN Capacitance (1)
Available over recommended operating range from TA = 25ºC, f = 1.0MHz, VCC = 5V (unless otherwise noted).
Symbol Test
Conditions
VOUT = 0V
VIN = 0V
Max.
Units
pF
COUT
CIN
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
8
6
¯¯¯
pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
tSU Data Setup Time
tH
Test Conditions
Min
50
Typ
Max
Units
ns
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
50
ns
tWH
tWL
fSCK
tLZ
125
125
DC
ns
ns
3
50
2
MHz
ns
¯¯¯¯¯
HOLD to Output Low Z
tRI(1)
Input Rise Time
Input Fall Time
µs
(1)
tFI
2
µs
¯¯¯¯¯
tHD
tCD
tWC
tV
100
100
ns
HOLD Setup Time
CL = 50pF
¯¯¯¯¯
HOLD Hold Time
ns
Write Cycle Time
10
ms
ns
Output Valid from Clock Low
Output Hold Time
250
tHO
tDIS
tHZ
0
ns
Output Disable Time
250
100
ns
¯¯¯¯¯
HOLD to Output High Z
ns
¯¯¯
tCS
tCSS
tCSH
250
250
250
ns
CS High Time
¯¯¯
ns
CS Setup Time
¯¯¯
CS Hold Time
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2012 Rev. G
CAT5401
Power Up Timing (1)(2)
Symbol Parameter
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
Write Cycle Limits
Symbol
Parameter
Write Cycle Time
Max
Units
tWR
5
ms
Reliability Characteristics
Symbol
Parameter
Reference Test Method
Min
1,000,000
100
Max
Units
(3)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Cycles/Byte
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
Years
V
(3)
VZAP
2000
(3)
ILTH
100
mA
Figure 1. Synchronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
H
t
SU
VIH
VIL
VALID IN
t
RI
t
FI
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
¯¯¯¯¯
Figure 2. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
t
HZ
HIGH IMPEDANCE
SO
t
LZ
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Dashed Line = mode (1, 1) - - - - - - -
Doc. No. MD-2012 Rev. G
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
INSTRUCTION AND REGISTER
DESCRIPTION
INSTRUCTION BYTE
DEVICE TYPE / ADDRESS BYTE
The next byte sent to the CAT5401 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of four Wiper
Control Registers. The format is shown in Table 2.
The first byte sent to the CAT5401 from the master/
processor is called the Device Address Byte. The
most significant four bits of the Device Type address
are a device type identifier. These bits for the
CAT5401 are fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address
byte, A1 - A0, are the internal slave address and must
match the physical device address which is defined by
the state of the A1 - A0 input pins for the CAT5401 to
successfully continue the command sequence. Only
the device which slave address matches the incoming
device address sent by the master executes the
instruction. The A1 - A0 inputs can be actively driven
by CMOS input signals or tied to VCC or VSS. The
remaining two bits in the device address byte must be
set to 0.
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
1
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
0
0
A1
A0
(LSB)
1
(MSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-2012 Rev. G
CAT5401
Registers is a non-volatile operation and will take a
maximum of 5ms.
Wiper Control and Data Registers
Wiper Control Register (WCR)
Write in Process
The CAT5401 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
The contents of the Data Registers are saved to
¯¯¯
nonvolatile memory when the CS input goes HIGH
after a write sequence is received. The status of the
internal write cycle can be monitored by issuing a
Read Status command to read the Write in Process
(WIP) bit.
Instructions
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in the
WCR
The Wiper Control Register is a volatile register that
loses its contents when the CAT5401 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
— Read Data Register – read the contents of the
selected Data Register
Data Registers (DR)
— Write Data Register – write a new value to the
selected Data Register
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
— Read Status – Read the status of the WIP bit
which when set to "1" signifies a write cycle is in
progress.
Table 3. Instruction Set
Note: 1/0 = data is one or zero
Instruction Set
I3 I2 I1 I0 R1 R0 WCR1/ P1
Instruction
WCR0/ P0 Operation
Read the contents of the Wiper Control
Register pointed to by P1-P0
Read Wiper Control
Register
1
0
0
1
0
0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
Write Wiper Control
Register
1
0
1
0
0
0
1/0
1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
Read Data Register
1
1
1
0
1
1
1
0
0
1
0
1
1/0 1/0
1/0 1/0
1/0 1/0
1/0
1/0
1/0
1/0
1/0
1/0
Write Data Register
XFR Data Register to
Wiper Control Register
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
XFR Wiper Control
Register to Data
Register
1
0
1
1
0
0
1
0
0
0
1
0
1/0 1/0
1/0 1/0
1/0 1/0
1/0
0
1/0
0
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Registers
Global XFR Data
Registers to Wiper
Control Registers
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Global XFR Wiper
Control Registers to
Data Register
0
0
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
Increment/Decrement
Wiper Control Register
0
0
0
1
1
0
0
1
0
0
0
0
1/0
0
1/0
1
Read WIP bit to check internal write cycle
status
Read Status (WIP bit)
Doc. No. MD-2012 Rev. G
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
— Gang XFR Data Register to Wiper Control
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of tWR to
complete. The transfer can occur between one of the
four potentiometers and one of its associated
registers; or the transfer can occur between all
potentiometers and one associated register.
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
— Gang XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
Increment/Decrement Command
The final command is Increment/Decrement (Figure
5). The Increment/Decrement command is different
from the other commands. Once the command is
issued the master can clock the selected wiper up
and/or down in one segment steps; thereby providing
a fine tuning capability to the host. For each SCK
clock pulse (tHIGH) while SI is HIGH, the selected wiper
will move one resistor segment towards the RH
terminal. Similarly, for each SCK clock pulse while SI
is LOW, the selected wiper will move one resistor
segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 3. These instructions
transfer data between the host/processor and the
CAT5401; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 3. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0
A2 A1 A0
A3
I3 I2 I1
I0
R1 R0 P1 P0
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 4. Three-Byte Instruction Sequence
0
1
0
1
0
0
SI
I3
I1
P1 P0 D7 D6 D5 D4 D3 D2 D1 D0
I0 R1 R0
I2
ID3 ID2
ID0 A3 A2 A1 A0
Internal
Address
ID1
Device ID
Instruction
Opcode
Data
Pot/WCR
WCR[7:0]
or
Data Register D[7:0]
Register Address
Address
Figure 5. Increment/Decrement Instruction Sequence
0
1
0
1
0
0
SI
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0 I3
I2
I0
R1 R0 P1 P0
I
N
C
I
D
E
C
1
I
D
E
C
n
N
C
2
N
C
n
Instruction
Opcode
Pot/WCR
Data
Register
Address
Internal
Address
Address 1
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-2012 Rev. G
CAT5401
Figure 6. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRID
SCK
SI
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0
1
0
1
0
0
A1 A0
1
1
0
0
0
1
0
0
P1 P0
7
0
6
0
5
5
4
3
2
2
2
2
1
1
1
1
0
0
0
0
¯¯¯
CS
¯¯¯
CS
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0
1
0
1
0
0
A1 A0
1
0
0
0
P1 P0
7
0
6
0
4
3
¯¯¯
CS
¯¯¯
CS
Read Data Register (DR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
R1 R0 P1 P0
DATA
0
1
0
1
0
0
1
0
1
1
0
1
7
6
5
4
3
¯¯¯
CS
¯¯¯
CS
Write Data Register (DR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
DATA
High
Voltage
Write
0
1
0
1
0
0
1
0
R1 R0 P1 P0
7
6
5
4
3
¯¯¯
CS
¯¯¯
CS
Cycle
Read (WIP) Status
DEVICE ADDRESSES
A1 A0
INSTRUCTION
DATA
0
1
0
1
0
0
0
1
0
1
0
0
0
1
7
0
6
0
5
0
4
0
3
0
2
1
W
I
¯¯¯
CS
¯¯¯
CS
0
0
P
Doc. No. MD-2012 Rev. G
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
R1 R0
0
1
0
1
0
0
0
0
0
1
0
0
¯¯¯
CS
¯¯¯
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
R1 R0
High
Voltage
Write
0
1
0
1
0
0
1
0
0
0
0
0
¯¯¯
CS
¯¯¯
CS
Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
R1 R0 P1 P0
High
Voltage
Write
0
1
0
1
0
0
1
1
1
0
¯¯¯
CS
¯¯¯
CS
Cycle
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
R1 R0 P1 P0
0
1
0
1
0
0
1
1
0
1
¯¯¯
CS
¯¯¯
CS
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
A1 A0
INSTRUCTION
DATA
. . .
0
1
0
1
0
0
0
0
1
0
0
0
P1 P0 I/D I/D
I/D I/D
¯¯¯
CS
¯¯¯
CS
Note:
¯¯¯
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-2012 Rev. G
CAT5401
PACKAGE OUTLINES
SOIC 24-Lead 300mils (W) (1)(2)
SYMBOL
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
NOM
MAX
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
A
A1
A2
b
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
b
e
L
θ
PIN#1 IDENTIFICATION
θ1
5°
15°
TOP VIEW
h
D
h
θ1
A2
θ
A
θ1
L
c
A1
SIDE VIEW
END VIEW
2HFor current Tape and Reel information, download the PDF file
from:
Notes:
(1) All dimensions are in millimeters, angles in degrees.
(2) Complies with JEDEC standard MO-013.
Doc. No. MD-2012 Rev. G
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT5401
(1)(2)
TSSOP 24-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.70
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
3HFor current Tape and Reel information, download the PDF file
from:
Notes:
(1) All dimensions are in millimeters, angles in degrees.
(2) Complies with JEDEC standard MO-153.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-2012 Rev. G
CAT5401
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
5401
W
I
-00
- T1
Package
W: SOIC
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
Resistance
25: 2.5kΩ
10: 10kΩ
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Company ID
50: 50kΩ
00: 100kΩ
Product Number
5401
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The device used in the above example is a CAT5401WI-00-T1 (SOIC, Industrial Temperature, 100kΩ, Tape & Reel).
(3) The lead finish is Matte-Tin.
Ordering Part Number
CAT5401WI-25
CAT5401WI-10
CAT5401WI-50
CAT5401WI-00
CAT5401YI-25
CAT5401YI-10
CAT5401YI-50
CAT5401YI-00
Doc. No. MD-2012 Rev. G
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
03/31/2004
F
Changed Preliminary designation to Final
Eliminated Commercial temp range in all areas
Updated Potentiometer characteristics notes
¯¯¯
Updated Pin Descriptions (A0, A1 and WP)
Updated notes for Absolute Max Ratings 80
and Potentiometer Characteristics
Added Example of Ordering Information
Deleted BGA package
10/16/2007
G
Added MD- to document number
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
1Hwww.catsemi.com
Document No: MD-2012
Revision:
G
Issue date:
10/16/07
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