CAT5401JI-00-TE13 [CATALYST]
Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface; 四路数字可编程电位计（ DPP ™ ）与64丝锥和SPI接口
| 型号： | CAT5401JI-00-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Quad Digitally Programmable Potentiometers (DPP⑩) with 64 Taps and SPI Interface |
| 文件： | 总18页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT5401
Quad Digitally Programmable Potentiometers (DPP™)
with 64 Taps and SPI Interface
TM
FEATURES
■ Automatic recall of saved wiper settings at
■ Four linear-taper digitally programmable
power up
potentiometers
■ 2.5 to 6.0 volt operation
■ 64 resistor taps per potentiometer
■ Standby current less than 1µA
■ 1,000,000 nonvolatile WRITE cycles
■ 100 year nonvolatile memory data retention
■ 24-lead SOIC, 24-lead TSSOP and BGA
■ Industrial temperature range
■ End to end resistance 2.5kΩ, 10kΩ, 50kΩ or 100kΩ
■ Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
■ Low wiper resistance, typically 80Ω
■ Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
wiper control register or any of the non-volatile data
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5401 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
aseriesof63resistiveelementsconnectedbetweentwo
externallyaccessibleendpoints.Thetappointsbetween
eachresistiveelementareconnectedtothewiperoutputs
with CMOS switches. A separate 6-bit control register
(WCR)independentlycontrolsthewipertapswitchesfor
each DPP. Associated with each wiper control register
are four 6-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
The CAT5401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
R
R
H3
R
R
H2
H1
H0
24
23
22
21
20
19
18
17
16
15
14
13
NC
R
24
23
22
21
20
19
18
17
16
15
14
13
WP
CS
R
V
1
SI
1
CC
R
2
A
2
L3
L0
1
R
R
A
R
R
3
R
R
3
H3
W0
H0
L1
CS
SCK
R
R
R
W0
W1
W2
W3
WIPER
CONTROL
REGISTERS
SPI BUS
INTERFACE
R
R
V
4
4
W3
H0
W0
CS
H1
SI
SO
5
R
5
0
L0
W1
SO
WP
SI
6
GND
NC
6
CC
CAT
5401
CAT
5401
HOLD
SCK
NC
7
7
WP
A0
A1
R
R
R
A
A
8
R
8
NONVOLATILE
DATA
REGISTERS
1
L3
CONTROL
LOGIC
W2
R
L2
R
9
R
9
H3
W3
L1
H2
R
R
H2
R
10
11
12
R
10
11
12
H1
L2
R
W2
R
W1
SCK
0
R
R
L3
R
L1
R
L2
L0
NC
SO
GND
HOLD
1
2
3
4
R
CS
WP
A
R
L1
W0
1
A
R
SI
R
W1
L0
B
C
D
E
F
V
R
R
V
CC
H0
H3
H1
H2
SS
NC
BGA
NC
R
R
R
SO
HOLD
SCK
R
W2
L3
R
W3
A
R
L2
0
Top View - Bump Side Down
1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2010, Rev. F
CAT5401
PIN DESCRIPTION
PIN DESCRIPTIONS
SI:
Serial Input
Pin
Pin
Pin
SI is the serial data input pin. This pin is used to input
all opcodes, byte addresses and data to be written to
the CAT5401. Input data is latched on the rising edge
of the serial clock.
(SOIC) (TSSOP) (BGA) Name Function
1
2
19
20
C1
B1
VCC
RL0
Supply Voltage
Low Reference Terminal
for Potentiometer 0
SO:
Serial Output
3
21
C2
RH0
High Reference Terminal
for Potentiometer 0
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5401. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
4
5
6
7
8
9
22
23
24
1
A1
A2
B2
B3
A3
A4
RW0
CS
WP
SI
Wiper Terminal for Potentiometer 0
Chip Select
Write Protection
SCK:
Serial Clock
Serial Input
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5401. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
2
A1
Device Address
3
RL1
Low Reference Terminal
for Potentiometer 1
10
4
C3
RH1
High Reference Terminal
for Potentiometer 1
A0, A1: Device Address Inputs
11
12
13
14
5
6
7
8
B4
C4
D4
E4
RW1
GND
NC
Wiper Terminal for Potentiometer 1
These inputs set the device address when address-
ing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5401.
Ground
No Connect
RW2
Wiper Terminal for
Potentiometer 2
15
16
9
D3
F4
RH2
RL2
High Reference Terminal
for Potentiometer 2
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
10
Low Reference Terminal
for Potentiometer 2
RW:
Wiper
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
17
18
19
20
21
22
11
12
13
14
15
16
F3
E3
E2
F2
F1
D2
SCK
HOLD
SO
Bus Serial Clock
Hold
CS:
Chip Select
Serial Data Output
Device Address, LSB
Wiper Terminal for Potentiometer 3
CS is the Chip select pin. CS low enables the
CAT5401 and CS high disables the CAT5401. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby mode (unless an internal
write operation is underway). The CAT5401 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence
being initiated. A low to high transition on CS after a
valid write sequence is what initiates an internal write
cycle.
A0
RW3
RH3
High Reference Terminal
for Potentiometer 3
23
24
17
18
E1
D1
RL3
NC
Low Reference Terminal
for Potentiometer 3
No Connect
WP:
Write Protect
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no
effect on any write operation.
HOLD: Hold
The HOLD pin is used to pause transmission to the CAT5401 while in the middle of a serial sequence without having to re-
transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high imped-
ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2010, Rev. F
2
CAT5401
SERIAL BUS PROTOCOL
The CAT5041 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5401 to interface directly with many
of today's popular microcontrollers. The CAT5041
containsan8-bitinstructionregister.Theinstruction set
and the operation codes are detailed in the instruction
set table 3.
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI pin,
withdatabeingclockedinontherisingedgeofSCK.The
first byte contains one of the six op-codes that define the
operation to be performed.
DEVICE OPERATION
The CAT5401 is four resistor arrays integrated with SPI
serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL). RH and RL are
symmetricalandmaybeinterchanged.Thetappositions
between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a
CMOS transistor switch. Only one tap point for each
potentiometerisconnectedtoitswiperterminalatatime
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Document No. 2010, Rev. F
3
CAT5401
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Voltage on any Pin with
Respect to VSS(1) ................... -2.0V to +VCC +2.0V
Recommended Operating Conditions:
V
CC with Respect to Ground ................ -2.0V to +7.0V
V
CC
= +2.5V to +6.0V
Package Power Dissipation
Temperature
Min
Max
Capability (TA = 25°C) ................................... 1.0W
Industrial
-40°C
85°C
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current.................................................. +12mA
Notes:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output
pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
RPOT
Parameter
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance Tolerance
RPOT Matching
Test Conditions
Min
Typ
100
50
Max
Units
kΩ
RPOT
kΩ
RPOT
10
kΩ
RPOT
2.5
kΩ
+20
1
%
%
Power Rating
25°C, each pot
50
mW
mA
IW
RW
Wiper Current
+6
Wiper Resistance
IW = +3mA @ VCC =3V
300
150
VCC
Ω
RW
Wiper Resistance
IW = +3mA @ VCC = 5V
80
Ω
VTERM
VN
Voltage on any RH or RL Pin
Noise
VSS = 0V
(1)
GND
V
TBD
1.6
nV/ Hz
%
Resolution
(1)
Absolute Linearity (2)
Rw(n)(actual)-R(n)(expected)
+1
LSB (4)
LSB (4)
ppm/°C
ppm/°C
pF
(5)
Relative Linearity (3)
Rw(n+1)-[Rw(n)+LSB
]
+0.2
(5)
TCRPOT
TCRATIO
CH/CL/CW
fc
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
(1)
(1)
+300
20
(1)
10/10/25
0.4
RPOT = 50kΩ
MHz
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(5) n = 0, 1, 2, ..., 63
Document No. 2010, Rev. F
4
CAT5401
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC
Power Supply Current
fSCK = 2MHz, SO Open
Inputs = GND
1
mA
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC; SO Open
VIN = GND to VCC
1
µA
µA
µA
10
10
ILO
VOUT = GND to VCC
VIL
-1
VCC x 0.3
VCC + 1.0
0.4
V
V
V
VIH
VOL1
Input High Voltage
VCC x 0.7
Output Low Voltage (VCC = 3.0V)
IOL = 3 mA
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Min
Typ
Max
8
Units
pF
Conditions
VOUT=0V
VIN=0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Document No. 2010, Rev. F
5
CAT5401
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Test
SYMBOL
tSU
PARAMETER
Min
50
Typ
Max UNITS
Conditions
Data Setup Time
Data Hold Time
ns
ns
ns
ns
tH
50
tWH
SCK High Time
125
125
DC
tWL
SCK Low Time
fSCK
tLZ
Clock Frequency
HOLD to Output Low Z
Input Rise Time
3
50
2
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
(1)
tRI
(1)
tFI
Input Fall Time
2
CL = 50pF
tHD
tCD
tWC
tV
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
10
250
tHO
tDIS
tHZ
tCS
tCSS
0
250
100
250
250
250
CS Setup Time
tCSH
CS Hold Time
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(1)
POWER UP TIMING
Over recommended operating conditions unless otherwise stated.
Symbol
tPUR
Parameter
Min
Typ
Max Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2010, Rev. F
6
CAT5401
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Typ
Max
Units
tWR
Write Cycle Time
5
ms
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)
ILTH
100
mA
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Figure 2. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
t
HZ
HIGH IMPEDANCE
SO
t
LZ
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
(3) Dashed Line= mode (1, 1) — — — —
Document No. 2010, Rev. F
7
CAT5401
INSTRUCTION BYTE
INSTRUCTION AND REGISTER
DESCRIPTION
ThenextbytesenttotheCAT5401containstheinstruction
andregisterpointerinformation.Thefourmostsignificant
bits used provide the instruction opcode I [3:0]. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of four Wiper Control Registers. The format
is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5401 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a
device type identifier. These bits for the CAT5401 are
fixed at 0101[B] (refer to Table 1).
Data Register Selection
The two least significant bits in the slave address byte,
A1 - A0, are the internal slave address and must match
thephysicaldeviceaddresswhichisdefinedbythestate
of the A1 - A0 input pins for the CAT5401 to successfully
continuethecommandsequence.Onlythedevicewhich
slave address matches the incoming device address
sent by the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS. The remaining two bits in the device
address byte must be set to 0.
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
1
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
0
0
A1
A0
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
Document No. 2010, Rev. F
8
CAT5401
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5401 contains four 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction;
it may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after
a write sequence is received. The status of the internal
write cycle can be monitored by issuing a Read Status
command to read the Write in Process (WIP) bit.
INSTRUCTIONS
Five of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register - read the current
wiperpositionoftheselectedpotentiometerintheWCR
The Wiper Control Register is a volatile register that
loses its contents when the CAT5401 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
— Write Wiper Control Register - change current
wiperpositionintheWCRoftheselectedpotentiometer
— Read Data Register - read the contents of the
selected Data Register
Data Registers (DR)
— Write Data Register - write a new value to the
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
selected Data Register
— Read Status - Read the status of the WIP bit which
Table 3. Instruction Set
Instruction Set
WCR1/ WCR0/
Instruction
I3
I2
I1
I0
R1
R0
Operation
P1
P0
Read Wiper Control
Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control
Register pointed to by P1-P0
Write Wiper Control Register
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write Data Register
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
XFR Data Register to Wiper
Control Register
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Wiper Control Register
to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
1/0 1/0
1/0 1/0
1/0 1/0
1/0
0
1/0
0
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
GlobalXFR DataRegisters
to Wiper Control Registers
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Regsister
Global XFR Wiper Control
Registers to Data Register
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Increment/Decrement Wiper
Control Register
0
0
0
1
1
0
0
1
0
0
0
0
1/0
0
1/0
1
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
Read WIP bit to check internal
write cycle status
Read Status (WIP bit)
Note: 1/0 = data is one or zero
Document No. 2010, Rev. F
9
CAT5401
when set to "1" signifies a write cycle is in progress.
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
bytWRL.AtransferfromtheWCR(currentwiperposition),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the four potentiometers and one
of its associated registers; or the transfer can occur
betweenallpotentiometersandoneassociatedregister.
— Global XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is different
from the other commands. Once the command is issued
the master can clock the selected wiper up and/or down
in one segment steps; thereby providing a fine tuning
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5401; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
capability to the host. For each SCK clock pulse (tHIGH
)
while SI is HIGH, the selected wiper will move one
resistor segment towards the RH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the RL
terminal.
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
See Instructions format for more detail.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated
Data Register.
— Global XFR Data Register to Wiper
Figure 7. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0
A2 A1 A0
A3
I3 I2 I1
I0
R1 R0 P1 P0
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 8. Three-Byte Instruction Sequence
0
1
0
1
SI
I3
I1
P1 P0 D7 D6 D5 D4 D3 D2 D1 D0
I0 R1 R0
I2
ID3 ID2
ID0 A3 A2 A1 A0
ID1
Internal
Address
Device ID
Instruction
Opcode
Data
Register Address
Address
Pot/WCR
WCR[7:0]
or
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
SI
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0 I3
I2
I0
R1 R0 P1 P0
I
I
D
E
C
1
I
D
E
C
n
N
N
C
2
N
C
n
Instruction
Opcode
Pot/WCR
Address 1
Data
C
Internal
Address
Register
Address
Document No. 2010, Rev. F
10
CAT5401
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRID
SCK
SI
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 0 1 0 0 P1 P0 7 6 5 4 3 2 1 0
CS
CS
0
0
Write Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 1 0 0 0 P1P0 7
0
6
5 4 3 2 1 0
CS
CS
0
Read Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 1 0 1 1 R1 R0 P1P0 7 6 5 4 3 2 1
0
0
CS
CS
Write Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
High Voltage
Write Cycle
0 1 0 1 0 0 A1 A0 1 1 0 0 R1 R0 P1P0 7 6 5 4 3 2 1
CS
CS
CS
Read (WIP) Status
DEVICE ADDRESSES
0 1 0 1 0 0 A1 A0 0 1 0 1 0 0 0 1 7 6 5 4 3
INSTRUCTION
DATA
W
2
0
1
0
CS
I
0 0 0 0
0
P
Document No. 2010, Rev. F
11
CAT5401
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
0 1 0 1 0 0 A1 A0 0 0 0 1 R1 R0 0 0
CS
CS
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High Voltage
Write Cycle
0 1 0 1 0 0 A1 A0 1 0 0 0 R1 R0 0 0
CS
CS
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High Voltage
Write Cycle
0 1 0 1 0 0 A1 A0 1 1 1 0 R1 R0 P1 P0
CS
CS
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
0 1 0 1 0 0 A1A0 1 1 0 1 R1 R0 P1 P0
CS
CS
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 0 0 A1 A0 0 0 1 0 0 0 P1 P0 I/D I/D
I/D I/D
CS
CS
• • •
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after CS goes high.
Document No. 2010, Rev. F
12
CAT5401
ORDERING INFORMATION
Prefix
Device #
Suffix
-TE13
CAT
5401
J
I
-10
Optional
Company ID
Product
Number
Tape & Reel
TE13: 2000/Reel
Package
J: SOIC
B: BGA
U: TSSOP
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Resistance
-25: 2.5kohm
-10: 10kohm
-50: 50kohm
-00: 100kohm
Temperature Range
Notes:
(1) The device used in the above example is a CAT5401JI-10-TE13 (SOIC, Industrial Temperature, 10kohm, Tape & Reel)
Document No. 2010, Rev. F
13
CAT5401
PACKAGING INFORMATION
24-LEAD 300 MIL WIDE SOIC (J)
0.2914 (7.40) 0.394 (10.00)
0.2992 (7.60) 0.419 (10.65)
0.5985 (15.20)
0.6141 (15.60)
0.0926 (2.35)
0.1043 (2.65)
0.050 (1.27) BSC
0.0040 (0.10)
0.0118 (0.30)
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
X 45
0.029 (0.75)
0.0091 (0.23)
0.0125 (0.32)
0 —8
0.016 (0.40)
0.050 (1.27)
Document No. 2010, Rev. F
14
CAT5401
PACKAGING INFORMATION CON'T
24 Lead TSSOP (U)
7.8 + 0.1
-A-
7.72 TYP
6.4
4.16 TYP
4.4 + 0.1
-B-
(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
0.2 C B A
ALL LEAD TIPS
LAND PATTERN RECOMMENDATION
PIN #1 INDENT.
1.1 MAX TYP
0.1 C
ALL LEAD TIPS
(0.9)
-C-
0.10 + 0.05 TYP
0.65 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
SEE DETAIL A
GAGE PLANE
0.25
0.09 - 0.20 TYP
0o- 8o
0.6+0.1
SEATING PLANE
DETAIL A
Document No. 2010, Rev. F
15
CAT5401
PACKAGING INFORMATION CON'T
24 Ball BGA
a
a
j
m
k
1
2
3
4
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
b
b
f
Top View (Bump Side Down)
Bottom View (Bump Side Up)
Note: Drawing not to scale
= Die orientation mark
d
c
e
Side View (Bump Side Down)
MillimetersInches
Symbol
Min
TBD
TBD
0.635
0.433
0.202
0.284
24
Nom
TBD
Max
TBD
TBD
Nom
TBD
TBD
Min
TBD
TBD
Max
Package Body Dimension X
Package Body Dimension Y
Package Height
a
b
c
d
e
f
TBD
TBD
TBD
0.505
0.395
0.110
0.180
0.765 0.02500 0.01988 0.03012
0.471 0.01705 0.01555 0.01854
0.294 0.00795 0.00433 0.01157
0.388 0.01118 0.00709 0.01528
Package Body Thickness
Ball Height
Ball Diameter
Total Ball Count
g
h
i
Ball Count X Axis
Ball Count Y Axis
Pins Pitch X Axis
4
6
j
0.5
Pins Pitch Y Axis
k
0.5
Edge to Ball Center (Corner)
Distance Along X
l
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Edge to Ball Center (Corner)
Distance Along Y
m
Document No. 2010, Rev. F
16
REVISION HISTORY
Date
Rev.
Reason
3/31/2004
F
Changed Preliminary designation to Final
Eliminated Commercial temp range in all areas
Updated Potentiometer characteristics notes
Updated Pin Descriptions (A0, A1 and WP)
Updated notes for Absolute Max Ratings and Potentiometer Characteristics
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
DPPs ™ AE ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Publication #: 2010
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Revison:
Issue date:
Type:
F
3/31/04
Final
www.catalyst-semiconductor.com
This datasheet has been download from:
www.datasheetcatalog.com
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