CAT522WI-TE13 [CATALYST]
Digital Potentiometer, 1 Func, PDSO14, LEAD-FREE, SOIC-14;型号: | CAT522WI-TE13 |
厂家: | CATALYST SEMICONDUCTOR |
描述: | Digital Potentiometer, 1 Func, PDSO14, LEAD-FREE, SOIC-14 光电二极管 转换器 |
文件: | 总11页 (文件大小:85K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
E
CAT522
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
TM
FEATURES
APPLICATIONS
■ Two 8-bit DPPs configured as programmable
■ Automated product calibration.
voltage sources in DAC-like applications
■ Remote control adjustment of equipment
■ Independent reference inputs
■ Offset, gain and zero adjustments in self-
■ Non-volatile NVRAM memory wiper storage
■ Output voltage range includes both supply rails
calibrating and adaptive control systems.
■ Tamper-proof calibrations.
■ 2 independently addressable buffered
■ DAC (with memory) substitute.
output wipers
■ 1 LSB accuracy, high resolution
■ Serial Microwire-like interface
■ Single supply operation: 2.7V - 5.5V
■ Setting read-back without effecting outputs
DESCRIPTION
dithered to test new output values without effecting the
stored settings and stored settings can be read back
without disturbing the DPP's output.
The CAT522 is a dual, 8-bit digitally-programmable
potentiometer (DPP™) configured for programmable
voltage and DAC-like applications. Intended for final
calibration of products such as camcorders, fax
machines and cellular telephones on automated high
volume production lines, it is also well suited for
self-calibrating systems and for applications where
equipment which requires periodic adjustment is either
difficult to access or in a hazardous environment.
TheCAT522iscontrolledwithasimple3-wire,microwire-
like serial interface. A Chip Select pin allows several
devices to share a common serial interface.
Communication back to the host controller is via a single
serial data line thanks to the CAT522 Tri-Stated Data
Output pin. A RDY/BSY output working in concert with
aninternallowvoltagedetectorsignalsproperoperation
of the non-volatile NVRAM memory Erase/Write cycle.
The CAT522 offers two independently programmable
DPPs each having its own reference inputs and each
capable of rail to rail output swing. The wipers are
buffered by rail to rail opamps. Wiper settings, stored in
non-volatile NVRAM memory, are not lost when the
device is powered down and are automatically
reinstated when power is returned. Each wiper can be
The CAT522 is available in the 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges. Both 14-pin plastic DIP and surface mount
packages are available.
PIN CONFIGURATION
FUNCTIONAL DIAGRAM
V
V
V
REFH2
13
REFH1
14
RDY/BSY
DD
DIP Package (P, L)
SOIC Package (J, W)
3
1
7
PROGRAM
CONTROL
PROG
1
2
3
4
5
14
13
12
11
10
9
V
V
V
V
V
V
V
1
2
3
4
5
14
13
12
11
10
9
V
V
V
V
V
V
V
DD
REFH1
REFH2
OUT1
DD
REFH1
REFH2
OUT1
CLK
RDY/BSY
CS
CLK
RDY/BSY
CS
5
2
DI
11
12
+
+
V
WIPER
CONTROL
REGISTERS
AND
28KΩ
OUT2
SERIAL
CONTROL
CLK
NVRAM
OUT2
4
OUT2
CAT522
CS
CAT522
V
28kΩ
OU
DI
DI
REFL2
REFL1
REFL2
REFL1
DO
6
7
DO
6
7
SERIAL
6
8
PROG
GND
DATA
8
PROG
GND
DO
OUTPUT
REGISTER
CAT522
8
9
10
V
V
REFL2
GND
REFL1
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 2004, Rev. D
1
CAT522
ABSOLUTE MAXIMUM RATINGS
Operating Ambient Temperature
Commercial (‘C’ or Blank suffix) ...... 0°C to +70°C
Industrial (‘I’ suffix)........................ -40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ........................ -65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
Supply Voltage*
VDD to GND ...................................... -0.5V to +7V
Inputs
CLK to GND............................ -0.5V to VDD +0.5V
CS to GND.............................. -0.5V to VDD +0.5V
DI to GND ............................... -0.5V to VDD +0.5V
RDY/BSY to GND ................... -0.5V to VDD +0.5V
PROG to GND ........................ -0.5V to VDD +0.5V
VREFH to GND ........................ -0.5V to VDD +0.5V
VREFL to GND ......................... -0.5V to VDD +0.5V
Outputs
*StressesabovethoselistedunderAbsoluteMaximumRatings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied.Deviceperformanceandreliabilitymaybeimpairedby
exposure to absolute rating conditions for extended periods of
time.
D0 to GND............................... -0.5V to VDD +0.5V
VOUT 1– 4 to GND................... -0.5V to VDD +0.5V
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
Test Method
(1)
VZAP
ESD Susceptibility
Latch-Up
2000
100
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)(2)
ILTH
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
POWER SUPPLY
Symbol Parameter
IDD1 Supply Current (Read)
IDD2
Conditions
Min
Typ
Max
Units
Normal Operating
Programming, VDD = 5V
VDD = 3V
—
—
400
1600
1000
—
600
2500
1600
5.5
µA
µA
µA
V
Supply Current (Write)
—
VDD
Operating Voltage Range
2.7
LOGIC INPUTS
Symbol Parameter
Conditions
Min
Typ
Max Units
IIH
Input Leakage Current
VIN = VDD
VIN = 0V
—
—
2
—
—
—
—
10
-10
VDD
0.8
µA
µA
V
IIL
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
VIH
VIL
0
V
LOGIC OUTPUTS
Symbol Parameter
Conditions
Min
VDD -0.3
—
Typ
—
Max
—
Units
VOH
VIL
High Level Output Voltage IOH = -40µA
V
V
V
Low Level Output Voltage IOL = 1 mA, VDD = +5V
IOL = 0.4 mA, VDD = +3V
—
0.4
0.4
—
—
Doc. No. 2004, Rev. D
2
CAT522
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
28
Max
Units
kΩ
RPOT
Potentiometer Resistance
RPOT to RPOT Match
Pot Resistance Tolerance
Voltage on VREFH pin
Voltage on VREFL pin
Resolution
—
+0.5
+1
+20
%
%
2.7
OV
VDD
V
VDD - 2.7
V
0.4
0.5
%
INL
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
1
0.5
10
3
LSB
LSB
Ω
DNL
0.25
ROUT
IOUT
mA
ppm/˚C
ppm/˚C
Ω
TCRPOT
300
8/8
TCRATIO Ratiometric TC
RISO
VN
Isolation Resistance
Noise
nV/√Hz
pF
CH/CL
fc
Potentiometer Capacitances
Frequency Response
Passive Attenuator
MHz
AC ELECTRICAL CHARACTERISTICS:
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Digital
Conditions
Min
Typ
Max
Units
tCSMIN
tCSS
tCSH
tDIS
Minimum CS Low Time
150
100
0
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
150
150
—
—
5
ns
ns
CS Setup Time
CS Hold Time
ns
DI Setup Time
50
ns
CL=100pF,
tDIH
DI Hold Time
50
ns
see note 1
tDO1
tDO0
tHZ
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
—
ns
—
ns
—
ns
tLZ
—
ns
tBUSY
tPS
—
ms
ns
150
700
500
300
DC
—
—
—
—
—
—
—
—
—
1
tPROG
ns
tCLK
tCLK
fC
H
ns
L
ns
MHz
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10 pF, VDD = +5V
CLOAD = 10 pF, VDD = +3V
—
—
3
6
10
10
µs
µs
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
Doc. No. 2004, Rev. D
3
CAT522
A. C. TIMING DIAGRAM
t
1
2
3
4
5
o
t
H
CLK
CLK
t
t
L
t
CSH
CSS
CLK
CS
t
CSMIN
t
DIS
DI
t
DIH
t
DO0
t
LZ
DO
t
HZ
t
DO1
PROG
t
PS
t
PROG
RDY/BSY
t
BUSY
t
1
2
3
4
5
o
Doc. No. 2004, Rev. D
4
CAT522
PIN DESCRIPTION
DPP addressing is as follows:
Pin
Name
Function
DPP OUTPUT
A0
0
A1
1
1
2
3
4
5
6
7
VDD
Power supply positive
Clock input pin
V
OUT1
OUT2
CLK
RDY/BSY
CS
V
1
1
Ready/Busy output
Chip select
DI
Serial data input pin
Serial data output pin
DO
PROG
EEPROM Programming Enable
Input
8
GND
Power supply ground
9
VREFL1
VREFL2
VOUT2
VOUT1
VREFH2
VREFH1
Minimum DPP 1 output voltage
Minimum DPP 2 output voltage
DPP 2 output
10
11
12
13
14
DPP 1 output
Maximum DPP 2 output voltage
Maximum DPP 1 output voltage
DEVICE OPERATION
CHIP SELECT
The CAT522 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retainedinnon-volatilememoryandwillnotbelostwhen
power is removed from the chip. Upon power up the
DPPsreturntothesettingsstoredinnon-volatilememory.
EachDPPcanbewrittentoandreadfromindependently
without effecting the output voltage during the read or
write cycle. Each output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
Chip Select (CS) enables and disables the CAT522’s
readandwriteoperations. WhenCSishighdatamaybe
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
DIGITAL INTERFACE
The CAT522’s clock controls both data flow in and out of
theICandnon-volatilememorycellprogramming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’srisingedge. Whileitisnotnecessaryfortheclock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
The CAT522 employs a 3 wire serial, Microwire-like
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
No clock is necessary upon system power-up. The
CAT522’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
Doc. No. 2004, Rev. D
5
CAT522
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
intothecontrolregisters. StandardCMOSandTTLlogic
families work well in this regard and it is recommended
thatanymechanicalswitchesusedforbreadboardingor
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
single serial data line and simplifies interfacing multiple
522s to a microprocessor.
WRITING TO MEMORY
Programming the CAT522’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followedbyatwobitDPPaddressandeightdatabitsare
clockedintotheDPPwipercontrolregisterviatheDIpin.
Data enters on the clock’s rising edge. The DPP output
changes to its new setting on the clock cycle following
D7, the last data bit.
V
REF
VREF, the voltage applied between pins VREFH &VREFL
,
sets the configured DPP’s Zero to Full Scale output
range where VREFL = Zero and VREFH = Full Scale. VREF
can span the full power supply range or just a fraction of
it. In typical applications VREFH &VREFL are connected
across the power supply rails. When using less than the
full supply voltage be mindful of the limits placed on
VREFL and VREFL as specified in the References section
of DC Electrical Characteristics.
Programming is accomplished by bringing PROG high
sometimeafterthestartbitandatleast150nspriortothe
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DPP wiper
control register will be ready to receive the next set of
address and data bits. The clock must be kept running
throughout the programming cycle. Internal control
circuitry takes care of generating and ramping up the
programmingvoltagefordatatransfertothenon-volatile
cells. The CAT522’s non-volatile memory cells will
endure over 1,000,000 write cycles and will retain data
for a minimum of 100 years without being refreshed.
READY/BUSY
When saving data to non-volatile memory, the Ready/
Busy ouput (RDY/BSY) signals the start and duration of
the non-volatile erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle
is complete. During this time the CAT522 will ignore any
data appearing at DI and no data will be output on DO.
READING DATA
Each time data is transferred into a DPP control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DPP’s output. This feature allows µPs to
poll DPPs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in non-volatile memory so that it can be
restored at the end of the read cycle. In Figure 2 CS
returns low before the 13th clock cycle completes. In
doingsothenon-volatilememorysettingisreloadedinto
the DPP wiper control register. Since this value is the
RDY/BSYisinternallyANDedwithalowvoltagedetector
circuitmonitoringVDD.IfVDDisbelowtheminimumvalue
required for non-volatile programming, RDY/BSY will
remain high following the program command indicating
afailuretorecordthedesireddatainnon-volatilememory.
DATA OUTPUT
Data is output serially by the CAT522, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
itshighimpedanceTri-StatemodewhenCSreturnslow.
Tri-Stating the DO pin allows several 522s to share a
Figure 1. Writing to Memory
Figure 2. Reading from Memory
t
1
2
3
4
5
6
7
8
9
10 11 12
N
N+1 N+2
t
1
2
3
4
5
6
7
8
9
10 11 12
o
o
CS
DI
CS
DI
NEW DPP DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
1
A0 A1
CURRENT DPP DATA
DO
DO
PROG
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
RDY/BSY
CURRENT
DPP VALUE
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
NEW
DPP VALUE
DPP
OUTPUT
NON-VOLATILE
NON-VOLATILE
VOLATILE
NON-VOLATILE
Doc. No. 2004, Rev. D
6
CAT522
Figure 3. Temporary Change in Output
sameasthatwhichhadbeentherepreviouslynochange
in the DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then a change would occur at the read
cycle’s conclusion.
t
1
2
3
4
5
6
7
8
9
10 11 12
N
N+1 N+2
o
CS
DI
NEW DPP DATA
TEMPORARILY CHANGE OUTPUT
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
The CAT522 allows temporary changes in DPP’s output
to be made without disturbing the settings retained in
non-volatile memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
D0 D1 D2 D3 D4 D5 D6 D7
DO
PROG
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
CURRENT
DPP VALUE
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP wiper settings
may be changed as many times as required and can be
made to any of the two DPPs in any order or sequence.
The temporary setting(s) remain in effect long as CS
remains high. When CS returns low all two DPPs will
returntotheoutputvaluesstoredinnon-volatilememory.
NON-VOLATILE
VOLATILE
NON-VOLATILE
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DPP wiper control register prior to programming. This is
becausetheCAT522’sinternalcontrolcircuitrydiscards
from the programming register the new data two clock
cycles after receiving it if no PROG signal is received.
APPLICATION CIRCUITS
DPP INPUT
DPP OUTPUT
CODE
ANALOG
OUTPUT
+5V
V
V
= ——— (V - V
) + V
DPP
FS
ZERO
ZERO
V
R
R
255
i
i
F
= 0.99 V
REF
FS
V
= 5V
F
REF
R = R
+15V
V
= 0.01 V
MSB LSB
1111 1111
I
ZERO
REF
V
V
REFH
DD
V
–
OUT
255
255
—— (.98 V
) + .01 V
= .990 V
V
= +4.90V
REF
REF
REF
OUT
CONTROL
& DATA
+
CAT522
OP 07
128
1000 0000
0111 1111
0000 0001
—— (.98 V
255
) + .01 V
) + .01 V
) + .01 V
= .502 V
= .498 V
= .014 V
V
V
V
= +0.02V
= -0.02V
= -4.86V
REF
REF
REF
REF
REF
REF
REF
REF
REF
OUT
OUT
OUT
-15V
GND
V
REFL
127
—— (.98 V
255
V
R
F
V
=
(
R ) -V
R +
F i
i
OUT
DPP
1
—— (.98 V
255
R
i
For R =R
i
F
0
0000 0000 —— (.98 V
) + .01 V
= .010 V
V
= -4.90V
REF
REF
REF
OUT
255
V
= 2V -V
OUT
DPP i
Bipolar DPP Output
+5V
R
I
R
F
+15V
V
V
DD
REFH
V
–
OUT
CONTROL
& DATA
+
CAT522
OP 07
DPP
-15V
GND
V
REFL
R
F
V
= (1 + –––) V
OUT
R
I
Amplified DPP Output
Doc. No. 2004, Rev. D
7
CAT522
APPLICATION CIRCUITS (Cont.)
V
+5V
V
+V
REF
REF
R
= —————
C
256 1 µA
*
+5V
V
REF
V
REFH
DD
Fine adjust gives ± 1 LSB change in V
OFFSET
V
REF
2
V
V
when V =
OFFSET
———
DD
REFH
127R
C
FINE ADJUST
DPP
+
)
OFFSET
(+V
) - (V
127R
C
REF
R
= ———————————
1 µA
FINE ADJUST
DPP
C
CAT522
+
(-V
) + (V
)
REF
OFFSET
R
= ———————————
1 µA
o
R
C
CAT522
COARSE ADJUST
DPP
+V
R
C
V
OFFSET
COARSE ADJUST
DPP
GND
V
REFL
+
+V
-V
R
o
V
OFFSET
–
+
-V
REF
GND
V
REFL
–
Coarse-Fine Offset Control by Averaging DPP Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DPP Outputs
for Dual Power Supply Systems
28 - 32V
V+
15K
10 µF
I > 2 mA
1N5231B
5.1V
V
= 5.000V
REF
V
V
REFH
DD
V
V
DD
REFH
10K
CONTROL
& DATA
+
MPT3055EL
CAT522
CONTROL
& DATA
LT 1029
CAT522
–
LM 324
4.02 K
GND
V
REFL
GND
V
OUTPUT
REFL
10 µF
35V
0 - 25V
@ 1A
1.00K
Digitally Trimmed Voltage Reference
Digitally Controlled Voltage Reference
Doc. No. 2004, Rev. D
8
CAT522
APPLICATION CIRCUITS (Cont.)
+5V
2.2K
V
V
REFH
4.7 µA
DD
LM385-2.5
+15V
I
= 2 - 255 mA
1 mA steps
SINK
+
DPP
2N7000
+5V
–
10K
10K
39
39
Ω
Ω
1W
1W
CONTROL
& DATA
CAT522
+
DPP
5 µA steps
2N7000
3.9K
–
GND
V
REFL
5M
5M
10K
10K
–
TIP 30
+
-15V
Current Sink with 4 Decades of Resolution
+15V
51K
+
TIP 29
–
10K
10K
+5V
V
V
REFH
DD
5M
5M
39 Ω1W
39Ω1W
DPP
–
CONTROL
& DATA
CAT522
BS170P
3.9K
1 mA steps
+
5M
5M
DPP
–
GND
V
REFL
BS170P
5 µA steps
+
LM385-2.5
-15V
I
= 2 - 255 mA
SOURCE
Current Source with 4 Decades of Resolution
Doc. No. 2004, Rev. D
9
CAT522
ORDERING INFORMATION
Prefix
Device #
Suffix
-TE13
CAT
522
J
I
Package
Optional
Company ID
Product
Number
Tape & Reel
TE13:
2000/Reel
P: PDIP
J: SOIC
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Temperature Range
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
Notes:
(1) The device used in the above example is a CAT522JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 2004, Rev. D
10
CAT522
REVISION HISTORY
Date
Rev.
Reason
3/16/2004
D
Updated Potentiometer Characteristics
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2
DPP ™
AE ™
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Publication #: 2004
Revison:
Issue date:
Type:
D
3/16/04
Final
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