CAT504JITE13 [CATALYST]
8-Bit Quad DACpot; 8位四路DACpot
| 型号： | CAT504JITE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 8-Bit Quad DACpot |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT504
8-Bit Quad DACpot
FEATURES
APPLICATIONS
■ Output settings retained without power
■ Output range includes both supply rails
■ 4 independently addressable outputs
■ 1 LSB Accuracy
■ Automated product calibration.
■ Remote control adjustment of equipment
■ Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
■ Tamper-proof calibrations.
■ Serial µP interface
■ Single supply operation: 2.7V-5.5V
■ Setting read-back without effecting outputs
DESCRIPTION
The CAT504 is a quad 8-Bit Memory DAC designed as
an electronic replacement for mechanical potentiom-
eters and trim pots. Intended for final calibration of
productssuchascamcorders,faxmachinesandcellular
telephones on automated high volume production lines,
it is also well suited for systems capable of self calibra-
tion, and applications where equipment which is either
difficult to access or in a hazardous environment, re-
quires periodic adjustment.
Control of the CAT504 is accomplished with a simple 3
wire serial interface. A Chip Select pin allows several
CAT504s to share a common serial interface and com-
munication back to the host controller is via a single
serial data line thanks to the CAT504’s Tri-Stated Data
Output pin.
The CAT504 operates from a single 3–5 volt power
supply drawing just a few milliwatts of power. When
storing data in EEPROM memory an additional 20 volt
low current supply is required.
The 4 independently programmable DAC's have an
output range which includes both supply rails. Output
settings, stored in non-volatile EEPROM memory, are
not lost when the device is powered down and are
automatically reinstated when power is returned. Each
output can be dithered to test new output values without
effecting the stored settings and stored settings can be
read back without disturbing the DAC’s output.
The CAT504 is available in the 0 to 70° C Commercial
and –40° C to + 85° C Industrial operating temperature
ranges and offered in 14-pin plastic DIP and Surface
mount packages.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
V
V
V
H
PP
DD
REF
DIP Package (P)
SOIC Package (J)
3
1
14
H
1
H
1
V
V
V
V
1
2
3
4
5
6
14
13
12
11
10
9
V
V
DD
1
2
3
4
5
6
14
13
12
11
10
9
DD
REF
REF
7
PROGRAM
CONTROL
PROG
CLK
CLK
OUT
13
12
11
10
6
OUT
V
1
2
3
4
DAC 1
DAC 2
OUT
2
3
4
2
3
4
V
V
V
V
PP
PP
OUT
V
OUT
OUT
V
OUT
V
OUT
CAT
504
CAT
504
CS
DI
CS
DI
5
2
DI
V
V
OUT
OUT
L
L
DATA
REGISTER
& EEPROM
DO
V
REF
GND
DO
V
REF
GND
SERIAL
CONTROL
CLK
PROG
PROG
8
7
8
7
DAC 3
DAC 4
V
OUT
4
CS
V
OUT
SERIAL
DATA
OUTPUT
REGISTER
DO
CAT504
8
9
GND
V
L
REF
Doc. No. 25048-0A 2/98 M-1
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT504
ABSOLUTE MAXIMUM RATINGS*
Operating Ambient Temperature
Supply Voltage
Commercial (‘C’ suffix) .................... 0°C to +70°C
Industrial (‘I’ suffix)...................... – 40°C to +85°C
Junction Temperature ..................................... +150°C
Storage Temperature ....................... –65°C to +150°C
Lead Soldering (10 sec max) .......................... +300°C
VDD to GND ......................................–0.5V to +7V
VPP to GND.....................................–0.5V to +22V
Inputs
CLK to GND............................–0.5V to VDD +0.5V
CS to GND..............................–0.5V to VDD +0.5V
DI to GND ...............................–0.5V to VDD +0.5V
PROG to GND ........................–0.5V to VDD +0.5V
VREFH to GND ........................–0.5V to VDD +0.5V
VREFL to GND .........................–0.5V to VDD +0.5V
Outputs
*StressesabovethoselistedunderAbsoluteMaximumRatings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied.Deviceperformanceandreliabilitymaybeimpairedby
exposure to absolute rating conditions for extended periods of
time.
D0 to GND...............................–0.5V to VDD +0.5V
VOUT 1– 4 to GND...................–0.5V to VDD +0.5V
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min
Max
Units
Test Method
(1)
VZAP
ESD Susceptibility
Latch-Up
2000
100
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)(2)
ILTH
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
DC ELECTRICAL CHARACTERISTICS:
VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
—
—
Bits
Accuracy
INL
Integral Linearity Error
ILOAD = 250 nA, TR = C
TR = I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
± 1
± 1
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ILOAD = 1 µA,
TR = C
TR = I
± 2
± 2
DNL
Differential Linearity Error
ILOAD = 250 nA, TR = C
TR = I
± 0.5
± 0.5
± 1.5
± 1.5
ILOAD = 1 µA,
TR = C
TR = I
Logic Inputs
IIH
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
VIN = VDD
VIN = 0V
—
—
2
—
—
—
—
10
–10
VDD
0.8
µA
µA
V
IIL
VIH
VIL
0
V
References
VRH
VRL
ZIN
VREFH Input Voltage Range
VREFL Input Voltage Range
VREFH–VREFL Resistance
2.7
GND
—
—
—
7k
VDD
VDD -2.7
—
V
V
Ω
Logic Outputs
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
IOH = – 40 µA
VDD –0.3
—
—
—
—
V
V
V
IOL = 1 mA, VDD = +5V
IOL = 0.4 mA, VDD = +3V
—
—
0.4
0.4
Doc. No. 25048-0A 2/98 M-1
2
CAT504
Units
DC ELECTRICAL CHARACTERISTICS (Cont.):
VDD = 2.7V to 5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Analog Output
FSO
ZSO
IL
Full-Scale Output Voltage
VR = VREFH–VREF
VR = VREFH–VREF
L
L
0.99 VR
—
0.995 VR
—
0.10 VR
1
V
Zero-Scale Output Voltage
DAC Output Load Current
DAC Output Impedance
0.005 VR
V
—
—
—
—
—
µA
ROUT
VDD = +5V
—
20k
40k
1
Ω
VDD = +3V
—
Ω
PSSR
Power Supply Rejection
ILOAD = 250 nA
—
LSB / V
Temperature
TCO
VOUT Temperature Coefficient
VREFH = +5V, VREFL = 0V
VDD = +5V, ILOAD = 250nA
—
—
—
200
—
µV/ °C
TCREF
Temperature Coefficient of
VREF Resistance
VREFH to VREF
L
700
ppm / °C
Power Supply
IDD
Supply Current
Excludes VREF
VPP = +19V
—
—
—
200
—
50
500
5.5
20
µA
µA
V
IPP
Programming Current
VDD
VPP
Operating Voltage Range
Programing Voltage Range
2.7
18
19
V
AC ELECTRICAL CHARACTERISTICS:
VDD = 2.7V to 5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Digital
tCSMIN
tCSS
tCSH
tDIS
Minimum CS Low Time
CS Setup Time
150
100
0
—
—
—
—
—
—
—
400
400
5
—
—
—
—
—
150
150
—
—
—
—
—
—
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
MHz
CS Hold Time
DI Setup Time
CL = 100 pF
50
50
—
see note 1
tDIH
DI Hold Time
tDO1
tDO0
tHZ
Output Delay to 1
Output Delay to 0
—
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Pulse Width
PROG Setup Time
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
—
tLZ
—
tPROG
tPS
3
150
500
300
DC
—
—
—
—
tCLK
tCLK
fC
H
L
Analog
tDS
DAC Settling Time to 1/2 LSB
CLOAD = 10 pF, VDD = +5V
CLOAD = 10 pF, VDD = +3V
—
—
3
6
10
10
µs
µs
Pin Capacitance
CIN
Input Capacitance
Output Capacitance
VIN = 0V, f = 1 MHz(2)
VOUT = 0V, f = 1 MHz(2)
—
—
8
6
—
—
pF
pF
COUT
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2.
2. These parameters are periodically sampled and are not 100% tested.
Doc. No. 25048-0A 2/98 M-1
3
CAT504
A. C. TIMING DIAGRAM
Doc. No. 25048-0A 2/98 M-1
4
CAT504
PIN DESCRIPTION
DAC addressing is as follows:
Pin
Name
Function
DAC OUTPUT
A0
0
A1
0
1
2
3
4
5
6
7
VDD
CLK
VPP
CS
Power supply positive.
Clock input pin
V
V
V
V
1
2
3
4
OUT
OUT
OUT
OUT
1
0
EEPROM Programming Voltage
Chip Select
0
1
DI
Serial data input pin.
Serial data output pin.
1
1
DO
PROG
EEPROM Programming Enable
Input
8
GND
Power supply ground.
9
VREF
L
Minimum DAC output voltage.
DAC output channel 4.
DAC output channel 3.
DAC output channel 2.
DAC output channel 1.
Maximum DAC output voltage.
10
11
12
13
14
VOUT
VOUT
VOUT
VOUT
4
3
2
1
VREF
H
DEVICE OPERATION
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
The CAT504 is a quad 8-bit Digital to Analog Converter
(DAC) whose outputs can be programmed to any one of
256 individual voltage steps. Once programmed, these
output settings are retained in non-volatile EEPROM
memoryandwillnotbelostwhenpowerisremovedfrom
the chip. Upon power up the DACs return to the settings
stored in EEPROM memory. Each DAC can be written
to and read from independently without effecting the
output voltage during the read or write cycle. Each
output can also be temporarily adjusted without chang-
ing the stored output setting, which is useful for testing
new output settings before storing them in memory.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT504’s clock controls both data flow in and out of
the IC and EEPROM memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’srisingedge. Whileitisnotnecessaryfortheclock
to be running between data transfers, the clock must be
operating in order to write to EEPROM memory, even
though the data being saved may already be resident in
the DAC control register.
DIGITAL INTERFACE
The CAT504 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
No clock is necessary upon system power-up. The
CAT504’s internal power-on reset circuitry loads data
from EEPROM to the DACs without using the external
clock.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
As data transfers are edge triggered clean clock transi-
tionsarenecessarytoavoidfalselyclockingdataintothe
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
CHIP SELECT
Chip Select (CS) enables and disables the CAT504’s
readandwriteoperations. WhenCSishighdatamaybe
Doc. No. 25048-0A 2/98 M-1
5
CAT504
V
CS high, a start bit followed by a two bit DAC address
and eight data bits are clocked into the DAC control
register via the DI pin. Data enters on the clock’s rising
edge. The DAC output changes to its new setting on the
clock cycle following D7, the last data bit.
REF
VREF,thevoltageappliedbetweenpinsVREFHandVREFL,
sets the DAC’s Zero to Full Scale output range where
VREFL=ZeroandVREFH=FullScale. VREF canspanthe
full power supply range or just a fraction of it. In typical
applications VREFHandVREFL are connected across the
power supply rails. When using less than the full supply
voltageVREFHisrestrictedtovoltagesbetweenVDD and
VDD/2 and VREFL to voltages between GND and VDD/2.
Programming is achieved by bringing PROG high for a
minimumof3mswhilesupplying18to20voltstotheVPP
pin. PROG must be brought high sometime after the
start bit and at least 150 ns prior to the rising edge of the
clock cycle immediately following the D7 bit. Two clock
cycles after the D7 bit the DAC control register will be
ready to receive the next set of address and data bits.
Theclockmustbekeptrunningthroughouttheprogram-
ming cycle. Internal control circuitry takes care of
rampingtheprogrammingvoltagefordatatransfertothe
EEPROM cells. The CAT504’s EEPROM memory cells
will endure over 100,000 write cycles and will retain data
for a minimum of 20 years without being refreshed.
V
PP
When saving data to non-volatile EEPROM memory an
external voltage of 18–20 volts must be applied to the
VPP pin. This voltage need only be present during the
programming cycle and may be removed or turned off
the remainder of the time. While it is not necessary to
remove or power down VPP between programming
cycles, some power sensitive applications may choose
to do so. In such cases, the VPP supply must be given
sufficient time to come up and stabilize before issuing
the PROG command.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the DI pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows µPs to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
isalsostoredinEEPROMsothatitcanberestoredatthe
end of the read cycle. In Figure 2 CS returns low before
the13th clockcyclecompletes. IndoingsotheEEPROM’s
setting is reloaded into the DAC control register. Since
this value is the same as that which had been there
previously no change in the DAC’s output is noticed.
Had the value held in the control register been different
from that stored in EEPROM then a change would occur
at the read cycle’s conclusion.
DATA OUTPUT
Data is output serially by the CAT504, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
itshighimpedanceTri-StatemodewhenCSreturnslow.
Tri-Stating the DO pin allows several 504s to share a
single serial data line and simplifies interfacing multiple
504s to a microprocessor.
WRITING TO MEMORY
Programming the CAT504’s EEPROM memory is ac-
complished through the application of an externally
generated programming voltage, VPP, and the control
signals: Chip Select (CS) and Program (PROG). With
Figure 1. Writing to Memory
Figure 2. Reading from Memory
t
1
2
3
4
5
6
7
8
9
10 11 12
N
N+1 N+2
t
1
2
3
4
5
6
7
8
9
10 11 12
o
o
CS
DI
CS
DI
NEW DAC DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DAC DATA
1
A0 A1
CURRENT DAC DATA
D0 D1 D2 D3 D4 D5 D6 D7
DO
DO
PROG
Vpp
D0 D1 D2 D3 D4 D5 D6 D7
PROG
DON'T CARE
Vpp
DON'T CARE
CURRENT
DAC VALUE
DAC
OUTPUT
CURRENT
DAC VALUE
NEW
DAC VALUE
NEW
DAC VALUE
DAC
OUTPUT
NON-VOLATILE
NON-VOLATILE
VOLATILE
NON-VOLATILE
Doc. No. 25048-0A 2/98 M-1
6
CAT504
TEMPORARILY CHANGE OUTPUT
Figure 3. Temporary Change in Output
TheCAT504 allowstemporarychangesinDAC’soutput
to be made without disturbing the settings retained in
EEPROM memory. This feature is particularly useful
when testing for a new output setting and allows for user
adjustment of preset or default values without losing the
original factory settings.
t
1
2
3
4
5
6
7
8
9
10 11 12
N
N+1 N+2
o
CS
NEW DAC DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
DI
CURRENT DAC DATA
D0 D1 D2 D3 D4 D5 D6 D7
DO
Figure 3 shows the control and data signals needed to
effect a temporary output change. DAC settings may be
changed as many times as required and can be made to
any of the four DACs in any order or sequence. The
temporarysetting(s)remainineffectlongasCSremains
high. WhenCSreturnslowallfourDACswillreturntothe
output values stored in EEPROM memory.
PROG
Vpp
DON'T CARE
DAC
OUTPUT
CURRENT
DAC VALUE
NEW
DAC VALUE
CURRENT
DAC VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
When it is desired to save a new setting acquired using
this feature, the new value must be reloaded into the
DAC control register prior to programming. This is be-
cause the CAT504’s internal control circuitry discards
the new data from the programming register two clock
cycles after receiving it (after reception is complete) if no
PROG signal is received.
APPLICATION CIRCUITS
+5V
+5V
R
R
i
F
+15V
+15V
V
V
H
L
V
V
H
L
DD
REF
DD
REF
–
–
+
V
V
OUT
OUT
CONTROL
& DATA
CONTROL
& DATA
+
CAT504
CAT504
OP 07
OP 07
-15V
-15V
GND
V
REF
GND
V
REF
R
F
V
= (1 + –––) V
OUT
DAC
R
V
= V
DAC
I
OUT
Buffered DAC Output
Amplified DAC Output
DAC INPUT
DAC OUTPUT
ANALOG
OUTPUT
+5V
CODE
= ——— (V - V
FS
V
V
) + V
ZERO
V
R
R
F
DAC
ZERO
i
i
255
= 0.99 V
REF
FS
V
= 5V
F
+15V
REF
V
= 0.01 V
REF
MSB LSB
1111 1111
R = R
V
V
H
L
DD
REF
I
ZERO
V
–
OUT
255
—— (.98 V
) + .01 V
REF
= .990 V
REF
V
= +4.90V
CONTROL
& DATA
REF
OUT
255
CAT504
+
OP 07
-15V
128
GND
V
REF
1000 0000
0111 1111
0000 0001
—— (.98 V
) + .01 V
REF
= .502 V
REF
V
= +0.02V
= -0.02V
= -4.86V
REF
OUT
255
V
R
F
V
=
(
R ) -V
R +
F i
i
127
OUT
DAC
—— (.98 V
) + .01 V
REF
= .498 V
REF
V
255
REF
OUT
R
i
1
—— (.98 V
) + .01 V
REF
= .014 V
REF
V
255
REF
OUT
For R =R
i
F
V
= 2V -V
OUT
DAC i
0
0000 0000 —— (.98 V
) + .01 V
REF
= .010 V
REF
V
= -4.90V
REF
OUT
255
Bipolar DAC Output
Doc. No. 25048-0A 2/98 M-1
7
CAT504
APPLICATION CIRCUITS (Cont.)
+5V
V
+V
REF
V
REF
R
= —————
C
256 1 µA
*
V
H
DD
REF
+5V
V
REF
Fine adjust gives ± 1 LSB change in V
OFFSET
V
REF
2
when V
=
———
127R
OFFSET
C
V
H
V
DD
REF
FINE ADJUST
DAC
+
)
OFFSET
(+V
) - (V
REF
127R
R
= ———————————
1 µA
C
C
FINE ADJUST
DAC
+
(-V
) + (V
)
REF
OFFSET
R
= ———————————
1 µA
o
R
C
COARSE ADJUST
DAC
+V
R
C
V
OFFSET
COARSE ADJUST
DAC
+
–
GND
V
L
REF
+V
-V
R
o
V
OFFSET
+
-V
REF
GND
V
L
REF
–
Coarse-Fine Offset Control by Averaging DAC Outputs
for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DAC Outputs
for Dual Power Supply Systems
28 - 32V
V+
I > 2 mA
15K
10 µF
1N5231B
5.1V
V
= 5.000V
REF
V
V
H
L
DD
REF
V
V
H
DD
REF
10K
CONTROL
& DATA
CONTROL
& DATA
LT 1029
+
–
MPT3055EL
CAT504
CAT504
LM 324
4.02 K
GND
V
REF
L
GND
V
REF
OUTPUT
10 µF
35V
0 - 25V
@ 1A
1.00K
Digitally Trimmed Voltage Reference
Digitally Controlled Voltage Reference
Doc. No. 25048-0A 2/98 M-1
8
CAT504
APPLICATION CIRCUITS (Cont.)
+5V
V
V
IN
REF
1.0 µF
LM 339
+
–
10K
V
V
H
+5V
+5V
+5V
+5V
+5V
WINDOW 1
WINDOW 2
WINDOW 3
WINDOW 4
WINDOW 5
DD
REF
V
REF
+
–
CAT504
V
WINDOW 1
WINDOW 2
PP
+
–
DAC 1
10K
10K
10K
10K
V
1
2
OUT
+
–
CS
DI
V
OUT
+
–
DAC 2
DAC 3
DAC 4
WINDOW 3
+
–
DO
V
3
4
OUT
+
–
PROG
WINDOW 4
WINDOW 5
V
OUT
+
–
CLK
+
–
GND
+
–
WINDOW STRUCTURE
GND
V
L
REF
Staircase Window Comparator
+5V
V
V
IN
REF
1.0 µF
LM 339
+
V
DD
V
H
REF
–
10K
CAT504
+5V
WINDOW 1
V
PP
+
–
DAC 1
V
H
REF
CS
DI
WINDOW 1
V
2
3
OUT
+
–
DAC 2
DAC 3
DAC 4
V
1
4
OUT
10K
+5V
WINDOW 2
+
–
WINDOW 2
WINDOW 3
DO
V
OUT
V
OUT
PROG
CLK
GND
+
–
10K
WINDOW STRUCTURE
+5V
WINDOW 3
+
–
GND
V
L
REF
Overlapping Window Comparator
Doc. No. 25048-0A 2/98 M-1
9
CAT504
APPLICATION CIRCUITS (Cont.)
+5V
2.2K
V
V
REF
4.7 µA
DD
LM385-2.5
+15V
I
= 2 - 255 mA
1 mA steps
SINK
DAC
+
–
2N7000
+5V
10K
10K
39Ω1W
39Ω 1W
CONTROL
& DATA
CAT504
DAC
+
–
5 µA steps
2N7000
3.9K
GND
V
L
5 meg
10K
5 meg
REF
10K
–
+
TIP 30
-15V
Current Sink with 4 Decades of Resolution
+15V
51K
+
–
TIP 29
10K
10K
+5V
V
V
H
DD
REF
5 meg
5 meg
39Ω 1W
39Ω 1W
DAC
–
+
CONTROL
& DATA
BS170P
3.9K
CAT504
1 mA steps
5 meg
5 meg
DAC
–
+
GND
V
L
REF
BS170P
5 µA steps
LM385-2.5
-15V
I
= 2 - 255 mA
SOURCE
Current Source with 4 Decades of Resolution
Doc. No. 25048-0A 2/98 M-1
10
CAT504
APPLICATION CIRCUITS (Cont.)
+12V
10K
1N914
1.0 µF
+12V
74C14
.005 µF
13
V
CC
1N914
2.5 µF
0.1 µF
0.01 µF
0.39 µF
4
8
TREB CAP
BASS CAP
0.47 µF
2
INPUT 1
IN 1
20V
IN5250B
3
10
1
19
V
pp
V
Z
OUT 1
OUTPUT 1
V
DD
CAT504
LM1040
1.0 µF
47K
14
V
REF
H
9
LOUDNESS
4
7
5
6
2
CHIP SELECT.
PROGRAM
DATA IN
CS
13
12
11
10
14
11
5
PROG
DI
V
1
2
3
4
VOLUME
OUT
47K
47K
47 µF
1
BALANCE
V
OUT
10 µF
10 µF
7
BYPASS
DO
TREBLE
BASS
DATA OUT
CLOCK
V
OUT
47K
18
16
CLK
V
OUT
0.22 0.22 0.22 0.22
µF
µF
µF
µF
9
8
V
L
REF
15
OUT 2
OUTPUT 2
GND
0.39 µF
0.47 µF
17
21
24
23
3
IN 2
BASS CAP
TREB CAP
INPUT 2
STEREO
0.01 µF
0.1 µF
GND
GND
22
ENHANCE
12
4.7K
Digital Stereo Control
Doc. No. 25048-0A 2/98 M-1
11
CAT504
ORDERING INFORMATION
Prefix
Device #
Suffix
-TE13
CAT
504
J
I
Optional
Company ID
Product
Number
Package
P: PDIP
J: SOIC
Tape & Reel
TE13: 2000/Reel
Temperature Range
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
Notes:
(1) The device used in the above example is a CAT504JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 25048-0A 2/98 M-1
12
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