CAT33C804AJI-TE7 [CATALYST]

EEPROM, 512X8, Serial, CMOS, PDSO16, 0.300 INCH, SOIC-16;


型号：	CAT33C804AJI-TE7
厂家：	CATALYST SEMICONDUCTOR
描述：	EEPROM, 512X8, Serial, CMOS, PDSO16, 0.300 INCH, SOIC-16 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
文件：	总14页 (文件大小：89K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary

CAT33C804A

4K-Bit Secure Access Serial E²PROM

FEATURES

■ Single 3V Supply

■ 100,000 Program/Erase Cycles

■ Password READ/WRITE Protection: 1 to 8 Bytes

■ Memory Pointer WRITE Protection

■ Sequential READ Operation

■ I/O Speed: 9600 Baud

–Clock Frequency: 4.9152 MHz Xtal

■ Low Power Consumption:

–Active: 3 mA

■ 256 x 16 or 512 x 8 Selectable Serial Memory

■ UART Compatible Asynchronous Protocol

–Standby: 250 µA

■ 100 Year Data Retention

■ Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

The CAT33C804A is a 4K-bit Serial E²PROM that safe-

guards stored data from unauthorized access by use of

a user selectable (1 to 8 byte) access code and a

movablememorypointer. Twooperatingmodesprovide

unprotected and password-protected operation allow-

ing the user to configure the device as anything from a

ROM to a fully protected no-access memory. The

CAT33C804A uses a UART compatible asynchronous

protocol and has a Sequential Read feature where data

can be sequentially clocked out of the memory array.

The device is available in 8-pin DIP or 16-pin SOIC

packages.

PIN CONFIGURATION

BLOCK DIAGRAM

DIP Package (P)

SOIC Package (J)

CLK

GND

64-BIT ACCESS CODE

ERR

GND

CONTROL BLOCK

ERR

GND

SERIAL

CLK

COMMUNI-

CATION

BLOCK

4K-BIT EEPROM

ARRAY

PIN FUNCTIONS

5074 FHD F01

R/W

ADDRESS

Pin Name

Function

BUFFER

DECODER

INSTRUCTION

Chip Select

DO⁽¹⁾

CLK

DI⁽¹⁾

Serial Data Output

Clock Input

INSTRUCTION

DECODER

ADDRESS

ERR

Serial Data Input

Parity Enable

STATUS

MEMORY

POINTER

ERR

V_CC

GND

Error Indication Pin

+3V Power Supply

Ground

33C804 F02

Note:

(1) DI, DO may be tied together to form a common I/O.

Characteristics subject to change without notice

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Voltage on Any Pin with

Respect to Ground⁽¹⁾........... –2.0V to +V_CC+ 2.0V

V_CCwith Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (T_a= 25°C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100mA

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Min.

100,000

100

Max.

Units

Cycles/Byte

Years

Reference Test Method

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(3)

N_END

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-up

(3)

V_ZAP

2000

100

Volts

(3)(4)

I_LTH

D.C. CHARACTERISTICS

V_CC= +3V ±10%,unless otherwise specified.

Limits

Typ.

Symbol

Parameter

Min.

Max.

Units

Test Conditions

I_CC

Power Supply Current

(Operating)

V_CC= 3.3V, CS = V_CC

DO is Unloaded.

I_SB

Power Supply Current

(Standby)

250

0.8

µA

V_CC= 3.3V, CS = 0V

DI = 0V, CLK = 0V

V_IL

Input Low Voltage

–0.1

V_IH

V_OL

V_OH

Input High Voltage

Output Low Voltage

Output High Voltage

Input Leakage Current

Output Leakage Current

0.4

I_OL= 2.1mA

2.4

I_OH= –400µA

V_IN= 3.3V

(5)

I_LI

µA

I_LO

V_OUT= 3.3V, CS = 0V

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

(5) PE pin test conditions: V < V < V

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

A.C. CHARACTERISTICS

V_CC= +3V ±10%,unless otherwise specified.

Limits

Typ.

Symbol

t_CSH

t_D

Parameter

CS Hold Time

Min.

Max.

Units

Test Conditions

C_L= 100pF

CLK to DO Delay

104

µs

V_IN= V_IHor V_IL

V_OUT= V_OHor V_OL

t_PD

CLK to DO Delay

150

(1) (2)

t_HZ

CLK to DO High-Z Delay

Program/Erase Pulse Width

CS Low Pulse Width

ERR Output Delay

t_EW

t_CSL

t_SV

100

150

C_L= 100pF

(1)

t_VCCS

V_CCto CS Setup Time

Clock Frequency

µs

f_CLK

4.9152

MHz

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t is measured from the falling edge of the clock to the time when the output is no longer driven.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

divided into a read-only area and a non-access area.

Figure2illlustratesthispartitioningofthememoryarray.

PASSWORD PROTECTION

The CAT33C804A is a 4K-bit E²PROM that features a

password protection scheme to prevent unauthorized

accesstotheinformationstoredinthedevice.Itcontains

an access code register which stores one to eight bytes

ofaccesscodealongwiththelengthofthataccesscode.

Additionally, a memory pointer register stores the ad-

dress that partitions the memory into protected and

unprotected areas. As shipped from the factory, the

deviceisunprogrammedandunprotected. Thelengthof

theaccesscodeisequaltozeroandthememorypointer

is fully accessible without an access code. Setting a

password and moving the memory pointer register to

coverallorpartofthememorysecuresthedevice. Once

secured, the memory is divided into a read/write area

and a read-only area with the entry of a valid access

code. If no access code is entered, the memory is

WRITE PROTECTION

Another feature of the CAT33C804A is WRITE-protec-

tion without the use of an access code. If the memory

pointer register is set to cover all or part of the memory,

without setting the access code register, the device may

be divided into an area which allows full access, and an

area which allows READ-only access. To write into the

READ-only area, the user can override the memory

pointer register for every WRITE instruction or he can

simply move the address in the memory pointer register

to uncover this area, and then write into the memory.

This mechanism prevents inadvertent overwriting of

important data in the memory without the use of an

access code. Figure 3 illustrates this partitioning of the

memory array.

Figure 1. A.C. Timing

VCCS

CLK

START BIT

STOP BIT

HIGH-Z

MARK

(1)

DATA TIMING

SPACE

BIT TIME

104 µs

CHARACTER TIME @ 9600 BAUD

33C804 F03

Note:

(1) If PE pin = 1.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

READ SEQUENTIAL

PIN DESCRIPTIONS

To allow for convenient reading of blocks of contiguous

data, the device has a READ SEQUENTIAL instruction

which accepts a starting address of the block and

continuously outputs data of subsequent addresses

until the end of memory, or until Chip Select goes LOW.

Chip Select is a TTL compatible input which, when set

HIGH, allows normal operation of the device. Any time

Chip Select is set LOW, it resets the device, terminating

all I/O communication, and puts the output in a high

impedance state. CS is used to reset the device if an

error condition exists or to put the device in a power-

down mode to minimize power consumption. It may also

be used to frame data transmission in applications

where the clock and data input have to be ignored from

time to time. Although CS resets the device, it does not

change the program/erase or the access-enable status,

nor does it terminate a programming cycle once it has

started. The program/erase and access-enable opera-

tions, once enabled, will remain enabled until specific

disablinginstructionsaresentoruntilpowerisremoved.

The CAT33C804A communicates with external devices

via an asynchronous serial communication protocol.

The data transmission may be a continuous stream of

data or it can be packed by pulsing Chip Select LOW in

between each packet of information. (Except for the

SEQUENTIAL READ instruction where Chip Select

must be held high).

Figure 2. Secure Mode

ACCESS REGISTER:

ACCESS CODE LENGTH:

MEMORY POINTER:

ACCESS CODE (1–8 BYTES)

1 TO 8

a…a

255 (x16)

511 (x8)

READ-ONLY

ACCESS

POINTER

ADDRESS

IN MEMORY

a…a

PASSWORD-ONLY

ACCESS

5074 FHD F04

(1)

Figure 3. Unprotected Mode

ACCESS REGISTER:

ACCESS CODE LENGTH:

MEMORY POINTER:

x…x

a…a

255 (x16)

511 (x8)

READ/WRITE/ERASE

ACCESS

POINTER

ADDRESS

IN MEMORY

a…a

READ-ONLY

ACCESS

5074 FHD F05

Note:

(1) x = DON’T CARE; a = ADDRESS BIT.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

CLK

The System Clock is a TTL compatible input pin that

allows operation of the device at a specified frequency.

The CAT33C804A is designed with an internal divider to

producea9600baudoutputforaninputclockfrequency

of 4.9152 MHz.

The Data Output pin is a tri-state TTL compatible output.

It is normally in a high impedance state unless a READ

or an ENABLE BUSY instruction is executed. Following

thecompletionofa16-bitor8-bitdatastream, theoutput

will return to the high impedance state. During a pro-

gram/erase cycle, if the ENABLE BUSY instruction has

been previously executed, the output will stay LOW

while the device is BUSY, and it will be set HIGH when

the program/erase cycle is completed. DO will stay

HIGH until the completion of the next instruction’s op-

codeand,ifthenextinstructionisaREAD,DOwilloutput

the appropriate data at the end of the instruction. If the

ENABLE BUSY instruction has not been previously

executed,DOwillstayinahighimpedancestate.DOwill

The Data Input pin is TTL compatible and accepts data

and instructions in a serial format. Each byte must begin

with “0” as a start bit. The device will accept as many

bytes as an instruction requires, including both data and

address bytes. Extra bits will be disregarded if they are

“1”s and extra “0”s will be misinterpreted as the start bit

of the next instruction. An instruction error will cause the

device to abort operation and all I/O communication will

be terminated until a reset is received.

Figure 4. Program/Erase Timing (x8 Format)

OP CODE

OP0–OP7

ADDRESS

A8–A15

ADDRESS

A0–A7

DATA

D0–D7

HIGH-Z

(1)

BUSY

33C804 F07

Figure 5. Program/Erase Timing (x16 Format)

OP CODE

OP0–OP7

ADDRESS

A0–A7

DATA

D8–D15

D0–D7

(1)

HIGH-Z

BUSY

33C804 F08

Note:

(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the

High-Z condition.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

also go to the high impedance state if an error condition

is detected. In the event an ENABLE BUSY instruction

has not been sent, a READ STATUS register instruction

canbeexecuted.Thisalsotellstheuserwhetherthepart

is in a program/erase cycle or an error condtion. When

the device is in a program/erase cycle it will output an 8

bit status word. If it does not, it is in an error condition.

include parity bits will not be interpreted correctly. Note:

The PE input is internally pulled down to GND (i.e.

default = no parity). As with all CMOS devices, CS, CLK

andDIinputsmustbeconnectedtoeitherHIGHorLOW,

and not left floating.

ERR

The Error indication pin is an open drain output. If either

an instruction or parity error exists, the ERR pin will

output a “0” until the device is reset. This can be done by

pulsing CS LOW.

TheParityEnablepinisaTTLcompatibleinput.IfthePE

pin is set HIGH, the device will be configured to commu-

nicate using even parity, and if the pin is set LOW, it will

use no parity. In this case, instructions or data that

Figure 6. Read Timing (x8 Format)

CLK

OP CODE

OP0–OP7

ADDRESS

A8–A15

ADDRESS

A0–A7

DATA

D0–D7

HIGH-Z

33C804 F09

Figure 7. Read Timing (x16 Format)

CLK

OP CODE

OP0–OP7

ADDRESS

A0–A7

DATA

D8–D15

D0–D7

HIGH-Z

33C804 F10

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

Seven instructions are used as control and status func-

tions:

DEVICE OPERATION

INSTRUCTIONS

DISBSY Disable Busy

ENBSY Enable Busy

The CAT33C804A instruction set includes 19 instruc-

tions.

EWEN

EWDS

NOP

Program/Erase Enable

Program/Erase Disable

No Operation

Sixinstructionsarerelatedtosecurityorwriteprotection:

DISAC

ENAC

MACC

Disable Access

Enable Access

Modify Access Code

ORG

RSR

Select Memory Organization

Read Status Register

UNPROTECTED MODE

OVMPR Override Memory Pointer Register

RMPR

WMPR

Read Memory Pointer Register

Write Memory Pointer Register

As shipped from the factory, the CAT33C804A is in the

unprotected mode. The access code length is set to 0,

and the memory pointer is at address 00 hex. While in

this mode, any portion of the E²PROM array can be read

or written to without an access code. A portion of the

memory may be protected from any write or clear

operation by setting the memory pointer to the appropri-

ate address via the WMPR (Write Memory Pointer

Six instructions are READ/WRITE/ERASE instructions:

ERAL Clear All Locations

ERASE Clear Memory Locations

READ

RSEQ

WRAL

WRITE

Read Memory

Read Sequentially

Write All

Write memory

WMPR

[address]

Note: All write instructions will automatically perform a clear before

writing data.

Figure 8. EWEN/EWDS Timing (x8 Format)

OP CODE

OP0–OP7

HIGH-Z

5076 FHD F11

Figure 9. EWEN/EWDS Timing (x16 Format)

OP CODE

OP0–OP7

HIGH-Z

5076 FHD F11

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

As shown previously in Figure 3, memory locations

below the address set in the memory pointer will be

program/erase protected. Thus, unintentional clearing

or writing of data in this area will be prevented, while

memory locations at or above the protected area still

allow full access. This protection does not apply to the

ERAL and WRAL commands which are not blocked by

the memory pointer.

The ENAC instruction, along with the access code,

enables access to the protected area of the device. The

EWEN instruction enables execution of the program/

erase operations. This portion of the memory is other-

wise inaccessible for any operation. Read-only access

isallowedwithouttheaccesscodeformemorylocations

at or above the address in the memory pointer.

The access code can be changed by the following

instruction:

SECURE MODE

As shown previously in Figure 2, in the secure mode,

memory locations at or above the address set in the

memorypointerallowREAD-onlyaccess. Memoryloca-

tions below that address will require an access code

before they can be accessed. The secure mode is

activated with an MACC (Modify Access Code) instruc-

tion followed by a user access code which can be one to

eight bytes in length.

ENAC

EWEN

MACC

[old access code]

[old code][new code][new code]

A two-tier protection scheme is implemented to protect

data against inadvertent clearing or writing. To write to

the memory, an EWEN (Program/Erase Enable) must

first be issued. The CAT33C804A will now allow pro-

gram/erase operations to be performed only on memory

locations at or above the address set in the memory

pointer. The remaining portion of the memory is still

protected.Tooverridethisprotection,anOVMPR(Over-

ride Memory Pointer Register—see Memory Pointer

struction which accesses the protected area:

EWEN

MACC

[old code][new code][new code]

The EWEN instruction enables the device to perform

program/erase operations. The new access code must

beenteredtwiceforverification.Ifthedevicealreadyhas

an access code, the old access code must be entered

before the new access code can be accepted. The

length of the password is incorporated into the MACC

portion of the instruction.

ENAC

[access code]

EWEN

OVMPR

WRITE

[address][ data]

Once the secure mode is activated, access to memory

locations is under software control. Access (read, write,

and clear instructions) to the memory locations below

the address in the memory pointer is allowed only if the

ENAC (Enable Access) instruction followed by the cor-

rect access code has been previously executed.

As an alternative to the OVMPR instruction, the WMPR

(Write Memory Pointer Register) instruction may be

used to move the memory pointer address to uncover

the area where writing is to be performed:

ENAC

EWEN

WMPR

WRITE

[access code]

ENAC

EWEN

WRITE

[access code]

[address][data]

[address]

[address ][data ]

Figure 10. ERR Pin Timing

CLK

HIGH-Z

ERR

5076 FHD F06

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

As shipped from the factory, the device is in the unpro-

tected mode. The length of the access code is user

selectable from a minimum of one byte to a maximum of

eight bytes (> 1.84x10¹⁹combinations). Loading a zero-

length access code will disable protection.

the operation is complete, the device returns to the

protected mode. If the device is in the secure mode both

of these instructions require the ENAC instruction and a

valid access code prior to their execution. The third

instruction is the RMPR (Read Memory Pointer Regis-

ter) which will place the current contents of the register

in the serial output buffer.

MEMORY POINTER REGISTER

The memory pointer enables the user to segment the

E²PROM array into two sections. In the unprotected

mode, the array can be segmented between read-only

and full access, while in the secure mode, the memory

may be segmented between read-only access and

password-onlyaccess.Threeinstructionsarededicated

tothememorypointeroperations.ThefirstoneisWMPR

(Write Memory Pointer Register). This instruction, fol-

lowed by an address, will load the memory pointer

in the E²PROM and can be modified only by another

WMPR instruction. The second instruction is OVMPR

(Override Memory Pointer Register) which allows a

single program/erase to be performed to memory loca-

tions below the address set in the memory pointer. This

instructionallowstheusertomodifydatainasegmented

array without having to move the memory pointer. Once

STATUS REGISTER

An eight bit status register is provided to allow the user

to determine the status of the CAT33C804A. The con-

tents of the first three bits of the register are 101 which

allows the user to quickly determine the condition of the

device. The next three bits indicate the status of the

device; they are parity error, instruction error and RDY/

BUSY status. The last two bits are reserved for future

use.

CLEAR ALL AND WRITE ALL

As a precaution, the ERAL instruction has to be entered

twice before it is executed. This measure is required as

a redundancy check on the incoming instruction for

possible transmission errors. The WRAL instruction

requires sending an ERAL first (this sets a flag only) and

Figure 11. Erase Timing (x8 Format)

OP CODE

OP0–OP7

ADDRESS

A8–A15

ADDRESS

A0–A7

NEXT INSTRUCTION

HIGH-Z

(1)

BUSY

33C804 F12

Figure 12. Erase Timing (x16 Format)

OP CODE

OP0–OP7

ADDRESS

A0–A7

NEXT INSTRUCTION

HIGH-Z

(1)

BUSY

33C804 F13

Note:

(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in High-Z

condition.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

then the WRAL instruction. The CAT33C804A will ac-

cept the following commands:

SYSTEM ERRORS

Whenever an error occurs, be it an instruction error

(unknown instruction), or parity error (perhaps caused

by transmission error), the device will stop its operation.

To return to normal operation, the device must be reset

by pulsing CS LOW and then set back to HIGH. Reset-

ting the device will not affect the ENAC, EWEN and

ENBSYstatus.Theerrormaybedeterminedbyentering

the READ STATUS REGISTER (RSR) instruction

immediatly following the reset. The status output is an

8-bit word with the first three bits being 101. This three

bit pattern indicates that the device is functioning nor-

mally. The fourth bit is “1” if a parity error occurred. The

fifth bit is a “1” if an instruction error occurred. The sixth

bit is a “1” if the device is in a program/erase cycle. The

last two bits are reserved for future use.

ERAL

WRAL

An ERAL will be executed

A WRAL will be executed

Both the ERAL and WRAL commands will program/

erase the entire array and will not be blocked by the

memory pointer.

THE PARITY BIT

The UART compatible protocol supports an even parity

bit if the PE pin of the device is set HIGH, otherwise,

there is no parity. If PE is set LOW and the incoming

instruction contains a parity bit, it may be interpreted as

the stop bit. When PE is HIGH, the CAT33C804A

expectsaparitybitattheendofeverybyte.Forexample,

the RSEQ instruction will look like this:

The reason for the “101” pattern is to distinguish be-

tween an error conditon (DO tri-stated) and a device

busystatus.Ifanerrorconditionexists,itwillnotrespond

to any input instruction from DI. However, if the device is

inaprogram/erasecycle, itrespondstotheRSRinstruc-

tion by outputting “101 00100”. If RSR is executed at the

end of a program/erase cycle, the output will be “101000

00”.

0 1100 1011 11

0 A15…A8 P1

0 A7…A0 P1

Thedevicethenoutputsdatacontinuouslyuntilitreaches

the end of the memory. Each byte of data contains 9 bits

with the ninth bit being the parity bit. The RSEQ instruc-

tion may be terminated at any time by bringing CS low;

the output will then go to high impedance.

1 0

1 X X X X X

PARITY

ERROR

INSTRUCTION RDY/BUSY

ERROR STATUS

FUTURE USE

5074 FHD F09

Figure 13. Asynchronous Communication Protocol

CHARACTER n

CHARACTER n+1

(1)

BITS 0–7

START

BIT

STOP

BIT

33C804 F14

Note:

(1) Parity bit if enabled; skipped if parity disabled.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

MACC Modify Access Code

INSTRUCTION SET

1101 [Length] [Old code] [New code]

[New code]

DISAC Disable Access

1000 1000

This instruction requires the user to enter the old access

code, if one was set previously, followed by the new

access code and a re-entry of the new access code for

verification. Within the instruction format, the variable

[Length]designatesthelengthoftheaccesscodeasthe

following:

This instruction will lock the memory from all program/

eraseoperationsregardlessofthecontentsofthememory

pointer. A write can be accomplished only by first enter-

ing the ENAC instruction followed by a valid access

code.

ENAC Enable Access

[Length] = [0] No access code. Set device to unpro-

tected mode.

1100 0101 [Access Code]

[Length] = [1–8] Length of access code is 1 to 8 bytes.

In the protected mode, this instruction, followed by a

valid access code, unlocks the device for read/write/

clear access.

[Length]=[>8] Illegalnumberofbytes.TheCAT33C804A

will ignore the rest of the transmission.

WMPR Write Memory Pointer Register

RMPR Read Memory Pointer Register

1100 0100 [A15–A8] [A7–A0] (x8 organization)

1100 0100 [A7–A0] (x16 organization)

1100 1010

Output the content of the memory pointer register to the

serial output port.

The WMPR instruction followed by 8 or 16 bits of

address (depending on the organization) will move the

pointer to the newly specified address.

OVMPR Override Memory Pointer Register

Figure 14. ERAL Timing (x8 Format)

OP CODE

OP0–OP7

OP CODE

OP0–OP7

NEXT INSTRUCTION

HIGH-Z

(1)

BUSY

33C804 F15

Figure 15. ERAL Timing (x16 Format)

OP CODE

OP0–OP7

OP CODE

OP0–OP7

NEXT INSTRUCTION

HIGH-Z

(1)

BUSY

33C804 F16

Note:

(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the

High-Z condition.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

ERASE Clear Memory

1000 0011

1100 0000 [A15–A8] [A7–A0] (x8 organization)

1100 0000 [A7–A0] (x16 organization)

Override the memory protection for the next instruction.

READ Read Memory

Erasedatainthespecifiedmemorylocation(setmemory

to “1”). After the instruction and the address have been

entered, the self-timed clear cycle will start. The DO pin

may be used to output the RDY/BUSY status by having

previously entered the ENSBY instruction. During the

clear cycle, DO will output a LOW for BUSY during this

cycle and a HIGH for ready after the cycle has been

completed.

1100 1001 [A15–A8] [A7–A0] (x8 organization)

1100 1001 [A7–A0] (x16 organization)

Output the contents of the addressed memory location

to the serial port.

WRITE Write Memory

1100 0001 [A15–A8] [A7–A0] [D7–D0] (x8 organization)

1100 0001 [A7–A0] [D15–D8] [D7–D0] (x16 organization)

ERAL Clear All

1000 1001

Write the 8-bit or 16-bit data to the addressed memory

location. After the instruction, address, and data have

been entered, the self-timed program/erase cycle will

start. The addressed memory location will be erased

before data is written. The DO pin may be used to output

the RDY/BUSY status by having previously entered the

ENBSYinstruction.Duringtheprogram/erasecycle,DO

willoutputaLOWforBUSYduringthiscycleandaHIGH

for READY after the cycle has been completed.

Erase the data of all memory locations (all cells set to

“1”). For protection against inadvertent chip clear, the

ERAL instruction is required to be entered twice.

Figure 16. WRAL Timing (x8 Format)

OP CODE

OP0–OP7

OP CODE

OP0–OP7

DATA

D0–D7

NEXT INSTRUCTION

HIGH-Z

(1)

BUSY

33C804 F17

Figure 17. WRAL Timing (x16 Format)

OP CODE

OP0–OP7

OP CODE

OP0–OP7

DATA

D0–D7

D8–D15

NEXT INSTRUCTION

(1)

HIGH-Z

BUSY

33C804 F18

Note:

(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the

High-Z condition.

Doc. No. 25044-00 2/98

Preliminary

CAT33C804A

WRAL Write All

EWEN Program/Erase Enable

1000 0001

1000 1001

Enable program/erase to be performed on non-pro-

tected portion of memory. This instruction must be

entered before any program/erase instruction will be

carriedout.Onceentered,itwillremainvaliduntilpower-

down or an EWDS (Program/Erase Disable) is ex-

ecuted.

1100 0011 [D15–D8] [D7–D0] (x16 organization)

1000 1001

1100 0011 [D7–D0] (x8 organization)

Write one or two bytes of data to all memory locations.

An ERAL will be automatically performed before the

WRAL is executed. For protection against inadvertent

clearing or writing of data, the ERAL instruction is

required to be entered preceding the WRAL instruction.

EWDS Program/Erase Disable

1000 0010

Disable all write and clear functions.

RSEQ Read Sequentially

ORG Select Memory Organization

1100 1011 [A15–A8] [A7–A0] (x8 organization)

1100 1011 [A7–A0] (x16 organization)

1000 011R (where R = 0 or 1)

Set memory organization to 512 x 8 if R = 0.

Set memory organization to 256 x 16 if R = 1.

Read memory starting from specified address, sequen-

tially to the highest address or until CS goes LOW. The

instruction is terminated when CS goes LOW.

RSR Read Status Register

ENBSY Enable Busy

1100 1000

1000 0100

Output the contents of the 8-bit status register. The

contents of the first three bits of the register are 101,

which allows the user to quickly determine whether the

device is listening or is in an error condition. The next

threebitsindicateparityerror,instructionerrorandRDY/

BUSY status. The last two bits are reserved for future

use.

EnablethestatusindicatoronDOduringprogram/erase

cycle. DO goes LOW then HIGH once the write cycle is

complete. DO will go to HIGH-Z at the end of the next op

code transmission.

DISBSY Disable Busy

1000 0101

NOP No Operation

Disable the status indicator on DO during program/

erase cycle.

1000 0000

No Operation.

ORDERING INFORMATION

Prefix

Device #

Suffix

CAT

33C804A

-TE13

Optional

Company ID

Product

Number

Temperature Range

Tape & Reel

TE13: 2000/Reel

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

A = Automotive (-40˚ to +105˚C)*

Package

P: PDIP

J: SOIC (JEDEC)

* -40˚C to +125˚C is available upon request

Notes:

33C804 F19

(1) The device used in the above example is a 33C804AJI-TE13 (SOIC, Industrial Temperature, Tape & Reel)

Doc. No. 25044-00 2/98

CAT33C804AJI-TE7 [CATALYST]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E