CAT28F002NA-12TT [CATALYST]
2 Megabit CMOS Boot Block Flash Memory; 2兆位的CMOS引导块闪存
| 型号： | CAT28F002NA-12TT |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 2 Megabit CMOS Boot Block Flash Memory |
| 文件： | 总16页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT28F002
Licensed Intel
second source
2 Megabit CMOS Boot Block Flash Memory
FEATURES
■ Electronic Signature
■ Fast Read Access Time: 90/120/150 ns
■ On-Chip Address and Data Latches
■ Blocked Architecture:
■ 100,000 Program/Erase Cycles and 10 Year
Data Retention
■ Standard Pinouts:
— 40-Lead TSOP
— One 16-KB Protected Boot Block
• Top or Bottom Locations
— 40-Lead PDIP
— Two 8-KB Parameter Blocks
— One 96-KB Main Block
■ High Speed Programming
■ Commercial, Industrial and Automotive Tem-
— One 128-KB Main Block
perature Ranges
■ Hardware Data Protection
■ Reset/Deep PowerDown Mode
— 0.2µA ICC Typical
■ Automated Program and Erase Algorithms
■ Automatic Power Savings Feature
■ Low Power CMOS Operation
■ 12.0V ± 5% Programming and Erase Voltage
— Acts as Reset for Boot Operations
DESCRIPTION
TheCAT28F002isahighspeed256KX8-bitelectrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after sale
code updates.
The CAT28F002 is designed with a signature mode
whichallowstheusertoidentifytheICmanufacturerand
device type. The CAT28F002 is also designed with on-
ChipAddressLatches, DataLatches, Programmingand
Erase Algorithms. A deep power-down mode lowers the
total Vcc power consumption 1µw typical.
The CAT28F002 has a blocked architecture with one 16
KB Boot Block, two 8 KB Parameter Blocks, one 96 KB
Main Block and one 128 KB Main Block. The Boot Block
section can be at the top or bottom of the memory map.
The Boot Block section includes a reprogramming write
lock out feature to guarantee data integrity. It is de-
signed to contain secure code which will bring up the
system minimally and download code to other locations
of CAT28F002.
The CAT28F002 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin TSOP and 40-pin PDIP packages.
BLOCK DIAGRAM
I/O –I/O
0
7
ADDRESS
COUNTER
I/O BUFFERS
WRITE STATE
MACHINE
ERASE VOLTAGE
SWITCH
STATUS
REGISTER
RP
WE
DATA
LATCH
SENSE
AMP
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
CE
OE
Y-GATING
16K-BYTE BOOT BLOCK
8K-BYTE PARAMETER BLOCK
8K-BYTE PARAMETER BLOCK
96K-BYTE MAIN BLOCK
Y-DECODER
A
–A
17
0
X-DECODER
VOLTAGE VERIFY
SWITCH
128K-BYTE MAIN BLOCK
28F002 F01
Doc. No. 25072-00 2/98 F-1
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT28F002
PIN CONFIGURATION
PDIP Package (P)
TSOP Package (T)
1
40
39
38
37
36
35
34
33
32
31
NC
NC
NC
A
0
CE
GND
OE
A
1
A
2
A
3
A
4
A
5
A
6
A
7
2
A
GND
NC
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
WE
RP
1
2
3
4
5
6
7
8
17
16
15
14
13
12
11
9
8
3
4
5
A
10
6
I/O
I/O
I/O
I/O
7
6
5
4
7
I/O
0
8
I/O
1
9
I/O
2
9
V
PP
10
11
12
13
14
15
16
17
18
19
20
V
CC
V
CC
10
11
12
13
14
15
16
17
18
I/O
RP
3
V
PP
DU
NC
A
V
WE
30
29
CC
NC
I/O
V
A
8
A
9
CC
3
I/O
4
28
27
26
25
24
23
22
21
I/O
I/O
I/O
OE
GND
CE
7
2
1
0
A
6
I/O
A
5
11
A
A
A
A
A
5
4
3
2
1
I/O
6
A
12
I/O
A
7
13
A
10
A
14
A
GND
A
0
15
A
19
20
A
17
16
NC
NC
PIN FUNCTIONS
Pin Name
Type
Function
A0–A17
Input
Address Inputs for
memory addressing
I/O0–I/O7
CE
I/O
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Input
Input
Input
OE
WE
VCC
VSS
VPP
Program/Erase
Voltage Supply
RP
DU
Input
Power Down
Do Not Use
28F002 F03
Doc. No. 25072-00 2/98 F-1
2
CAT28F002
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100K
10
Max.
Units
Cycles/Byte
Years
Test Method
(3)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Limits
Max.
8
Symbol
Test
Min
Units
pF
Conditions
VIN = 0V
(3)
CIN
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
(3)
COUT
12
25
pF
VOUT = 0V
VPP = 0V
(3)
CVPP
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25072-00 2/98 F-1
3
CAT28F002
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V ±10%, unless otherwise specified
Limits
Max.
±1.0
Symbol
Parameter
Min.
Unit
Test Conditions
VIN = VCC or VSS
ILI
Input Leakage Current
µA
VCC = 5.5V
ILO
Output Leakage Current
±10
µA
µA
VOUT = VCC or VSS
VCC = 5.5V
,
ISB1
VCC Standby Current CMOS
100
CE = VCC ±0.2V = RP
VCC = 5.5V
ISB2
IPPD
ICC1
VCC Standby Current TTL
VPP Deep Powerdown Current
VCC Active Read Current
1.5
5.0
55
mA
µA
CE = RP = VIH, VCC = 5.5V
RP = GND±0.2V
mA
VCC = 5.5V, CE = GND,
IOUT = 0mA, f = 10 MHz
(1)
ICC2
VCC Programming Current
VCC Erase Current
50
30
mA
mA
VCC = 5.5V,
Programming in Progress
(1)
ICC3
VCC = 5.5V,
Erase in Progress
IPPS
VPP Standby Current
±10
200
µA
µA
VPP < VCC
VPP > VCC
IPP1
VPP Read Current
200
20
µA
VPP = VPPH
(1)
IPP2
VPP Programming Current
mA
VPP = VPPH
Programming in Progress
VPP = VPPH
,
(1)
IPP3
VPP Erase Current
15
mA
,
Erase in Progress
VIL
Input Low Level
–0.5
0.8
0.45
V
V
VOL
VIH
Output Low Level
IOL = 5.8mA, VCC = 4.5V
Input High Level
2.0
2.4
VCC+0.5
V
VOH1
VID
Output High Level TTL
A9 Signature Voltage
A9 Signature Current
V
IOH = -2.5mA, VCC = 4.5V
A9 = VID
10.8
13.2
500
1.0
V
IID
µA
µA
mA
µA
µA
V
A9 = VID
ICCD
ICCES
IPPES
IRP
VCC Deep Powerdown Current
VCC Erase Suspend Current
VPP Erase Suspend Current
RP Boot Block Unlock Current
Output High Level TTL
RP = GND±0.2V
Erase Suspended CE = VIH
Erase Suspended VPP=VPPH
RP = VHH
10
200
500
VOH2
0.85 VCC
VCC = VCCMIN
IOH = -1.5mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25072-00 2/98 F-1
4
CAT28F002
SUPPLY CHARACTERISTICS
Symbol
Limits
Parameter
Min
2.0
4.5
0
Max.
Unit
V
VLKO
VCC
VCC Erase/Write Lock Voltage
VCC Supply Voltage
5.5
6.5
V
VPPL
VPPH
VHH
VPP During Read Operations
VPP During Erase/Program
RP, OE Unlock Voltage
VPP Lock-Out Voltage
V
11.4
10.8
0
12.6
13.2
6.5
V
V
VPPLK
V
A.C. CHARACTERISTICS, Read Operation
= +5V ±10%, unless otherwise specified
V
CC
JEDEC Standard
Symbol Symbol
28F002-90 28F002-12 28F002-15
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tELQV
tAVQV
tGLQV
-
tRC
tCE
Read Cycle Time
90
120
120
120
40
150
150
150
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE Access Time
90
90
40
tACC
tOE
tOH
Address Access Time
OE Access Time
Output Hold from Address OE/CE Change
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
RP High to Output Delay
0
0
0
0
0
0
0
0
0
(1)(6)
tGLQX
tELQX
tGHQZ
tEHQZ
tPHQV
tOLZ
(1)(6)
tLZ
tDF
tHZ
(1)(2)
(1)(2)
30
30
30
30
30
30
tPWH
300
300
300
(3)(4)(5)
Figure 1. A.C. Testing Input/Output Waveform
2.4 V
2.0 V
0.8 V
INPUT PULSE LEVELS
0.45 V
REFERENCE POINTS
5108 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
5108 FHD F04
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
Doc. No. 25072-00 2/98 F-1
5
CAT28F002
A.C. CHARACTERISTICS, Program/Erase Operation
V
CC
= +5V ±10%, unless otherwise specified.
JEDEC Standard
Symbol Symbol
28F002-90 28F002-12 28F002-15
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tWC
tAS
Write Cycle Time
90
50
0
120
50
0
150
50
0
ns
ns
tAVWH
tWHAX
tDVWH
tWHDX
tELWL
Address Setup to WE Going High
Address Hold Time from WE Going High
Data Setup Time to WE Going High
Data Hold Time from WE Going High
CE Setup Time to WE Going Low
CE Hold Time from WE Going High
WE Pulse Width
tAH
tDS
tDH
tCS
tCH
tWP
tWPH
ns
40
0
40
0
40
0
ns
ns
0
0
0
ns
tWHEH
tWLWH
tWHWL
tPHWL
tPHHWH
tVPWH
tWHQV1
tWHQV2
tWHQV3
tWHQV4
tQVVL
0
0
0
ns
50
20
215
100
100
6
50
20
215
100
100
6
50
20
215
100
100
6
ns
WE High Pulse Width
ns
(1)
tPS
RP to WE Going Low
ns
(1)
tPHS
tVPS
—
RP VHH Setup to WE Going High
VPP Setup to WE Going High
Duration of Programming Operations
Duration of Erase Operations (Boot)
ns
(1)
ns
µs
—
0.3
0.3
0.3
0.6
0
0.3
0.3
0.6
0
Sec
Sec
Sec
ns
—
Duration of Erase Operations (Parameter) 0.3
—
Duration of Erase Operations (Main)
VPP Hold from Valid Status Reg Data
RP VHH Hold from Status Reg Data
Boot Block Relock Delay
0.6
0
(1)
(1)
tVPH
tQVPH
tPHH
—
0
0
0
ns
(1)
tPHBR
100
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25072-00 2/98 F-1
6
CAT28F002
ERASE AND PROGRAMMING PERFORMANCE
28F002-90
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
28F002-12
28F002-15
Parameter
Boot Block Erase Time
Parameter Block Erase Time
Main Block Erase Time
Main Block Program Time
1.0
1.0
2.4
1.2
7
7
1.0
1.0
2.4
1.2
7
7
1.0
1.0
2.4
1.2
7
7
Sec
Sec
Sec
14
4.2
14
4.2
14
4.2 Sec
(1)
FUNCTION TABLE
Pins
Mode
RP
CE
VIL
VIL
VIH
VIL
VIL
OE
VIL
VIH
X
WE
VIH
VIH
X
VPP
X
I/O
Notes
Read
VIH
VIH
VIH
VIH
VIH
DOUT
High-Z
High-Z
31H
Output Disable
Standby
X
X
Signature (MFG)
Signature (Device)
VIL
VIL
VIH
VIH
X
A0 = VIL, A9 = 12V
X
7CH-28F002T A0 = VIH, A9 = 12V
7DH-28F002B
Write Cycle
VIH
VIL
VIL
X
VIH
X
VIL
X
X
X
DIN
During Write Cycle
Deep Power Down
HIGH-Z
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when V is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
PP
addresses and data required for programming and erase operations.
First Bus Cycle
Operation Address DIN
Second Bus Cycle
Mode
Operation Address
DIN
DOUT
Read Array/Reset
Write
Write
X
FFH
Program Setup/
Program
AIN
40H
10H
Write
Read
AIN
X
DIN
Read Status Reg.
Clear Status Reg.
Write
X
70H
St. Reg. Data
Write
Write
X
50H
20H
Erase Setup/Erase
Confirm
Block ad
Write
Write
Block ad
X
D0H
D0H
Erase Suspend/
Erase Resume
Write
X
B0H
Read Sig (Mfg)
Read Sig (Dev)
Write
Write
X
X
90H
90H
Read
Read
0000H
0001H
31H
7CH-28F002T
7DH-28F002B
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (V , V , V
, V )
PPH
IH
IL
PPL
Doc. No. 25072-00 2/98 F-1
7
CAT28F002
READ OPERATIONS
Read Mode
applying the required high voltage on address pin A9
while the other address line are held at VIL.
The CAT28F002 memory can be read from any of its
Blocks (Boot Block, Main Block or Parameter Block),
Status Register and Signature Information by sending
the Read Command Mode to the Command Register.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O7 to I/O0:
CAT28F002 automatically resets to Read Array mode
upon initial device power up or after exit from deep
power down. A Read operation is performed with both
CE and OE low and with RP and WE high. Vpp can be
either high or low. The data retrieved from the I/O pins
reflectsthecontentsofthememorylocationcorrespond-
ing to the state of the 18 address pins. The respective
timing waveforms for the read operation are shown in
Figure 3. Refer to the AC Read characteristics for
specific timing parameters.
Catalyst Code = 0011 0001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O7 to I/O0:
CAT28F002T = 0111 1100 (7CH)
CAT28F002B = 0111 1101 (7DH)
Standby Mode
With CE at a logic-high level, the CAT28F002 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con-
sumption. Theoutputsareplacedinahigh-impendance
state independent of the OE status.
Signature Mode
The signature mode allows the user to identify the IC
manufacturerandthetypeofthedevicewhilethedevice
residesinthetargetsystem. Thismodecanbeactivated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
Deep Power-Down
When RP is at logic-low level, the CAT28F002 is placed
in a Deep Power-Down mode where all the device
circuitry are disabled, thereby reducing the power con-
sumption to 0.25µW.
The conventional method is entered as a regular read
mode by driving the CE and OE low (with WE high), and
Figure 3. A.C. Timing for Read Operation
STANDBY
DEVICE AND
OUPUTS
DATA VALID
STANDBY
POWER DOWN
POWER UP
ADDRESS SELECTION
ENABLED
ADDRESS STABLE
ADDRESSES
CE (E)
t
(t
)
AVAV RC
t
EHQZ
OE (G)
t
(t
)
GHQZ DF
t
(t
GLQV OE
)
WE (W)
t
(t
ELQV CE
)
t
(t
)
t
GLQX OLZ
OH
t
(t
)
ELQX LZ
HIGH-Z
HIGH-Z
OUTPUT VALID
DATA (I/O)
RP (P)
t
(t
)
AVQV ACC
)
t
(t
PHQV PWH
28F002 F05
Doc. No. 25072-00 2/98 F-1
8
CAT28F002
block erasure. During the first write cycle, a Command
20H (Erase Setup) is first written to the Command
Register, followed by the Command D0H (Erase Con-
firm). These commands require both appropriate com-
mand data and an address within Block to be erased.
Also, Block erasure can only occur when VPP= VPPH.
WRITE OPERATIONS
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Array
The device can be put into a Read Array Mode by
initiating a write cycle with FFH on the data bus. The
device is also in a standard Read Array Mode after the
initial device power up and when comes out of the Deep
Power-Down mode.
Block preconditioning, erase and verify are all handled
internally by the Write State Machine, invisible to the
system. After receiving the two command erase se-
quence the CAT28F002 automatically outputs Status
Register data when read (Fig.5). The CPU can detect
the completion of the erase event by checking if the
SR.7 of the Status Register is set.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register. A read cycle
from address 0000H with CE and OE low (and WE high)
will output the device signature.
SR.5 will indicate whether the erase was successful. If
aneraseerrorisdetected, theStatusRegistershouldbe
cleared. The device will be in the Status Register Read
Mode until another command is issued.
ERASE SUSPEND/ERASE RESUME
Catalyst Code = Catalyst Code = 0011 0001 (31H)
The Erase Suspend Command allows erase sequence
interruption in order to read data from another block of
memory. Once the erase sequence is started, writing
the Erase Suspend command (B0H) to the Command
Register requests that the WSM suspend the erase
sequence at a predetermined point in the erase algo-
rithm. The CAT28F002 continues to output Status Reg-
isterdatawhenread,aftertheEraseSuspendcommand
is written to it. Polling the WSM Status and Erase
Suspend Status bits will determine when the erase
operation has been suspended (both will be set to “1s”).
A Read cycle from address 0001H retrieves the
binary code for the device on outputs I/O7 to I/O0:
CAT28F002T = 0111 1100 (7CH)
CAT28F002B = 0111 1101 (7DH)
To terminate the operations, it is necessary to write
another valid command into the register.
STATUS REGISTER
The device may now be given a Read ARRAY Com-
mand, which allows any locations 'not within the block
being erased' to be read. Also, you can either perform
a Read Status Register or resume the Erase Operation
by sending Erase Resume (D0H), at which time the
WSM will continue with the erase sequence. The Erase
Suspend Status and WSM Status bits of the Status
Register will be cleared.
The 28F002 contains an 8-bit Status Register. The
Status Register is polled to check for write or erase
completion or any related errors. The Status Register
may be read at any time by issuing a Read Status
Register (70H) command. All subsequent read opera-
tions output data from the Status Register, until another
valid command is issued. The contents of the Status
Register are latched on the falling edge of OE or CE,
whichever occurs last in the read cycle. OE or CE must
be toggled to VIH before further reads to update the
status register latch.
PROGRAM SETUP/PROGRAM COMMANDS
Programmingisexecutedbyatwo-writesequence. The
program Setup command (40H) is written to the Com-
mand Register, followed by a second write specifying
the address and data (latched on the rising edge of WE)
to be programmed. The WSM then takes over, control-
ling the program and verify algorithms internally. After
the two-command program sequence is written to it, the
CAT28F002 automatically outputs Status Register data
when read (see figure 4; Byte Program Flowchart). The
CPU can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register Command is valid while
programming is active.
TheEraseStatus(SR.5)andProgramStatus(SR.4)are
set to 1 by the WSM and can only be reset issuing Clear
Status Register (50H) These two bits can be polled for
failures, thus allowing more flexibility to the designer
when using the CAT28F002. Also, VPP Status (SR.3)
when set to 1 must be reset by system software before
anyfurtherbyteprogramsorblockerasesareattempted.
ERASE SETUP/ERASE CONFIRM
Erase is executed one block at a time, initiated by a two
cycle command sequence. The two cycle command
sequence provides added security against accidental
Doc. No. 25072-00 2/98 F-1
9
CAT28F002
WSMS
7
ESS
6
ES
5
PS
4
VPPS
3
R
2
R
1
R
0
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
NOTES:
The Write State Machine Status Bit must first be checked to
determine program or erase completion, before the
Program or Erase Status bits are checked for success.
If the Program AND Erase Status bits are set to “1s” during an
erase attempt, an improper command sequence was
entered. Attempt the operation again.
0 = Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
0 = Erase in Progress/Completed
SR.5 = ERASE STATUS
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = PROGRAM STATUS
1 = Error in Byte Program
0 = Successful Byte Program
SR.3 = VPP STATUS
If V low status is detected, the Status Register must be
PP
cleared before another program or erase operation is
attempted.
The V Status bit, unlike an A/D converter, does not provide
PP
continuous indication of V level. The WSM interrogates
the V level only after the program or erase command
PP
PP
1 = V Low Detect; Operation Abort
sequences have been entered and informs the system if
PP
0 = V Okay
V
has not been switched on. The V Status bit is not
PP PP
PP
SR.2 -SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked
out when polling the Status Register.
guaranteed to report accurate feedback between V
and
PPL
V
.
PPH
When the Status Register indicates that programming is
complete, the Program Status bit should be checked. If
programerrorisdetected, theStatusRegistershouldbe
cleared. The internal WSM verify only detects errors for
“1s” that do not successfully program to “0s”. The
Command Register remains in Read Status Register
mode until further commands are issued to it.
Erase Confirm commands, they should be written to an
address within the address range of the block to be
erased. Figure 5 shows a system software flowchart for
block erase.
The entire sequence is performed with VPP at VPPH
.
Abort occurs when RP transitions to VIL, or VPP drops to
VPPL. Although the WSM is halted, byte data is partially
programmed or Block data is partially erased at the
location where it was aborted. Block erasure or a repeat
of byte programming will initialize this data to a known
value.
If erase/byte program is attempted while VPP = VPPL, the
Status bit (SR.5/SR.4) will be set to “1”. Erase/Program
attempts while VPPL < VPP < VPPH produce spurious
results and should not be attempted.
EMBEDDED ALGORITHMS
The CAT28F002 integrates the Quick Pulse program-
ming algorithm on-chip, using the Command Register,
Status Register and Write State Machine (WSM). On-
chip integration dramatically simplifies system software
and provides processor-like interface timings to the
Command and Status Registers. WSM operation, inter-
nal program verify, and VPP high voltage presence are
monitored and reported via appropriate Status Register
bits. Figure 4 shows a system software flowchart for
device programming.
BOOT BLOCK PROGRAM AND ERASE
The boot block is intended to contain secure code which
will minimally bring up a system and control program-
ming and erase of other blocks of the device, if needed.
Therefore, additional “lockout” protection is provided to
guarantee data integrity. Boot block program and erase
operations are enabled through high voltage VHH on
either RP or OE, and the normal program and erase
command sequences are used. Reference the AC
Waveforms for Program/Erase.
As above, the Quick Erase algorithm is now imple-
mented internally, including all preconditioning of block
data. WSM operation, erase verify and VPP high voltage
presencearemonitoredandreportedthroughtheStatus
Register. Additionally, if a command other than Erase
Confirm is written to the device after Erase Setup has
been written, both the Erase Status and Program Status
bits will be set to “1”. When issuing the Erase Setup and
If boot block program or erase is attempted while RP is
at VIH, either the Program Status or Erase Status bit will
be set to “1”, reflective of the operation being attempted
and indicating boot block lock. Program/erase attempts
while VIH < RP < VHH produce spurious results and
should not be attempted.
Doc. No. 25072-00 2/98 F-1
10
CAT28F002
IN-SYSTEM OPERATION
For on-board programming, the RP pin is the most
convenient means of altering the boot block. Before
issuingProgramorEraseconfirmscommands,RPmust
transitiontoVHH.HoldRPatthishighvoltagethroughout
the program or erase interval (until after Status Register
confirm of successful completion). At this time, it can
return to VIH or VIL.
Figure 4 Byte Programming Flowchart
START
Bus
Operation Command Comments
WRITE 40H,
BYTE ADDRESS
Write
Write
Read
Program
Setup
Data = 40H
Address = Bytes to be Programmed
Program
Data to be programmed
Address = Byte to be Programmed
WRITE BYTE
ADDRESS/DATA
Status Register Data.
Toggle OE or CE to update
Status Register
READ STATUS
REGISTER
Check SR.7
NO
SR.7 = 1?
Standby
1 = Ready, 0 = Busy
Repeat for subsequent bytes.
YES
FULL STATUS
CHECK IF DESIRED
Full Status check can be done after each byte or after a sequence
of bytes.
Write FFH after the last byte programming operation to reset the
device to Read Array Mode.
BYTE PROGRAM
COMPLETED
FULL STATUS CHECK PROCEDURE
STATUS REGISTER DATA
READ (SEE ABOVE)
Bus
Operation Command Comments
NO
NO
V
RANGE
ERROR
Standby
Check SR.3
PP
SR.3 = 0?
1 = V Low Detect
PP
YES
BYTE PROGRAM
ERROR
Standby
Check SR.3
1 = Byte Program Error
SR.4 = 0?
YES
SR.3 MUST be cleared, if set during a program attempt, before
further attempts are allowed by the Write State Machine.
BYTE PROGRAM
SUCCESSFUL
SR.3 is only cleared by the Clear Status Register Command, in
case where multiple bytes are programmed before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Doc. No. 25072-00 2/98 F-1
11
CAT28F002
Figure 5 Block Erase Flowchart
START
Bus
Operation Command Comments
WRITE 20H,
BLOCK ADDRESS
Write
Erase
Setup
Data = 20H
Address = Within Block to be erased
WRITE D0H
BLOCK ADDRESS
Write
Read
Erase
Data - D0H
Address = Within Block to be erased
READ STATUS
REGISTER
Status Register Data.
Toggle OE or CE to update
Status Register
ERASE SUSPEND
LOOP
NO
NO
YES
SUSPEND
ERASE?
SR.7 = 1?
Standby
Check SR.7
1 = Ready, 0 = Busy
YES
Repeat for subsequent blocks.
FULL STATUS
CHECK IF DESIRED
Full Status check can be done after each block or after a sequence
of blocks.
BLOCK ERASE
COMPLETED
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
FULL STATUS CHECK PROCEDURE
STATUS REGISTER DATA
READ (SEE ABOVE)
Bus
Operation Command Comments
NO
V RANGE
PP
ERROR
SR.3 = 0?
YES
Standby
Check SR.3
1 = V Low Detect
PP
COMMAND SEQUENCE
ERROR
YES
SR.4,5 = 1?
NO
Standby
Check SR.4
Both 1 = Command Sequence Error
BLOCK ERASE
ERROR
NO
SR.5 = 0?
Standby
Check SR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during a erase attempt, before further
attempts are allowed by the Write State Machine.
BLOCK ERASE
SUCCESSFUL
SR.3 is only cleared by the Clear Status Register Command, in
cases where multiple blocks are erased before full status is
checked.
If error is detected, clear the Status Register before attempting retry
or other error recovery.
Doc. No. 25072-00 2/98 F-1
12
CAT28F002
Figure 6 Block Erase Suspend/Resume Flowchart
START
Bus
Operation Command
Comments
WRITE B0H
WRITE 70H
Write
Erase
Suspend
Data = B0H
Write
Erase
Data = 70H
Status Register
READ STATUS
REGISTER
Standby/
Ready
Read Status Register
Check SR.7
1 = Ready, 0 = Busy
Toggle OE or CE to Update
Status Register
NO
SR.7 = 1?
YES
NO
SR.6 = 1?
Standby
Check SR.6
1 = Suspended
ERASE HAS
COMPLETED
YES
WRITE FFH
Write
Read
Read Array
Data = FFH
DONE
READING?
NO
Read array data from block other
than that being erased.
YES
WRITE D0H
Write
Erase Resume Data = D0H
CONTINUE
ERASE
Doc. No. 25072-00 2/98 F-1
13
CAT28F002
Figure 7. A.C. Timing for Program/Erase Operation
WRITE
V
POWER-UP
WRITE PROGRAM OR
ERASE SETUP COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
CC
& STANDBY
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
V
IH
ADDRESSES (A)
CE (E)
A
A
IN
IN
V
V
IL
t
t
t
AVAV
AVWH
WHAX
IH
V
IL
t
t
ELWL
WHEH
t
WHGL
V
IH
OE (G)
V
V
IL
t
WHWL
IH
WE (W)
V
IL
t
WLWH
t
t
DVWH
WHDX
V
IH
HIGH Z
VALID
SRD
DATA (I/O)
D
D
D
IN
IN
IN
t
V
PHWL
IL
t
t
PHHWH
QVPH
V
HH
6.5V
V
IH
RP (P)
V
IL
t
t
VPWH
QVVL
V
PPH
V
PPL
V
(V)
PP
V
IH
V
IL
28F002 F09
POWER UP/DOWN PROTECTION
POWER SUPPLY DECOUPLING
The CAT28F002 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F002 is reset to the Read Mode on
power up.
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitorbetweenVCC andVSS andVPP andVSS.These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Doc. No. 25072-00 2/98 F-1
14
CAT28F002
ALTERNATE CE-CONTROLLED WRITES
= +5V ±10%, unless otherwise specified
V
CC
JEDEC Standard
Symbol Symbol
28F002-90 28F002-12 28F002-15
Min. Max. Min. Max. Min. Max. Unit
Parameter
tAVAV
tWC
tAS
Write Cycle Time
90
50
0
120
50
0
150
50
0
ns
ns
tAVEH
tEHAX
tDVEH
tEHDX
tWLEL
tEHWH
tELEH
Address Setup to CE Going High
Address Hold Time from CE Going High
Data Setup Time to CE Going High
Data Hold Time from CE Going High
WE Setup Time to CE Going Low
WE Hold Time from CE Going High
CE Pulse Width
tAH
tDS
tDH
tWS
tWH
tCP
tEPH
ns
40
0
40
0
40
0
ns
ns
0
0
0
ns
0
0
0
ns
50
30
215
100
100
6
50
30
215
100
100
6
50
30
215
100
100
6
ns
tEHEL
CE Pulse Width High
ns
(1)
tPHEL
tPS
tPHS
tVPS
—
RP High Recovery to CE Going Low
RP VHH Setup to CE Going High
VPP Setup to CE Going High
Duration of Programming Operations
Duration of Erase Operations (Boot)
ns
(1)
(1)
tPHHEH
tVPEH
tEHQV1
tEHQV2
tEHQV3
tEHQV4
tQVVL
tQVPH
ns
ns
µs
—
0.3
0.3
0.3
0.6
0
0.3
0.3
0.6
0
Sec
Sec
Sec
ns
—
Duration of Erase Operations (Parameter) 0.3
—
Duration of Erase Operations (Main)
VPP Hold from Valid Status Reg Data
RP VHH Hold from Status Reg Data
Boot Block Relock Delay
0.6
0
(1)
(1)
tVPH
tPHH
—
0
0
0
ns
(1)
tPHBR
100
100
100
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25072-00 2/98 F-1
15
CAT28F002
ORDERING INFORMATION
Prefix
Device #
28F002
Suffix
CAT
T
-12
B
I
T
Optional
Company ID
Product
Number
Temperature Range
Tape & Reel
T: 500/Reel
Boot Block
B: Bottom
T: Top
Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
A = Automotive (-40˚ to 105˚C)*
Package
T: 40-pin TSOP
P: 40-pin PDIP
Speed
90: 90 ns
12: 120 ns
15: 150 ns
* -40˚ to +125˚C is available upon request
28F002 F13
Note:
(1) The device used in the above example is a CAT28F002TI-12BT (TSOP, Industrial Temperature, 120ns access time, Bottom Boot
Block, Tape & Reel)
Doc. No. 25072-00 2/98 F-1
16
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