CAT28C256N-15T [CATALYST]
256K-Bit Parallel EEPROM; 256K位并行EEPROM
| 型号： | CAT28C256N-15T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 256K-Bit Parallel EEPROM |
| 文件： | 总12页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28C256
256K-Bit Parallel EEPROM
TM
FEATURES
■ Hardware and software write protection
■ Fast read access times: 120/150ns
■ Automatic page write operation:
–1 to 64 bytes in 5ms
■ Low power CMOS dissipation:
–Active: 25 mA max
–Page load timer
–Standby: 150 µA max
■ End of write detection:
–Toggle bit
■ Simple write operation:
–On-chip address and data latches
–Self-timed write cycle with auto-clear
–DATA polling
■ 100,000 program/erase cycles
■ 100 year data retention
■ Fast write cycle time:
–5ms max
■ CMOS and TTL compatible I/O
■ Commerical, industrial and automotive
temperature ranges
DESCRIPTION
The CAT28C256 is a fast, low power, 5V-only CMOS
parallel EEPROM organized as 32K x 8-bits. It requires a
simple interface for in-system programming. On-chip
addressanddatalatches,self-timedwritecyclewithauto-
clear and VCC power up/down write protection eliminate
additional timing and protection hardware. DATA Polling
and Toggle status bits signal the start and end of the self-
timed write cycle. Additionally, the CAT28C256 features
hardware and software write protection.
The CAT28C256 is manufactured using Catalyst’s ad-
vancedCMOSfloatinggatetechnology. Itisdesignedto
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
BLOCK DIAGRAM
32,768 x 8
EEPROM
ARRAY
ROW
DECODER
ADDR. BUFFER
A –A
6
14
& LATCHES
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
64 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
AND
TIMER
TOGGLE BIT
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
5
Doc. No. 1004, Rev. D
© 2004 by Catalyst Semiconductor, Inc.
1
Characteristics subject to change without notice
CAT28C256
PIN CONFIGURATION
DIP Package (P, L)
PLCC Package (N, G)
A
A
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
14
12
2
A
A
3
A
4
3 2 1 32 31 30
7
6
5
4
3
2
1
0
0
1
2
13
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
4
A
6
5
4
3
2
1
0
8
8
A
5
A
9
9
A
6
A
11
11
NC
OE
A
A
7
OE
TOP VIEW
A
8
A
10
10
11
12
13
A
9
CE
10
CE
I/O
A
10
11
12
13
14
I/O
7
NC
I/O
I/O
I/O
I/O
V
I/O
7
6
I/O
I/O
5
0
6
14 15 16 17 18 19 20
I/O
4
I/O
3
SS
TSOP Package (8mm X 13.4mm) (T13, H13)
28
OE
1
2
3
4
5
6
7
8
A
10
27
26
25
24
23
22
21
20
19
18
17
16
15
A
A
A
A
13
WE
CE
I/O
I/O
I/O
I/O
I/O
11
9
8
7
6
5
4
3
V
A
A
CC
14
GND
9
I/O
I/O
1
I/O
12
2
A
10
11
12
13
14
7
A
A
A
A
6
5
4
3
0
A
A
1
A
2
0
PIN FUNCTIONS
Pin Name
Function
Address Inputs
Pin Name
WE
Function
Write Enable
5V Supply
Ground
A0–A14
I/O0–I/O7
CE
Data Inputs/Outputs VCC
Chip Enable
VSS
NC
OE
Output Enable
No Connect
Doc. No. 1004, Rev. D
2
CAT28C256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
Parameter
Endurance
Min.
100,000
100
Max.
Units
Cycles/Byte
Years
Test Method
(1)
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
VCC = 5V 10%, unless otherwise specified.
Limits
Symbol
Parameter
Min. Typ.
Max.
Units
Test Conditions
ICC
VCC Current (Operating, TTL)
30
mA
CE = OE = VIL, f=8MHz
All I/O’s Open
(5)
ICCC
VCC Current (Operating, CMOS)
25
mA
CE = OE = VILC, f=8MHz
All I/O’s Open
ISB
VCC Current (Standby, TTL)
VCC Current (Standby, CMOS)
1
mA
CE = VIH, All I/O’s Open
(6)
ISBC
150
µA
CE = VIHC,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
–10
–10
10
10
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC
,
CE = VIH
(6)
VIH
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
VCC +0.3
0.8
V
V
V
V
V
(5)
VIL
–0.3
2.4
VOH
VOL
VWI
IOH = –400µA
0.4
IOL = 2.1mA
3.5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
(5) V
(6) V
= –0.3V to +0.3V.
ILC
IHC
= V –0.3V to V +0.3V.
CC
CC
Doc. No. 1004, Rev. D
3
CAT28C256
MODE SELECTION
Mode
CE
L
WE
H
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
L
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
CI/O
Test
Max.
10
Units
pF
Conditions
VI/O = 0V
VIN = 0V
(1)
Input/Output Capacitance
Input Capacitance
(1)
CIN
6
pF
A.C. CHARACTERISTICS, Read Cycle
VCC=5V + 10%, Unless otherwise specified
28C256-12
Min. Max.
28C256-15
Symbol
tRC
Parameter
Min. Max. Units
Read Cycle Time
120
120
120
50
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCE
CE Access Time
150
150
70
tAA
Address Access Time
OE Access Time
tOE
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
0
0
(1)
tOLZ
0
(1)(2)
tHZ
50
50
0
50
50
(1)(2)
tOHZ
(1)
tOH
0
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 1004, Rev. D
4
CAT28C256
A.C. CHARACTERISTICS, Write Cycle
VCC=5V+10%, unless otherwise specified
28C256-12
28C256-15
Symbol Parameter
Min. Max. Min. Max.
Units
ms
ns
tWC
tAS
tAH
tCS
tCH
tCW
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
5
5
0
0
50
0
50
0
ns
ns
CE Hold Time
0
0
ns
(3)
CE Pulse Time
100
0
100
0
ns
tOES
tOEH
OE Setup Time
ns
OE Hold Time
0
0
ns
(3)
tWP
tDS
WE Pulse Width
100
50
10
5
100
50
10
5
ns
Data Setup Time
Data Hold Time
ns
tDH
ns
(1)
tINIT
Write Inhibit Period After Power-up
Byte Load Cycle Time
10
10
ms
µs
(1)(4)
tBLC
0.1
100
0.1
100
Figure 1. A.C. Testing Input/Output Waveform(2)
V
- 0.3V
CC
2.0 V
0.8 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
Doc. No. 1004, Rev. D
5
CAT28C256
Byte Write
DEVICE OPERATION
Awritecycleisexecutedwhenboth CEand WEarelow,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 5 ms.
Read
Data stored in the CAT28C256 is transferred to the data
bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Doc. No. 1004, Rev. D
6
CAT28C256
Page Write
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
The page write mode of the CAT28C256 (essentially an
extended BYTE WRITE mode) allows from 1 to 64 bytes
ofdatatobeprogrammedwithinasingleEEPROMwrite
cycle. This effectively reduces the byte-write time by a
factor of 64.
limitation as long as WE is pulsed low within tBLC MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
whichwritesnewdatabackintothecell. Apagewritewill
only write data to the locations that were addressed and
will not rewrite the entire page.
FollowinganinitialWRITEoperation(WEpulsedlow,for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
anddatabytesintoa64bytetemporarybuffer. Thepage
address where data is to be written, specified by bits A6
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A5
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
BYTE n
BYTE n+1
Doc. No. 1004, Rev. D
7
CAT28C256
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
InadditiontotheDATAPollingfeatureoftheCAT28C256,
the device offers an additional method for determining
the completion of a write cycle. While a write cycle is in
progress, reading data from the device will result in I/O6
togglingbetweenoneandzero. However, oncethewrite
is complete, I/O6 stops toggling and valid data can be
read from the device.
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
I/O
D
= X
D
= X
D
= X
OUT
7
IN
OUT
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
Note:
(1) Beginning and ending state of I/O is indeterminate.
6
Doc. No. 1004, Rev. D
8
CAT28C256
HARDWARE DATA PROTECTION
The following is a list of hardware data protection fea-
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
tures that are incorporated into the CAT28C256.
(1) VCC sense provides for write protection when VCC
falls below 3.5V min.
SOFTWARE DATA PROTECTION
The CAT28C256 features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28C256 is
in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 3.5V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
5555
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
2AAA
2AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
5555
5555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED
(1)
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
2AAA
TO ANY ADDRESS
20
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
5555
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 1004, Rev. D
9
CAT28C256
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
anEEPROMprogrammer(orfortestingpurposes)there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Doc. No. 1004, Rev. D
10
CAT28C256
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28C256
N
I
-15
T
Tape & Reel
Optional Product
Company Number
ID
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)*
Package
P: PDIP
N: PLCC
Speed
12: 120ns
15: 150ns
T13: TSOP (8mmx13.4mm)
L: PDIP (Lead free, Halogen free)
G: PLCC (Lead free, Halogen free)
H13: TSOP (8mmx13.4mm) (Lead free, Halogen free)
* -40°C to +125°C isavailable upon request
Notes:
(1) The device used in the above example is a CAT28C256NI-15T (PLCC, Industrial temperature, 150ns Access Time, Tape & Reel).
Doc. No. 1004, Rev. D
11
REVISION HISTORY
Date
Revision Comments
3/29/2004
04/19/04
C
D
Added Green packages in all areas.
Delete data sheet designation
Update Block Diagram
Update Ordering Information
Update Revision History
Update Rev Number
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issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
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Corporate Headquarters
1250 Borregas Avenue
Publication #: 1004
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Revison:
D
Issue date:
04/19/04
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