CAT25C04U-TE13 [CATALYST]
1K/2K/4K/8K/16K SPI Serial CMOS E2PROM; 1K / 2K / 4K / 8K / 16K SPI串行E2PROM CMOS
| 型号： | CAT25C04U-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1K/2K/4K/8K/16K SPI Serial CMOS E2PROM |
| 文件： | 总10页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advanced Information
CAT25C01/02/04/08/16
1K/2K/4K/8K/16K SPI Serial CMOS E2PROM
FEATURES
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 10 MHz SPI Compatible
■ 1.8 to 6.0 Volt Operation
■ Hardware and Software Protection
■ Zero Standby Current
■ Self-Timed Write Cycle
■ 8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP
■ 16/32-Byte Page Write Buffer
■ Low Power CMOS Technology
■ SPI Modes (0,0 & 1,1)
■ Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C01/02/04/08/16 is de-
signed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/
14-pin TSSOP packages.
The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS E2PROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits.Catalyst’sad-
vanced CMOS Technology substantially reduces de-
vice power requirements. The CAT25C01/02/04 fea-
tures a 16-byte page write buffer. The 25C08/16 fea-
tures a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
ChipSelect(CS).InadditiontotheChipSelect,theclock
PIN CONFIGURATION
TSSOP Package (U14)
DIP Package (P)
TSSOP Package (U)
SOIC Package (S)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
V
CS
SO
CS
SO
CS
SO
WP
CC
V
CC
CC
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
HOLD
NC
NC
NC
CS
SO
NC
NC
NC
WP
HOLD
SCK
SI
HOLD
SCL
SI
HOLD
SCK
SI
WP
WP
V
SS
V
SS
V
SS
BLOCK DIAGRAM
SCK
SI
MSOP Package (R)*
SENSE AMPS
SHIFT REGISTERS
V
SS
1
2
3
4
8
7
6
5
CS
SO
WP
V
CC
HOLD
SCK
V
SI
SS
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
*CAT 25C01/02 only
PIN FUNCTIONS
SO
SI
I/O
CONTROL
Pin Name
SO
Function
Serial Data Output
Serial Clock
E2PROM
ARRAY
CS
SPI
CONTROL
LOGIC
XDEC
WP
SCK
WP
HOLD
SCK
Write Protect
BLOCK
PROTECT
LOGIC
VCC
+1.8V to +6.0V Power Supply
Ground
VSS
DATA IN
STORAGE
CS
Chip Select
SI
Serial Data Input
Suspends Serial Input
No Connect
HIGH VOLTAGE/
TIMING CONTROL
HOLD
NC
STATUS
REGISTER
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 25067-00 5/00
1
CAT25C01/02/04/08/16
Advanced Information
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
3
0
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
ISB
Power Supply Current
(Operating Read)
mA
VCC = 5.5V
FCLK = 5MHz
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
4.5V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25067-00 5/00
2
Advanced Information
CAT25C01/02/04/08/16
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) – – – – –
A.C. CHARACTERISTICS
Limits
2.5V-6.0V
1.8V-6.0V
4.5V-5.5V
Test
UNITS Conditions
SYMBOL PARAMETER
Min.
50
Max. Min.
Max. Min. Max.
tSU
tH
Data Setup Time
Data Hold Time
20
20
75
75
20
20
40
40
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
DC
5
50
2
DC
10
50
2
(1)
tRI
(1)
tFI
Input Fall Time
2
2
2
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
tCD
CL = 50pF
tWC
tV
10
5
5
250
80
80
tHO
0
0
0
tDIS
tHZ
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tWPH
NOTE:
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
50
50
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25067-00 5/00
3
CAT25C01/02/04/08/16
Advanced Information
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK for SPI modes (0,0 & 1,1) .
FUNCTIONAL DESCRIPTION
The CAT25C01/02/04/08/16 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C01/02/04/08/16 to
interface directly with many of today’s popular
microcontrollers. The CAT25C01/02/04/08/16 contains
an8-bitinstructionregister. (Theinstructionset andthe
operation codes are detailed in the instruction set table)
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C01/
02/04/08/16 and CS high disables the CAT25C01/02/
04/08/16. CS high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C01/02/04/08/16 draws ZERO current in the
Standbymode. Ahightolow transitiononCSisrequired
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what
initiates an internal write cycle.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
PIN DESCRIPTION
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C01/02/04/08/16. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C01/02/04/08/16. During a
read cycle, data is shifted out on the falling edge of the
serial clock for SPI modes (0,0 & 1,1).
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C01/02/04/08/16. Opcodes, byte addresses,
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
(1)
(1)
WRITE
(2)(3)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) X=0 for 25C01, 25C02, 25C08, 25C16. X=A8 for 25C04
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 25067-00 5/00
4
Advanced Information
CAT25C01/02/04/08/16
HOLD: Hold
STATUS REGISTER
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C01/02/04/08/16 while in the
middleofaserialsequencewithouthavingtore-transmit
entiresequenceatalatertime.Topause,HOLDmustbe
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,HOLDisbroughthigh,whileSCKislow.
(HOLD should be held high any time this function is not
being used.) HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C01/
02/04/08/16 is busy with a write operation. When set to
1awritecycleisinprogressandwhensetto0thedevice
indicates it is ready. This bit is read onlyThe WEL (Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WELbitcanonlybesetbytheWRENinstructionandcan
be reset by the WRDI instruction.
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
PR_MODE SPI_MODE
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
None
Protection
BP1
0
BP0
0
No Protection
0
1
25C01: 60-7F
25C02: C0-FF
25C04: 180-1FF
25C08: 0300-03FF
25C16: 0600-07FF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25C01: 40-7F
25C02: 80-FF
25C04: 100-1FF
25C08: 0200-03FF
25C16: 0400-07FF
25C01: 00-7F
25C02: 00-FF
25C04: 000-1FF
25C08: 0000-03FF
25C16: 0000-07FF
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
0
1
X
1
0
1
0
1
Low
Low
High
High
Protected
Protected
Protected
Writable
1
X
X
Doc. No. 25067-00 5/00
5
CAT25C01/02/04/08/16
Advanced Information
writes(reset the latch) to the device. Disabling writes
will protect the device against inadvertent writes.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C01/02/04/08/
16, followed by the 16-bit address for 25C08/16. (only
10-bit addresses are used for 25C08, 11-bit addresses
are used for 25C16. The rest of the bits are don't care
bits) and 8-bit address for 25C01/02/04 (for the 25C04,
bit 3 of the read data instruction contains address A8).
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memoryatthenextaddresscanbereadsequentiallyby
continuing to provide clock pulses. The internal ad-
dress pointer is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counterrollsoverto0000hallowingthereadcycletobe
continuedindefinitely. Thereadoperationisterminated
by pulling the CS high. To read the status register,
RDSR instruction should be sent. The contents of the
statusregisterareshiftedoutontheSOline. Thestatus
register may be read at any time even during a write
cycle. Read sequece is illustrated in Figure 4. Reading
status register is illustrated in Figure 5.
DEVICE OPERATION
Write Enable and Disable
The CAT25C01/02/04/08/16 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 25067-00 5/00
6
Advanced Information
CAT25C01/02/04/08/16
WRITE Sequence
Byte Write
The CAT25C01/02/04/08/16 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C01/02/04/08/16.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C01/02/04/08/16. The CS must be brought high
after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately
after the WREN instruction without CS being brought
high, the data will not be written to the array because the
write enable latch will not have been properly set. Also,
for a successful write operation the address of the
memory location(s) to be programmed must be outside
the protected address field location selected by the
block protection level.
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits) and 8-bit address
for 25C01/02/04 (for the 25C04, bit 3 of the read data
instructioncontainsaddressA8). Programmingwillstart
after the CS is brought high. Figure 6 illustrates byte
write sequence.
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) – – – –
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
1
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 25067-00 5/00
7
CAT25C01/02/04/08/16
Advanced Information
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
remain constant.The only restriction is that the X (X=16
for 25C01/02/04 and X=32 for 25C08/16) bytes must
reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “rollover”tothefirstaddressofthepageand
overwrite any data that may have been written. The
CAT25C01/02/04/08/16 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C01/02/04/08/16 features page write capa-
bility. Aftertheinitialbyte, thehostmaycontinuetowrite
up to 16 bytes of data to the CAT25C01/02/04 and 32
bytes of data for 25C08/16. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address will
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 25067-00 5/00
8
Advanced Information
CAT25C01/02/04/08/16
DESIGN CONSIDERATIONS
after the proper number of clock cycles to start an
internal write cycle. Access to the array during an
internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C01/02/04/08/16, and the serial output
pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again.
The CAT25C01/02/04/08/16 powers up in a write
disable state and in a low power standby mode. A
WREN instruction must be issued to perform any writes
to the device after power up. Also,on power up CS
should be brought low to enter a ready state and
receive an instruction. After a successful byte/page
write or status register write, the CAT25C01/02/04/08/
16 goes into a write disable mode. CS must be set high
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
Data Data
Byte 2 Byte 3
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
0
0
1
0
ADDRESS
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
t
CSH
WP
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 25067-00 5/00
9
CAT25C01/02/04/08/16
ORDERING INFORMATION
Advanced Information
Prefix
Device #
Suffix
-1.8
25C16
CAT
TE13
I
S
Optional
Company ID
Temperature Range
Tape & Reel
Product
Number
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)2
TE13: 2000/Reel
25C16: 16K
25C08: 8K
25C04: 4K
25C02: 2K
25C01: 1K
Package
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
P = 8-pin PDIP
R = 8-pin MSOP3
S = 8-pin SOIC
U = 8-pin TSSOP
U14 = 14-pin TSSOP
Notes:
(1) The device used in the above example is a 25C16SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) -40°C to 125°C is available upon request
(3) CAT25C01, CAT25C02 only
Doc. No. 25067-00 5/00
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