CAT25C04LI-1.8TE13 [CATALYST]
1K/2K/4K SPI Serial CMOS EEPROM; 1K / 2K / 4K SPI串行EEPROM CMOS
| 型号： | CAT25C04LI-1.8TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1K/2K/4K SPI Serial CMOS EEPROM |
| 文件： | 总15页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25C01, CAT25C02, CAT25C04
1K/2K/4K SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
I 10 MHz SPI compatible
The CAT25C01/02/04 is a 1K/2K/4K Bit SPI Serial
CMOS EEPROM internally organized as 128x8/256x8/
512x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25C01/02/04 features a 16-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C01/
02/04 is designed with software and hardware write
protectionfeaturesincludingBlockWriteprotection.The
device is available in 8-pin DIP, 8-pin SOIC and 8-pin
TSSOP packages.
I 1.8 to 5.5 volt operation
I 16-byte page write buffer
I Hardware and software protection
I Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
I Low power CMOS technology
I SPI modes (0,0 & 1,1)
I Industrial temperature range
I 1,000,000 program/erase cycles
I 100 year data retention
I Self-timed write cycle
I RoHS compliant “
” & “
”
8-pin PDIP, SOIC and TSSOP packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (V)
TSSOP (Y)
V
CC
CS
1
8
V
CC
SI
CS
SO
2
3
4
7
6
5
HOLD
SCK
SI
CAT25C01
CAT25C02
CAT25C04
WP
WP
SO
V
SS
HOLD
SCK
PIN FUNCTIONS
Pin Name
SO
Function
V
SS
Serial Data Output
Serial Clock
SCK
WP
Write Protect
VCC
+1.8V to +5.5V Power Supply
Ground
VSS
CS
Chip Select
SI
Serial Data Input
Suspends Serial Input
HOLD
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
1
CAT25C01, CAT25C02, CAT25C04
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground(1)
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(2)
Symbol
NEND(*)
TDR
Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
Endurance
Data Retention
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
ICC
Parameter
Test Conditions
Min
Max
1
Units
mA
Supply Current
Standby Current
Read or Write at 5 MHz
ISB
All I/O Pins at GND or VCC
CS = VCC
,
2
µA
IL
I/O Pin Leakage
Pin at GND or VCC
2
µA
V
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
-0.5
VCC x 0.3
VIH
VCC x 0.7 VCC + 0.5
V
VOL1
VOL2
VCC > 2.5 V, IOL = 3.0 mA
VCC > 1.8 V, IOL = 1.0 mA
0.4
0.2
V
V
PIN IMPEDANCE CHARACTERISTICS
TA = 25°C, f = 1 MHz, VCC = 5 V
Symbol
Parameter
Conditions
VIN = 0 V
Min
Max
8
Units
pF
(2)
CIN
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Low Impedance
(2)
CIN
VIN = 0 V
6
pF
ZWPL
ILWPH
VIN < 0.5 V
5
70
kΩ
WP Input High Leakage
VIN > VCC x 0.7
2
µA
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin
may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
2
CAT25C01, CAT25C02, CAT25C04
A.C. CHARACTERISTICS
SYMBOL PARAMETER
CAT25CXX-1.8
1.8V-5.5V
CAT25CXX
2.5V-5.5V 4.5V-5.5V
Test
Min.
50
Max. Min.
Max. Min. Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
20
20
75
75
DC
20
20
40
40
ns
ns
50
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
5
50
2
DC
10
50
2
MHz
ns
(1)
tRI
µs
(1)
tFI
Input Fall Time
2
2
2
µs
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
ns
ns
(4)
CL = 50pF
(note 2)
tWC
tV
5
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
250
75
40
tHO
0
0
0
tDIS
tHZ
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tWPH
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
50
50
(1)(3)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source I max/I max; C =50pF
OL
OH
L
(3)
(4)
t
t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
WC
PUW CC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
3
CAT25C01, CAT25C02, CAT25C04
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C01/02/04 supports the SPI bus data
transmissionprotocol.ThesynchronousSerialPeripheral
Interface (SPI) helps the CAT25C01/02/04 to interface
directly with many of today’s popular microcontrollers.
The CAT25C01/02/04 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25C01/02/04. During a read
cycle, data is shifted out on the falling edge of the serial
clock for SPI modes (0,0 & 1,1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
(1)
(1)
WRITE
Note:
(1) X=0 for CAT25C01, CAT25C02. X=A8 for CAT25C04.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
4
CAT25C01, CAT25C02, CAT25C04
SCK: Serial Clock
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
SCKistheserialclockpin.Thispinisusedtosynchronize
the communication between the microcontroller and the
CAT25C01/02/04. Opcodes, byte addresses, or data
presentontheSIpinarelatchedontherisingedgeofthe
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C01/
02/04 and CS high disables the CAT25C01/02/04. CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C01/
02/04 draws ZERO current in the Standby mode. A high
to low transition on CS is required prior to any sequence
beinginitiated. AlowtohightransitiononCSafteravalid
write sequence is what initiates an internal write cycle.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C01/20/40whileinthemiddleofaserialsequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during
thetimethepartispaused, andtransitionsontheSIpins
will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held
highanytimethisfunctionisnotbeingused.) HOLDmay
be tied high directly to VCC or tied to VCC through a
resistor. Figure 9 illustrates hold timing sequence.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
STATUS REGISTER
7
6
1
5
1
4
1
3
2
1
0
WPEN
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
None
Protection
BP1
0
BP0
0
No Protection
0
1
CAT25C01: 60-7F
CAT25C02: C0-FF
CAT25C04: 180-1FF
CAT25C01: 40-7F
CAT25C02: 80-FF
CAT25C04: 100-1FF
CAT25C01: 00-7F
CAT25C02: 00-FF
CAT25C04: 000-1FF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
0
1
1
X
X
X
1
0
1
0
1
Writable
Low
Low
High
High
Protected
Protected
Protected
Writable
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
5
CAT25C01, CAT25C02, CAT25C04
STATUS REGISTER
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C01/
02/04 is busy with a write operation. When set to 1 a
write cycle is in progress and when set to 0 the device
indicatesitisready. Thisbitisreadonly. TheWEL(Write
Enable) bit indicates the status of the write enable latch.
When set to 1, the device is in a Write Enable state and
when set to 0 the device is in a Write Disable state. The
WELbitcanonlybesetbytheWRENinstructionandcan
be reset by the WRDI instruction.
DEVICE OPERATION
Write Enable and Disable
The CAT25C01/02/04 contains a write enable latch.
This latch must be set before any write operation. The
device powers up in a write disable state when VCC is
applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable writes
(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected,
the user may only read from the protected portion of the
array. These bits are non-volatile.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C01/02/04,
followed by the 8-bit address for CAT25C01/02/04 (for
theCAT25C04,bit3ofthereaddatainstructioncontains
address A8).
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
Figure 2. WREN Instruction Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)
Figure 3. WRDI Instruction Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
6
CAT25C01, CAT25C02, CAT25C04
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
atthenextaddresscanbereadsequentiallybycontinuing
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000hallowingthereadcycletobecontinuedindefinitely.
The read operation is terminated by pulling the CS high.
To read the status register, RDSR instruction should
be sent. The contents of the status register are shifted
out on the SO line. The status register may be read at
any time even during a write cycle. Read sequece is
illustratedinFigure4. Readingstatusregisterisillustrated
in Figure 5.
Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C01/02/04.
TheCSmustbebroughthighaftertheWRENinstruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
8-bit address for CAT25C01/02/04 (for the 25C04, bit 3
of the read data instruction contains address A8).
Programming will start after the CS is brought high.
Figure 6 illustrates byte write sequence.
WRITE Sequence
The CAT25C01/02/04 powers up in a Write Disable
state.Priortoanywriteinstructions,theWRENinstruction
must be sent to CAT25C01/02/04. The device goes into
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
SK
BYTE ADDRESS
A7 A6 A5 A4 A3 A2 A1 A0
OPCODE
SI
0
0
0
0
X
*
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
D7 D6 D5 D4 D3 D2 D1 D0
MSB
*Please check the instruction set table for address
X=0 for 25010, 25020 ; X=A8 for 25040
Note: Dashed line = mode (1,1)----
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
7
CAT25C01, CAT25C02, CAT25C04
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
address will remain constant. The only restriction is that
the X (X=16 for CAT25C01/02/04) bytes must reside on
the same page. If the address counter reaches the end
of the page and clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written. The CAT25C01/02/04
is automatically returned to the write disable state at the
completion of the write cycle. Figure 8 illustrates the
page write sequence.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.
Page Write
The CAT25C01/02/04 features page write capability.
After the initial byte, the host may continue to write up to
16 bytes of data to the CAT25C01/02/04. After each
byte of data received, lower order address bits are
internally incremented by one; the high order bits of
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
13 14 15 16 17 18 19 20 21 22 23
SK
SI
OPCODE
BYTE ADDRESS
DATA IN
X*
D7 D6 D5 D4 D3 D2 D1 D0
A0
0
0
0
0
0
1
0
A7
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
*X=0 for 25010, 25020 ; X=A8 for 25040
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
8
CAT25C01, CAT25C02, CAT25C04
DESIGN CONSIDERATIONS
ming is continued. On power up, SO is in a high
impedance. Ifaninvalidopcodeisreceived, nodatawill
be shifted into the CAT25C01/02/04, and the serial
output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again.
TheCAT25C01/02/04powersupinawritedisablestate
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write, the
CAT25C01/02/04 goes into a write disable mode. CS
must be set high after the proper number of clock cycles
to start an internal write cycle. Access to the array
during an internal write cycle is ignored and program-
Whenpoweringdown, thesupplyshouldbetakendown
to 0V, so that the CAT25C01/02/04 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C01/02/04
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
Figure 8. Page Write Instruction Timing
CS
16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1
0
1
2
3
4
5
6
7
8
13 14 15 16-23 24-31
SK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS
A7 A0
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
X*
0
1
0
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – – *X=0 for CAT25C01, CAT25C02; X=A8 for CAT25C04
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
t
HZ
HIGH IMPEDANCE
SO
t
LZ
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line= mode (1, 1) – – – – –
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
9
CAT25C01, CAT25C02, CAT25C04
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
0.120
0.015
0.115
0.014
0.045
0.355
0.300
0.300
0.240
0.210
0.130
0.018
0.060
0.365
0.195
0.022
0.070
0.400
0.325
0.325
0.280
b2
D
D2
E
0.310
0.250
E1
e
0.100 BSC
eB
L
0.430
0.150
0.115
0.130
24C02_8-LEAD_DIP_(300P).eps
Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
10
CAT25C01, CAT25C02, CAT25C04
8-LEAD 150 MIL WIDE SOIC (V)
E1
E
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
A1
A2
b
0.0040
0.0532
0.013
0.0098
0.0688
0.020
C
0.0075
0.1890
02284
0.149
0.0098
0.1968
0.2440
0.1574
D
E
E1
e
0.050 BSC
f
0.0099
0.0196
24C02_8-LEAD_SOIC.eps
θ1
0°
8°
Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
11
CAT25C01, CAT25C02, CAT25C04
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ1
Notes:
1. All dimensions in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
12
CAT25C01, CAT25C02, CAT25C04
ORDERING INFORMATION
Prefix
Device #
Suffix
-1.8
25C04
CAT
TE13
I
V
Optional
Company ID
Temperature Range
I = Industrial (-40°C to +85°C)
Tape & Reel
Product
Number
25C04: 4K
25C02: 2K
25C01: 1K
Package
L: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
V: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
Y: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Operating Voltage
Blank (VCC = 2.5V to 5.5V)
1.8 (VCC = 1.8V to 5.5V)
Notes:
(1) The device used in the above example is a CAT25C04VI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
13
CAT25C01, CAT25C02, CAT25C04
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
VV
VV
25C04LI
25C04VI
YYWWC
YYWWC
CSI = Catalyst Semiconductor, Inc.
25C04L = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
C = Product Revision
VV = Voltage Range
CSI = Catalyst Semiconductor, Inc.
25C04V = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
C = Product Revision
VV = Voltage Range
1.8V - 5.5V = 18
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
2.5V - 5.5V = Blank
8-Lead TSSOP
YMCV
25Y04
Y = Production Year
M = Production Month
C = Die Revision
25Y04 = Device Code
I = Industrial Temperature Range
V = Voltage Range
1.8V - 5.5V = 8
2.5V - 5.5V = Blank
Notes:
(1) The circle on the package marking indicates the location of Pin 1.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1105, Rev. B
14
REVISION HISTORY
Date
Rev.
Reason
10/13/05
A
Initial Issue
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Publication #: 1105
Phone: 408.542.1000
Revison:
B
Fax: 408.542.1200
Issue date:
12/23/05
www.catalyst-semiconductor.com
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