CAT25C02SE-1.8TE13 [CATALYST]
EEPROM, 256X8, Serial, CMOS, PDSO8, SOIC-8;
| 型号： | CAT25C02SE-1.8TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDSO8, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT25C01/02/04/08/16
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
TM
FEATURES
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Self-timed write cycle
■ 10 MHz SPI compatible
■ 1.8 to 6.0 volt operation
■ Hardware and software protection
■ Low power CMOS technology
■ SPI modes (0,0 & 1,1)*
■ 8-pin DIP/SOIC, 8/14-pin TSSOP and 8-pin MSOP
■ 16/32-byte page write buffer
■ Block write protection
■ Commercial, industrial, automotive and
– Protect 1/4, 1/2 or all of EEPROM array
extended temperature ranges
DESCRIPTION
input (SCK), data in (SI) and data out (SO) are required
to access the device. The HOLD pin may be used to
suspend any serial communication without resetting the
serialsequence.TheCAT25C01/02/04/08/16isdesigned
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/14-pin
TSSOP packages.
The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit
SPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces
device power requirements. The CAT25C01/02/04
features a 16-byte page write buffer. The 25C08/16
featuresa32-bytepagewritebuffer.Thedeviceoperates
via the SPI bus serial interface and is enabled though a
ChipSelect(CS).InadditiontotheChipSelect,theclock
PIN CONFIGURATION
TSSOP Package (U14, Y14)
SOIC Package (S, V)
DIP Package (P, L)
TSSOP Package (U, Y)
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SO
NC
NC
V
CC
HOLD
1
2
3
4
8
7
6
5
V
CS
SO
V
CS
SO
CS
SO
WP
V
CC
CC
CC
HOLD
SCK
SI
HOLD
SCL
SI
HOLD
SCK
SI
NC
WP
WP
NC
V
SS
V
SS
V
SS
NC
NC
WP
SCK
SI
V
BLOCK DIAGRAM
SS
8
MSOP Package (R, Z)*
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
8
7
6
5
CS
SO
WP
V
CC
HOLD
SCK
V
SI
SS
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
*CAT25C01/02 only
PIN FUNCTIONS
Pin Name
SO
Function
SO
SI
I/O
CONTROL
Serial Data Output
Serial Clock
E2PROM
ARRAY
CS
SCK
WP
SPI
CONTROL
LOGIC
XDEC
WP
HOLD
SCK
Write Protect
VCC
+1.8V to +6.0V Power Supply
Ground
BLOCK
PROTECT
LOGIC
VSS
CS
Chip Select
DATA IN
STORAGE
SI
Serial Data Input
Suspends Serial Input
No Connect
HOLD
NC
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
*Other SPI modes available on request.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. N
1
CAT25C01/02/04/08/16
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
3
1
mA
VCC = 5.5V
FCLK = 5MHz
(6)
ISB
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(5)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(5)
VIH
VCC x 0.7
VOL1
VOH1
2.7V≤V <5.5V
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) V
and V
are reference values only and are not tested.
ILMIN
IHMAX
(6) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
Doc. No. 1016, Rev. N
2
CAT25C01/02/04/08/16
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
VOUT=0V
VIN=0V
Output Capacitance (SO)
8
6
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Limits
1.8V-6.0V
Min.
2.5V-6.0V
4.5V-5.5V
Test
Max. Min.
Max. Min. Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
50
50
20
20
75
75
DC
20
20
40
40
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
250
250
DC
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
5
50
2
DC
10
50
2
(1)
tRI
(1)
tFI
Input Fall Time
2
2
2
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
40
40
CL = 50pF
(3)
tWC
tV
10
5
5
(2)
250
75
40
tHO
0
0
0
tDIS
tHZ
250
150
75
50
75
50
tCS
500
500
500
150
150
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tWPH
NOTE:
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
50
50
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C = 50pF
L
(3)
t
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
WC
Doc. No. 1016, Rev. N
3
CAT25C01/02/04/08/16
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25C01/02/04/08/16 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C01/02/04/08/16 to
interface directly with many of today’s popular
microcontrollers. The CAT25C01/02/04/08/16 contains
an8-bitinstructionregister. (Theinstructionset andthe
operation codes are detailed in the instruction set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C01/02/04/08/16. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C01/02/04/08/16. During a
read cycle, data is shifted out on the falling edge of the
serial clock for SPI modes (0,0 & 1,1).
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
(1)
(1)
WRITE
(2)(3)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Note:
(1) X=0 for 25C01, 25C02, 25C08, 25C16. X=A8 for 25C04
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1016, Rev. N
4
CAT25C01/02/04/08/16
and the 25C01/02/04/08/16. Opcodes, byte addresses,
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK for SPI modes (0,0 & 1,1) .
04/08/16. CS high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway) The
CAT25C01/02/04/08/16 draws ZERO current in the
Standbymode. Ahightolow transitiononCSisrequired
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what
initiates an internal write cycle.
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C01/
02/04/08/16 and CS high disables the CAT25C01/02/
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25C01
CAT25C02
CAT25C04
CAT25C08
CAT25C16
A6 - A0
A7
—
8
8
A7 - A0
A7 - A0 (A8 = X bit from Opcode)
A9 - A0
—
8
A15 - A10
A15 - A11
16
16
A10 - A0
STATUS REGISTER
7
6
0
5
1
4
3
2
1
0
WPEN
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
None
Protection
BP1
0
BP0
0
No Protection
0
1
25C01: 60-7F
25C02: C0-FF
25C04: 180-1FF
25C08: 0300-03FF
25C16: 0600-07FF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25C01: 40-7F
25C02: 80-FF
25C04: 100-1FF
25C08: 0200-03FF
25C16: 0400-07FF
25C01: 00-7F
25C02: 00-FF
25C04: 000-1FF
25C08: 0000-03FF
25C16: 0000-07FF
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
0
1
X
1
0
1
0
1
Low
Low
High
High
Protected
Protected
Protected
Writable
1
X
X
Doc. No. 1016, Rev. N
5
CAT25C01/02/04/08/16
WP: Write Protect
STATUS REGISTER
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
The Status Register indicates the status of the device.
TheRDY(Ready)bitindicateswhethertheCAT25C01/
02/04/08/16 is busy with a write operation. When set to
1 a write cycle is in progress and when set to 0 the
device indicates it is ready. This bit is read only. The
WEL (Write Enable) bit indicates the status of the write
enable latch. When set to 1, the device is in a Write
Enable state and when set to 0 the device is in a Write
Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
HOLD: Hold
The BP0 and BP1 (Block Protect) bits indicate which
blocksarecurrentlyprotected. Thesebitsaresetbythe
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
theentirememorybysettingthesebits. Onceprotected
the user may only read from the protected portion of the
array. These bits are non-volatile.
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C01/02/04/08/16 while in the
middleofaserialsequencewithouthavingtore-transmit
entiresequenceatalatertime.Topause,HOLDmustbe
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,HOLDisbroughthigh,whileSCKislow.
HOLD should be held high any time this function is not
being used. HOLD may be tied high directly to VCC or
tied to VCC through a resistor. Figure 9 illustrates hold
timing sequence.
The WPEN (Write Protect Enable) is an enable bit for
the WP pin. The WP pin and WPEN bit in the status
register control the programmable hardware write pro-
tectfeature. Hardwarewriteprotectionisenabledwhen
WP is lowandWPENbitissettohigh. Theusercannot
write to the status register, (including the block protect
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. N
6
CAT25C01/02/04/08/16
bits and the WPEN bit) and the block protected sections
in the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefi-
nitely.ThereadoperationisterminatedbypullingtheCS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle. Read
sequeceisillustratedinFigure4. Readingstatusregister
is illustrated in Figure 5.
DEVICE OPERATION
Write Enable and Disable
The CAT25C01/02/04/08/16 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable
writes(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
WRITE Sequence
The CAT25C01/02/04/08/16 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C01/02/04/08/16.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C01/02/04/08/16. The CS must be brought high
after the WREN instruction to enable writes to the
device.Ifthewriteoperationisinitiatedimmediatelyafter
the WREN instruction without CS being brought high,
the data will not be written to the array because the write
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the
protected address field location selected by the block
protection level.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instructionistransmittedtotheCAT25C01/02/04/08/16,
followed by the 16-bit address for 25C08/16. (only 10-bit
addresses are used for 25C08, 11-bit addresses are
used for 25C16. The rest of the bits are don't care bits)
and 8-bit address for 25C01/02/04 (for the 25C04, bit 3
of the read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
Figure 4. Read Instruction Timing
CS
*
*
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
A
N
A
0
SI
0
0
0
0
X*
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the Byte Address Table.
*X = 0 for CAT25C01, CAT25C02, CAT25C08 and CAT25C16; X = A8 for CAT25C04
Note: Dashed Line= mode (1, 1) – – – –
Doc. No. 1016, Rev. N
7
CAT25C01/02/04/08/16
Byte Write
bility. After the initial byte, the host may continue to write
up to 16 bytes of data to the CAT25C01/02/04 and 32
bytes of data for 25C08/16. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address will
remain constant.The only restriction is that the X (X=16
for 25C01/02/04 and X=32 for 25C08/16) bytes must
reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “rollover”tothefirstaddressofthepageand
overwrite any data that may have been written. The
CAT25C01/02/04/08/16 is automatically returned to the
write disable state at the completion of the write cycle.
Figure 8 illustrates the page write sequence.
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08/16. (only 10-bit addresses are
used for 25C08, 11-bit addresses are used for 25C16.
The rest of the bits are don't care bits) and 8-bit address
for 25C01/02/04 (for the 25C04, bit 3 of the read data
instruction contains address A8). Programming will
startaftertheCSisbroughthigh.Figure6illustratesbyte
write sequence. During an internal write cycle, all
commands will be ignored except the RDSR (Read
Status Register) instruction.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Page Write
The CAT25C01/02/04/08/16 features page write capa-
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) – – – – –
Figure 6. Write Instruction Timing
CS
*
*
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
BYTE ADDRESS*
A
DATA IN
A
N
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
X*
0
1
0
HIGH IMPEDANCE
SO
*Please check the Byte Address Table
X = 0 for CAT25C01, CAT25C02 and CAT25C08, CAT25C16; X = A8 for CAT25C04.
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. N
8
CAT25C01/02/04/08/16
DESIGN CONSIDERATIONS
The CAT25C01/02/04/08/16 powers up in a write
disable state and in a low power standby mode. A
WREN instruction must be issued to perform any writes
to the device after power up. Also,on power up CS
should be brought low to enter a ready state and
receive an instruction. After a successful byte/page
write or status register write, the CAT25C01/02/04/08/
16 goes into a write disable mode. CS must be set high
after the proper number of clock cycles to start an
internal write cycle. Access to the array during an
internal write cycle is ignored and programming is
continued. On power up, SO is in a high impedance. If
an invalid op code is received, no data will be shifted
into the CAT25C01/02/04/08/16, and the serial output
pin (SO) will remain in a high impedance state until the
falling edge of CS is detected again.
Whenpoweringdown,thesupplyshouldbetakendown
to 0V, so that the CAT25C01/02/04/08/16 will be reset
when power is ramped back up. If this is not possible,
then, following a brown-out episode, the CAT25C01/
02/04/08/16 can be reset by refreshing the contents of
the Status Register (See Application Note AN10).
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) – – – – –
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
BYTE ADDRESS*
A
OPCODE
Data
Byte 1
Data
Data
Data Byte N
A
N
0
0
0
0
X*
0
1
0
0
0
Byte 2 Byte 3
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table.
*X = 0 for CAT25C01, CAT25C02, CAT25C08 and CAT25C16; X = A8 for CAT25C04.
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. N
9
CAT25C01/02/04/08/16
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) – – – – –
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
t
CSH
WP
Note: Dashed Line= mode (1, 1) – – – – –
Doc. No. 1016, Rev. N
10
CAT25C01/02/04/08/16
ORDERING INFORMATION
Prefix
Device #
Suffix
-1.8
25C16
CAT
TE13
I
S
Optional
Company ID
Temperature Range
Tape & Reel
TE13: 2000/Reel
Product
Number
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
E = Extended (-40°C to +125°C)
25C16: 16K
25C08: 8K
25C04: 4K
25C02: 2K
25C01: 1K
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
Package
P = 8-pin PDIP
R = 8-pin MSOP2
S = 8-pin SOIC
U = 8-pin TSSOP
U14 = 14-pin TSSOP
L = 8-pin PDIP (Lead free, Halogen free)
Z = 8-pin MSOP2 (Lead free, Halogen free)
V = 8-pin SOIC, JEDEC (Lead free, Halogen free)
Y = 8-pin TSSOP (Lead free, Halogen free)
Y14 = 8-pin TSSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 25C16SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
(2) CAT25C01, CAT25C02 only
REVISION HISTORY
Date
Rev.
Reason
8/3/2004
M
Updated Features
Updated DC Operating Characteristics table & notes
02/01/2005
N
Update Ordering Information
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Publication #: 1016
Revison:
N
Issue date:
02/01/05
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