CAT25320VI-1.8-GT3 [CATALYST]
EEPROM, 4KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, MS-012, SOIC-8;
| 型号： | CAT25320VI-1.8-GT3 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 4KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, MS-012, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25320
32K-Bit SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
I 10 MHz SPI compatible
I 1.8 to 5.5 volt operation
I Hardware and software protection
I Low power CMOS technology
I SPI modes (0,0 &1,1)
The CAT25320 is a 32K-Bit SPI Serial CMOS EEPROM
internally organized as 4Kx8 bits. Catalyst’s advanced
CMOS Technology substantially reduces device power
requirements. The CAT25320 features a 64-byte page
write buffer. The device operates via the SPI bus serial
interface and is enabled though a Chip Select (CS). In
addition to the Chip Select, the clock input (SCK), data
in (SI) and data out (SO) are required to access the
device. The HOLD pin may be used to suspend any
serial communication without resetting the serial se-
quence. The CAT25320 is designed with software and
hardware write protection features including Block write
protection. The device is available in 8-pin DIP, SOIC
and TSSOP packages.
I Industrial temperature range
I 1,000,000 program/erase cycles
I 100 year data tetention
I Self-timed write cycle
I RoHS compliant “
” & “
”
8-pin PDIP and 8-pin SOIC packages
I 64-Byte page write buffer
I Block write protection
– Protect 1/4, 1/2 or all of EEPROM array
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (V)
TSSOP (Y)
V
CC
CS
1
8
V
CC
SI
CS
SO
2
3
4
7
6
5
HOLD
SCK
SI
WP
CAT25320
V
SS
WP
SO
HOLD
SCK
PIN FUNCTIONS
Pin Name
Function
V
SS
SO
Serial Data Output
Serial Clock
SCK
WP
VCC
VSS
CS
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
SI
Serial Data Input
Suspends Serial Input
HOLD
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1109, Rev. B
1
CAT25320
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground(1)
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(2)
Symbol
NEND(*)
TDR
Parameter
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
Endurance
Data Retention
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
V
CC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
Max
Units
ICC
ISB1
ISB2
Supply Current
Read, Write, VCC = 5.0V, fSCK = 10MHz,
SO open
2
mA
Standby Current
Standby Current
Input Leakage Current
VIN = GND or VCC , CS = VCC , WP = VCC
VCC = 5V
,
2
4
µA
µA
VIN = GND or VCC , CS = VCC , WP = GND,
VCC = 5V
IL
VIN = GND or VCC
-2
-1
2
1
µA
µA
V
ILO
Output Leakage Current CS = VCC , VOUT = GND or VCC
Input Low Voltage
(3)
VIL
VIH
-0.5
0.3VCC
(3)
Input High Voltage
0.7VCC VCC + 0.5
V
VOL1
VOH1
VOL2
VOH2
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VCC > 2.5V, IOL = 3.0mA
VCC > 2.5V, IOH = -1.6mA
VCC > 1.8V, IOL = 150µA
VCC > 1.8V, IOH = -100µA
0.4
VCC - 0.8V
0.2
V
V
V
VCC - 0.2V
V
PIN CAPACITANCE(2)
TA = 25°C, f = 1 MHz, VCC = 5V
Symbol
Test Conditions
Max
Units
Conditions
VOUT = 0 V
VIN = 0 V
COUT
Output Capacitance (SO)
8
pF
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
(1) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(3) VIL and VIH are reference values and are not tested.
© 2006 by Catalyst Semiconductor, Inc.
Doc. No. 1111, Rev. B
2
Characteristics subject to change without notice
CAT25320
A.C. CHARACTERISTICS
SYMBOL PARAMETER
CAT250XX-1.8
1.8V-5.5V
CAT250XX
2.5V-5.5V
Test
Min.
Max.
Min.
Max.
Conditions UNITS
tSU
tH
Data Setup Time
Data Hold Time
30
30
75
75
DC
20
20
40
40
DC
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
5
50
2
10
50
2
MHz
ns
(1)
tRI
µs
(1)
tFI
Input Fall Time
2
2
µs
tHD
tCD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
0
0
ns
10
10
ns
(4)
CL = 50pf
tWC
tV
5
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
75
40
tHO
0
0
tDIS
tHZ
50
20
25
100
tCS
50
50
50
10
10
15
15
15
10
10
tCSS
tCSH
tWPS
tWPH
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
(1)(3)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V to 0.7V
CC
CC
Input rise and fall times: ≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C =50pF
L
(3)
(4)
t
t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
WC
PUW CC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1111, Rev. B
3
CAT25320
FUNCTIONAL DESCRIPTION
PIN DESCRIPTION
The CAT25320 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT25320 to interface directly with
manyoftoday’spopularmicrocontrollers.TheCAT25320
contains an 8-bit instruction register. (The instruction
set andtheoperationcodesaredetailedintheinstruction
set table)
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25320.Inputdataislatchedontherisingedgeofthe
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25320. During a read cycle,
data is shifted out on the falling edge of the serial clock.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
SCK: Serial Clock
SCKistheserialclockpin.Thispinisusedtosynchronize
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
H
t
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
Enable Write Operations
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
WRITE
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
4
CAT25320
the communication between the microcontroller and the
CAT25320. Opcodes, byte addresses, or data present
on the SI pin are latched on the rising edge of the SCK.
Data on the SO pin is updated on the falling edge of the
SCK.
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0. Figure 10 illustrates the WP timing
sequence during a write operation.
CS: Chip Select
CS istheChipselectpin. CSlowenablestheCAT25320
and CS high disables the CAT25320. CS high takes the
SO output pin to high impedance and forces the devices
into a Standby Mode (unless an internal write operation
is underway). A high to low transition on CS is required
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what
initiates an internal write cycle.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25320 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
islow.TheSOpinisinahighimpedancestateduringthe
timethepartispaused, andtransitionsontheSIpinswill
beignored.Toresumecommunication,HOLDisbrought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
BP0
0
0
1
1
0
1
0
1
None
No Protection
0C00-0FFF
800-0FFF
0000-0FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
Protected
Blocks
Unprotected
Blocks
Status
WPEN
WP
X
WEL
Register
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1111, Rev. B
5
CAT25320
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
controltheprogrammablehardwarewriteprotectfeature.
HardwarewriteprotectionisenabledwhenWPis lowand
WPENbitissettohigh.Theusercannotwritetothestatus
register (including the block protect bits and the WPEN
bit) and the block protected sections in the memory array
when the chip is hardware write protected. Only the
sections of the memory array that are not block protected
can be written. Hardware write protection is disabled
when either WP pin is high or the WPEN bit is zero.
STATUS REGISTER
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25320
is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
write enable latch . When set to 1, the device is in a
Write Enable state and when set to 0 the device is in a
Write Disable state. The WEL bit can only be set by the
WREN instruction and can be reset by the WRDI
instruction.
DEVICE OPERATION
Write Enable and Disable
The BP0 and BP1 (Block Protect) bits indicate which
blocksarecurrentlyprotected. Thesebitsaresetbythe
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
theentirememorybysettingthesebits. Onceprotected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The CAT25320 contains a write enable latch. This latch
must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to
thedevice. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
Figure 2. WREN Instruction Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) — — — —
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
6
CAT25320
READ Sequence
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Reading status register
is illustrated in Figure 5.
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25320, followed by
the16-bitaddress(thefourmostsignificantbitsaredon't
care).
WRITE Sequence
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address, FFFh is reached, the address counter rolls
over to 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by pulling
the CS high. Read sequece is illustrated in Figure 4.
The CAT25320 powers up in a Write Disable state. Prior
to any write instructions, the WREN instruction must be
sent to CAT25320. The device goes into Write enable
state by pulling the CS low and then clocking the WREN
instruction into CAT25320. The CS must be brought
high after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately
after the WREN instruction without CS being brought
high, the data will not be written to the array because the
write enable latch will not have been properly set. Also,
for a successful write operation the address of the
memory location(s) to be programmed must be outside
the protected address field location selected by the
block protection level.
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
ADDRESS
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1111, Rev. B
7
CAT25320
Byte Write
address will remain constant. The only restriction is that the
64 bytes must reside on the same page. If the address
counter reaches the end of the page and clock continues,
the counter will “roll over” to the first address of the page
and overwrite any data that may have been written. The
CAT25320 is automatically returned to the write disable
state at the completion of the write cycle. Figure 8 illustrates
the page write sequence.
Once the device is in a Write Enable state, the user
may proceed with a write sequence by setting the CS
low, issuing a write instruction via the SI line, followed
by the 16-bit address (four most significant bits are
don't care), and then the data to be written. Program-
ming will start after the CS is brought high. Figure 6
illustrates byte write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
Status Register Write
To write to the status register, the WRSR instruction should
be sent. Only Bit 2, Bit 3 and Bit 7 of the status register can
be written using the WRSR instruction. Figure 7 illustrates
the sequence of writing to status register.
The Status Register can be read to determine if the
write cycle is still in progress. If Bit 0 of the Status
Register is set at 1, write cycle is in progress. If Bit 0
is set at 0, the device is ready for the next instruction.
DESIGN CONSIDERATIONS
The CAT25320 powers up in a write disable state and in a
low power standby mode. A WREN instruction must be
issued to perform any writes to the device after power up.
After power up CS must be brought low to enter a ready
state and receive an instruction. After a successful byte/
page write or status register write the CAT25320 goes into
Page Write
The CAT25320 features page write capability. After
the first initial byte the host may continue to write up
to 64 bytes of data to the CAT25320. After each byte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) — — — —
Figure 7. WRSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
8
7
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) — — — —
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
8
CAT25320
a write disable mode. CS must be set high after the proper If an invalid code is received, no data will be shifted into
number of clock cycles to start an internal write cycle. the CAT25320 and the serial output pin (SO) will remain
Access to the array during an internal write cycle is in a high impedance state until the falling edge of CS is
ignored and programming iscontinued. Onpowerup, SO detected again.
is in a high impedance.
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SCK
SI
DATA IN
Data Data
Byte 2 Byte 3
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
0
0
1
0
ADDRESS
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) — — — —
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line = mode (1, 1) — — — —
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
t
CSH
WP
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1111, Rev. B
9
CAT25320
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
0.120
0.015
0.115
0.014
0.045
0.355
0.300
0.300
0.240
0.210
0.130
0.018
0.060
0.365
0.195
0.022
0.070
0.400
0.325
0.325
0.280
b2
D
D2
E
0.310
0.250
E1
e
0.100 BSC
eB
L
0.430
0.150
0.115
0.130
Notes:
1. Complies with JEDEC Standard MS001.
2. All dimensions are in inches.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
10
CAT25320
8-LEAD 150 MIL WIDE SOIC (V)
E1
E
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
NOM
MAX
A1
A2
b
0.0040
0.0532
0.013
0.0098
0.0688
0.020
C
0.0075
0.1890
02284
0.149
0.0098
0.1968
0.2440
0.1574
D
E
E1
e
0.050 BSC
f
0.0099
0.0196
θ1
0°
8°
Notes:
1. Complies with JEDEC specification MS-012 dimensions.
2. All linear dimensions in millimeters.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1111, Rev. B
11
CAT25320
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
θ1
Notes:
1. All dimensions in millimeters.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
12
CAT25320
TAPE AND REEL
Direction of Feed
Device Orientation
SPROKET HOLE
TOP COVER
TAPE THICKNESS (t1)
0.10mm (0.004) MAX THICK
DEVICE ORIENTATION
EMBOSSED
CARRIER
PIN 1
PIN 1
PIN 1
EMBOSSMENT
TDFN
SOIC
TSSOP
Reel Dimensions(1)
T
40mm (1.575) MIN.
ACCESS HOLE
AT SLOT LOCATION
B*
A
D*
C
N
FULL RADIUS*
TAPE SLOT IN CORE
FOR TAPE START.
2.5mm (0.098) MIN WIDTH
10mm (0.394) MIN DEPTH
* DRIVE SPOKES OPTIONAL, IF USED
ASTERISKED DIMENSIONS APPLY.
G (MEASURED AT HUB)
Embossed Carrier Dimensions
A
TAPE
SIZE
MAX
QTY/REEL
B MIN
C
D* MIN N MIN
20.2 50
G
T MAX
330
(13.00)
1.5
(0.059)
12.80 (0.504)
12.4 (0.488) _18.4_
12MM
3000
13.20 (0.5200) (0.795) (1.969) 14.4 (0.558) (0.724)
Component/Tape Size Cross-Reference
Component
Package Type
V, Y
Tape Size (W)
Part Pitch (P)
8L SOIC, TSSOP
12mm
8mm
Notes:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1111, Rev. B
13
CAT25320
Embossed Carrier Dimensions (12 Pape Only)
10 PITCHES
CUMULATIVE TOLERANCE
ON TAPE 0.2mm( 0.008)
K
D
P
0
T
P
2
TOP
COVER
TAPE
E
(2)
A
0
F
W
(2)
B
B
0
K
1
0
P
CENTER LINES
OF CAVITY
D
1
FOR COMPONENTS
2.0mm X 1.2mm
AND LARGER
EMBOSSMENT
FOR MACHINE REFERENCE ONLY
INCLUDING DRAFT AND RADII
USER DIRECTION OF FEED
CONCENTRIC ABOUT B
0
Embossed Tape—Constant Dimensions(1)
Tape Sizes
D
E
P0
T Max.
D1 Min.
A0 B0 K0(2)
1.5 (0.059)
1.6 (0.063)
1.65 (0.065)
1.85 (0.073)
3.9 (0.153)
4.1 (0.161)
400
(0.016)
1.5
(0.059)
12mm
Embossed Tape—Variable Dimensions(1)
Tape Sizes
B1 Max.
F
K Max.
P2
R Min.
W
P
8.2
5.45 (0.0215)
4.5
(0.177)
1.95 (0.077)
2.05 (0.081)
30
(1.181)
11.7 (0.460) 7.9 (0.275)
12.3 (0.484) 8.1 (0.355)
12mm
(0.0323) 5.55 (0.0219)
Note:
(1) Metric dimensions will govern; English measurements rounded, for reference only and in parentheses.
(2) A B K are determined by component size. The clearance between the component and the cavity must be within 0.05 (0.002) min. to
0
0
0
0.65 (0.026) max. for 12mm tape, 0.05 (0.002) min. to 0.90 (0.035) max. for 16mm tape, and 0.05 (0.002) min. to 1.00 (0.039) max. for
24mm tape and larger. The component cannot rotate more than 20° within the determined cavity, see Component Rotation.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
14
CAT25320
Prefix
Device #
25320
Suffix
-1.8
V
CAT
– GT3
I
Temperature Range
I = Industrial (-40°C to +85°C)
Optional
Company ID
Product
Number
Operating Voltage
Blank = 2.5V to 5.5V
1.8 = 1.8V to 5.5V
Package
L: PDIP (Lead free, Halogen free)
V: SOIC, JEDEC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Lead Finish/Tape & Reel
G: NiPdAu Lead Plating
T: Tape & Reel
3: 3000/Reel
Notes:
(1) The device used in the above example is a CAT25320VI-1.8GT3 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
© 2006 by Catalyst Semiconductor, Inc.
Doc No. 1111, Rev. B
15
Characteristics subject to change without notice
CAT25320
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
VV
25320LI
YYWWB
VV
25320VI
YYWWB
CSI = Catalyst Semiconductor, Inc.
VV = Voltage Range
CSI = Catalyst Semiconductor, Inc.
VV = Voltage Range
1.8V - 5.5V = 18
1.8V - 5.5V = 18
2.5V - 5.5V = Blank
2.5V - 5.5V = Blank
25320L = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
B = Product Revision
25320V = Device Code
I = Temperature Range
YY = Production Year
WW = Production Week
B = Product Revision
8-Lead TSSOP
YMBV
25320I
Y = Production Year
M = Production Month
B = Die Revision
25320 = Device Code
I = Industrial Temperature Range
V = Voltage Range
1.8V - 5.5V = 8
2.5V - 5.5V = Blank
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1111, Rev. B
16
REVISION HISTORY
Date
Rev.
A
Reason
12/20/05
03/21/06
Initial Issue
B
Update D.C. Operating Characteristics
Update A.C. Characteristics
Update Pin Description
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1111
Revison:
B
Issue date:
03/21/06
相关型号：
CAT25320VI-GT3C
4K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8
ONSEMI
CAT25320VI-T3C
4K X 8 SPI BUS SERIAL EEPROM, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOIC-8
ONSEMI
CAT25320VP2EGT3
IC 4K X 8 SPI BUS SERIAL EEPROM, PDSO8, 2 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-229, TDFN-8, Programmable ROM
ONSEMI
©2020 ICPDF网 联系我们和版权申明