CAT24WC12833KITE13 [CATALYST]
128K-Bit I2C Serial CMOS EEPROM; 128K位I2C串行EEPROM CMOS
| 型号： | CAT24WC12833KITE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 128K-Bit I2C Serial CMOS EEPROM |
| 文件： | 总9页 (文件大小：405K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT24WC128
128K-Bit I2C Serial CMOS EEPROM
TM
FEATURES
I 1MHz I2C Bus Compatible*
I Write Protect Feature
– Entire Array Protected When WP at VIH
I 100,000 Program/Erase Cycles
I 100 Year Data Retention
I 1.8 to 6 Volt Operation
I Low Power CMOS Technology
I 64-Byte Page Write Buffer
I 8-Pin DIP, 8-Pin SOIC or 14-pin TSSOP
I "Green" Package Options Available
I Self-Timed Write Cycle with Auto-Clear
I Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC128 is a 128K-bit Serial CMOS E2PROM
internally organized as 16384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
CAT24WC128 features a 64-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP
packages.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P, L)
EXTERNAL LOAD
1
2
3
4
8
7
6
5
V
NC
NC
CC
TSSOP Package (U14, Y14)
WP
SENSE AMPS
SHIFT REGISTERS
D
OUT
NC
SCL
SDA
V
1
2
3
4
5
6
14
13
12
11
10
9
NC
NC
NC
ACK
CC
V
SS
WP
NC
NC
NC
SCL
V
V
CC
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
NC
NC
NC
SOIC Package (J, W, K, X)
512
START/STOP
1
2
3
4
8
7
6
5
V
SDA
NC
NC
NC
CC
SDA
V
7
8
SS
LOGIC
WP
SCL
SDA
EEPROM
256X512
V
SS
XDEC
256
CONTROL
LOGIC
WP
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
SDA
SCL
WP
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
Write Protect
VCC
VSS
+1.8V to +6V Power Supply
Ground
SCL
STATE COUNTERS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1038, Rev. E
1
CAT24WC128
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
I
I
Power Supply Current - Read
1
mA
f
V
= 100 KHz
=5V
CC1
SCL
CC
Power Supply Current - Write
Standby Current
3
1
mA
f
= 100 KHz
=5V
CC2
SCL
V
CC
(5)
µA
V
V
= GND or V
SB
IN
CC
=5V
CC
I
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
3
3
µA
µA
V
V
= GND to V
LI
IN
CC
V
OUT
= GND to V
CC
LO
V
V
V
V
–1
x 0.7
V
x 0.3
IL
CC
Input High Voltage
V
CC
V
+ 0.5
V
IH
CC
Output Low Voltage (V
Output Low Voltage (V
= +3.0V)
= +1.8V)
0.4
0.5
V
I
I
= 3.0 mA
OL1
OL2
CC
OL
V
= 1.5 mA
CC
OL
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP)
8
6
pF
pF
(3)
CIN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
Doc. No. 1038, Rev. E
2
CAT24WC128
A.C. CHARACTERISTICS
= +1.8V to +6V, unless otherwise specified
V
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min. Max.
Min.
Max.
400
0.9
Min.
Max.
1000
0.55
Units
kHz
µs
FSCL
tAA
Clock Frequency
100
SCL Low to SDA Data Out
and ACK Out
0.1
3.5
0.05
1.2
0.05
0.5
(1)
tBUF
Time the Bus Must be Free Before 4.7
a New Transmission Can Start
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.0
0.6
1.2
0.6
0.6
0.25
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
0.4
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
0.25
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
0
ns
ns
µs
ns
µs
ns
ms
Data In Setup Time
100
100
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
1.0
0.3
0.3
(1)
tF
300
300
100
tSU:STO
tDH
4.7
0.6
50
0.25
50
100
tWR
10
10
10
(1)(2)
Power-Up Timing
Symbol
Parameter
Max.
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24WC128 supports the I2C Bus data transmis-
STOP conditions for bus access. The CAT24WC128
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
Doc. No. 1038, Rev. E
3
CAT24WC128
I2C BUS PROTOCOL
PIN DESCRIPTIONS
The features of the I2C bus protocol are defined as
follows:
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
(1) Data transfer may be initiated only when the bus
is not busy.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
WP: Write Protect
START Condition
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC128 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1038, Rev. E
4
CAT24WC128
DEVICE ADDRESSING
knowledge, the CAT24WC128 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The seven most
significant bits of the 8-bit slave address are fixed as
1010XXX (Fig. 5), where X can be a 0 or 1. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC128. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC128 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
After the Master sends a START condition and the slave
address byte, the CAT24WC128 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC128 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
Page Write
TheCAT24WC128respondswithanacknowledgeafter
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
The CAT24WC128 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24WC128 will respond with an
When the CAT24WC128 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
X
X
R/W
X
X is Don't Care, can be a '0' or a '1'.
5
Doc. No. 1038, Rev. E
CAT24WC128
protected and becomes read only. The CAT24WC128
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device’s failure to send an acknowledge
after the first byte of data is received.
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain un-
changed.
IftheMastertransmitsmorethan64bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
READ OPERATIONS
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC128 in a single write cycle.
The READ operation for the CAT24WC128 is initiated in
the same manner as the write operation with one excep-
tion, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ,Selective/RandomREADandSequentialREAD.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC128 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC128 is still busy with the
write operation, no ACK will be returned. If
CAT24WC128 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Immediate/Current Address Read
The CAT24WC128’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E=16383),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24WC128
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
WRITE PROTECTION
Selective/Random Read
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
Selective/Random READ operations allow the Master
device to select at random any memory location for a
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
15
8
7
SDA LINE
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
*
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
*=Don't Care Bit
Doc. No. 1038, Rev. E
6
CAT24WC128
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC128 acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one. The
CAT24WC128 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
data. The CAT24WC128 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operation will terminate when the Master fails to re-
spond with an acknowledge, thus sending the STOP
condition.
The data being transmitted from CAT24WC128 is out-
putted sequentially with data from address N followed
by data from address N+1. The READ operation ad-
dress counter increments all of the CAT24WC128 ad-
dress bits so that the entire memory array can be read
during one operation. If more than E (where E=16383)
bytes are read out, the counter will ‘wrap around’ and
continue to clock out data bytes.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC128 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
24WC128 F10
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
SLAVE
ADDRESS
A
DATA
15
8
7
SDA LINE
S
S
P
* *
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
*=Don't Care Bit
Doc. No. 1038, Rev. E
7
CAT24WC128
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
ORDERING INFORMATION
Prefix
Device #
24WC128
Suffix
Rev A(2)
CAT
K
-1.8
I
TE13
Temperature Range
Optional
Company ID
Product
Number
Tape & Reel
Blank = Commercial (0° - 70°C)
I = Industrial (-40° - 85°C)
A = Automotive (-40° - 105°C)*
Die Revision
Operating Voltage
Blank: 2.5V - 6.0V
1.8: 1.8V - 6.0V
Package
P: PDIP
K: SOIC (EIAJ)
J: SOIC (JEDEC)
U14: 14 pin TSSOP
L: PDIP (Lead free, Halogen free)
X: SOIC (EIAJ, Lead free, Halogen free)
W: SOIC (JEDEC, Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
* -40° to +125°C is available upon request
Notes:
(1) The device used in the above example is a 24WC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWA). For additional
information, please contact your Catalyst sales office.
Doc. No. 1038, Rev. E
8
REVISION HISTORY
Date
Revision Comments
04/18/04
B
Delete data sheet designation
Update Features
Update Pin Configuration
Update Ordering Information
07/23/04
08/05/04
03/11/05
C
D
E
Add die revision to Ordering Information
Update DC Operating Characteristics & notes
Update Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1038
Revison:
E
Issue date:
03/11/05
Fax: 408.542.1200
www.catalyst-semiconductor.com
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