CAT24WC03LA [CATALYST]

EEPROM, 256X8, Serial, CMOS, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8;


型号：	CAT24WC03LA
厂家：	CATALYST SEMICONDUCTOR
描述：	EEPROM, 256X8, Serial, CMOS, PDIP8, LEAD AND HALOGEN FREE, PLASTIC, DIP-8 可编程只读存储器
文件：	总8页 (文件大小：46K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary

CAT24WC03/05/09/17

2K/4K/8K/16K-Bit Serial E²PROM

FEATURES

■ 400 KHZ I²C Bus Compatible*

■ 1.8 to 6.0Volt Operation

■ Self-Timed Write Cycle with Auto-Clear

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ Low Power CMOS Technology

■ 8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package

■ Write Protect Feature

–Top 1/2 Array Protected When WP at V_IH

■ Commercial, Industrial and Automotive

Temperature Ranges

■ 16-Byte Page Write Buffer

DESCRIPTION

ments. The CAT24WC03/05/09/17 features a 16-byte

page write buffer. The device operates via the I²C bus

serial interface, has a special write protection feature,

and is available in 8-pin DIP or 8-pin SOIC

TheCAT24WC03/05/09/17isa2K/4K/8K/16K-bitSerial

CMOS E²PROM internally organized as 256/512/1024/

2048 words of 8 bits each. Catalyst’s advanced CMOS

technology substantially reduces device power require-

PIN CONFIGURATION

BLOCK DIAGRAM

EXTERNAL LOAD

DIP Package (P)

SOIC Package (J)

SENSE AMPS

SHIFT REGISTERS

OUT

ACK

SCL

SDA

SCL

SDA

WORD ADDRESS

BUFFERS

COLUMN

DECODERS

START/STOP

TSSOP Package (U)

SDA

(** Available for 24WC03 only)

LOGIC

E²PROM

XDEC

SCL

SDA

CONTROL

LOGIC

PIN FUNCTIONS

DATA IN STORAGE

Pin Name

Function

A0, A1, A2

SDA

Device Address Inputs

Serial Data/Address

Serial Clock

HIGH VOLTAGE/

TIMING CONTROL

SCL

STATE COUNTERS

Write Protect

SLAVE

ADDRESS

COMPARATORS

V_CC

+1.8V to +6.0V Power Supply

Ground

V_SS

24WCXX F03

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

Characteristics subject to change without notice

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Voltage on Any Pin with

Respect to Ground⁽¹⁾........... –2.0V to +V_CC+ 2.0V

V_CCwith Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C) .................................. 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100mA

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Min.

1,000,000

100

Max.

Units

Cycles/Byte

Years

Reference Test Method

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(3)

N_END

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-up

(3)

V_ZAP

2000

Volts

(3)(4)

I_LTH

100

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Limits

Typ.

Symbol

Parameter

Min.

Max.

Units

µA

Test Conditions

f_SCL= 100 KHz

I_CC

Power Supply Current

(5)

I_S

Standby Current (V_CC= 5.0V)

Input Leakage Current

V_IN= GND or V_CC

V_IN= GND to V_CC

V_OUT= GND to V_CC

I_LI

I_LO

Output Leakage Current

Input Low Voltage

V_IL

–1

V_CCx 0.3

V_CC+ 0.5

0.4

V_IH

Input High Voltage

V_CCx 0.7

V_OL1

V_OL2

Output Low Voltage (V_CC= 3.0V)

Output Low Voltage (V_CC= 1.8V)

I_OL= 3 mA

0.5

I_OL= 1.5 mA

CAPACITANCE T = 25°C, f = 1.0 MHz, V

= 5V

Symbol

Test

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL, WP)

Max.

Units

Conditions

V_I/O= 0V

V_IN= 0V

(3)

C_I/O

(3)

C_IN

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

(5) Standby Current (I ) = 0µA (<900nA).

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

A.C. CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Read & Write Cycle Limits

Symbol

Parameter

1.8V, 2.5V

4.5V-5.5V

Min.

Max.

100

Min.

Max.

Units

kHz

F_SCL

T_I⁽¹⁾

Clock Frequency

400

200

Noise Suppression Time

200

Constant at SCL, SDA Inputs

t_AA

SCL Low to SDA Data Out

and ACK Out

3.5

µs

(1)

t_BUF

Time the Bus Must be Free Before

a New Transmission Can Start

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

0.6

1.2

0.6

µs

4.7

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

4.7

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

Data In Hold Time

µs

Data In Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

100

(1)(2)

Power-Up Timing

Symbol

t_PUR

Parameter

Max.

Units

Power-up to Read Operation

Power-up to Write Operation

t_PUW

Write Cycle Limits

Symbol

Parameter

Min.

Typ.

Max

Units

t_WR

Write Cycle Time

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t

and t

are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The CAT24WC03/05/09/17 supports the I²C Bus data

transmission protocol. This Inter-Integrated Circuit Bus

protocol defines any device that sends data to the bus to

be a transmitter and any device receiving data to be a

receiver.DatatransferiscontrolledbytheMasterdevice

which generates the serial clock and all START and

STOP conditions for bus access. The CAT24WC03/05/

09/17 operates as a Slave device. Both the Master and

Slave devices can operate as either transmitter or re-

ceiver, but the Master device controls which mode is

activated.Amaximumof8devices(24WC03),4devices

(24WC05),2devices(24WC09)and1device(24WC17)

may be connected to the bus as determined by the

device address inputs A0, A1, and A2.

SCL: Serial Clock

TheCAT24WC03/05/09/17serialclockinputpinisused

to clock all data transfers into or out of the device. This

is an input pin.

SDA: Serial Data/Address

The CAT24WC03/05/09/17 bidirectional serial data/ad-

dress pin is used to transfer data into and out of the

device. The SDA pin is an open drain output and can be

wire-ORed with other open drain or open collector

outputs.

A0, A1, A2: Device Address Inputs

These inputs set device address when cascading mul-

tiple devices. When these pins are left floating the

default values are zeros.

A maximum of eight devices can be cascaded when

using 24WC03 device. All three address pins are used

Figure 1. Bus Timing

HIGH

LOW

SCL

SU:STA

HD:DAT

HD:STA

SU:DAT

SU:STO

SDA IN

BUF

SDA OUT

5020 FHD F03

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

5020 FHD F04

Figure 3. Start/Stop Timing

SDA

SCL

START BIT

STOP BIT

5020 FHD F05

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

I²C BUS PROTOCOL

for 24WC03. If only one 24WC03 is addressed on the

bus, all three address pins (A0, A1, and A2) can be left

floating or connected to V_SS

The following defines the features of the I²C bus proto-

col:

A total of four devices can be addressed on a single bus

when using 24WC05 device. Only A1 and A2 address

pins are used with this device. The A0 address pin is a

no connect pin and can be tied to V_SSor left floating. If

only one 24WC05 is being addressed on the bus, the

address pins (A1 and A2) can be left floating or con-

nected to V_SS.

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

Onlytwodevicescanbecascadedwhenusing24WC09.

TheonlyaddresspinusedwiththisdeviceisA2. TheA0

and A1address pins are no connect pins and can be tied

to V_SSor left floating. If only one 24WC09 is being

addressed on the bus, the address pin (A2) can be left

floating or connected to V_SS.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT24WC03/05/09/17

monitortheSDAandSCLlinesandwillnotresponduntil

this condition is met.

The 24WC17 is a stand alone device. In this case, all

address pins (A0, A1and A2) are no connect pins and

can be tied to V_SSor left floating.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

WP: Write Protect

IftheWPpinistiedtoV_CCtheupperhalfofmemoryarray

becomes Write Protected (READ only)(locations 80H to

FFH for 24WC03, locations 100H to 1FFH for 24WC05,

locations 200H to 3FFH for 24WC09, locations 400H to

7FFH for 24WC17). When the WP pin is tied to V_SSor

left floating normal read/write operations are allowed to

the device.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master then sends the address

of the particular slave device it is requesting. The four

Figure 4. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

5020 FHD F06

Figure 5. Slave Address Bits

24WC03

24WC05

24WC09

24WC17

A0 R/W

a8 R/W

a10 a9

A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.

** a8, a9 and a10 correspond to the address of the memory array address word.

***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

most significant bits of the 8-bit slave address are fixed

as 1010 for the CAT24WC03/05/09/17 (see Fig. 5). The

next three significant bits (A2, A1, A0) are the device

addressbitsanddefinewhichdeviceorwhichpartofthe

devicetheMasterisaccessing. UptoeightCAT24WC03,

four CAT24WC05, two CAT24WC09, and one

CAT24WC17 may be individually addressed by the

system. The last bit of the slave address specifies

whether a Read or Write operation is to be performed.

When this bit is set to 1, a Read operation is selected,

and when set to 0, a Write operation is selected.

monitors the line for an acknowledge. Once it receives

this acknowledge, the CAT24WC03/05/09/17 will con-

tinue to transmit data. If no acknowledge is sent by the

Master, the device terminates data transmission and

waits for a STOP condition.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

the byte address that is to be written into the address

pointer of the CAT24WC03/05/09/17. After receiving

another acknowledge from the Slave, the Master device

transmits the data byte to be written into the addressed

memory location. The CAT24WC03/05/09/17 acknowl-

edge once more and the Master generates the STOP

condition, at which time the device begins its internal

programming cycle to nonvolatile memory. While this

internal cycle is in progress, the device will not respond

to any request from the Master device.

After the Master sends a START condition and the slave

address byte, the CAT24WC03/05/09/17 monitors the

bus and responds with an acknowledge (on the SDA

line) when its address matches the transmitted slave

address. The CAT24WC03/05/09/17 then performs a

Read or Write operation depending on the state of the

R/W bit.

Acknowledge

Afterasuccessfuldatatransfer, eachreceivingdeviceis

requiredtogenerateanacknowledge.TheAcknowledg-

ing device pulls down the SDA line during the ninth clock

cycle, signaling that it received the 8 bits of data.

Page Write

The CAT24WC03/05/09/17 responds with an acknowl-

edge after receiving a START condition and its slave

address. If the device has been selected along with a

write operation, it responds with an acknowledge after

receiving each 8-bit byte.

The CAT24WC03/05/09/17 writes up to 16 bytes of data

in a single write cycle, using the Page Write operation.

ThePageWriteoperationisinitiatedinthesamemanner

as the Byte Write operation, however instead of termi-

nating after the initial word is transmitted, the Master is

allowedtosendupto15additionalbytes.Aftereachbyte

has been transmitted the CAT24WC03/05/09/17 will

respond with an acknowledge, and internally increment

When the CAT24WC03/05/09/17 is in a READ mode it

transmits 8 bits of data, releases the SDA line, and

Figure 6. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA LINE

5020 FHD F08

Figure 7. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

DATA n

DATA n+1

DATA n+P

SDA LINE

NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0

24WCXX F09

24WCXX FO9

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

the low order address bits by one. The high order bits

remain unchanged.

device’s failure to send an acknowledge after the first

byte of data is received.

If the Master transmits more than 16 bytes prior to

sendingtheSTOPcondition,theaddresscounter‘wraps

around’,andpreviouslytransmitteddatawillbeoverwrit-

ten.

READ OPERATIONS

The READ operation for the CAT24WC03/05/09/17 is

initiated in the same manner as the write operation with

the one exception that the R/W bit is set to a one. Three

different READ operations are possible: Immediate Ad-

dress READ, Selective READ and Sequential READ.

Once all 16 bytes are received and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point all received data is written to

the CAT24WC03/05/09/17 in a single write cycle.

Immediate Address Read

Acknowledge Polling

The CAT24WC03/05/09/17’s address counter contains

the address of the last byte accessed, incremented by

one. In other words, if the last READ or WRITE access

was to address N, the READ immediately following

would access data from address N+1. If N=E (where E

= 255 for 24WC03, 511 for 24WC05, 1023 for 24WC09,

and 2047 for 24WC17), then the counter will ‘wrap

around’ to address 0 and continue to clock out data.

After the CAT24WC03/05/09/17 receives its slave ad-

dress information (with the R/W bit set to one), it issues

anacknowledge,thentransmitsthe8-bitbyterequested.

The master device does not send an acknowledge but

will generate a STOP condition.

The disabling of the inputs can be used to take advan-

tage of the typical write cycle time. Once the stop

condition is issued to indicate the end of the host’s write

operation, the CAT24WC03/05/09/17 initiates the inter-

nalwritecycle. ACKpollingcanbeinitiatedimmediately.

This involves issuing the start condition followed by the

slave address for a write operation. If the CAT24WC03/

05/09/17isstillbusywiththewriteoperation, noACKwill

be returned. If the CAT24WC03/05/09/17 has com-

pleted the write operation, an ACK will be returned and

the host can then proceed with the next read or write

operation.

Selective Read

WRITE PROTECTION

Selective READ operations allow the Master device to

select at random any memory location for a READ

operation. The Master device first performs a ‘dummy’

write operation by sending the START condition, slave

address and byte address of the location it wishes to

read. After the CAT24WC03/05/09/17 acknowledge the

word address, the Master device resends the START

condition and the slave address, this time with the R/W

bitsettoone.TheCAT24WC03/05/09/17thenresponds

withitsacknowledgeandsendsthe8-bitbyterequested.

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to V_CC, the upper half (locations 80H

toFFHfor24WC03,locations100Hto1FFHfor24WC05,

locations 200H to 3FFH for 24WC09, locations 400H to

7FFHfor24WC17)ofthememoryarrayisprotectedand

becomes read only. The CAT24WC03/05/09/17 will

accept both slave and byte addresses, but the memory

locationaccessedisprotectedfromprogrammingbythe

Figure 8. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

DATA

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

5020 FHD F10

Doc. No. 25063-00 2/98 S-1

CAT24WC03/05/09/17

Preliminary

The master device does not send an acknowledge but

will generate a STOP condition.

respond with an acknowledge, thus sending the STOP

condition.

Sequential Read

The data being transmitted from the CAT24WC03/05/

09/17isoutputtedsequentiallywithdatafromaddressN

followed by data from address N+1. The READ opera-

tion address counter increments all of the CAT24WC03/

05/09/17 address bits so that the entire memory array

can be read during one operation. If more than the E

(where E = 255 for 24WC03, 511 for 24WC05, 1023 for

24WC09, and 2047 for 24WC17) bytes are read out, the

counterwill“wraparound”andcontinuetoclockoutdata

bytes.

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT24WC03/05/09/17 sends the

initial 8-bit byte requested, the Master will respond with

an acknowledge which tells the device it requires more

data. The CAT24WC03/05/09/17 will continue to output

an 8-bit byte for each acknowledge sent by the Master.

The operation is terminated when the Master fails to

Figure 9. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

24WCXX F11

Figure 10. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

5020 FHD F12

ORDERING INFORMATION

Prefix

Device #

24WC03

Suffix

CAT

-1.8

TE13

Optional

Company ID

Temperature Range

Product Number

24WC03: 2K

24WC05: 4K

24WC09: 8K

24WC17: 16K

Tape & Reel

TE13: 2000/Reel

Blank = Commercial (0˚ - 70˚C)

I = Industrial (-40˚ - 85˚C)

A = Automotive (-40˚ - 105˚C)*

Package

Operating Voltage

Blank: 2.5V - 6.0V

1.8: 1.8V - 6.0V

P: PDIP

J: SOIC (JEDEC)

U: TSSOP **

* -40˚ to +125˚C is available upon request

** Available for 24WC03

Notes:

(1) The device used in the above example is a 24WC03JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating

Voltage, Tape & Reel)

Doc. No. 25063-00 2/98 S-1

CAT24WC03LA [CATALYST]

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