CAT24FC01WE-TE13 [CATALYST]
CAT24FC01WE-TE13;
| 型号： | CAT24FC01WE-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | CAT24FC01WE-TE13 |
| 文件： | 总10页 (文件大小：627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24FC01
1-kb I2C Serial EEPROM
FEATURES
I 400 kHz (2.5 V) I2C bus compatible
I 2.5 to 5.5 volt operation
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, SOIC, TSSOP and MSOP packages
- “Green” package option available
I 256 x 8 memory organization
I Hardware write protect
I Low power CMOS technology
I 16-byte page write buffer
I Industrial and extended temperature ranges
I Self-timed write cycle with auto-clear
DESCRIPTION
The CAT24FC01 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP, SOIC, TSSOP and MSOP
packages.
The CAT24FC01 is a 1-kb Serial CMOS EEPROM
internallyorganizedas128wordsof8bitseach.Catalyst’s
advanced CMOS technology substantially reduces
device power requirements.
PIN CONFIGURATION
BLOCK DIAGRAM
EXTERNAL LOAD
DIP Package (P, L, GL)
SOIC Package (J, W, GW)
SENSE AMPS
SHIFT REGISTERS
D
OUT
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
ACK
0
1
2
CC
0
1
2
V
CC
WP
WP
V
CC
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SCL
SDA
V
SCL
SDA
SS
V
V
SS
SS
START/STOP
LOGIC
SDA
WP
TSSOP Package (U, Y, GY)
1
2
3
4
8
7
6
5
A
A
A
0
1
2
V
CC
WP
E2PROM
XDEC
CONTROL
LOGIC
SCL
SDA
V
SS
MSOP Package (R, Z, GZ)
DATA IN STORAGE
1
2
3
4
8
7
6
5
V
A0
A1
A2
CC
WP
HIGH VOLTAGE/
TIMING CONTROL
SCL
SDA
V
SS
SCL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
A
0
A1
A2
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
SCL
WP
Write Protect
VCC
2.5 V to 5.5 V Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I C Bus Protocol.
2
VSS
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1073, Rev. G
1
CAT24FC01
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current(2) ....................... 100 mA
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias
–55°C to +125°C
Storage Temperature....................... –65°C to +150°C
*COMMENT
Voltage on Any Pin with
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outsideofthoselistedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to any absolute maximum rating for extended periods
Respect to Ground(1) ............–2.0 V to VCC + 2.0 V
VCC with Respect to Ground ............. –2.0 V to +7.0 V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
may affect device performance and reliability.
RELIABILITY CHARACTERISTICS(3)
Symbol
Parameter
Endurance
MinTyp
1,000,000
100
Max its Un
(3)
NEND
Cycles/Byte
Years
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
4000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
= 2.5 V to 5.5 V, unless otherwise specified.
CC
Symbol
ICC
Parameter
Test Conditions
fSCL = 400 kHz
Min
Typ
Max
Units
mA
mA
µA
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (VCC = 5.0 V)
Input Leakage Current
1
3
1
1
1
ICC
fSCL = 400 kHz
(5)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
ILO
VIL
VIH
VOL
µA
Output Leakage Current
Input Low Voltage
µA
–1
VCC x 0.3
VCC + 1.0
0.4
V
V
V
Input High Voltage
VCC x 0.7
Output Low Voltage (VCC = 3.0 V)
IOL = 3 mA
CAPACITANCE T = 25°C, f = 400 kHz, V
= 5 V
CC
A
Symbol
Test
Conditions
VI/O = 0 V
VIN = 0 V
Min
Typ
Max
8
Units
pF
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
(3)
CIN
6
pF
Note:
(1) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V + 0.5 V, which may overshoot to V + 2.0 V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1.0 V to V + 1.0 V.
CC
(5) Maximum standby current (I ) = 10µA for the Extended Automotive temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1073, Rev. G
2
CAT24FC01
A.C. CHARACTERISTICS
V
= 2.5 V to 5.5 V, unless otherwise specified.
CC
Read & Write Cycle Limits
Symbol
Parameter
2.5 V - 5.5 V
MinMax
its Un
FSCL
TI(1)
tAA
Clock Frequency
0
400
100
900
kHz
ns
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
ns
(1)
tBUF
Time the Bus Must be Free Before a New Transmission
Can Start
1300
ns
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
600
1300
600
ns
ns
ns
ns
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
600
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
Data In Hold Time
0
ns
ns
ns
ns
ns
ns
Data In Setup Time
100
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
300
300
(1)
tF
tSU:STO
tDH
600
100
(1)(2)
Power-Up Timing
Symbol
Parameter
MinTyp
MinTyp
Max
Max
its Un
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
Write Cycle Limits
Symbol
Parameter
its Un
tWR
Write Cycle Time
5
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1073, Rev. G
3
CAT24FC01
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The CAT24FC01 bidirectional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
TheCAT24FC01supportstheI2CBusdatatransmission
protocol.ThisInter-IntegratedCircuitBusprotocoldefines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. Data
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditionsforbusaccess. TheCAT24FC01operatesas
a Slave device. Both the Master and Slave devices can
operate as either transmitter or receiver, but the Master
device controls which mode is activated. A maximum of
8devicesmaybeconnectedtothebusasdeterminedby
the device address inputs A0, A1, and A2.
A0, A1, A2: Device Address Inputs
Theseinputssetdeviceaddresswhencascadingmultiple
devices. A maximum of eight devices can be cascaded
when using the device.
WP: Write Protect
This input, when tied to GND, allows write operations to
theentirememory. ForCAT24FC01whenthispinistied
to VCC, the entire array of memory is write protected.
When left floating, memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT24FC01 serial clock input pin is used to clock all
datatransfersintooroutofthedevice. Thisisaninputpin.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1073, Rev. G
4
CAT24FC01
I2C BUS PROTOCOL
and define which device the Master is accessing. Up to
eight CAT24FC01 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
address byte, the CAT24FC01 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC01 then performs a Read or a Write operation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC01 monitors the
SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
STOP Condition
The CAT24FC01 responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
When the CAT24FC01 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC01 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC01 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0 R/W
Normal Read and Write
DEVICE ADDRESS
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1073, Rev. G
5
CAT24FC01
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24FC01 in a single write cycle.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24FC01. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
the data byte to be written into the addressed memory
location. The CAT24FC01 acknowledges once more
and the Master generates the STOP condition, at which
time the device begins its internal programming to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24FC01 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24FC01 is still busy with
the write operation, no ACK will be returned. If the
CAT24FC01hascompletedthewriteoperation, anACK
will be returned and the host can then proceed with the
next read or write operation.
Page Write
WRITE PROTECTION
The CAT24FC01 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted the CAT24FC01 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
The CAT24FC01 is designed with a hardware protect
pin that enables the user to protect the entire memory.
Thehardware protection feature of the CAT24FC01 is
designed into the part to provide added flexibility to the
design engineers. The write protection feature of
CAT24FC01allowstheusertoprotectagainstinadvertent
programming of the memory array. If the WP pin is tied
toVcc,theentirememoryarrayisprotectedandbecomes
read only. The entire memory becomes write protected
regardlessofwhetherthewriteprotectregisterhasbeen
written or not. When WP pin is tied to Vcc, the user
cannot program the write protect register. If the WP pin
is left floating or tied to Vss, the device can be written
into.
If the Master transmits more than 16 bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+7
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1073, Rev. G
6
CAT24FC01
Read Operations
read. After the CAT24FC01 acknowledge the word
address,theMasterdeviceresendstheSTARTcondition
and the slave address, this time with the R/W bit set to
one. The CAT24FC01 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
The READ operation for the CAT24FC01 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
Sequential Read
TheCAT24FC01’saddresscountercontainstheaddress
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N + 1. If N = 217, the counter
willnot‘wraparound’. AftertheCAT24FC01receivesits
slave address information (with the R/W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
The Sequential READ operation can be initiated by
eithertheImmediateAddressREADorSelectiveREAD
operations. After the CAT24FC01 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC01 will continue to output a byte for
each acknowledge sent by the Master. The operation
willterminateoperationwhentheMasterfailstorespond
withanacknowledge,thussendingtheSTOPcondition.
The data being transmitted from the CAT24FC01 is
outputtedsequentiallywithdatafromaddressNfollowed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC01
address bits so that the entire memory array can be
read during one operation.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1073, Rev. G
7
CAT24FC01
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1073, Rev. G
8
CAT24FC01
ORDERING INFORMATION
Prefix
Device #
24FC01
Suffix
CAT
J
I
TE13
REV-E
Optional
Company ID
Temperature Range
I = Industri
E = Extended (-40°C to +125°C)
Tape & Reel
Product
Number
Die Revision: E, F
Package
P: PDIP
J: SOIC, JEDEC
R: MSOP
U: TSSOP
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a CAT24FC01JI-TE13 REV-E (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Doc No. 1073, Rev. G
9
Characteristics subject to change without notice
REVISION HISTORY
Date
Revision Comments
03/01/04
A
B
Initial Issue
05/15/04
Updated D.C. Operating Characteristics
Updated Write Cycle Limits
Updated Ordering Information
Updated Revision History
Updated Rev Number
06/07/04
07/27/04
C
D
Updated Write Cycle Limits
Updated table notes on page 2
1/27/05
E
F
Added Die Revision E to Ordering Information
03/23/05
Updated Features
Updated Description
Updated Pin Function
Updated Reliability Characteristics
Updated D.C. Operating Characteristics
Updated A.C. Characteristics
Updated Ordering Information
08/02/05
G
Update Pin Configuration
Update Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Publication #: 1073
Phone: 408.542.1000
Revison:
G
Fax: 408.542.1200
Issue date:
08/02/05
www.caalyst-semiconductor.com
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