CAT24C256YI-GT2 [CATALYST]
EEPROM, 32KX8, Serial, CMOS, PDSO8, 4.4 MM, GREEN, MO-153, TSSOP-8;
| 型号： | CAT24C256YI-GT2 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 32KX8, Serial, CMOS, PDSO8, 4.4 MM, GREEN, MO-153, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总17页 (文件大小：741K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24C256
256-Kb I2C CMOS Serial EEPROM
fEATuRES
DEVICE DESCRIPTIOn
n Sꢂpports Staꢃdard aꢃd fast I2C Protocol
n 1.8V to 5.5V Sꢂpplꢄ Voltaꢅe Raꢃꢅe
n 64-ꢁꢄte Paꢅe Write ꢁꢂꢆꢆer
The CAT24C256 is a 256-Kb Serial CMOS EEPROM,
internally organized as 32,768 words of 8 bits each.
It features a 64-byte page write buffer and supports
both the Standard (ꢀ00kHz) as well as Fast (400kHz)
I2C protocol.
n Hardware Write Protectioꢃ ꢆor eꢃtire memorꢄ
n Schmitt Triꢅꢅers aꢃd noise Sꢂppressioꢃ filters
oꢃ I2C ꢁꢂs Iꢃpꢂts (SCꢀ aꢃd SDA).
Write operations can be inhibited by taking the WP pin
High (this protects the entire memory).
n ꢀow power CMOS techꢃoloꢅꢄ
n 1,000,000 proꢅram/erase cꢄcles
n 100 ꢄear data reteꢃtioꢃ
External address pins make it possible to address up to
eight CAT24C256 devices on the same bus.
n Iꢃdꢂstrial temperatꢂre raꢃꢅe
n RoHS-compliaꢃt 8-piꢃ PDIP, SOIC, TSSOP aꢃd
8-pad TDfn packaꢅes
for Orderiꢃꢅ Iꢃꢆormatioꢃ details, see paꢅe 15.
PIn COnfIguRATIOn
funCTIOnAꢀ SyMꢁOꢀ
PDIP (ꢀ)
SOIC (W, X)
TSSOP (y)
TDfn (ZD2)
V
CC
A
1
8
V
CC
0
SCL
A
2
3
4
7
6
5
WP
1
2
A
SCL
SDA
A , A , A
CAT24C256
SDA
2
1
0
V
SS
For the location of Pin ꢀ, please consult the
corresponding package drawing.
WP
V
SS
PIn funCTIOnS
A0, Aꢀ, A2
SDA
SCL
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
WP
VCC
VSS
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
ꢀ
CAT24C256
AꢁSOꢀuTE MAXIMuM RATIngS(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground(2)
-65°C to +ꢀ50°C
-0.5 V to +6.5 V
REꢀIAꢁIꢀITy CHARACTERISTICS(3)
Sꢄmbol Parameter
Miꢃ
ꢀ,000,000
ꢀ00
uꢃits
(4)
NEND
TDR
Endurance
Program/ Erase Cycles
Years
Data Retention
D.C. OPERATIng CHARACTERISTICS
VCC = ꢀ.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Sꢄmbol Parameter
ICC Supply Current
ISB
Test Coꢃditioꢃs
Miꢃ
Max
uꢃits
Read or Write at 400kHz
All I/O Pins at GND or VCC
Pin at GND or VCC
ꢀ
mA
µA
µA
V
Standby Current
I/O Pin Leakage
ꢀ
ꢀ
IL
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
-0.5
VCC x 0.3
VIH
VOLꢀ
VOL2
VCC x 0.7 VCC + 0.5
V
VCC ≥ 2.5 V, IOL = 3.0mA
0.4
0.2
V
VCC < 2.5 V, IOL = ꢀ.0mA
V
PIn IMPEDAnCE CHARACTERISTICS
VCC = ꢀ.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Sꢄmbol Parameter
Coꢃditioꢃs
Miꢃ
Max
8
uꢃits
pF
(3)
CIN
SDA I/O Pin Capacitance
VIN = 0V
(3)
CIN
IWP
Input Capacitance (other pins)
VIN = 0V
6
pF
(5)
WP Input Current
(CAT24C256 Rev. C - New Product)
VIN < VIH, VCC = 5.5V
VIN < VIH, VCC = 3.3V
VIN < VIH, VCC = ꢀ.8V
VIN > VIH
200
ꢀ50
ꢀ00
ꢀ
µA
notes:
(ꢀ) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -ꢀ.5V or overshoot to no more than VCC + ꢀ.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Qꢀ00
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
The variable WP input impedance is available only for Die Rev. C, New Product.
© Catalyst Semiconductor, Inc.
Doc. No. MD-ꢀꢀ04, Rev. F
2
Characteristics subject to change without notice
CAT24C256
A.C. CHARACTERISTICS(1)
VCC = ꢀ.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Staꢃdard
fast
Sꢄmbol
Parameter
Miꢃ
Max
Miꢃ
Max
uꢃits
FSCL
Clock Frequency
ꢀ00
400
kHz
tHD:STA
START Condition Hold Time
4
0.6
µs
tLOW
tHIGH
Low Period of SCL Clock
High Period of SCL Clock
4.7
4
ꢀ.3
0.6
µs
µs
tSU:STA
tHD:DAT
tSU:DAT
START Condition Setup Time
Data In Hold Time
4.7
0
0.6
0
µs
µs
ns
ns
ns
µs
µs
µs
ns
ns
µs
µs
ms
ms
Data In Setup Time
250
ꢀ00
(2)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
ꢀ000
300
300
300
(2)
tF
tSU:STO
tBUF
4
0.6
ꢀ.3
4.7
tAA
3.5
0.9
tDH
ꢀ00
ꢀ00
Ti(2)
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
ꢀ00
ꢀ00
tSU:WP
tHD:WP
tWR
0
0
WP Hold Time
2.5
2.5
Write Cycle Time
5
ꢀ
5
ꢀ
(2, 3)
tPU
Power-up to Ready Mode
notes:
(ꢀ) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST COnDITIOnS
Input Levels
0.2 x VCC to 0.8 x VCC
≤ 50ns
Input Rise and Fall Times
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load
Current Source: IOL = 3mA (VCC ≥ 2.5V); IOL = ꢀ mA (VCC < 2.5V); CL = ꢀ00pF
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
3
CAT24C256
I2C ꢁuS PROTOCOꢀ
POWER-On RESET (POR)
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDAline to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘ꢀ’.
The CAT24C256 Die Rev. C incorporates Power-On
Reset (POR) circuitry which protects the internal logic
against powering up in the wrong state.
The device will power up into Standby mode after VCC
exceeds the POR trigger level and will power down
into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a tem-
porary loss of power.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure ꢀ).
PIn DESCRIPTIOn
SCꢀ:The Serial Clock input pin accepts the Serial Clock
generated by the Master.
START
TheSTARTconditionprecedesallcommands.Itconsists
of a HIGH to LOW transition on SDAwhile SCLis HIGH.
TheSTARTactsasa‘wake-up’calltoallreceivers.Absent
a START, a Slave will not respond to commands.
SDA: The Serial Data I/O pin receives input data and
transmitsdatastoredinEEPROM.Intransmitmode,this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
STOP
A0, A1 aꢃd A2: The Address pins accept the device ad-
dress. These pins have on-chip pull-down resistors.
TheSTOPconditioncompletesallcommands.Itconsists
of a LOW to HIGH transition on SDAwhile SCLis HIGH.
The STOP starts the internal Write cycle (when follow-
ing a Write command) or sends the Slave into standby
mode (when following a Read command).
WP: The Write Protect input pin inhibits all write op-
erations, when pulled HIGH. This pin has an on-chip
pull-down resistor.
Device Addressiꢃꢅ
funCTIOnAꢀ DESCRIPTIOn
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to ꢀ0ꢀ0, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A2, Aꢀ and A0, select
one of 8 possible Slave devices. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
The CAT24C256 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
devicereceivingdataasareceiver.Dataflowiscontrolled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C256
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A0, Aꢀ, and A2.
Ackꢃowledꢅe
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the byte address and every data
byte presented in Write mode. In Read mode the Slave
shifts out a data byte, and then releases the SDA line
during the 9th clock cycle. If the Master acknowledges
the data, then the Slave continues transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by sending a STOP to
the Slave. Bus timing is illustrated in Figure 4.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
4
CAT24C256
fiꢅꢂre 1. Start/Stop Timiꢃꢅ
SCL
SDA
START
STOP
CONDITION
CONDITION
fiꢅꢂre 2. Slave Address ꢁits
1
0
1
0
A
A
A
0
R/W
2
1
DEVICE ADDRESS
fiꢅꢂre 3. Ackꢃowledꢅe Timiꢃꢅ
BUS RELEASE DELAY (TRANSMITTER)
BUS RELEASE DELAY (RECEIVER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK SETUP (≥ t
)
SU:DAT
START
ACK DELAY (≤ t
)
AA
fiꢅꢂre 4. ꢁꢂs Timiꢃꢅ
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
t
AA
DH
SDA OUT
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
5
CAT24C256
WRITE OPERATIOnS
ꢁꢄte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be
written (Figure 5). The Slave acknowledges all 4 bytes,
and the Master then follows up with a STOP, which in
turn starts the internal Write operation (Figure 6). During
internal Write, the Slave will not acknowledge any Read
or Write request from the Master.
Paꢅe Write
TheCAT24C256contains32,768bytesofdata,arranged
in 5ꢀ2 pages of 64 bytes each.Atwo byte address word,
following the Slave address, points to the first byte to be
written. The most significant bit of the address word is
‘don’t care’, the next 9 bits identify the page and the last
6 bits identify the byte within the page. Up to 64 bytes
can be written in one Write cycle (Figure 7).
The internal byte address counter is automatically in-
cremented after each data byte is loaded. If the Master
transmitsmorethan64databytes, thenearlierbyteswill
be overwritten by later bytes in a ‘wrap-around’ fashion
(withintheselectedpage).TheinternalWritecyclestarts
immediately following the STOP.
Ackꢃowledꢅe Polliꢃꢅ
Acknowledge polling can be used to determine if the
CAT24C256 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
TheCAT24C256willnotacknowledgetheSlaveaddress,
as long as internal Write is in progress.
Hardware Write Protectioꢃ
With the WP pin held HIGH, the entire memory is pro-
tectedagainstWriteoperations.IftheWPpinisleftfloating
or is grounded, it has no impact on the operation of the
CAT24C256. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first
data byte (Figure 8). If the WP pin is HIGH during the
strobeinterval,theCAT24C256willnotacknowledgethe
data byte and the Write request will be rejected.
Deliverꢄ State
The CAT24C256 is shipped erased, i.e., all bytes are
FFh.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
6
CAT24C256
fiꢅꢂre 5. ꢁꢄte Write Timiꢃꢅ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
A
–A
A –A
DATA
15
8
7
0
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
= Don't Care Bit
*
fiꢅꢂre 6. Write Cꢄcle Timiꢃꢅ
SCL
th
SDA
8
Bit
ACK
Byte n
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
fiꢅꢂre 7. Paꢅe Write Timiꢃꢅ
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
= Don't Care Bit
*
fiꢅꢂre 8. WP Timiꢃꢅ
ADDRESS
BYTE
DATA
BYTE
1
8
9
1
8
SCL
a
a
d
7
d
0
SDA
WP
7
0
t
SU:WP
t
HD:WP
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
7
CAT24C256
READ OPERATIOnS
Immediate Address Read
In standby mode, the CAT24C256 internal address
counterpointstothedatabyteimmediatelyfollowingthe
last byte accessed by a previous operation. If that ‘previ-
ous’ byte was the last byte in memory, then the address
counter will point to the ꢀst memory byte, etc.
When, following a START, the CAT24C256 is presented
with a Slave address containing a ‘ꢀ’ in the R/W bit
position (Figure 9), it will acknowledge (ACK) in the 9th
clock cycle, and will then transmit data being pointed
at by the internal address counter. The Master can stop
further transmission by issuing a NoACK, followed by a
STOP condition.
Selective Read
The Read operation can also be started at an address
different from the one stored in the internal address
counter. The address counter can be initialized by per-
forming a ‘dummy’Write operation (Figure ꢀ0). Here the
START is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired two byte address. Instead
of following up with data, the Master then issues a 2nd
START, followed by the ‘Immediate Address Read’ se-
quence, as described earlier.
Seqꢂeꢃtial Read
If the Master acknowledges the ꢀst data byte transmitted
by the CAT24C256, then the device will continue trans-
mitting as long as each data byte is acknowledged by
the Master (Figure ꢀꢀ). If the end of memory is reached
during sequential Read, then the address counter will
‘wrap-around’tothebeginningofmemory,etc.Sequential
Read works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
8
CAT24C256
fiꢅꢂre 9. Immediate Address Read Timiꢃꢅ
S
T
A
R
T
S
T
BUS ACTIVITY:
MASTER
SLAVE
O
P
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
th
8
Bit
DATA OUT
NO ACK
STOP
fiꢅꢂre 10. Selective Read Timiꢃꢅ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
SLAVE
ADDRESS
A
– A
A – A
DATA
ꢀ5
8
7
0
SDA LINE
S
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
= Don't Care Bit
*
fiꢅꢂre 11. Seqꢂeꢃtial Read Timiꢃꢅ
S
T
BUS ACTIVITY:
MASTER
SLAVE
O
P
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
9
CAT24C256
PACKAgE OuTꢀInE DRAWIngS
PDIP 8-ꢀead 300 mils (ꢀ)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
L
c
b2
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/docꢂmeꢃts/tapeaꢃdreel.pdꢆ
notes:
(ꢀ) All dimensions are in millimeters.
(2) Complies with JEDEC MS-00ꢀ.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
ꢀ0
CAT24C256
SOIC 8-ꢀead 150 mils (W)
SYMBOL
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/docꢂmeꢃts/tapeaꢃdreel.pdꢆ
notes:
(1) Complies with JEDEC specification MS-012 dimensions.
(2) All linear dimensions are in millimeters.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
ꢀꢀ
CAT24C256
SOIC 8-ꢀead 208 mils (X)
E
b
D
c
A
θ1
e
A1
L
SYMBOL
MIN
NOM
MAX
A1
A
b
c
D
E
0.05
0.25
2.03
0.48
0.25
5.33
8.26
5.38
0.36
0.19
5.13
7.75
5.13
E1
e
1.27 BSC
L
θ1
0.51
0°
0.76
8°
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/docꢂmeꢃts/tapeaꢃdreel.pdꢆ
notes:
(1) Complies with EIAJ specification.
(2) All linear dimensions are in millimeters.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
ꢀ2
CAT24C256
TSSOP 8-ꢀead 4.4mm (y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.40
E
E1
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0.75
0°
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/docꢂmeꢃts/tapeaꢃdreel.pdꢆ
notes:
(ꢀ) All dimensions are in milimiters. Angles in degrees
(2) Complies with JEDEC MO-ꢀ53.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
ꢀ3
CAT24C256
TDfn 8-Pad 3 x 4.9mm (ZD2)
D
A
DETAIL A
DAP SIZE
2.6 x 3.3mm
E
E2
PIN #1
IDENTIFICATION
A1
PIN #1 IDENTIFICATION
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A2
A
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
MAX
A
A1
A2
A3
b
0.80
0.05
0.65
0.02
A1
A3
FRONT VIEW
0.55
0.20 REF
0.30
b
0.25
2.90
0.90
4.80
0.90
0.35
3.10
1.10
5.00
1.10
D
3.00
D2
E
1.00
L
4.90
E2
e
1.00
e
0.65 TYP
0.60
DETAIL A
L
0.50
0.70
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/docꢂmeꢃts/tapeaꢃdreel.pdꢆ
notes:
(ꢀ) All dimensions are in milimiters.
(2) Complies with JEDEC MO-229.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
ꢀ4
CAT24C256
ORDERIng InfORMATIOn
Prefix
Device #
24C256
Suffix
CAT
W
I
—
G
T3
Company ID
Temperature Range
I = Industrial (-40°C to +85°C)
Product
Number
Tape & Reel
T: Tape & Reel
2: 2000/Reel(4)(5)
3: 3000/Reel
Package
Lead Finish
L: PDIP
Blank: Matte-Tin(4)
G: NiPdAu
W: SOIC, JEDEC
X: SOIC, EIAJ(4)
Y: TSSOP
ZD2: TDFN (3x4.9mm)(5)
notes:
(ꢀ) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT24C256WI-GT3 (SOIC-JEDEC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT24C256XI-T2.
(5) The TDFN 3x4.9mm (ZD2) package is available in 2000 pcs/reel, i.e., CAT24C256ZD2I-GT2.
(6) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. MD-ꢀꢀ04, Rev. F
ꢀ5
CAT24C256
REVISIOn HISTORy
Date
Revisioꢃ Commeꢃts
ꢀ0/07/05
A
B
C
Initial Issue
Update Ordering Information
Add Tape and Reel Specifications
ꢀꢀ/ꢀ6/05
02/02/06
Update Ordering Information
Update Package Outlines. Add SOIC, EIAJ Package Outlines
Update A.C. Characteristics. Add A.C. Test Conditions
Update Figures ꢀ, 3 and 4
0ꢀ/ꢀ2/07
D
Delete Package Marking. Deleted Tape and Reel
Update Ordering Information
Update Features/Packages
Update Pin Configuration
Update Pin Impedance Characteristics
Add Power-On Reset (POR) text.
Update Hardware Write Protection
05/08/07
08/ꢀ5/07
E
F
Add WP Timing (Figure 8) (Renumbered Figures 9 & ꢀꢀ)
Add 8-Lead TSSOP Package Outline
Add 8-pad TDFN 3x4.9mm Package Outline
Updated Ordering Information
Updated PDIP, SOIC, TSSOP, and TDFN Package Outline Drawings
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. MD-ꢀꢀ04, Rev. F
ꢀ6
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™ and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS
FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD
PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANYAND ALL LIABILITYARISING OUT OF ANY SUCH USE OR
APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death
may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled “Advance
Information” or “Preliminary” and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor
applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.ꢀ000
Fax: 408.542.ꢀ200
www.catsemi.com
Publication #: MD-ꢀꢀ04
Revison:
F
Issue date:
08/ꢀ5/07
相关型号：
©2020 ICPDF网 联系我们和版权申明